JP6565351B2 - Capacitor charger - Google Patents

Description

  The present invention relates to control of a capacitor charging device that periodically charges a capacitor to a set voltage in a pulse power source that generates a high-voltage, large-current pulse using a power capacitor as a DC power source.

  A pulse power source used as a power source for an excimer laser, an ozonizer, or the like applies a capacitor voltage periodically charged by a charging device to a primary side of a pulse transformer through a saturable reactor, for example, and a secondary side thereof. A pulse current that is boosted to a low level is generated, and charging and pulse compression of the capacitor are repeated with multiple stages of capacitors and saturable reactors connected to the secondary side of the pulse transformer. It is configured to generate.

  The main circuit configuration (charging circuit) of the capacitor charging device in the pulse power supply and the control block are configured as shown in FIG. 3, for example.

  In FIG. 3, the positive terminal of the DC power source 1 is connected to the negative terminal of the DC power source 1 through a semiconductor switching element 2, a reactor 3, a current detecting shunt resistor 4, a free-wheeling diode 5 with a polarity shown and a capacitor 6. ing.

  A semiconductor switching element 7 is connected in parallel with the capacitor 6, that is, between the common connection point of the shunt resistor 4 and the free wheel diode 5 and the negative terminal of the DC power supply 1.

  Between the common connection point of the semiconductor switching element 2 and the reactor 3 and the negative electrode end of the DC power supply 1, a free-wheeling diode 8 having the illustrated polarity is connected.

  Reference numeral 11 denotes a voltage detector that detects the voltage E of the DC power supply 1, and reference numeral 12 denotes a voltage detector that detects the voltage (initial voltage Vc 0 and charging voltage V) of the capacitor 6.

  Reference numeral 13 denotes an A / D converter that performs analog / digital conversion on the detected voltage of the voltage detector 11 using a charging signal (rising edge) input from the charging signal generator 14 as a trigger (charging trigger). This is an A / D converter that performs analog / digital conversion of the detection voltage of the voltage detector 12 using a charging signal (rising edge) input from the signal generator 14 as a trigger (charging trigger).

  Reference numeral 16 denotes an output voltage of the A / D converter 13 (voltage E of the DC power supply 1), an output voltage of the A / D converter 15 (initial voltage Vc0 and charging voltage V of the capacitor 6), and a charging voltage command unit 17 Is an arithmetic circuit that receives the charge voltage command value output from the input terminal, calculates an expression (3), which will be described later, and obtains and outputs an ON period ΔT ′ of the semiconductor switching elements 2 and 7.

  Reference numeral 18 denotes a counter that outputs an ON signal during the period ΔT ′ calculated by the arithmetic circuit 16. The ON signal is triggered by a charging signal (rising edge) input from the charging signal generator 14 as a trigger (charging trigger). Output starts.

  Reference numeral 19a denotes a gate circuit that generates and outputs a gate signal for controlling the semiconductor switching element 7 to be ON during the period of ΔT ′ of the ON signal from the counter 18.

  Reference numeral 19b denotes a gate circuit that generates and outputs a gate signal for controlling the semiconductor switching element 2 to be on during the period of ΔT ′ of the on signal from the counter 18.

  The capacitor charging apparatus configured as shown in FIG. 3 charges the capacitor 6 to a voltage given by the charge voltage command value within a predetermined charging period Tchg (for example, 50 μsec). Further, the charging voltage of the capacitor 6 is discharged to, for example, a pulse transformer (not shown) during the discharging period. This operation is repeated 4000 times per second, for example.

  The operation of the circuit of FIG. 3 will be described with reference to FIG.

  FIG. 4A shows a charging signal output from the charging signal generator 14, and this charging signal is a continuous signal having an on period for charging the capacitor 6 and an off period for discharging the capacitor 6 as one cycle.

  FIG. 4B shows an on / off control signal for the semiconductor switching element 7, and FIG. 4C shows an on / off control signal for the semiconductor switching element 2. ΔT ′ calculated in (1).

  FIG. 4D shows the current of the reactor 3, and FIG. 4E shows the voltage of the capacitor 6.

  First, when the charging signal in FIG. 4A rises at time t1, the semiconductor switching elements 2 and 7 are controlled to be turned on for a period of ΔT ′ using this as a trigger (FIGS. 4B and 4C). A current flows through the charging circuit through the path (1) (positive electrode end of the DC power source 1 → semiconductor switching element 2 → reactor 3 → shunt resistor 4 → semiconductor switching element 7 → negative electrode end of the DC power source 1).

  As a result, when the current I flowing through the charging circuit when ΔT ′ elapses, the reactor value of the reactor 3 is L, and the voltage of the DC power supply 1 is E.

  It becomes.

At the same time, the reactor 3 accumulates (1/2) · LI ² energy.

  Next, at time t2 when ΔT ′ has elapsed, the semiconductor switching elements 2 and 7 are simultaneously turned off (FIGS. 4B and 4C), and the charging circuit of FIG. → Shunt resistor 4 → freewheeling diode 5 → capacitor 6 → freewheeling diode 8 → reactor 3) current flows.

  As a result, the energy stored in the reactor 3 (FIG. 4D) is entirely transferred to the capacitor 6 (FIG. 4E). The voltage of the capacitor 6 reaches the charging voltage command value at time t3 when the current of the reactor 3 becomes zero.

  When the capacitor capacity of the capacitor 6 is C, the initial voltage of the capacitor 6 is Vc0, and the voltage of the capacitor 6 after energy transfer is V, according to the law of energy conservation,

  From equations (1) and (2),

  Holds.

  After that, at time t5 when the on period of the charging signal in FIG. 4A ends and the off period starts, the charging voltage of the capacitor 6 is discharged to, for example, a pulse transformer side (not shown) (for example, the capacitor 6 and the pulse transformer). Is discharged when a switch (not shown) connected between the two is turned on.

  Then, at time t6 when the on period of the next cycle of the charging signal in FIG. 4A starts, the charging signal rises again and the same operation as described above is repeated.

  The charging device of FIG. 3 receives the charging voltage command from the charging voltage command unit 17 and then receives the charging signal from the charging signal generation unit 14 in order to obtain high-speed and high-accuracy (for example, 0.1%) charging accuracy. At the same time that the semiconductor switching elements 2 and 7 are turned on as a trigger, the voltage E of the DC power source 1 is detected, and the arithmetic circuit 16 calculates ΔT ′ by the calculation of equation (3). Is turned off, the capacitor 6 is charged to the charge voltage command value by one switching.

  In addition, the thing of the patent documents 1 and 2 was proposed as the charging device of the capacitor | condenser relevant to this invention, for example.

Japanese Patent Laid-Open No. 2007-037204 JP 2002-218743 A

In the circuit configuration of FIG. 3, when the semiconductor switching elements 2 and 7 are turned off while a current is flowing through the path (1) shown in the figure, the current flows back to the free- wheeling diodes 5 and 8 as shown in the path (2) shown in the figure. In the meantime, a surge voltage is generated at both ends of the semiconductor switching elements 2 and 7 due to the influence of the inductance on the circuit. For this reason, a snubber circuit may be required to prevent the semiconductor switching elements 2 and 7 from being damaged by a surge voltage.

Regarding the semiconductor switching element 7, it is possible to make the capacitor 6 serve as a snubber circuit by reducing the inductance in the circuit of the free wheel diode 5 , the capacitor 6 and the semiconductor switching element 7. A dedicated surge absorbing snubber circuit may be required. Even when the semiconductor switching element 2 has a resistance to withstand a surge, there is a problem that a large switching loss occurs when the current is interrupted and the device efficiency is lowered.

  The present invention solves the above-described problems, and an object of the present invention is to provide a capacitor charging device that eliminates the need for a snubber circuit by cutting off a zero current of a semiconductor switching element and reduces switching loss when the current is cut off. is there.

According to another aspect of the present invention, there is provided a capacitor charging apparatus, wherein one end of a capacitor is connected to one end of a first semiconductor switching element via a cathode and an anode of a diode, and the anode and the first of the diode are connected to each other. A common connection point at one end of each of the semiconductor switching elements is connected to a positive terminal of a DC power source via a reactor and a second semiconductor switching element, and the other end of the capacitor and the other end of the first semiconductor switching element are connected to the DC A capacitor charging device having a charging circuit configured to be connected to a negative electrode end of a power source, and periodically charging the capacitor with DC power of the DC power source,
Based on a charging signal in which an on period for charging the capacitor and an off period for discharging are repeated,
On-controlling the first semiconductor switching element and the second semiconductor switching element at a start time of an on period of the charging signal;
The first semiconductor switching element is off-controlled at the time when the first period from the start time of the on period of the charging signal to an arbitrary time before the end of the on period ends,
From the start time of the on period of the charging signal, current flows from the reactor of the charging circuit to the capacitor by turning off the first semiconductor switching element, and after the current becomes zero, the on period of the charging signal ends. A period up to an arbitrary time until is defined as a second period, and a control unit that controls the second semiconductor switching element to turn off at the time when the second period ends is provided.

  In the above configuration, the first and second semiconductor switching elements are on-controlled during the first period and during the same period as the first period within the second period, and the second semiconductor switching is performed from the DC power source. A current flows through the element, the reactor, and the first semiconductor switching element, and energy is accumulated in the reactor.

  Next, during a period from the end of the first period to the end of the second period, the first semiconductor switching element is turned off and the on control of the second semiconductor switching element is continued. During this period, the stored energy of the reactor is transferred to the capacitor connected in parallel to the first semiconductor switching element, and the capacitor is charged.

  Next, when the current flowing through the charging circuit due to charging of the capacitor is zero, the second semiconductor switching element is controlled to be off, so that no surge voltage is generated and switching loss at the time of current interruption is reduced. Thus, destruction of the semiconductor switching element can be prevented. As a result, the efficiency of the apparatus is improved, and a snubber circuit is not required, so that the cost of the apparatus can be reduced.

The capacitor charging device according to claim 2 is the capacitor charging device according to claim 1, wherein the control unit includes:
When the first period is ΔT, the reactor value of the reactor is L, and the voltage of the DC power supply is E, the current I that flows through the charging circuit when the first period elapses,

And define
The capacitor capacity of the capacitor is C, the voltage of the capacitor at the start time of the on period of the charging signal is Vc0, and the current i (t) that flows through the charging circuit after elapse of t time after the first period ends. ,

And define
A time T from the end of the first period until i (t) = 0 is obtained.

Is calculated by
The charging voltage of the capacitor when i (t) = 0 is set as a charging voltage command V ^* .

And define
From the equation (7), the first period ΔT is

An arithmetic circuit for calculating by
A circuit for generating a first control signal for turning on the first semiconductor switching element at the start time of ΔT calculated by the arithmetic circuit, and for turning off the first semiconductor switching element at the end time of ΔT;
The second semiconductor switching element is turned on at the start time of ΔT calculated by the arithmetic circuit, and the second semiconductor switching device is turned on at a time between the lapse of the ΔT + T and the end time of the charging signal. A circuit for generating a second control signal for controlling off of the element;
It is characterized by having.

  According to the above configuration, ΔT (equation (8)), which is the first period, and time T (equation (6)) from when the first period ends until the current of the charging circuit becomes zero are calculated. Calculated by the circuit.

Therefore, the capacitor can be charged to the voltage of the charging voltage command V ^* (formula (7)) with high speed and high accuracy.

  In addition, a second control for turning off the second semiconductor switching element at a time from when the ΔT + T elapses until the end time of the charging signal, that is, a time zone in which the current of the charging circuit is zero. A signal can be generated.

(1) According to the first and second aspects of the present invention, the second semiconductor switching element is provided when the current flowing through the charging circuit is zero without changing the configuration of the conventional capacitor charging circuit. It can be controlled off.

For this reason, no surge voltage is generated, and the switching loss at the time of current interruption can be reduced to prevent the semiconductor switching element from being destroyed. As a result, the efficiency of the apparatus is improved, and a snubber circuit is not required, so that the cost of the apparatus can be reduced.
(2) According to the invention described in claim 2, the capacitor can be charged to the voltage of the charging voltage command V ^* (formula (7)) with high speed and high accuracy.

  In addition, a second control for turning off the second semiconductor switching element at a time from when the ΔT + T elapses until the end time of the charging signal, that is, a time zone in which the current of the charging circuit is zero. A signal can be generated.

The block diagram of the charging device of the capacitor | condenser by the example of embodiment of this invention. 1 shows waveforms of respective parts of the charging device of FIG. 1, (a) is a waveform diagram of a charging signal, (b) is a waveform diagram of an on / off control signal of the semiconductor switching element 7, and (c) is an on state of the semiconductor switching element 2. The waveform diagram of the OFF control signal, (d) is the current waveform diagram of the reactor 3, and (e) is the voltage waveform diagram of the capacitor 6. The block diagram which shows an example of the conventional charging device of a capacitor | condenser. 3A and 3B show waveforms of respective parts of the charging device of FIG. 3, in which FIG. 3A is a waveform diagram of a charging signal, FIG. 3B is a waveform diagram of an on / off control signal of the semiconductor switching element 7, and FIG. The waveform diagram of the OFF control signal, (d) is the current waveform diagram of the reactor 3, and (e) is the voltage waveform diagram of the capacitor 6.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments. FIG. 1 shows a main circuit configuration (charging circuit) of a capacitor charging device according to this embodiment and a block of a control unit, and the same parts as those in FIG.

  1 differs from FIG. 3 in that an arithmetic circuit 26 and counters 18a and 18b are provided in place of the arithmetic circuit 16 and counter 18 of FIG. 3, and the other parts are configured in the same manner as in FIG. Yes.

  The arithmetic circuit 26 outputs an output voltage of the A / D converter 13 (voltage E of the DC power supply 1), an output voltage of the A / D converter 15 (initial voltage Vc0 and charging voltage V of the capacitor 6), and a charging voltage command. The charging voltage command value output from the unit 17 is input, and expressions (6) and (8) to be described later are calculated, and the on-period ΔT (first period) and the charging circuit after ΔT ends Is a computation circuit that computes a time T until the current flowing through becomes zero, outputs information of ΔT to the counter 18a, and outputs information of ΔT, T to the counter 18b. The arithmetic circuit 26 is composed of, for example, a digital signal processor (DSP) or the like.

  Reference numeral 18a denotes a counter that outputs an ON signal for a period of ΔT calculated by the arithmetic circuit 26. The ON signal is output using a charging signal (rising edge) input from the charging signal generator 14 as a trigger (charging trigger). Be started.

  Reference numeral 19a denotes a gate circuit that creates and outputs a gate signal for controlling the semiconductor switching element 7 to be ON during the period of ΔT of the ON signal from the counter 18a.

  18b receives the charging signal from the charging signal generator 14 and ΔT and T calculated by the arithmetic circuit 26, and ΔT + T has elapsed from the rising edge of the charging signal (charging trigger) (the charging circuit after the end of the first period). This is a counter that outputs an ON signal during a period (second period) after the charging signal becomes an OFF period after the current of the current becomes zero.

  Reference numeral 19b denotes a gate circuit that creates and outputs a gate signal for controlling the semiconductor switching element 2 to turn on during the second period of the on signal from the counter 18b.

  The charging signal generator 14, the arithmetic circuit 26, the counter 18a, and the gate circuit 19a constitute a circuit for generating the first control signal of the present invention.

  The charging signal generator 14, the arithmetic circuit 26, the counter 18b, and the gate circuit 19b constitute a circuit for generating the second control signal of the present invention.

  The semiconductor switching element 7 is the first semiconductor switching element of the present invention, and the semiconductor switching element 2 is the second semiconductor switching element of the present invention.

  Next, the operation of the circuit of FIG. 1 will be described with reference to FIG. FIG. 2A shows a charging signal output from the charging signal generator 14, and this charging signal is a continuous signal having an on period for charging the capacitor 6 and an off period for discharging the capacitor 6 as one cycle.

  FIG. 2B shows an ON / OFF control signal for the semiconductor switching element 7, and the ON period is ΔT (first period) calculated by the arithmetic circuit 26.

  FIG. 2 (c) shows an on / off control signal for the semiconductor switching element 2. The on period is after ΔT and T calculated by the arithmetic circuit 26 have elapsed from the rising edge of the charging signal (FIG. 2 (a)). This is the second period up to an arbitrary time until the charging signal is turned off.

  FIG. 2D shows the current of the reactor 3, and FIG. 2E shows the voltage of the capacitor 6.

  First, when the charging signal in FIG. 2A rises at time t1, the semiconductor switching elements 2 and 7 are turned on using this as a trigger (FIGS. 2B and 2C), and the charging circuit in FIG. Current flows through the path (1) (positive electrode end of DC power source 1 → semiconductor switching element 2 → reactor 3 → shunt resistor 4 → semiconductor switching element 7 → negative electrode end of DC power source 1).

  As a result, when the current I flowing through the charging circuit when ΔT has elapsed, the reactor value of the reactor 3 is L, and the voltage of the DC power supply 1 is E.

  It becomes.

  Further, energy is accumulated in the reactor 3.

  Next, at the time t2 when ΔT has elapsed, the ON signal of the counter 18a is terminated and only the semiconductor switching element 7 is controlled to be turned OFF (FIG. 2B), and the charging circuit of FIG. Current flows through the positive terminal of the DC power source 1 → the semiconductor switching element 2 → the reactor 3 → the shunt resistor 4 → the freewheeling diode 5 → the capacitor 6 → the negative terminal of the DC power source 1.

  At this time, if the capacitor capacity of the capacitor 6 is C and the initial voltage of the capacitor 6 is Vc0, the current i (t) after the elapse of time t after the semiconductor switching element 7 is turned off at time t2 is expressed by the equation (5). The current flows through the charging circuit until i (t) = 0 (time t3), and the energy of the reactor 3 is transferred to the capacitor 6 (FIGS. 2D and 2E). Information on the current flowing through the charging circuit is obtained by the shunt resistor 4.

  From Expression (5), the time T from when the semiconductor switching element 7 is turned off until i (t) = 0 is expressed by Expression (6) and is calculated by the arithmetic circuit 26.

When the current has ended (i (t) = 0) (time t3), the charging voltage (= charging voltage command V ^* ) of the capacitor 6 can be expressed by equation (7).

Further, when sin * sin ⁻¹ = cos * cos ⁻¹ = 1 is used, ΔT (first period) can be obtained from the equation (7), and can be expressed by the equation (8). Calculates ΔT in equation (8).

ΔT calculated in this way corresponds to the current passing time during which the energy that can charge the capacitor 6 up to the charging voltage command V ^* can be accumulated in the reactor 3 from the equations (7) and (8). I can say that.

As shown in the time t1 to the time t3, the voltage E of the DC power source 1 obtained by the charging voltage command V ^* , the voltage detector 11, and the A / D converter 13 by using the same control unit as in the prior art (FIG. 3). From the initial voltage Vc0 of the capacitor 6 obtained by the voltage detector 12 and the A / D converter 15, ΔT is calculated by the arithmetic circuit 26, and the capacitor 6 is turned off after the semiconductor switching element 7 is turned on for the period of ΔT. Can be charged to the charging voltage command (V ^* ) with high speed and high accuracy.

  Next, at an arbitrary time t4 from the time t3 when ΔT + T has elapsed to the on-period end time (t5) of the charging signal, the output of the on-signal of the counter 18b (the on-signal corresponding to the second period) ends. The semiconductor switching element 2 is turned off (FIG. 2C).

  At this time t4, since the current flowing through the charging circuit is zero, no surge voltage is generated when the semiconductor switching element 2 is turned off, and the switching loss when the current is interrupted is reduced to prevent the semiconductor switching element 2 from being destroyed. be able to. This improves device efficiency and eliminates the need for a snubber circuit, thereby reducing the cost of the device.

  At time t4 when the semiconductor switching element 2 is turned off, the on-period of the charging signal in FIG. 2 (a) ends from the time t3 when the current flows through the path (2) in FIG. 1 (discharge of the capacitor 6). It can be arbitrarily determined until time t5 (the period starts), and the time setting is set by the counter 18b.

  At time t5 when the on-period of the charging signal in FIG. 2A ends, the charging voltage (FIG. 2E) of the capacitor 6 is discharged to the pulse transformer side (not shown), and then the charging signal in FIG. At time t6 when the ON period starts again, the semiconductor switching elements 2 and 7 are simultaneously turned ON, and thereafter the same operation is repeated.

DESCRIPTION OF SYMBOLS 1 ... DC power source 2, 7 ... Semiconductor switching element 3 ... Reactor 4 ... Shunt resistor 5, 8 ... Free-wheeling diode 6 ... Capacitor 11, 12 ... Voltage detector 13, 15 ... A / D converter 14 ... Charge signal generation part 17 ... charging voltage command section 18a, 18b ... counter 19a, 19b ... gate circuit 26 ... arithmetic circuit

Claims (2)

One end of the capacitor is connected to one end of the first semiconductor switching element via the cathode and anode of the diode, and the common connection point of the anode of the diode and one end of the first semiconductor switching element is connected to the reactor and the second semiconductor switching. A charging circuit configured to be connected to a positive electrode end of a DC power source through an element, and to connect the other end of the capacitor and the other end of the first semiconductor switching element to a negative electrode end of the DC power source; A capacitor charging device that periodically charges a capacitor with DC power of a power source,
Based on a charging signal in which an on period for charging the capacitor and an off period for discharging are repeated,
On-controlling the first semiconductor switching element and the second semiconductor switching element at a start time of an on period of the charging signal;
The first semiconductor switching element is off-controlled at the time when the first period from the start time of the on period of the charging signal to an arbitrary time before the end of the on period ends,
From the start time of the on period of the charging signal, current flows from the reactor of the charging circuit to the capacitor by turning off the first semiconductor switching element, and after the current becomes zero, the on period of the charging signal ends. A period of time until an arbitrary time until is defined as a second period, and a control unit that controls the second semiconductor switching element to turn off at a time when the second period ends is provided. Charging device. The controller is
When the first period is ΔT, the reactor value of the reactor is L, and the voltage of the DC power supply is E, the current I that flows through the charging circuit when the first period elapses,
And define
The capacitor capacity of the capacitor is C, the voltage of the capacitor at the start time of the on period of the charging signal is Vc0, and the current i (t) that flows through the charging circuit after elapse of t time after the first period ends. ,
And define
A time T from the end of the first period until i (t) = 0 is obtained.
Is calculated by
The charging voltage of the capacitor when i (t) = 0 is set as a charging voltage command V ^* .
And define
From the equation (7), the first period ΔT is
An arithmetic circuit for calculating by
A circuit for generating a first control signal for turning on the first semiconductor switching element at the start time of ΔT calculated by the arithmetic circuit, and for turning off the first semiconductor switching element at the end time of ΔT;
The second semiconductor switching element is turned on at the start time of ΔT calculated by the arithmetic circuit, and the second semiconductor switching device is turned on at a time between the lapse of the ΔT + T and the end time of the charging signal. A circuit for generating a second control signal for controlling off of the element;
The capacitor charging device according to claim 1, further comprising: