JP6565368B2 - Circuit device and electronic device - Google Patents

Description

  The present invention relates to a circuit device, an electronic device, and the like.

  Conventionally, a circuit device for a drive circuit using an inductor such as a switching regulator is known. This circuit device is provided with a driving transistor (switching transistor) for flowing a driving current through the inductor. For example, a rectifying diode is provided at the output terminal of the drive current of the drive transistor. Specifically, a diode is mounted on a circuit board together with a circuit device (IC) as an external component.

  In the ON period in which the drive transistor is turned on, the drive current from the drive transistor flows to the inductor, and electric energy is converted into magnetic energy and stored in the inductor. On the other hand, in the off period when the driving transistor is turned off, the magnetic energy stored in the inductor is discharged as electric energy through the diode.

  As a conventional technique of such a circuit device for a switching regulator, for example, there is a technique disclosed in Patent Document 1. Further, as a conventional technique related to a protection circuit when an overcurrent flows through a load, a wiring short circuit, or a connector connection failure, there are techniques disclosed in Patent Documents 2 and 3, for example.

JP 2013-84992 A JP 2010-45567 A JP 2009-231969 A

  In the circuit device in which the diode is provided at the output terminal of the drive transistor as described above, for example, when there is a mounting failure of the diode, a large negative voltage is applied to the output terminal by the inductor that is an inductive load, and the circuit device is It has been found that a situation such as deterioration or destruction occurs. For example, if there is a mounting failure in a diode as an external component, the current discharge path from the inductor is interrupted, so that the current flows inside the circuit device, and a negative voltage surge occurs at the output terminal. . There is a possibility that a situation such as deterioration or destruction of the circuit element of the circuit device may occur due to the negative voltage surge.

  According to some aspects of the present invention, there is provided a circuit device, an electronic device, or the like that can effectively suppress deterioration or destruction of circuit elements of a circuit device even when a terminal voltage abnormality occurs at the output terminal of the drive transistor. Can be provided.

  One aspect of the present invention is a drive transistor that outputs a drive current for an inductor to an output terminal, a control circuit that controls an on / off operation of the drive transistor, a detection circuit that detects abnormality of a terminal voltage of the output terminal, Including a surge absorption circuit connected to an output terminal, the control circuit, when a terminal voltage abnormality is detected by the detection circuit in the off period of the drive transistor, to turn on the operation of the surge absorption circuit, The present invention relates to a circuit device that causes the surge absorbing circuit to absorb an overvoltage surge generated at an output terminal.

  According to one aspect of the present invention, the on / off operation of the drive transistor that outputs the drive current of the inductor to the output terminal is controlled by the control circuit, and the terminal voltage abnormality of the output terminal is detected by the detection circuit. When a terminal voltage abnormality is detected during the off period of the drive transistor, the operation of the surge absorbing circuit is turned on, and an overvoltage surge generated at the output terminal is absorbed by the surge absorbing circuit. For example, when the terminal voltage of the output terminal is in an abnormal state during the off period of the driving transistor, there is a possibility that the circuit element of the circuit device is deteriorated or destroyed. In this regard, according to one aspect of the present invention, when a terminal voltage abnormality of the output terminal is detected, the operation of the surge absorption circuit is turned on, and the amplitude of the overvoltage surge can be reduced. Therefore, it is possible to provide a circuit device or the like that can effectively suppress deterioration or destruction of circuit elements of the circuit device even when a terminal voltage abnormality occurs at the output terminal of the drive transistor.

  In one aspect of the present invention, the surge absorption circuit is a discharge circuit that causes a discharge current to flow from a low-potential-side power supply side to the output terminal side when the terminal voltage abnormality is detected during the off period of the drive transistor. May be included.

  In this way, when a terminal voltage abnormality is detected, a discharge operation is performed in which a discharge current flows from the low potential side power supply side to the output terminal side, and the amplitude of the overvoltage surge can be reduced. become.

  In the aspect of the invention, the discharge circuit may include a bipolar transistor that causes the discharge current to flow from the low-potential-side power supply side to the output terminal side.

  In this way, for example, using a bipolar transistor that turns on when a terminal voltage abnormality is detected, it is possible to realize a discharge operation in which a discharge current flows at a high speed from the low-potential side power supply side to the output terminal side. become.

  In one embodiment of the present invention, the control circuit detects the terminal voltage abnormality in which the terminal voltage is continuously lower than a determination voltage in a determination period set within the off period of the drive transistor. In addition, the operation of the surge absorbing circuit may be turned on.

  In this way, when the terminal voltage is continuously lower than the determination voltage in the determination period set within the off period, the operation of the surge absorption circuit is turned on and the overvoltage surge is absorbed. It becomes like this. Therefore, by comparing the terminal voltage with the determination voltage over the entire off period, the determination period should be limited to a given period within the off period even if the terminal voltage abnormality cannot be determined appropriately. It becomes possible to cope with this. Therefore, it is possible to determine a more appropriate and accurate terminal voltage abnormality.

  In one embodiment of the present invention, a determination timing register that stores timing information of the determination period may be included.

  In this way, it is possible to set, using the determination timing register, at which timing within the OFF period the determination period is set and the terminal voltage is compared with the determination voltage. Accordingly, it is possible to set the appropriate determination period according to the individual difference of the circuit device and realize the determination of the terminal voltage abnormality, so that it is possible to suppress the variation in the determination result due to the individual difference.

  In one aspect of the present invention, a determination voltage setting register that stores setting information of a voltage level of the determination voltage may be included.

  In this way, it is possible to use the determination voltage setting register to determine which voltage level the determination voltage is used to compare with the terminal voltage. Accordingly, it is possible to set the appropriate determination voltage according to the individual differences of the circuit devices and realize the determination of the terminal voltage abnormality, so that it is possible to suppress variations in the determination result due to the individual differences.

  In the aspect of the invention, the control circuit may detect the terminal voltage abnormality in the m-th off period to the m + n (m and n are integers of 1 or more) of the driving transistor. The operation of the surge absorbing circuit may be turned on.

  In this way, the operation of the surge absorption circuit is turned on when, for example, terminal voltage abnormality is detected continuously over the m-th to m + n off periods. Therefore, for example, it is possible to effectively suppress a situation in which an erroneous detection of a terminal voltage abnormality occurs due to noise or the like and the operation of the surge absorbing circuit is turned on.

  Moreover, in one aspect of the present invention, a detection number register that stores n + 1 information corresponding to the number of detection times of the terminal voltage abnormality may be included.

  In this way, it is possible to determine the terminal voltage abnormality by setting an appropriate number of detections according to individual differences of circuit devices.

  In the aspect of the invention, the output terminal may be a terminal to which a cathode of a diode through which a current flowing through the inductor flows during the off period of the driving transistor is connected.

  In this way, even when a terminal voltage abnormality occurs due to, for example, a connection failure of the diode, the current path through the diode is interrupted, the terminal voltage abnormality is detected. The operation of the surge absorption circuit can be turned on.

  In one embodiment of the present invention, the semiconductor device further includes a protective element having a protective diode having a cathode connected to the output terminal, the diode being a Schottky barrier diode, and the forward voltage of the protective diode is the Schottky barrier. It may be higher than the forward voltage of the diode.

  In this way, even when a current flows in the protective diode of the protective element instead of the Schottky barrier diode that has a poor connection or the like during the off period of the driving transistor, the Schottky barrier diode and the protective diode It is possible to detect a terminal voltage abnormality by effectively utilizing the difference in forward voltage.

  In one embodiment of the present invention, the detection circuit uses the current that flows from the high-potential-side power supply to the output terminal when the terminal voltage becomes a negative voltage during the off period of the driving transistor, and the terminal voltage abnormality is detected. May be detected.

  In this way, when the terminal voltage becomes a negative voltage, the current flowing from the high potential side power source to the output terminal can be effectively used, and the terminal voltage abnormality can be detected by the detection circuit.

  In one aspect of the present invention, abnormality detection information for notifying that the terminal voltage abnormality is detected may be output.

  In this way, it is possible to notify the external device that the terminal voltage abnormality has been detected using the abnormality detection information. Therefore, the external device can use this abnormality detection information to confirm that the operation of the surge absorbing circuit is turned on due to the terminal voltage abnormality.

  In the aspect of the invention, the control circuit may stop the on / off operation of the driving transistor when the terminal voltage abnormality is detected in the off period of the driving transistor.

  In this way, when the terminal voltage abnormality is detected, the on / off operation of the drive transistor is stopped, and the subsequent occurrence of the terminal voltage abnormality can be suppressed. Therefore, it is possible to provide a circuit device or the like that can effectively suppress deterioration or destruction of circuit elements of the circuit device even when a terminal voltage abnormality occurs at the output terminal of the drive transistor.

  According to another aspect of the present invention, there is provided an electronic apparatus including any one of the circuit devices described above.

1 is a configuration example of a circuit device according to the present embodiment. The structural example of the switching regulator to which the circuit apparatus of this embodiment was applied. Explanatory drawing about terminal voltage abnormality. The signal waveform diagram explaining operation | movement of this embodiment. The signal waveform diagram explaining operation | movement of this embodiment. The 1st structural example of a surge absorption circuit. The 2nd structural example of a surge absorption circuit. 3 is a detailed configuration example of a circuit device according to the present embodiment. 3 shows a detailed configuration example of a determination circuit. The signal waveform diagram explaining operation | movement of this embodiment. The signal waveform diagram explaining operation | movement of this embodiment. 1 is a first configuration example of a detection circuit. The 2nd structural example of a detection circuit. Explanatory drawing of the test | inspection mode performed after power activation. Explanatory drawing of the output method of abnormality detection information. Explanatory drawing of the output method of abnormality detection information. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Circuit Device FIG. 1 shows a basic configuration example of a circuit device according to this embodiment. The circuit device of FIG. 1 includes a drive transistor SWT, a control circuit 10, a detection circuit 30, and a surge absorption circuit 40. The circuit device can include a protection element PR, an output terminal TSW, and a power supply terminal TVB. The circuit device according to the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The drive transistor SWT (switching transistor) outputs a drive current for the inductor L to the output terminal TSW. For example, the output voltage VSW (drive voltage) is output to the output terminal TSW to drive the inductor L. The drive transistor SWT can be realized by, for example, a P-type transistor (MOS transistor), and a control signal CT from the control circuit 10 is input to the gate thereof. The power supply voltage VB on the high potential side is supplied to the source of the drive transistor SWT via the power supply terminal TVB. The drain of the drive transistor SWT is connected to the node NSW of the output terminal TSW.

  The control circuit 10 performs various controls and various processes of the circuit device. Specifically, the control circuit 10 controls the on / off operation of the drive transistor SWT. For example, the control circuit 10 controls the drive transistor SWT to repeat the on period and the off period. In other words, an on / off control signal CT is output to the gate of the drive transistor SWT to control to turn on or off the drive transistor SWT. The control circuit 10 can be realized by a logic circuit generated by an automatic placement and routing method such as a gate array or various processors such as a microcomputer.

  The detection circuit 30 performs various detection processes. For example, the terminal voltage VSW is detected. Specifically, the detection circuit 30 detects an abnormality in the terminal voltage VSW of the output terminal TSW (output voltage of the drive transistor SWT). For example, it is detected whether or not the terminal voltage VSW is a negative voltage having an abnormal voltage value (a negative voltage whose absolute value is equal to or greater than a predetermined value). For example, the detection circuit 30 detects whether or not the terminal voltage VSW is lower than a determination voltage (for example, about −0.5 V) described later. When the control circuit 10 detects that the terminal voltage VSW is lower than the determination voltage in the determination period within the off period of the drive transistor SWT (when it is detected that the terminal voltage VSW has continuously decreased), Judge that a terminal voltage abnormality occurred. As will be described later, the detection circuit 30 detects a terminal voltage abnormality using a current flowing from the high-potential-side power supply VB to the output terminal TSW side when the terminal voltage VSW becomes a negative voltage during the off period of the drive transistor SWT. Detected. In the present embodiment, VSW is appropriately called an output voltage or a terminal voltage.

  The surge absorbing circuit 40 is connected to the output terminal TSW, for example. The surge absorbing circuit 40 is a circuit that absorbs a surge (instantaneous potential change) of an overvoltage (voltage exceeding the rating of the circuit device) generated at the output terminal TSW (discharges a charge caused by the surge). For example, the surge absorption circuit 40 includes a discharge circuit 42. The discharge circuit 42 is a circuit that causes a discharge current (charge) to flow from the low potential side power supply (GND) side to the output terminal TSW side. Specifically, the discharge circuit 42 causes a discharge current to flow from the low potential side power supply side to the output terminal TSW side when a terminal voltage abnormality is detected during the off period of the drive transistor SWT.

  The protection element PR (internal protection element) is an element for protecting the circuit device (electrostatic protection, overcurrent absorption). In FIG. 1, for example, an N-type transistor (MOS transistor) in which the gate and the source are connected and set to the off state is used as the protection element PR. The protection diode DI is a body diode (parasitic diode) of this N-type transistor. Thus, the protection element PR has the protection diode DI whose cathode is connected to the output terminal TSW. The anode of the diode DI is connected to, for example, a node of a low potential side power supply (GND). The direction from the node of the low-potential side power source to the node NSW of the output terminal TSW is the forward direction of the diode DI. The protection element PR is not limited to the element having the configuration shown in FIG. 1, and various types of protection elements in which a protection diode DI is formed between the output terminal TSW and the low-potential side power source can be employed.

  The power supply terminal TVB and the output terminal TSW are external connection terminals (pads, pins) of the circuit device. The terminals of these TVB and TSW are connected to the wiring on the circuit board on which the circuit device is mounted. Then, it is electrically connected to an external device of the circuit device through the wiring.

  The output terminal TSW is a terminal to which the cathode of the diode SB is connected. That is, the diode SB as an external component is mounted on the circuit board together with the circuit device, and the cathode of the diode SB is connected to the output terminal TSW via the wiring on the circuit board. The anode of the diode SB is connected to the node of the low potential side power source, for example. The direction from the node of the low-potential side power supply to the node NSW of the output terminal TSW is the forward direction of the diode SB.

  In the diode SB, a current flowing through the inductor L flows during the off period of the drive transistor SWT. For example, during the ON period of the drive transistor SWT, the drive current from the drive transistor SWT is supplied to the inductor L. On the other hand, during the off period of the drive transistor SWT, the current stored in the inductor L (current stored as magnetic energy) flows through the diode SB. That is, magnetic energy is accumulated in the inductor L when a drive current from the drive transistor SWT flows during the ON period. A current based on this magnetic energy flows from the low potential side power supply (GND) to the inductor L via the diode SB in the off period.

  The diode SB is, for example, a Schottky barrier diode (Schottky connection element). A Schottky barrier diode is a diode that uses a Schottky barrier generated by the connection between a metal and a semiconductor. Since the Schottky barrier diode is operated by majority carriers, the forward voltage (voltage drop in the forward direction) is low and the switching speed (electron mobility) is high as compared with the PN junction diode. As described above, when the diode SB having a low forward voltage is used, there is an advantage that, for example, power loss when performing the switching regulation operation can be minimized.

  In this embodiment, the forward voltage of the protection diode DI is higher than the forward voltage of the diode SB of the Schottky barrier. For example, when the forward voltage of the diode DI of the PN junction is about 0.6V, the forward voltage of the Schottky barrier diode SB is about 0.4V (about 0.2V to 0.5V), for example. become.

  FIG. 2 is a diagram illustrating a configuration example of a switching regulator to which the circuit device of this embodiment is applied. Note that the switching regulator to which the circuit device of the present embodiment is applied is not limited to the configuration in FIG. 2, and the present embodiment can be applied to switching regulators having various configurations different from those in FIG. 2. The circuit to which the circuit device of this embodiment is applied is not limited to a switching regulator, and this embodiment can be applied to various circuits such as a power supply circuit and a drive circuit using an inductor.

  In FIG. 2, a switching regulator is configured by the circuit device of the present embodiment, and an inductor L (coil), a capacitor C (capacitor), a diode SB, and resistors RF1 and RF2 provided as external components. The switching regulator performs a switching regulation operation for generating the power supply voltage VOUT based on a PWM signal (Pulse Width Modulation). Specifically, the power supply voltage VB is supplied to the circuit device via the power supply terminal TVB, and the power supply voltage VOUT obtained by stepping down the power supply voltage VB by the switching regulation operation in which the drive transistor SWT (switching transistor) is turned on / off. Is generated at the node NOUT. The power supply voltage VOUT is supplied to an external load 90 (external device or the like).

  For example, the drive transistor SWT is turned on / off by a PWM signal based on a clock signal. When the driving transistor SWT is turned on / off, the intermittent DC voltage output signal QSW (VSW) is output to the outside via the output terminal TSW of the circuit device. This output signal QSW is a signal that becomes the power supply voltage VB during the ON period of the drive transistor SWT. The output signal QSW is input to an LC circuit including an inductor L and a capacitor C, so that a power supply voltage VOUT obtained by stepping down the power supply voltage VB is generated at the node NOUT.

  For example, in the ON period of the drive transistor SWT, the power supply voltage VB is output as the output signal QSW, and electric energy is converted into magnetic energy and stored in the inductor L. On the other hand, in the off period of the drive transistor SWT, the node NSW of the output signal QSW is in a high impedance state, and the magnetic energy stored in the inductor L is discharged as electric energy through the diode SB. The magnitude of the power supply voltage VOUT is set by the duty ratio that is the time ratio between the on period and the off period.

  Specifically, the voltage dividing circuit 92 configured by the resistors RF1 and RF2 generates a feedback voltage VFB obtained by dividing the power supply voltage VOUT. The resistors RF1 and RF2 are connected in series between the node NOUT of the power supply voltage VOUT and the node of the low potential side power supply (GND). The voltage divided by the resistors RF1 and RF2 (the voltage at the node NFB) is input to the control circuit 10 via the terminal TFB of the circuit device as the feedback voltage VFB. In the control circuit 10, for example, a comparison process between the reference voltage and the feedback voltage VFB is performed, and a control signal CT that is a PWM signal is generated based on the result of the comparison process. Then, the drive transistor SWT is turned on / off based on the control signal CT, whereby a constant power supply voltage VOUT is generated at the node NOUT.

  As described above, in the present embodiment, the diode SB is mounted on the circuit board (module). However, when the diode SB has a connection failure due to a mounting failure such as a solder failure or disconnection (electrically disconnected). ), A large negative voltage surge (instantaneous potential change exceeding the rating of the circuit device) may be applied to the output terminal TSW by the inductor L which is an inductive load. Such a negative voltage surge is not assumed in the rated specifications of the circuit device, and thus may cause deterioration or destruction of the circuit device, a decrease in reliability, or the like.

  That is, when the diode SB is opened due to poor connection or the like, the amplitude on the negative side increases during the off period of the drive transistor SWT. As a result, the drain voltage of the drive transistor SWT is greatly reduced to the negative voltage side. For example, in an on period or the like, an excessive voltage is applied between the source and drain of the drive transistor SWT, resulting in deterioration or destruction.

  Here, as shown in FIG. 1, the circuit device is provided with a protection element PR, and the cathode of a diode DI (body diode, parasitic diode) of the protection element PR is connected to the output terminal TSW. Therefore, even if a large negative voltage surge is applied to the output terminal TSW during the OFF period of the drive transistor SWT due to a poor connection of the diode SB, the overcurrent based on this negative voltage surge is absorbed by the diode DI of the protection element PR. It is also possible to do. That is, when a current flows from GND (VSS) to the output terminal TSW via the diode DI, an overcurrent based on a negative voltage surge is absorbed to suppress deterioration and destruction of the circuit device.

  However, the external Schottky barrier diode SB is a diode whose forward voltage is small and a large switching current is expected to flow, for example, in order to reduce loss during switching regulation operation. . On the other hand, the diode DI of the protection element PR has a large forward voltage, and the value of the current assumed to flow is smaller than that of the diode SB. Therefore, the diode DI alone cannot absorb a large negative voltage surge applied to the output terminal TSW.

  For example, FIG. 3 shows a waveform of the terminal voltage VSW of the output terminal TSW. A waveform WVS (broken line) is a waveform when the diode SB is normally connected, and a waveform WVP (solid line) is a waveform when the diode SB is disconnected due to poor connection or the like.

  When the diode SB is normally connected, the terminal voltage VSW rises to the power supply voltage VB in the on period TON in which the drive transistor SWT is turned on. When the on-period TON is switched to an off-period TOF in which the drive transistor SWT is turned off, the terminal voltage VSW decreases to the voltage VFS, which is a negative voltage, due to the current flowing through the inductor L (inductive load). This voltage VFS is a voltage corresponding to the forward voltage of the diode SB of the Schottky barrier. Thereafter, the terminal voltage VSW gradually increases with the passage of time, resulting in a waveform WVS as shown in FIG.

  On the other hand, when the diode SB is poorly connected during mounting or is disconnected in the market in an incompletely connected mounting state, the current flowing through the inductor L during the off period of the driving transistor SWT is: Only the protection element PR via the diode DI is used.

  The forward voltage of the diode DI of the protection element PR is larger than the forward voltage of the diode SB of the Schottky barrier. For this reason, in the waveform WVP, when the driving transistor SWT is switched from the ON period TON to the OFF period TOF, the terminal voltage VSW decreases to the voltage VFP corresponding to the forward voltage of the diode DI. This voltage VFP is a voltage lower in the negative direction than voltage VFS in waveform WVS. Thereafter, the terminal voltage VSW gradually increases as time passes, so that the waveform WVP is obtained when the connection of the diode SB is poor.

  As apparent from FIG. 3, when the connection of the diode SB is poor, the terminal voltage VSW greatly fluctuates in the negative voltage direction during the off period TOF, and a large negative voltage surge is applied to the output terminal TSW. When this negative voltage surge is applied continuously, for example, a plurality of times, a phenomenon occurs in which the drive transistor SWT is destroyed due to deterioration over time.

  For example, when viewed from a completed electronic device in which the circuit device is incorporated, it is a serious problem that the circuit device (IC) is destroyed due to poor connection of the diode SB. For this reason, even if the inspection after the mounting is enhanced so that the connection failure of the diode SB does not occur, if the circuit device may be destroyed by the inspection or the like, it takes a lot of trouble to repair, and This will increase costs. In addition, when the connection failure of the diode SB becomes apparent after passing the shipping inspection and entering the market, it takes much more man-hours and costs to cope with it. In addition, although there is a connection failure in the diode SB, even when the connection is not completely disconnected, when a negative voltage surge is repeatedly applied, the drive transistor SWT and the like of the circuit device gradually break down, Reliability is greatly reduced.

  Therefore, in the present embodiment, the detection circuit 30 in FIG. 1 detects an abnormality in the terminal voltage VSW of the output terminal TSW. Then, the control circuit 10 turns on the operation of the surge absorbing circuit 40 when a terminal voltage abnormality is detected in the off period TOF of the drive transistor SWT. Specifically, when a terminal voltage abnormality is detected, the control circuit 10 activates the control signal CS instructing the surge absorption operation (eg, H level) to turn on the operation of the surge absorption circuit 40. Thereby, the surge absorbing circuit 40 absorbs the surge of the overvoltage generated at the output terminal TSW. For example, after that (in the off period thereafter), the operation of the surge absorbing circuit 40 is always turned on, for example, so that a negative voltage surge is not applied to the output terminal TSW. Note that the operation of the surge absorbing circuit 40 may be turned on only during the target off period or a plurality of off periods including the off period.

  Specifically, as shown in the waveform WVP in FIG. 3, when a terminal voltage abnormality in which an excessive negative voltage surge is applied to the output terminal TSW is detected in the off period TOF, the operation of the surge absorbing circuit 40 is changed. Turn on (enable). And the surge of the negative voltage is absorbed by the discharge operation by the surge absorption circuit 40 whose operation is turned on. For example, the discharge circuit 42 of the absorption circuit 40 performs a discharge operation in which a discharge current (charge) is passed from the low potential side power supply (GND) side to the output terminal TSW side, thereby reducing the absolute value of the voltage level of the negative voltage surge. .

  By operating the surge absorbing circuit 40 in this way, the absolute value of the voltage level of the negative voltage surge (overvoltage in a broad sense) applied to the output terminal TSW is reduced. Thereafter, the operation of the surge absorbing circuit 40 is always turned on, for example, so that a negative amplitude surge with a large amplitude is not applied to the drain of the driving transistor SWT. In this way, it is possible to significantly reduce the adverse effects such as the stress that the negative voltage surge exerts on the drive transistor SWT. As a result, deterioration and destruction of the drive transistor SWT and the like due to a negative voltage surge can be suppressed, and the circuit device can be repaired before destruction and the reliability can be greatly improved.

  Further, in the present embodiment, it is possible to always detect such terminal voltage abnormality during operation of the circuit device. Therefore, for example, as the initial failure, there was no connection failure of the diode SB, but even when the connection failure of the diode SB becomes apparent as the product usage period elapses, the negative voltage due to the connection failure is reduced. The surge absorbing circuit 40 can be operated by detecting a surge. Therefore, it is possible to suppress deterioration and destruction of the circuit device due to changes over time. In the present embodiment, an application example of the method of the present embodiment in the case where the terminal voltage abnormality is caused by a negative voltage surge will be mainly described, but the method of the present embodiment is not limited to this. For example, the method of the present embodiment can also be applied to detection and determination of terminal voltage abnormality due to a positive voltage surge.

  FIG. 4 is a signal waveform diagram illustrating the operation of the circuit device of this embodiment. As shown in FIG. 4, when the control signal CT input to the gate of the drive transistor SWT becomes L level, the P-type drive transistor SWT is turned on. On the other hand, when the control signal CT becomes H level, the drive transistor SWT is turned off. Then, by repeating the ON period TON and the OFF period TOF of the drive transistor SWT, the switching regulator operation of the switching regulator is realized. Specifically, the voltage value of the power supply voltage VOUT in FIG. 3 is set by the duty ratio between the on period TON and the off period TOF. For example, by performing PWM control with a duty ratio of 1/3, it is possible to generate a power supply voltage VOUT (eg, 1.1 V) obtained by reducing the power supply voltage VB (eg, 3.3 V) to 1/3.

  Then, terminal voltage abnormality is detected at E1 in FIG. That is, it is detected that a large negative voltage surge as shown by the waveform WVP in FIG. 3 is applied to the output terminal TSW due to poor connection of the diode SB or the like. For example, as described later, when it is detected whether the terminal voltage VSW is lower than the determination voltage, it is determined that the terminal voltage abnormality has occurred. Specifically, when it is detected that the terminal voltage VSW is continuously lower than the determination voltage in the determination period set within the OFF period TOF of the drive transistor SWT, the terminal voltage abnormality has occurred. Determined.

  When such a terminal voltage abnormality is detected, the detection result is latched by the latch signal LT, and the terminal voltage abnormality detection signal QD becomes H level (active) as indicated by E2. When the terminal voltage abnormality occurs in this way, the operation of the surge absorbing circuit 40 is turned on as indicated by E3. Then, the discharge circuit 42 of the surge absorption circuit 40 whose operation is turned on absorbs a negative voltage surge by performing a discharge operation of discharging electric charge from the low potential side power supply (GND) to the output terminal TSW side, Minimize the amplitude of the surge.

  For example, also in the next off period and the off period thereafter, the operation of the surge absorbing circuit 40 is turned on to perform the operation of absorbing the negative voltage surge. Note that when the operation of the surge absorbing circuit 40 is turned on, the waveform of the terminal voltage VSW also actually changes, but this waveform change is omitted in E1 of FIG.

  FIG. 5 is a signal waveform diagram for explaining the operation of the modification of the circuit device of this embodiment. In FIG. 5, the operation of the surge absorbing circuit 40 is not turned on only when the terminal voltage abnormality is detected once, but the method of turning on the operation of the surge absorbing circuit 40 is adopted when it is detected a plurality of times. ing.

  For example, in FIG. 5, the terminal voltage abnormality is detected in the first off period as shown by A1, the detection result is latched by the latch signal LT, and the terminal voltage abnormality detection signal QD becomes H level as shown by A2. It has become. After that, as indicated by A3, the terminal voltage abnormality is detected even in the next second off period, and the detection result is latched by the latch signal LP. Thus, when the terminal voltage abnormality detection signal QD becomes H level as indicated by A4, the operation of the surge absorbing circuit 40 is turned on as indicated by A5. That is, when the terminal voltage abnormality is detected twice as in A2 and A4, the operation of the surge absorbing circuit 40 is turned on. That is, when the terminal voltage abnormality is detected a plurality of times, the surge absorbing circuit 40 shifts from the operation-off state to the operation-on state. For example, also in the next off period and the off period thereafter, the operation of the surge absorbing circuit 40 is turned on to perform the operation of absorbing the negative voltage surge. Note that the waveform change due to surge absorption is also omitted in A3 of FIG.

  As described above, according to the present embodiment, even when a negative voltage surge exceeding the rating is applied to the output terminal TSW in the OFF period TOF of the drive transistor SWT, the terminal voltage abnormality due to the negative voltage surge is applied. Is detected by the detection circuit 30, and the surge absorption circuit 40 whose operation is turned on absorbs the negative voltage surge and reduces the amplitude of the surge. Therefore, when a large negative voltage surge is applied to the output terminal TSW due to, for example, the diode SB being disconnected due to mounting failure, this can be detected and the surge absorbing circuit 40 can absorb the surge. Accordingly, since the stress applied to the drive transistor SWT can be reduced, deterioration and destruction of the circuit device can be suppressed, and reliability and the like can be improved.

  In FIG. 5, when a terminal voltage abnormality is detected in the first off period to the second off period (mth to m + n off periods in a broad sense, where m and n are integers of 1 or more) of the drive transistor SWT. In addition, the operation of the surge absorbing circuit 40 is turned on. That is, when the number of detections of terminal voltage abnormality is a plurality of times (n + 1), the surge absorbing circuit 40 is operated. In this way, even when a terminal voltage abnormality is erroneously detected due to noise or the like superimposed on the terminal voltage VSW, this can be dealt with. That is, it is possible to prevent a situation in which the surge absorbing circuit 40 is unnecessarily operated due to erroneous detection of an abnormal terminal voltage, and a stable operation of the circuit device can be realized.

  In the present embodiment, the control circuit 10 may stop the on / off operation of the drive transistor SWT when a terminal voltage abnormality is detected in the off period TOF of the drive transistor SWT. For example, when the terminal voltage abnormality of the output terminal TSW is detected in the OFF period TOF of the drive transistor SWT, the control circuit 10 stops the switching of the drive transistor SWT from the OFF period TOF to the ON period TON. For example, the drive transistor SWT is always turned off to prevent the drive transistor SWT from being turned on / off.

  For example, in the switching regulator of FIG. 2, a switching regulator operation in which a constant power supply voltage VOUT is generated is realized by turning on and off the driving transistor SWT. However, when a terminal voltage abnormality is detected, This on / off operation is stopped. If the on / off operation is stopped in this manner, the drive transistor SWT is not switched from on to off thereafter, and the negative voltage generated by switching from the on period TON to the off period TOF as shown in FIG. Surge will not occur. As a result, deterioration and destruction of the drive transistor SWT and the like due to a negative voltage surge can be suppressed, and the reliability of the circuit device can be improved.

  Taking FIG. 5 as an example, when a terminal voltage abnormality is detected twice as in A2 and A4, the on / off operation of the drive transistor SWT is stopped as shown in A6. That is, when the terminal voltage abnormality is detected a plurality of times, the operation of the drive transistor SWT shifts from the operation enable state to the operation stop state.

  In this case, when a large negative voltage surge is applied to the output terminal TSW due to the disconnection of the diode SB due to mounting failure or the like, this can be detected and the operation of the drive transistor SWT can be stopped. Deterioration and destruction of the apparatus can be suppressed, and reliability and the like can be improved.

  For example, the surge absorption operation by the surge absorption circuit 40 can suppress deterioration or destruction of the circuit device, but if the on / off operation of the drive transistor SWT is repeated after the terminal voltage abnormality is detected, wasteful power consumption is generated. There is a problem that it occurs. Further, there is a problem that the stress applied to the drive transistor SWT may not be completely removed only by the surge absorbing operation by the surge absorbing circuit 40. In this regard, the above problem can be solved by adopting a method of stopping the on / off operation of the drive transistor SWT when a terminal voltage abnormality is detected.

  In FIG. 5, when a terminal voltage abnormality is detected in the first off period to the second off period (mth to m + n off period) of the drive transistor SWT, the on / off operation of the drive transistor SWT is stopped. Yes. That is, the ON / OFF operation is stopped when the number of detections of the terminal voltage abnormality is a plurality of times (n + 1). In this way, even when a terminal voltage abnormality is erroneously detected due to noise or the like superimposed on the terminal voltage VSW, this can be dealt with. That is, it is possible to prevent a situation in which the operation of the drive transistor SWT is stopped due to erroneous detection of the terminal voltage abnormality, and a stable operation of the circuit device can be realized.

  In FIG. 5, when a terminal voltage abnormality is detected, as shown in A5 and A6, the surge absorption operation on control for turning on the operation of the surge absorption circuit 50 and the on / off operation for stopping the on / off operation of the drive transistor SWT are performed. Although both the operation stop controls are performed, the present embodiment is not limited to this. For example, when a terminal voltage abnormality is detected, only one of surge absorption operation on control and on / off operation stop control may be performed. Alternatively, the surge absorption operation on control is performed only when a terminal voltage abnormality is detected once as shown by A2 in FIG. 5, and the on / off operation stop control is performed by a plurality of terminal voltage abnormalities as shown by A4. You may make it carry out on condition that it was detected twice.

  6 and 7 show a detailed configuration example of the surge absorbing circuit 40. FIG. The surge absorption circuit 40 includes a discharge circuit 42 that causes a discharge current to flow from the low potential side power supply (GND) side to the output terminal TSW side when a terminal voltage abnormality is detected. In FIG. 6, the discharge circuit 42 includes a bipolar transistor BPD that causes a discharge current to flow from the low-potential side power supply side to the output terminal TSW side.

  The bipolar transistor BPD is, for example, an NPN transistor, and has an emitter connected to the node NSW of the output terminal TSW and a collector connected to a node of the low potential side power supply (GND). The base is connected to the drain node of the transistor TR for operation ON control. The transistor TR is, for example, an N-type transistor (MOS transistor), the control signal CS from the control circuit 10 is input to the gate, and the source is connected to the node of the low potential side power supply. The resistor RU provided between the base of the bipolar transistor BPD and the node NSW is a pull-up resistor for preventing the base potential from being in a floating state when the transistor TR is turned off.

  When the terminal voltage abnormality is detected in the off period of the drive transistor SWT, the control circuit 10 sets the control signal CS to H level (active). As a result, the N-type transistor TR is turned on and the bipolar transistor BPD is turned on, whereby the discharging operation of the discharging circuit 42 constituted by the bipolar transistor BPD is performed. By this discharge operation, a discharge current flows from the collector (GND) of the bipolar transistor BPD to the emitter (TSW), thereby realizing an operation of absorbing a negative voltage surge. That is, the amplitude of the negative voltage surge (WVP) in FIG. 3 is reduced, and the stress applied to the drive transistor SWT can be reduced.

  In FIG. 7, the discharge circuit 42 includes a plurality of bipolar transistors BPD1, BPD2, and BPD3 connected in a Darlington connection. A resistor RU3 provided between the base of the bipolar transistor BPD3 and the node NSW is a pull-up resistor for preventing the base potential from being in a floating state when the transistor TR is turned off. Also in FIG. 7, when the terminal voltage abnormality is detected and the control signal CS from the control circuit 10 becomes H level, the transistor TR is turned on, so that the Darlington-connected bipolar transistors BPD1, BPD2, and BPD3 are turned on. become. As a result, the discharge current caused by the discharge operation of the discharge circuit 42 flows, so that a negative voltage surge absorbing operation is realized.

  The configuration of the surge absorbing circuit 40 is not limited to that shown in FIGS. 6 and 7, and various modifications can be made. For example, as the surge absorbing circuit 40, circuits having various configurations for performing a discharging operation for absorbing an overvoltage surge when a terminal voltage abnormality is detected can be employed. For example, the discharge operation may be realized using a circuit element other than a bipolar transistor.

2. Detailed Configuration Example FIG. 8 shows a detailed configuration example of the circuit device of this embodiment. The circuit device according to the present embodiment is not limited to the configuration shown in FIG. 8, and various modifications such as omitting some of the components or adding other components are possible.

  In the configuration example of FIG. 8, in addition to the control circuit 10, the detection circuit 30, and the drive transistor SWT, a determination timing register 50, a detection number register 52, and a determination voltage setting register 54 are further provided. These registers can be realized by a storage device such as a flip-flop circuit or a RAM.

  In FIG. 8, the control circuit 10 has a terminal in which the terminal voltage VSW is continuously lower than the determination voltage (VT in FIG. 11) in the determination period (TDT in FIG. 11 described later) set in the off period of the drive transistor SWT. When a voltage abnormality is detected, the surge absorbing circuit 40 is turned on. Alternatively, the on / off operation of the drive transistor SWT is stopped. In this case, the determination timing register 50 stores timing information of the determination period. The determination period timing information is setting information such as the determination period start timing (t1 in FIG. 11) and the determination period length (t2).

  The determination voltage setting register 54 stores setting information of the voltage level of the determination voltage (VT). Thereby, the determination voltage can be variably set. The detection circuit 30 performs a terminal voltage abnormality detection process using the determination voltage set by the setting information in the determination voltage setting register 54. That is, the detection circuit 30 can determine whether or not the terminal voltage VSW is lower than the determination voltage (VT) set by the determination voltage setting register 54.

  The detection number register 52 stores information on the number of detections of terminal voltage abnormality. That is, in the present embodiment, as described with reference to FIG. 5, the operation of the surge absorbing circuit 40 is turned on when the terminal voltage abnormality is continuously detected a plurality of times. That is, when a terminal voltage abnormality is detected in the m-th to m + n off periods (first to second off periods in FIG. 5) of the driving transistor, the operation of the surge absorbing circuit 40 is turned on. Alternatively, the on / off operation of the drive transistor SWT is stopped. In this case, the detection number register 52 stores n + 1 information corresponding to the number of terminal voltage abnormality detections.

  The control circuit 10 includes a switch control circuit 12, an operation control circuit 14, and a determination circuit 16. The switch control circuit 12 performs switch control for turning on and off the drive transistor SWT. That is, the switch control circuit 12 outputs the control signal CT described with reference to FIGS. 4 and 5 to the gate of the drive transistor SWT and performs control to turn on or off the drive transistor SWT. In the case of the application example to the switching regulator described in FIG. 2, the switch control circuit 12 generates a control signal CT of the PWM signal based on the feedback voltage VFB and outputs it to the gate of the drive transistor SWT.

  The operation control circuit 14 controls the operation of the switch control circuit 12, the determination circuit 16, the detection circuit 30, and the like. For example, the operation of each circuit is controlled based on the determination result from the determination circuit 16 or the like.

  The determination circuit 16 performs a determination process for detecting abnormality in the terminal voltage of the output terminal TSW. For example, the determination circuit 16 performs a determination process for detecting a terminal voltage abnormality based on a detection result signal from the detection circuit 30, timing information from the determination timing register 50, detection number information from the detection number register 52, and the like. .

  FIG. 9 shows a detailed configuration example of the determination circuit 16. As shown in FIG. 9, the determination circuit 16 includes a detection output duration determination circuit 18 and a detection count circuit 20. Operations of the detection output duration determination circuit 18 and the detection count circuit 20 are controlled by the operation control circuit 14.

  The detection output duration determination circuit 18 receives the detection result signal QC from the detection circuit 30 and the timing information of the determination period from the determination timing register 50. Then, based on the detection result signal QC and the timing information (t1, t2), it is determined whether or not the terminal voltage VSW is continuously lower than the determination voltage (VT) in the determination period (TDT). If it is lower, the detection output duration determination circuit 18 outputs the determination pulse signal PL to the detection count circuit 20.

  The detection count circuit 20 receives the detection count information from the detection count register 52 and the determination pulse signal PL from the detection output duration determination circuit 18. Each time the determination pulse signal PL becomes active, the count value is counted up (updated). When the count value reaches the number of detections set by the detection number information, the terminal voltage abnormality determination result signal QRS is output. For example, assuming that the number of times of detection is set to 2, when the count value reaches 2, the determination result signal QRS becomes a voltage level that instructs the operation of the surge absorbing circuit 40 to be turned on. Alternatively, the determination result signal QRS becomes a voltage level instructing to stop the operation of the drive transistor SWT.

  10 and 11 are signal waveform diagrams for explaining the operation of the detailed configuration example of this embodiment. As shown in FIG. 10, in the ON period TON of the drive transistor SWT, the terminal voltage VSW is set to the power supply voltage VB. In the OFF period TOF, the terminal voltage VSW becomes a negative voltage VM lower than GND (= 0V), and then the voltage level gradually increases.

  In FIG. 11, the determination period TDT is set within the OFF period TOF of the drive transistor SWT. Specifically, the determination timing register 50 stores information on t1 and t2 as timing information. t1 is information for determining the start timing of the determination period TDT, and t2 is information for determining the length of the determination period TDT. In FIG. 11, t1 is information specifying the length from the start timing of the on period TON to the start timing of the determination period TDT.

  In FIG. 11, a waveform WVS (broken line) schematically shows a waveform of the terminal voltage VSW when the diode SB is normally connected. The waveform WVP (solid line) schematically shows the waveform of the terminal voltage VSW when the diode SB is disconnected due to poor connection or the like.

  In the waveform WVP when the diode SB is disconnected, in the determination period TDT within the first OFF period TOF (the m-th OFF period), the terminal voltage VSW continues to generate the determination voltage VT as indicated by B1 in FIG. It is below. That is, as shown in B2, the detection signal QC of the detection circuit 30 is continuously at the L level during the determination period TDT. Therefore, in this case, the detection output duration determination circuit 18 of FIG. 9 determines that there is a terminal voltage abnormality, and outputs the determination pulse signal PL as shown at B3. As a result, the count value of the detection count circuit 20 that has received the determination pulse signal PL is counted up from 0 to 1, for example.

  In the waveform WVS when the diode SB is not disconnected, the determination pulse signal PL is not output because the terminal voltage VSW does not continue below the determination voltage VT in the determination period TDT.

  Also in the determination period TDT within the next OFF period TOF (the (m + 1) th OFF period), in the waveform WVP, the terminal voltage VSW continues to be lower than the determination voltage VT as indicated by B4. That is, as shown in B5, the detection signal QC is continuously at the L level in the determination period TDT. Accordingly, also in this case, the detection output duration determination circuit 18 determines that there is a terminal voltage abnormality, and outputs the determination pulse signal PL as indicated by B6. As a result, the count value of the detection count circuit 20 is counted up from 1 to 2, for example. In FIG. 11, the number of detection times set in the detection number register 52 is two. Therefore, when the count value of the detection count circuit 20 reaches 2 corresponding to the detection count, the operation of the surge absorption circuit 40 is turned on as indicated by B7. Further, as indicated by B8, the on / off operation of the drive transistor SWT is stopped.

  As described with reference to FIG. 1 and the like, when the diode SB is disconnected due to poor connection or the like, the diode DI of the protection element PR inside the circuit device becomes a current path through which the current from the inductor L flows during the OFF period TOF. . The forward voltage of the Schottky barrier diode SB is, for example, about 0.4 V, whereas the forward voltage of the PN junction diode DI of the protection element PR is about 0.6 V, and the difference between It is about 0.2V. Therefore, for example, in FIG. 3, the waveform WVS when the current flows through the inductor L via the diode SB and the waveform WVP when the diode SB is disconnected and the current flows through the inductor L via the diode DI of the protection element PR. Is required to set the determination voltage VT within this range of 0.2V. For this reason, for example, even when there is a process variation for each lot of ICs of the circuit device, it is difficult to set an appropriate determination voltage VT and make adjustments so that erroneous determination of terminal voltage abnormality does not occur. There is a problem that there is.

  Therefore, in this embodiment, the terminal voltage VSW and the determination voltage VT are not simply compared, and the determination period TDT is set within the OFF period TOF as indicated by B2 and B5 in FIG. As shown in B1 and B4, when the terminal voltage VSW continues to fall below the determination voltage VT in the negative voltage direction within the determination period TDT, a terminal voltage abnormality is detected as shown in B3 and B6. It is determined that

  The timing (length) of the determination period TDT can be variably adjusted by setting timing information (t1, t2) in the determination timing register 50. Also, the voltage level of the determination voltage VT can be variably adjusted by setting the determination voltage setting register 54.

  Then, for example, in the product shipping process or the inspection process, the appropriate timing information of the determination period TDT and the setting information of the appropriate voltage level of the determination voltage VT are written in the determination timing register 50 and the determination voltage setting register 54. To. For example, the timing of the determination period TDT and the determination voltage VT are adjusted so that the terminal voltage abnormality is not erroneously detected while the diode SB is normally connected. Then, the timing information of the adjusted determination period TDT and the setting information of the voltage level of the determination voltage VT are written in the determination timing register 50 and the determination voltage setting register 54. The information written in these registers is stored and saved in a non-volatile memory provided in, for example, a circuit device or a circuit board.

  In this way, during actual operation of the product, the terminal voltage abnormality is determined using the determination period TDT in which the timing is appropriately adjusted and the determination voltage VT in which the voltage level is appropriately adjusted. As a result, even when there are variations in the forward voltage of the diode due to, for example, a product lot, it becomes possible to cope with this. As a result, it is possible to provide a circuit device that can prevent deterioration or destruction of the circuit device or the like due to a negative voltage surge caused by poor connection of the diode SB or the like, while preventing erroneous detection of terminal voltage abnormality. Become.

  Further, when the operation of the surge absorbing circuit 40 is turned on or the on / off operation of the drive transistor SWT is stopped only by detecting the terminal voltage abnormality once, for example, an appropriate power source by a switching regulator is then used. There is a problem that it becomes impossible to generate the voltage (VOUT). For example, it is preferable that an erroneous detection of an abnormal terminal voltage occurs due to noise superimposed on the terminal voltage VSW and the operation of the surge absorption circuit 40 is turned on or the on / off operation of the drive transistor SWT is stopped. Absent.

  Therefore, in this embodiment, as shown in B3 and B6 of FIG. 11, the operation of the surge absorption circuit 40 is turned on and the on / off operation of the drive transistor SWT is stopped on condition that a terminal voltage abnormality is detected a plurality of times. To do. That is, when the terminal voltage abnormality is detected continuously in the mth to m + n off periods (first and second off periods in FIG. 11) of the drive transistor SWT, the operation of the surge absorbing circuit 40 is turned on. Or, the on / off operation of the drive transistor SWT is stopped. In this case, the detection number information (n + 1) can also be set in the detection number register 52 so that the number of detections can be adjusted in, for example, a shipping process or an inspection process.

  In this way, even if a terminal voltage abnormality is erroneously detected due to noise or the like superimposed on the terminal voltage VSW, the terminal voltage abnormality is not continuously detected over a plurality of off periods. The surge absorbing circuit 40 will not operate. Further, the on / off operation of the drive transistor SWT is not stopped. Accordingly, it is possible to properly realize the operation of the surge absorbing circuit 40 and the stop of the on / off operation of the drive transistor SWT when the connection failure of the diode SB is prevented while preventing erroneous detection of the terminal voltage abnormality.

  The number of detections may not be a variable number, but may be a fixed number. Further, it is possible to perform a modification in which the operation of the surge absorbing circuit 40 is turned on or the operation of the drive transistor SWT is stopped by detecting the terminal voltage abnormality once instead of detecting a plurality of times.

3. Detection Circuit FIGS. 12 and 13 show detailed configuration examples of the detection circuit 30. The detection circuit 30 is not limited to the configuration shown in FIGS. 12 and 13, and various modifications such as omitting some of the components or adding other components are possible.

  In FIG. 12, the detection circuit 30 includes resistors R1 to Rj (j is an integer of 2 or more), switch elements SW1 to SWj, a bipolar transistor BP, and inverters IV1 and IV2. The resistor R1 and the switch element SW1 are provided in series between the node of the power supply voltage VB and the node NA1. Similarly, the resistor Ri and the switch element SWi are also provided in series between the node of the power supply voltage VB and the node NA1, and the resistor Rj and the switch element SWj (1 <i <j) are also connected to the node of the power supply voltage VB and the node NA1. Are provided in series. Then, the control circuit 10 performs on / off control of the switch elements SW1 to SWj, so that the resistance value between the node of the power supply voltage VB and the node NA1 is variably adjusted. Note that the connection configuration of the resistors R1 to Rj and the switch elements SW1 to SWj is not limited to the configuration of FIG. 12, and may be any connection configuration that can variably set at least the resistance value between the power supply voltage VB and the node NA1.

  For example, in the ON period TON of the drive transistor SWT, the node NSW of the output terminal TSW is at the voltage level of the power supply voltage VB, so that the bipolar transistor BP whose base is connected to GND is turned off. As a result, the voltage level of the node NA1 becomes the H level that is the voltage level of the power supply voltage VB, and the detection signal QC of the detection circuit 30 also becomes the H level.

  On the other hand, when the driving transistor SWT is turned off, the node NSW of the output terminal TSW becomes a negative voltage, so that a potential difference is generated between the base and the emitter of the bipolar transistor BP, and the bipolar transistor BP is turned on. IA flows.

  At this time, the voltage VNA1 of the node NA1 can be expressed as VNA1 = VB−IA × R, where R is a resistance value between the node of the power supply voltage VB and the node NA1. Then, the threshold voltage of the first-stage inverter IV1 to which the voltage VNA1 of the node NA1 is input is set to Vth (for example, Vth = 1.2V). Then, when the current IA flows through the bipolar transistor BP due to a negative voltage surge and the voltage VNA1 = VB−IA × R of the node NA1 falls below the threshold voltage Vth of the inverter IV1, the detection signal QC is L Become a level. That is, when the voltage VNA1 = VB−IA × R falls below the threshold voltage Vth due to a large current IA flowing in the bipolar transistor BP due to a surge of a negative voltage having a large absolute value, the detection signal QC is set to the L level. Thus, it becomes possible to detect a terminal voltage abnormality due to a negative voltage surge.

  In the detection circuit 30 shown in FIG. 12, the voltage level of the determination voltage VT can be adjusted by adjusting the resistance value by setting the switch elements SW1 to SWj on and off.

  For example, when the determination voltage VT is set to a low voltage level, the switch elements SW1 to SWj are turned on / off so that the resistance value R between the node of the power supply voltage VB and the node NA1 is high. In this way, even when the absolute value of the negative surge voltage is small and the current IA flowing through the bipolar transistor BP is small, the voltage at the node NA1 becomes VNA1 = VB−IA × R <Vth, The detection signal QC changes to the L level. Therefore, the determination voltage VT can be set to a low voltage level.

  On the other hand, when the determination voltage VT is set to a high voltage level, the switch elements SW1 to SWj are turned on / off so that the resistance value R between the node of the power supply voltage VB and the node NA1 becomes low. In this way, when the absolute value of the negative surge voltage increases and the current IA flowing through the bipolar transistor BP increases, the voltage at the node NA1 becomes VNA1 = VB−IA × R <Vth. Thus, the detection signal QC changes to the L level. Therefore, the determination voltage VT can be set to a high voltage level.

  As described above, in FIG. 12, the on / off setting information of the switch elements SW <b> 1 to SWj is the setting information of the voltage level of the determination voltage VT, and this setting information is stored in the determination voltage setting register 54.

  The detection circuit 30 in FIG. 13 includes P-type transistors TB1, TB2, TB3, N-type transistor TB4, bipolar transistors BP1 to BP7, resistors RB1, RB2, RB3, an inverter IV, and a logic circuit LG.

  In FIG. 13, when a bias voltage BS is input to the gates of the transistors TB1 and TB2, a constant bias current flows through the path RT1 and the path RT2. In the ON period TON of the drive transistor SWT, the control signal CT becomes L level as shown in FIG. 4, and therefore, the detection circuit is input by inputting an H level signal to the first input terminal of the logic circuit LG. The 30 detection signals QC are at the H level.

  On the other hand, when a negative voltage surge is applied to the node NSW of the output terminal TSW during the OFF period TOF of the driving transistor SWT, a large current IB flows through the transistor TB4. Since most of the current IB flows through the path RT2, the voltage level of the node NB3 decreases, and the bipolar transistor BP5 whose base-emitter voltage is reduced is turned off. As a result, the voltage level of the node NB4 rises due to the pull-up resistor RB2, and the P-type transistor TB3 is turned off. As a result, the voltage level of the node NB5 becomes L level by the pull-down resistor RB3. At this time, since the voltage level of the control signal CT is H level in the off period TOF, L level signals are input to both the first and second input terminals of the logic circuit LG, and the detection signal QC is H level. Changes from L to L level. Therefore, it is possible to detect a terminal voltage abnormality due to a negative voltage surge.

  12 and 13 uses the currents IA and IB flowing from the high potential side power supply VB to the output terminal TSW side when the terminal voltage VSW becomes a negative voltage during the OFF period TOF of the drive transistor SWT. Terminal voltage abnormality is detected. That is, the terminal voltage abnormality is detected using the currents IA and IB that flow when a negative voltage surge is applied to the output terminal TSW. For example, in FIG. 12, the current IA flowing due to the negative voltage surge is converted into a voltage by resistors (R1 to Rj), thereby realizing a comparison process between the terminal voltage VSW and the determination voltage VT. In this way, it is possible to detect a negative voltage surge during the OFF period TOF of the drive transistor SWT properly and detect a terminal voltage abnormality.

4). Detection Mode In the present embodiment, the control circuit 10 executes an inspection mode in which it is determined whether or not to stop the on / off operation of the drive transistor SWT by detecting a terminal voltage abnormality after the circuit device is powered on. Specifically, the inspection mode is executed after the circuit device is powered on and after the soft start period for driving the drive transistor SWT ends. This inspection mode is performed, for example, in a product shipping process or an inspection process.

  FIG. 14 is a flowchart for explaining this inspection mode. When power is turned on to the circuit device (electronic device in which the circuit device is incorporated) (step S1), the drive transistor SWT is soft-started (step S2). In the soft start period, for example, a switching regulation operation in which the drive capability of the drive transistor SWT is reduced is performed.

  Next, the inspection mode is executed (step S3). That is, an inspection mode for inspecting a connection failure of an external component or the like is executed. Specifically, an inspection mode is executed in which it is determined whether or not the terminal voltage abnormality is detected and the operation of the drive transistor SWT is stopped. If a terminal voltage abnormality is detected (step S4: YES), the operation of the drive transistor SWT is stopped (step S5). On the other hand, when the terminal voltage abnormality is not detected (step S4: NO), the process shifts to a normal operation mode in which the circuit device operates normally (step S6).

  According to the method shown in FIG. 14, for example, initial defective products can be identified and eliminated in a shipping process or the like. For example, when a terminal voltage abnormality is detected by executing the inspection mode, the circuit device (electronic device) is determined to be an initial defective product and is excluded.

  Further, according to the method of FIG. 14, for example, every time a circuit device (electronic device) is powered on, an inspection mode for detecting a terminal voltage abnormality can be executed. For example, during operation of the circuit device, a terminal voltage abnormality is not always detected, but an inspection mode for detecting a terminal voltage abnormality is executed every time the power is turned on. This makes it possible to determine whether or not to stop the operation of the drive transistor SWT by detecting a terminal voltage abnormality based on a connection failure of the diode SB or the like each time the power is turned on.

  In FIG. 14, after the power is turned on and the soft start period has elapsed, an inspection mode for detecting a terminal voltage abnormality is executed. For example, if the operation is started in a state where the drive capability of the drive transistor SWT is high, a large inrush current may occur. When such an inrush current occurs, a change in the potential of the power supply voltage when the inrush current occurs adversely affects other circuits, causing problems such as unstable operation of the circuit device. For this reason, for example, in the soft start period after power-on, for example, soft start is performed in which the drive capability of the drive transistor SWT is lower than that in normal operation. In the present embodiment, the power supply voltage (VOUT in FIG. 2) generated by the switching regulator is stepped down by a built-in regulator (series regulator, constant voltage generation circuit), and the power supply voltage after stepping down is output to the outside. Good. In this case, during the soft start period, soft start may be performed in which the drive capability of the drive transistor constituting the regulator is lower than that during normal operation.

  In FIG. 14, after such a soft start period ends, an inspection mode for detecting a terminal voltage abnormality is executed. Accordingly, since the inspection mode is executed after the operation of the circuit device is stabilized by the soft start, it is possible to suppress the occurrence of erroneous detection of the terminal voltage abnormality.

  That is, if a test mode for detecting a terminal voltage abnormality is executed without performing a soft start and the operation of the circuit device is unstable, the determination is made, for example, when the terminal voltage VSW is unstable. A comparison process with the voltage VT or the like is performed, and there is a high possibility of erroneous detection of terminal voltage abnormality.

  In this regard, if the test mode is executed after the soft start period ends and the circuit device operates stably, the terminal voltage VSW and the like can be compared with the determination voltage VT while the terminal voltage VSW and the like is stable. The occurrence of erroneous detection of voltage abnormality can be effectively reduced.

  In the circuit device according to the present embodiment, it is desirable to output abnormality detection information notifying that a terminal voltage abnormality has been detected. That is, by outputting the abnormality detection information, it is notified that the operation of the surge absorbing circuit 40 is turned on and the on / off operation of the drive transistor SWT is stopped due to the detection of the terminal voltage abnormality.

  In this case, various methods can be assumed as the method for outputting the abnormality detection information. For example, in FIG. 15, when a terminal voltage abnormality is detected, the control circuit 10 writes an abnormality detection flag that is abnormality detection information in the abnormality detection notification register 56. The circuit device is provided with an I / F (interface) unit 60 that performs an interface process with an external device, and the external device such as a microcomputer is connected to an abnormality detection notification register 56 or the like via the I / F unit 60. Has access to registers. Accordingly, when the external device reads the abnormality detection flag (abnormality detection information in a broad sense) from the abnormality detection notification register 56 via the I / F unit 60, the abnormality detection information is output from the circuit device. .

  In FIG. 16, a terminal TAB for outputting an abnormality detection signal SAB that is abnormality detection information is provided. When a terminal voltage abnormality is detected, the control circuit 10 outputs an abnormality detection signal SAB (abnormality detection information in a broad sense) to an external device via the terminal TAB, whereby abnormality detection information is output from the circuit device. Will come to be.

  Note that the abnormality detection information output method is not limited to the method shown in FIGS. 15 and 16, and various modifications can be made. The terminal TAB may also be used as a terminal that outputs another signal (for example, a data signal).

  For example, when a terminal voltage abnormality occurs and the operation of the surge absorbing circuit 40 is turned on or the driving transistor SWT is turned off and on, the switching regulator of FIG. 2 is taken as an example, so that an appropriate power supply voltage VOUT is not output. End up. For this reason, each device of the electronic apparatus to which the power supply voltage VOUT is supplied cannot operate normally, and the external device cannot know the cause unless any measures are taken.

  Therefore, in FIGS. 15 and 16, a method of outputting abnormality detection information from the circuit device when a terminal voltage abnormality occurs is employed. By doing so, the external device can confirm that the operation of the surge absorbing circuit 40 is turned on or the on / off operation of the drive transistor SWT is stopped due to the abnormality of the terminal voltage based on the abnormality detection information. . Therefore, for example, by displaying the occurrence of such an abnormality on the display unit of the electronic device, for example, it is possible to inform the user of the electronic device, and for example, prompt repair. As a result, user convenience, device reliability, and the like can be improved.

  For example, in a stage where the voltage level of the negative voltage surge due to the connection failure of the diode SB or the like is not at a level that destroys the drive transistor SWT of the circuit device by only one surge, as shown in FIGS. By outputting the abnormality detection information, it is notified that some abnormality has occurred in the terminal voltage. In this way, it is possible to notify the user or the like of the terminal voltage abnormality at a stage before the circuit device is destroyed. Therefore, the circuit device can be repaired before it is destroyed, and the reliability can be greatly improved.

5. Electronic Device FIG. 17 shows a configuration example of an electronic device to which the circuit device 200 of this embodiment is applied. The electronic device includes a processing unit 300, a storage unit 310, an operation unit 320, an input / output unit 330, a circuit device 200, a bus 340 connecting these units, and a motor 280. In the following, a description will be given by taking, as an example, a printer that controls the head and paper feed by motor drive as the electronic device, but this embodiment is not limited to this, and various electronic devices (for example, smartphones, mobile phones, digital cameras) , A video camera, a car navigation system, a robot, a game machine, a watch, a health appliance, an information processing device, or the like.

  The input / output unit 330 is configured by an interface such as a USB connector or a wireless LAN, and receives image data and document data. The input data is stored in the storage unit 310 which is an internal storage device such as a DRAM. When the printing instruction is received by the operation unit 320, the processing unit 300 starts a printing operation of data stored in the storage unit 310. The processing unit 300 sends an instruction to the circuit device 200 in accordance with the print layout of the data, and the circuit device 200 rotates the motor 280 based on the instruction to move the head and feed the paper.

  The circuit device 200 includes the switching regulator described in FIG. 2 and the like, and a regulator (not shown). The switching regulator steps down the high power supply voltage for driving the motor 280 to generate the first power supply voltage. The regulator steps down the first power supply voltage to generate a second power supply voltage. The processing unit 300, the storage unit 310, the input / output unit 330, and the like operate based on the second power supply voltage.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configuration and operation of the circuit device and the electronic device, the generation method of the power supply voltage, and the like are not limited to those described in the present embodiment, and various modifications can be made.

SWT ... Drive transistor, L ... Inductor, SB, DI ... Diode,
BPD, BPD1, BPD2, BPD3 ... Bipolar transistors,
TR transistor, PR ... protection element, TSW ... output terminal, TVB power supply terminal,
VB: power supply voltage, VSW: terminal voltage (output voltage),
C: Capacitor, RF1, RF2 ... Resistance,
TON ... on period, TOF ... off period, R1-Rj ... resistance,
BP ... Bipolar transistor, IV1, IV2 ... Inverter,
BP1 to BP7: bipolar transistors, RB1 to RB3: resistors,
TB1 to TB4 ... transistor, IV ... inverter, LG ... logic circuit,
DESCRIPTION OF SYMBOLS 10 ... Control circuit, 12 ... Switch control circuit, 14 ... Operation control circuit, 16 ... Determination circuit,
18 ... detection output duration determination circuit, 20 ... detection count circuit, 30 ... detection circuit,
40 ... surge absorption circuit, 42 ... discharge circuit,
50: Determination timing register, 52: Detection frequency register,
54 ... judgment voltage setting register, 56 ... abnormality detection notification register,
60 ... I / F section, 90 ... load

Claims (13)

A driving transistor that outputs a driving current for the inductor to an output terminal; and
A control circuit for controlling the on / off operation of the drive transistor;
A detection circuit for detecting abnormality of the terminal voltage of the output terminal;
Including a surge absorbing circuit connected to the output terminal,
The output terminal is a terminal to which a cathode of a diode through which a current flowing through the inductor flows during an off period of the driving transistor is connected;
The control circuit includes:
When a terminal voltage abnormality is detected by the detection circuit during an off period of the driving transistor, the surge absorption circuit is turned on to cause the surge absorption circuit to absorb an overvoltage surge generated at the output terminal. A circuit device characterized by the above. In claim 1,
The surge absorbing circuit is
A circuit device comprising: a discharge circuit that causes a discharge current to flow from a low-potential-side power supply side to the output terminal side when the terminal voltage abnormality is detected during the off period of the drive transistor. In claim 2,
The discharge circuit is:
A circuit device comprising a bipolar transistor that causes the discharge current to flow from the low-potential-side power supply side to the output terminal side. In any one of Claims 1 thru | or 3,
The control circuit includes:
When the terminal voltage abnormality is detected in which the terminal voltage is continuously lower than the determination voltage in the determination period set within the OFF period of the driving transistor, the operation of the surge absorbing circuit is turned on. A circuit device characterized by the above. In claim 4,
A circuit device comprising a determination timing register for storing timing information of the determination period. In claim 4 or 5,
A circuit device comprising a determination voltage setting register for storing setting information of a voltage level of the determination voltage. In any one of Claims 1 thru | or 6.
The control circuit includes:
When the terminal voltage abnormality is detected in an m-th off period to an m + n (m, n is an integer of 1 or more) off period of the driving transistor, the operation of the surge absorbing circuit is turned on. A circuit device. In claim 7,
A circuit device comprising a detection number register for storing n + 1 information corresponding to the number of detections of the terminal voltage abnormality. In any one of Claims 1 thru | or 8 .
Including a protection element having a protection diode having a cathode connected to the output terminal;
The diode is a Schottky barrier diode;
The circuit device according to claim 1, wherein a forward voltage of the protection diode is higher than a forward voltage of the Schottky barrier diode. In any one of Claims 1 thru | or 9 ,
The detection circuit includes:
The circuit device characterized in that the terminal voltage abnormality is detected by using a current flowing from a high-potential-side power source to the output terminal when the terminal voltage becomes a negative voltage during the off period of the driving transistor. In any one of Claims 1 thru | or 10 .
An abnormality detection information for notifying that the terminal voltage abnormality is detected is output. In any one of Claims 1 thru | or 11 ,
The control circuit includes:
The circuit device, wherein when the terminal voltage abnormality is detected in the off period of the driving transistor, the on / off operation of the driving transistor is stopped. An electronic apparatus comprising the circuit arrangement as claimed in any one of claims 1 to 12.

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