JP6569564B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device in which ion irradiation is performed at a desired position using a mask.

  Conventionally, inverters and the like have been provided with semiconductor elements such as insulated gate field effect transistors (hereinafter referred to as IGBT (Insulated Gate Bipolar Transistor)) and free-wheeling diodes (hereinafter referred to as FWD (Free Wheeling Diode)). A semiconductor device is used. In this semiconductor device, lifetime control by He (helium) ray irradiation is performed in order to improve switching characteristics. Conventionally, a method of irradiating the entire surface of the wafer with He has been used as a method for irradiating the He line. However, in recent years, He is irradiated only to a region to be irradiated to further improve the characteristics of the semiconductor device. Is now being done. “Partial irradiation” is a method in which non-irradiated areas are covered with a metal mask and He line irradiation is performed, and He is irradiated only to areas not covered with a metal mask.

  However, when a metal mask is used, the metal mask is disposed in the vicinity of the wafer. “Partial irradiation” is performed by providing an opening at a desired position of the metal mask, and contaminants such as metal adhere to the metal mask when the opening is processed. For this reason, a contaminant is irradiated to the wafer at the same time when the He beam is irradiated, and contamination that contaminates the wafer occurs. Due to the influence, there are concerns such as deterioration of device characteristics and a decrease in reliability of the semiconductor device. In addition, when cross-contamination is performed in the post process, that is, when a contaminated wafer is transferred into the post-process apparatus and the post-process is performed, contaminants adhere to the post-process apparatus, resulting in the post-process apparatus. This also causes contamination of other wafers.

  As a method for manufacturing a semiconductor device that can solve these problems, a manufacturing method disclosed in Patent Document 1 can be given. Specifically, an absorber made of aluminum or the like is arranged on the wafer side of the metal mask, and the wafer is irradiated with He rays while the metal mask and the absorber are integrated. Thus, if an absorber is arrange | positioned at the wafer side among metal masks, it can suppress that a contaminant is irradiated to a wafer by an absorber.

Japanese Patent No. 2963204

  However, as described in Patent Document 1, it is difficult to align the wafer and the metal mask in the manufacturing method in which He-beam irradiation is performed using a metal mask in which an absorber is integrated on the wafer side. Become. That is, even if it tries to perform alignment by confirming the element pattern of a wafer through the opening part formed in a metal mask, it cannot be confirmed because it is blocked by the absorber and cannot be aligned.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of accurately aligning a metal mask while suppressing exposure of a contaminant to a wafer.

  In order to achieve the above object, in the method of manufacturing a semiconductor device according to claim 1, a wafer (40) constituting a semiconductor substrate (10) on which the semiconductor device is formed is prepared, and an ion irradiation apparatus (30). And irradiating the wafer with ions to form a damaged region (24) at a predetermined depth of the semiconductor substrate. In forming the damaged region, the wafer is held by the wafer holder (32), and the metal mask (33) provided with the opening (33a) is disposed opposite to the wafer, and the control unit (36). Align the metal mask with respect to the wafer by adjusting the position of the metal mask at, and store information on the adjustment position of the metal mask when the alignment is performed in the control unit, and the metal mask and the wafer. In addition, an absorber (34) for adjusting the depth of ion irradiation is disposed between the metal mask and the metal mask at the adjustment position stored in the controller, and after the alignment, Ion irradiation is performed through the metal mask and absorber with the absorber sandwiched between the metal mask and the wafer. It has to.

  Thus, ion irradiation is performed in a state where the absorber is disposed between the metal mask and the wafer. For this reason, it is possible to prevent the contaminant attached when the opening is formed in the metal mask from being blocked by the absorber and irradiated to the wafer side. Therefore, it is possible to suppress the contamination of the wafer, and it is also possible to suppress the cross contamination that occurs when the contaminated wafer moves to the subsequent process.

  Further, before the absorber is arranged, the metal mask is aligned with the wafer, and the control unit stores information on the adjustment position of the metal mask. For this reason, when the absorber is placed between the metal mask and the wafer, alignment is accurately performed only by adjusting the position of the metal mask based on the information on the adjustment position of the metal mask stored in the control unit. Can be taken.

  Therefore, it is possible to accurately align the metal mask while suppressing exposure of the contaminant to the wafer.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is sectional drawing of a He ray irradiation apparatus. It is the perspective view which showed the mode of alignment alignment of the metal mask with respect to the wafer performed before performing He line irradiation, and the installation of an absorber. It is sectional drawing which showed the mode in the case of forming a damage area | region in the deep position of a semiconductor substrate by He ray irradiation. It is sectional drawing which showed the mode in the case of forming a damage area | region in the shallow position of a semiconductor substrate by He ray irradiation. It is the perspective view which showed the mode of alignment alignment of the metal mask with respect to the wafer performed before performing He line irradiation concerning 2nd Embodiment, and the installation of an absorber. It is the perspective view which showed the mode of alignment of the metal mask with respect to the wafer performed before performing He line irradiation concerning 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

  First Embodiment A first embodiment will be described. First, a semiconductor device including an IGBT will be described as a semiconductor device manufactured by the manufacturing method described in this embodiment. The semiconductor device is preferably used as a power switching element used in a power supply circuit such as an inverter or a DC / DC converter. Specifically, the semiconductor device according to the present embodiment is configured as follows.

  The semiconductor device shown in FIG. 1 is configured to include a cell region and an outer peripheral region surrounding the cell region, and FIG. 1 shows a cross section of an IGBT provided in the cell region.

As shown in FIG. 1, the IGBT is formed using a semiconductor substrate 10. The semiconductor substrate 10 is basically composed of an N ⁻ -type silicon substrate, and each part constituting the IGBT is formed by performing various semiconductor processes such as an impurity layer forming process on the substrate. It is said that.

A drift layer 11 is constituted by an N ⁻ -type portion of the semiconductor substrate 10, and a P-type base layer 12 is formed on the drift layer 11, that is, on the one surface 10 a side of the semiconductor substrate 10. A plurality of trenches 13 are formed so as to penetrate the base layer 12 and reach the drift layer 11, and the base layer 12 is separated into a plurality of trenches 13.

At least a part of the base layer 12 separated into a plurality functions as a channel region. Specifically, in a part of the base region 12 separated into a plurality, a portion in contact with a trench gate structure described later functions as a channel region. An N ⁺ -type emitter region 14 and a P ⁺ -type body region 15 are formed so as to be sandwiched between the emitter regions 14 in a portion of the base layer 12 that functions as a channel region.

  In the case of this embodiment, the emitter region 14 and the body region 15 are formed only in a part that functions as a channel region of the plurality of base layers 12 separated by the trench 13, and in the remaining part Not formed. For this reason, only a part of the base layer 12 where the emitter region 14 and the body region 15 are formed performs the IGBT operation, and the remaining part is a thinned region where a channel region is not formed.

  The emitter region 14 is configured to have a higher impurity concentration than the drift layer 11, terminates in the base layer 12, and is in contact with the side surface of the trench 13. On the other hand, the body region 15 has a higher impurity concentration than the base layer 12 and is formed so as to terminate in the base layer 12 like the emitter region 14.

  Each trench 13 includes a gate insulating film 16 formed so as to cover the inner wall surface of each trench 13 and a gate electrode 17 made of polysilicon or the like formed on the gate insulating film 16. Embedded. Thereby, a trench gate structure is configured.

  On one surface 10 a side of the semiconductor substrate 10, an interlayer insulating film 18 made of BPSG or the like is formed on the base layer 12. In the interlayer insulating film 18, a contact hole 18 a that exposes a part of the emitter region 14 and the body region 15 is formed.

  An upper electrode 19 is formed on the interlayer insulating film 18. The upper electrode 19 is electrically connected to the emitter region 14 and the body region 15 through the contact hole 18a, and is also electrically connected to the base region 12 through the body region 15. In the thinning region, the upper electrode 19 is directly connected to the base region 12 through the contact hole 18a.

  Further, on the side opposite to the base layer 12 side of the drift layer 11, that is, on the other surface 10 b side of the semiconductor substrate 10, an N-type field stop (hereinafter referred to as FS) whose N-type impurity concentration is higher than that of the drift layer 11. A layer 20 is formed. Although this FS layer 20 is not necessarily required, it is possible to improve the breakdown voltage and steady loss performance by preventing the depletion layer from spreading, and to increase the injection amount of holes injected from the other surface 10b side of the semiconductor substrate 10. Be prepared to control.

  A P-type collector layer 21 is formed on the opposite side of the drift layer 11 with the FS layer 20 interposed therebetween.

  A lower electrode 23 is formed on the collector layer 21, that is, on the other surface 10 b side of the semiconductor substrate 10. The lower electrode 23 functions as a collector electrode in the IGBT.

  Further, damage regions 24 are formed on the one surface 10a side and the other surface 10b side of the semiconductor substrate 10. Specifically, on the one surface 10a side and the other surface 10b side, the damage region 24 is formed at a position to be a thinning region in each trench gate structure.

  By providing such a damaged region 24, holes in the drift layer 11 in the IGBT, that is, excess carriers recombine with the damaged region 24 and disappear. For this reason, it is possible to suppress the injection of IGBT holes into other elements, such as FWD, and to improve the characteristics of the semiconductor device, such as improving the switching characteristics.

  The semiconductor device manufactured by the manufacturing method according to the present embodiment is configured by the above structure. Helium irradiation is performed when forming the damaged region 24 in the semiconductor device configured as described above. Hereinafter, the details of the He beam irradiation apparatus used for the He beam irradiation will be described.

  As shown in FIG. 2, the He-ray irradiation apparatus 30 includes a chamber 31, a plate 32, a metal mask 33, an absorber 34, a He-line output unit 35, a control unit 36, and the like.

  The chamber 31 is a container for performing He-ray irradiation by accommodating a wafer 40 in a state before being divided into chips, that is, a substrate including a plurality of the semiconductor devices together with the plate 32, the metal mask 33, and the like. A plate 32 or the like is installed at a predetermined position of the chamber 31. The plate 32 may be installed in the chamber 31 in any form. For example, after the plate 32 is mounted on a rail (not shown) extending to a predetermined position of the chamber 31, the plate 32 is placed on the rail. It is done by moving.

  The plate 32 serves as a wafer holder that holds the wafer 40 when performing He-ray irradiation. For example, as shown in FIG. 3, the plate 32 includes an annular holding portion 32 a that holds a substantially circular wafer 40, and one surface of the wafer 40 is opened from an opening provided in the holding portion 32 a. The wafer 40 is arranged so as to be exposed. For example, the wafer 40 is arranged so that the lower side of the paper surface in FIG. 1 is exposed from the plate 32 when attached to the plate 32. The plate 32 is placed at a predetermined position in the chamber 31 in a state where the wafer 40 is arranged, so that He line irradiation is performed.

  Further, the plate 32 is provided with a holding piece 32b, and the metal mask 33 and the like are held by the holding piece 32b.

  In the present embodiment, the plate 32 is provided with a holding portion 32a and the wafer 40 can be directly held by the holding portion 32a. For example, the holding portion 32a is separated from the plate 32 as a wafer holder. Can also be configured. In this case, for example, the holding unit 32a and the wafer 40 may be held by the holding piece 32b. Of course, the plate 32 may be provided with a holding component that is not the holding piece 32b, and the holding portion 32a and the wafer 40 may be held via the holding component, or the holding piece 32b may be held. Further, the state of the wafer 40 when it is attached to the plate 32 may be at any stage in the manufacturing process. For example, the base layer 12, the body region 15, the emitter region 14, and the trench gate structure are formed on the front surface side of the semiconductor substrate 10, and the FS layer 20, the collector layer 21, and the cathode layer 22 are formed on the back surface side of the semiconductor substrate 10. The state before the lower electrode 23 is formed.

  The metal mask 33 has a structure in which an opening 33a is formed at a position where He irradiation is desired. The opening 33 a is formed at a position corresponding to the thinning region, for example, and is formed by drilling a circular metal plate constituting the metal mask 33. For this reason, contaminants, such as aluminum which adheres at the time of drilling, existed in the end face of the opening 33a. Note that the thickness of the metal mask 33 is set such that the He line irradiation is not performed on the wafer 40 at a position other than the opening 33a when the He line irradiation is performed on the wafer 40.

  In addition, the relative position of the metal mask 33 with respect to the plate 32 can be adjusted. Specifically, as relative position adjustment, position adjustment in the XY direction with the surface of the plate 32 as the XY plane, one direction on the XY plane as the X direction, and a direction perpendicular to the X direction as the Y direction, Angle adjustment in the circumferential direction around an arbitrary point on the XY plane is possible. For this reason, the relative position of the metal mask 33 with respect to the plate 32 is determined such that the XY coordinates on the XY plane and the circumferential angle θ centered on an arbitrary point on the XY plane have a predetermined value. It is held by the plate 32.

  In the present embodiment, a form in which the metal mask 33 is directly attached to the plate 32 by using the holding pieces 32b is adopted as a form in which the metal mask 33 is determined and held relative to the plate 32. However, this is only an example, and the metal mask 33 can be held independently of the plate 32 using a holding tool (not shown). Further, instead of using the holding piece 32b, the metal mask 33 and the plate 32 may be directly attached to the plate 32 by sandwiching the periphery of the metal mask 33 and the plate 32 with clips. Of course, even when the holding piece 32b is used, the periphery of the metal mask 33 and the plate 32 can be clamped using a clip, and in this case, the relative positional deviation between the metal mask 33 and the plate 32 can be suppressed. In the present embodiment, the metal mask 33 is formed of a circular plate-shaped member, but may have other shapes such as a square shape. In particular, when the metal mask 33 can be held independently of the plate 32, the shape of the metal mask 33 is arbitrary because the attachment to the plate 32 need not be considered.

  The absorber 34 is a plate-like member having a predetermined thickness, and is used to adjust the He ray irradiation depth, that is, the range, to the wafer 40 when the He 40 is irradiated with the He ray. Yes. The absorber 34 is a plate-like member in which no opening or the like is formed. For this reason, almost no contaminants are present in the absorber 34, and the contaminants are not irradiated onto the wafer 40 using the absorber as a contamination source during He-ray irradiation. The absorber 34 is disposed between the metal mask 33 and the plate 32, so that the wafer 40 is not exposed at least from the opening 33 a of the metal mask 33 by the absorber 34. In the case of the present embodiment, the absorber 34 is formed of a rectangular plate-like member, but may have other shapes such as a circular shape.

  The absorber 34 is sandwiched, for example, between the metal mask 33 and the plate 32 or the wafer 40 held on the plate 32. As described above, when the metal mask 33 and the plate 32 are sandwiched using a clip, the absorber 34 is also sandwiched so as to be sandwiched between them. Even when the metal mask 33 is held independently from the plate 32, the absorber 34 may be sandwiched between the metal mask 33 and the plate 32.

  The He line output unit 35 outputs He line as ion irradiation, and is arranged at a position facing the wafer 40 when the wafer 40 and the plate 32 are installed in the chamber 31. In the present embodiment, the He line output unit 35 that outputs He lines at a predetermined acceleration voltage is used. However, the acceleration voltage may be variable.

  The controller 36 adjusts the position of the metal mask 33 and also adjusts the position during alignment. The control unit 36 stores information on the adjustment position of the metal mask 33, that is, information on the XY coordinates on the XY plane and information on the angle θ in the circumferential direction centered on an arbitrary point on the XY plane as (x, y, θ). The position of the metal mask 33 can be adjusted according to the information.

  As described above, the He-ray irradiation device 30 is configured. Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. However, although only the He-ray irradiation method is different from the conventional method in the method of manufacturing the semiconductor device according to the present embodiment, it is the same as the conventional method except the He-ray irradiation method. For this reason, here, the He-ray irradiation method using the He-ray irradiation apparatus 30 configured as described above will be mainly described.

First, an N ⁻ type semiconductor substrate 10 is prepared, and a base layer 12, a body region 15, an emitter region 14 and a trench gate structure are formed on the surface side of the semiconductor substrate 10 by a well-known method. Then, the FS layer 20 and the collector layer 21 are formed on the back side of the semiconductor substrate 10, and then the He region is irradiated to form the damaged region 24.

  Specifically, the wafer 40 after the process of forming each part on the front surface side and the back surface side of the semiconductor substrate 10 as described above is prepared, and as shown in FIG. Attach to. Next, the metal mask 33 is disposed opposite to the wafer 40 and alignment is performed. For example, the element formation pattern formed on the wafer 40 is observed using infrared rays, and the position of the opening 33a of the metal mask 33 and the planned formation area of the damage area 24 in the wafer 40 are aligned based on this observation. Can be aligned. When infrared rays are used, since the element formation pattern can be observed through transmission, the metal mask 33 can be aligned by observing the pattern of the trench gate structure. Alternatively, an alignment mark may be provided on one surface of the wafer 40 on the side where the He-ray irradiation is performed, and the alignment between the metal mask 33 and the wafer 40 can be performed using the alignment mark as a reference. At this time, (x, y, θ) is stored as information on the adjustment position of the metal mask 33 when alignment is performed in the control unit 36.

  Thereafter, the metal mask 33 is separated from the plate 32 as shown in FIG. 3B, and the absorber 34 is disposed between the metal mask 33 and the wafer 40 as shown in FIG. Then, based on (x, y, θ), which is information regarding the adjustment position of the metal mask 33 stored in the control unit 36, the metal mask 33 is aligned again, and the metal mask 33 and the wafer 40 are installed. The absorber 34 is sandwiched between the plate 32 and the formed plate 32.

  In this way, even if the absorber 34 is arranged in front of the wafer 40, even if a portion serving as a reference for alignment such as an element formation pattern and an alignment mark of the wafer 40 cannot be confirmed, the metal mask 33 can be accurately obtained. Can be aligned.

  Then, by performing He line irradiation from the He line output unit 35, He line irradiation is performed on a desired position of the wafer 40 through the opening 33 a of the metal mask 33.

  Here, the thickness of the absorber 34 to be used is changed according to the He ray irradiation depth. That is, when the damaged region 24 is formed on the one surface 10a side of the semiconductor substrate 10, the He line irradiation is performed to a deeper position. Therefore, for example, as shown in FIG. 4A, when the damaged region 24 having a depth of 75 μm is formed when the thickness of the semiconductor substrate 10 is 90 μm, the thickness of the absorber 34 is set to 245 μm. Further, when the damaged region 24 is formed on the other surface 10b side of the semiconductor substrate 10, He line irradiation is performed at a relatively shallow position. Therefore, for example, when the damaged region 24 having a depth of 10 μm is formed when the thickness of the semiconductor substrate 10 is 90 μm as shown in FIG. 4B, the thickness of the absorber 34 is set to 290 μm. As described above, the absorber 34 has a relatively small thickness when it is desired to increase the He-ray irradiation depth, and the absorber 34 is thicker than that when it is desired to reduce the depth.

  Even when the thickness of the absorber 34 is changed in this way, it is necessary to replace the absorber 34. Therefore, it is necessary to remove the absorber 34 by separating the metal mask 33 from the plate 32. However, since (x, y, θ), which is information relating to the adjustment position of the metal mask 33, is stored in the control unit 36, the alignment of the metal mask 33 is accurately performed even when the absorber 34 is replaced with a different thickness. It becomes possible to take.

  As described above, in the present embodiment, He beam irradiation is performed in a state where the absorber 34 is disposed between the metal mask 33 and the wafer 40. For this reason, it is possible to prevent the contaminant attached when the opening 33a is formed in the metal mask 33 from being blocked by the absorber 34 and being irradiated to the wafer 40 side. Therefore, it is possible to suppress the contamination of the wafer, and it is also possible to suppress the cross contamination generated when the contaminated wafer 40 moves to the subsequent process.

  Further, before the absorber 34 is arranged, the metal mask 33 is aligned with the wafer 40, and the control unit 36 stores (x, y, θ), which is information relating to the adjustment position of the metal mask 33. For this reason, when the absorber 34 is disposed between the metal mask 33 and the wafer 40, only the position adjustment of the metal mask 33 is performed based on the information regarding the adjustment position of the metal mask 33 stored in the control unit 36. Thus, alignment can be accurately performed.

  Therefore, according to the manufacturing method of this embodiment, it is possible to accurately align the metal mask while suppressing the contaminants from being irradiated onto the wafer.

  Second Embodiment A second embodiment will be described. This embodiment is different from the first embodiment because the arrangement method of the metal mask 33, the absorber 34, and the plate 32 is changed with respect to the first embodiment, and the other is the same as the first embodiment. Only the part will be described.

  In the present embodiment, the alignment of the metal mask 33 can be accurately obtained without storing the information regarding the adjustment position of the metal mask 33 in the control unit 36.

  Specifically, as shown in FIG. 5A, when the alignment of the metal mask 33 with respect to the wafer 40 is performed, the distance between the wafer 40 and the metal mask 33 is set to be equal to or greater than the thickness of the absorber 34. . For example, if the thickness of the absorber 34 is about 310 μm, the distance between the wafer 40 and the metal mask 33 is set to 310 μm or more. For the alignment, the same method as in the first embodiment can be applied.

  Then, after aligning the metal mask 33, the absorber 34 is inserted between the metal mask 33 and the wafer 40 as shown in FIG. At this time, since a gap larger than the thickness of the absorber 34 is provided between the metal mask 33 and the wafer 40, the absorber 34 is inserted between the metal mask 33 and the wafer 40 without moving the metal mask 33. it can. The subsequent steps are the same as in the first embodiment.

  Thus, if the distance between the metal mask 33 and the wafer 40 is equal to or greater than the thickness of the absorber 34, the metal mask 33 is not moved after the metal mask 33 is aligned. And the wafer 40 can be inserted. Therefore, the metal mask 33 can be accurately aligned, and the same effect as that of the first embodiment can be obtained.

  (Third Embodiment) A third embodiment will be described. In the present embodiment, the metal mask 33 is provided with the function of the absorber 34 with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment are described. explain.

  The metal mask 33 used in the method for manufacturing a semiconductor device of this embodiment shown in FIG. 6A also has the function as the absorber 34 described in the first embodiment. Specifically, the metal mask 33 does not include the opening 33a for He-ray irradiation described in the first embodiment, but instead includes a recess 33b at the position of the opening 33a. The recess 33b is formed in order to partially thin the metal mask 33, and the thickness of the metal mask 33 is equivalent to the absorber 34 at the bottom of the recess 33b.

  In the present embodiment, an alignment hole 33c that is a through hole is formed at a location different from the concave portion 33b in the metal mask 33, more specifically at a position on the outer peripheral side of the portion of the wafer 40 that is a chip. ing. Through this alignment hole 33c, the metal mask 33 can be aligned with the wafer 40. For example, an alignment mark formed on the wafer 40 can be confirmed through the alignment hole 33c.

  Further, as shown in FIG. 6B, a spacer 37 is provided between the metal mask 33 and the wafer 40 so as to be sandwiched between the metal mask 33 and the wafer 40 after the alignment of the metal mask 33. Yes. The spacer 37 is formed in, for example, an annular shape, is sandwiched between the metal mask 33 and the wafer 40 so that the metal mask 33 does not contact the wafer 40, covers the alignment hole 33c, and extends from the alignment hole 33c to the wafer 40. So that it is not exposed.

  In this way, the metal mask 33 also has a function as the absorber 34. Even if the contaminant is attached to one surface of the metal mask 33 where the recess 33b is formed, the contaminant is hardly attached to the opposite surface. For this reason, even if He beam irradiation is performed through the metal mask 33, contamination on the wafer 40 can be suppressed.

  Further, the alignment can be accurately achieved by forming the alignment hole 33c in the metal mask 33. Then, the wafer 40 is prevented from coming into contact with the metal mask 33 while the exposure of the wafer 40 from the alignment hole 33c is suppressed by the spacer 37 during the He line irradiation. For this reason, even if He beam irradiation is performed through the metal mask 33, contamination on the wafer 40 can be suppressed.

  (Other embodiment) This invention is not limited to above-described embodiment, In the range described in the claim, it can change suitably.

  For example, in the above-described embodiment, He line irradiation has been described as an example of lifetime control. However, the lifetime is not limited to He line, and other lifetimes such as irradiation of light ions such as hydrogen are performed. The present invention can also be applied to control.

  In addition, as an example of a method for manufacturing a semiconductor device, an example provided with an IGBT has been described. However, the present invention can also be applied to a semiconductor device including another element to which ion irradiation is performed, for example, a diode. Of course, the present invention can also be applied to a semiconductor device provided with an FWD in addition to the IGBT.

  Moreover, the material, the shape, etc. of each part which comprises the He beam irradiation apparatus 30 demonstrated by each said embodiment showed only an example, and can be changed suitably. For example, although the case where the plate 32, the metal mask 33, and the absorber 34 are comprised with aluminum was demonstrated, you may comprise with another material. For example, the absorber 34 can be configured by silicon (Si) or silicon carbide (SiC). When the absorber 34 is made of SiC, since SiC optically transmits light, the metal mask 33 should be aligned while the absorber 34 is sandwiched between the metal mask 33 and the wafer 40. Is also possible. For this reason, it becomes possible to align the metal mask 33 more accurately.

  Further, the above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible. For example, the spacer 37 described in the third embodiment may be disposed between the absorber 34 and the wafer 40 in the first and second embodiments so that the absorber 34 does not contact the wafer 40.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 23 Damaged area 30 He line | wire irradiation apparatus 32 Plate 33 Metal mask 33a Opening part 33b Recessed part 33c Alignment hole 34 Absorber 36 Control part

Claims (1)

A method for manufacturing a semiconductor device, comprising:
Preparing a wafer (40) constituting a semiconductor substrate (10) on which a semiconductor device is formed;
Performing ion irradiation on the wafer using an ion irradiation apparatus (30) to form a damage region (24) at a position at a predetermined depth of the semiconductor substrate,
In forming the damage area,
Holding the wafer in a wafer holder (32) and disposing a metal mask (33) provided with an opening (33a) opposite the wafer;
The control unit (36) adjusts the position of the metal mask to align the metal mask with respect to the wafer, and controls the information regarding the adjustment position of the metal mask when the alignment is performed. Remembering in the department,
An absorber (34) for adjusting the ion irradiation depth is disposed between the metal mask and the wafer, and the control unit is configured to align the metal mask with the adjustment position stored in the controller. And doing
A method of manufacturing a semiconductor device, wherein after the alignment, the ion irradiation is performed through the metal mask and the absorber in a state where the absorber is sandwiched between the metal mask and the wafer.

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