JP6583111B2 - Arithmetic unit - Google Patents

Description

  The present invention relates to an arithmetic device that repeatedly executes an addition comparison selection operation.

  In recent years, there has been an increasing need for distance measurement and recognition processing using an in-vehicle camera in order to prevent automobile accidents and to enable automatic driving. Since an in-vehicle image processing apparatus is an embedded system, it is necessary to realize processing within a required time with limited performance and resources. For example, a stereo camera is difficult in principle to measure an object with few patterns. For this reason, a technique that can robustly detect a road surface having a weak pattern by introducing a global method that takes into account the smoothness of the entire parallax image has been developed in recent years. As such a main method, there is a method for determining a parallax combination that minimizes the overall cost by a kind of dynamic programming called a Viterbi (hereinafter referred to as Viterbi) algorithm.

  As the amount of calculation of the Viterbi algorithm, as the transition state, that is, the number of nodes increases, the amount of processing increases exponentially. In the case of a stereo camera, the number of transition states is equal to the number of parallaxes (usually several tens to several hundreds or more), so that the amount of calculation increases. For such a problem, paying attention to the algorithm and reusing the result of the adjacent transition state that has already been calculated, the calculation amount that was proportional to the square of the number of nodes in the past can be doubled. There has been considered a method for realizing a reduction in the amount of calculation (see, for example, Patent Document 1). According to such a method, the processing time can be shortened. However, in order to realize the above processing in a built-in environment such as an in-vehicle environment over several million pixels of a stereo camera, further speedup is required. .

JP 2015-114269 A JP 2014-045480 A

  To solve the problem of speeding up Viterbi operations, a dedicated circuit in which addition, comparison, and selection (hereinafter referred to as ACS) circuits, which are basic processing elements of Viterbi operations, are connected in series has been proposed (for example, see Patent Document 2). ). According to this method, compared with the case where a single ACS circuit is used recursively, it can be expected to increase the speed by reducing the processing time overhead in clock transfer. However, in this case, the number of stages of ACS circuits that pass through has not decreased, and there is a limit to improving the throughput.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an arithmetic device capable of realizing high-speed calculation while maintaining good calculation accuracy.

According to the first aspect of the present invention, the arithmetic device (12) executes arithmetic processing using the previous arithmetic result for each of the plurality of input data in a predetermined order. The calculation process compares any one of the plurality of input data with data obtained by adding a predetermined constant to the previous calculation result, and selects a value satisfying a predetermined condition from each of the data Thus, the addition comparison selection calculation is output as the calculation result. The arithmetic device divides a series of arithmetic processes for a plurality of input data into a plurality of parts in the order described above, and a division unit (21, 22, 31 to 34) that executes each in parallel, and the order is adjacent to 2 Out of the two division units, the calculation results output from the last stage of the previous division unit are collectively compared with the calculation results output from the respective division units of the later division unit, and the predetermined condition is satisfied. And an integration unit (23, 35, 41) that executes an integration process for selecting and outputting values .

  According to such a configuration, since a series of arithmetic processing is divided into a plurality of pieces and executed in parallel, the time required for the arithmetic processing is shortened compared to a case where the series of arithmetic processing is sequentially processed. Further, since the integration unit is provided, the calculation result output from the division unit having the next order also takes into consideration the calculation result in the division unit having the previous order, and the calculation does not become inaccurate. Therefore, according to the present means, it is possible to realize high-speed calculation while maintaining good calculation accuracy.

The figure which shows typically the structure of the distance detection apparatus which concerns on 1st Embodiment. The figure which shows the specific structure of a process part typically. A flowchart schematically showing the contents of the distance calculation process The figure which shows the structure of the cost correction processing circuit typically The figure which shows the structure of the ACS circuit in a division part typically The figure which shows the structure of the ACS circuit in an integrated part typically The figure which shows typically the 1st structural example of the cost correction processing circuit which concerns on 2nd Embodiment. The figure which shows typically the 2nd structural example of the cost correction processing circuit which concerns on 2nd Embodiment.

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
A distance detection device 1 illustrated in FIG. 1 is a device that detects a distance to each point in a captured image by detecting parallax of a plurality of captured images. The distance detection device 1 is designed so that the correspondence between pixels constituting a plurality of captured images, that is, parallax can be obtained with high accuracy by applying the Viterbi algorithm, which is a dynamic programming method, in a plurality of directions. ing.

  The distance detection device 1 is mounted on a vehicle such as a passenger car, and includes two imaging units 2 and 3, a processing unit 4, and a vehicle control unit 5. The imaging units 2 and 3 are not limited to two, and for example, three or more imaging units may be provided. The imaging units 2 and 3 are each configured as a known camera in which the traveling direction of the vehicle is within the imaging range. The imaging units 2 and 3 constitute a stereo camera, and are set so as to perform simultaneous and periodic imaging.

  The processing unit 4 acquires captured images captured by the imaging units 2 and 3 and executes various processes described later. The vehicle control unit 5 executes processing for controlling the vehicle using the processing result obtained by the processing unit 4. For example, the vehicle control unit 5 acquires distance information at each point in the imaging range by the imaging units 2 and 3 from the processing unit 4, and recognizes the target position and the relative speed based on the distance information. And the vehicle control part 5 performs vehicle control, such as changing a driving | running track, when there exists a possibility that a target may interfere with driving | running | working.

  The function of the processing unit 4 can be realized by, for example, a configuration as shown in FIG. That is, in this case, the processing unit 4 includes a CPU 7, a DMA controller 8, a main memory 9, and a dedicated accelerator 10 that are communicably connected via the bus 6. The dedicated accelerator 10 includes a program control unit 11, a cost correction processing circuit 12, other arithmetic circuits 13, a load / store control circuit 14, a local memory 15, and a data register 16.

  The basic operation and function of the above configuration are as follows. That is, the host CPU 7 notifies the dedicated accelerator 10 of a target processing request. Data to be processed is sequentially transferred from the main memory 9 to the local memory 15 of the dedicated accelerator 10 via the DMA controller 8.

  The program control unit 11 reads a target processing program based on a processing request from the CPU 7 and transmits a control signal for specifying a target process, a target register, and the like to each circuit. The load / store control circuit 14 loads or stores an array in units of a plurality of data from the local memory 15 based on the control signal.

  The cost correction processing circuit 12 and the other arithmetic circuit 13 read and process the data of the target register based on the control signal, and write back to the register. When the processing program is completed, the program control unit 11 transfers a completion notification to the CPU 7 and the DMA controller 8. Further, the completed processing data is transferred from the local memory 15 to the main memory 9 via the DMA controller 8. Thereafter, the host CPU 7 determines the next processing and transfers the next processing request to the dedicated accelerator 10. The processing unit 4 executes various processes by repeating the above operation.

  In the distance detection device 1 of the present embodiment, the processing unit 4 performs the same processing as the distance calculation processing disclosed in Japanese Patent Laid-Open No. 2015-114269 (hereinafter also referred to as Literature 1). That is, as shown in FIG. 3, first, in step S1, captured images captured by the imaging units 2 and 3 are acquired. In the subsequent step S2, processing such as correction of image distortion or posture deviation by the lens of the captured image is performed, and the captured image is collimated.

  In step S3, a corresponding point search process is performed. In the corresponding point search process, for example, the correspondence between each pixel constituting a reference image that is a captured image by the imaging unit 2 and each pixel that constitutes a comparison image that is a captured image by the imaging unit 3, for example, the same thing is captured. The process of associating locations. Since the specific content of the corresponding point search processing is disclosed in Document 1, description thereof is omitted here. Subsequently, in step S4, the distance to the target shown in each pixel is calculated according to the parallax of the corresponding point in each pixel. In step S <b> 5, correspondence data between these pixels and distances is output to the vehicle control unit 5.

  However, in the present embodiment, further speeding up of the calculation is realized by adding a device as described below to the corresponding point search processing. In other words, in the corresponding point search process of Literature 1, the round-robin calculation is reiterated to repeat the binary comparison by reusing the previous minimum cost result, thereby reducing the processing load. The inventor of the present application sets “s (u, v) = uv” in Document 1, but linearity is maintained if “s (u, v) = λ | uv |”. I found out. Where λ is a predetermined constant. In this case, λ is added to the previous result and compared with the value of the next node, and the smaller value is used as the next result. That is, in this case, the ACS operation is a basic repeating unit.

  Here, when using the conventional technology in which ACS circuits for performing ACS operations are connected in series, the operation and selection using the previous result are repeatedly processed in series, that is, sequentially processed. The effect of speed reduction due to circuit delay and the like is large. Therefore, it can be considered that such sequential processing is divided and executed in parallel. However, there is a concern that if the sequential processing in which the calculation result depends on the subsequent calculation is simply divided and parallelized, the calculation becomes inaccurate and the accuracy is lowered.

  In consideration of these points, in this embodiment, on the premise of introducing the linearity of the transition cost, the circuit that performs the sequential processing is divided into a plurality of blocks and operated in parallel, and each of the blocks that are operated in parallel The results were compared and integrated. Specifically, the cost correction processing circuit 12 of the present embodiment has a configuration as shown in FIG. Note that the cost correction processing circuit 12 corresponds to an arithmetic device that executes arithmetic processing using the previous arithmetic result for each of a plurality of input data in a predetermined order.

  The cost correction processing circuit 12 divides a circuit that performs sequential processing into a first-half division unit 21 and a second-half division unit 22 and performs parallel processing, and finally, the integration unit 23 integrates the results of the respective stages. In the following, each data of the input data array input to the cost correction processing circuit 12 is referred to as input data [1], input data [2],..., Input data [N], and the cost correction processing circuit 12 The data of the output data array output from is called output data [1], output data [2],..., Output data [N]. In the present embodiment, the number N of these data is an even number.

  The first-half division unit 21 includes ACS circuits 24 [2] to 24 [N / 2] that use the input data [2] to [N / 2] as input data, respectively. The latter half division unit 22 includes ACS circuits 24 [N / 2 + 2] to 24 [N] that use the input data [N / 2 + 2] to [N] as input data, respectively. Hereinafter, the ACS circuit 24 [2] to the ACS circuit 24 [N] may be collectively referred to as the ACS circuit 24.

  The ACS circuit 24 has a configuration as shown in FIG. That is, the ACS circuit 24 includes an adder 25 and a comparison selector 26. The adder 25 adds a constant λ to the calculation result output from the previous stage. In this embodiment, the constant λ is a positive value, and the adder 25 performs pure addition. Further, the value of the constant λ can be changed as appropriate by register setting or the like. The comparison selector 26 compares the output data of the adder 25 with the input data at the main stage, selects a value satisfying a predetermined condition from the data, and outputs the selected value as a calculation result at the main stage. Specifically, the comparison selector 26 selects the smaller value of each data and outputs it as the operation result of this stage.

  For example, the ACS circuit 24 [2] adds the constant λ to the input data [1] and compares it with the input data [2], and outputs the smaller value as the operation result of the main stage and the ACS of the next stage. Output to the circuit 24 [3] as the previous calculation result. Then, the ACS circuit 24 [3] in the next stage adds a constant λ to the operation result in the previous stage output from the ACS circuit 24 [2] and compares it with the input data [3]. While outputting as the calculation result of this stage, it outputs as the calculation result of the previous stage to the ACS circuit 24 [4] of the next stage.

  Further, the ACS circuit 24 [N / 2 + 2] adds a constant λ to the input data [N / 2 + 1] and compares it with the input data [N / 2 + 2], and uses the smaller value as the operation result of this stage. And output to the next stage ACS circuit 24 [N / 2 + 3] as the calculation result of the previous stage. Then, the next stage ACS circuit 24 [N / 2 + 3] adds the constant λ to the previous stage calculation result output from the ACS circuit 24 [N / 2 + 2] and compares it with the input data [N / 2 + 3]. The smaller value is output to the integration unit 23 as the calculation result of the main stage and is output as the calculation result of the previous stage to the ACS circuit 24 [N / 2 + 4] of the next stage.

  In such a configuration, the input data [1] becomes the output data [1] as it is, and the calculation results output from the ACS circuits 24 [2] to 24 [N / 2] included in the first division unit 21 are respectively output. Data [2] to [N / 2]. However, the calculation result output from the ACS circuit 24 [N / 2] is also given to the integration unit 23.

  The integrating unit 23 includes ACS circuits 27 [N / 2 + 1] to 27 [N] that use the output of each stage of the dividing unit 22 as input data. Hereinafter, the ACS circuit 27 [N / 2 + 1] to the ACS circuit 27 [N] may be collectively referred to as the ACS circuit 27.

  The ACS circuit 27 is configured as shown in FIG. In other words, the ACS circuit 27 includes an adder 28 and a comparison selector 29. The adder 28 adds α to the result of the last stage of the first half, that is, the calculation result output from the ACS circuit 24 [N / 2]. α is a value obtained by multiplying a number representing the order in the latter half by a constant λ.

For example, in the case of the ACS circuit 27 [N / 2 + 1], the order in the second half is “1”, so “α = 1 × λ”. In the case of the ACS circuit 27 [N / 2 + 2], the order in the second half is “2”. Therefore, “α = 2 × λ”, and in the case of the ACS circuit 27 [N], since the order in the latter half is “N / 2”, “α = (N / 2) × λ”. Therefore, when the ACS circuit 27 [X] is used, α is expressed by the following (1).
α = (X−N / 2) × λ (1)

  The comparison selector 29 compares the output data of the adder 28 with the calculation result output from each stage of the dividing unit 22 and outputs the smaller value as the final result of each stage in the latter half. For example, the ACS circuit 27 [N / 2 + 1] adds α (= 1 × λ) to the calculation result of the final stage of the first half and compares it with the input data [N / 2 + 1], and the smaller value is compared with that of the main stage. The final result is output as output data [N / 2 + 1]. Further, the ACS circuit 27 [N / 2 + 2] adds α (= 2 × λ) to the operation result of the last stage of the first half, and is smaller than the operation result output from the ACS circuit 24 [N / 2 + 2]. This value is output as the final result of this stage, that is, as output data [N / 2 + 2].

  The integration unit 23 having such an ACS circuit 27 has data proportional to the calculation result of the final stage of the dividing unit 21 (= output data of the adder 28) and the calculation output from each stage of the dividing unit 22. The result is compared, and the smaller value is output as the final result of each stage in the latter half of the series of ACS calculation processes. That is, the integration unit 23 integrates the operation results output from the final stage of the first division unit 21 for each calculation result output from each stage of the second division unit 22. Yes.

According to this embodiment described above, the following effects can be obtained.
The cost correction processing circuit 12 according to the present embodiment executes the ACS operation using the previous operation result for each of the input data [1] to [N] in the input data array according to the order of the input data array. Then, the cost correction processing circuit 12 divides a series of ACS calculation processes for a plurality of input data [1] to [N] into the first half and the second half along the above-described order, and executes division units 21 and 22 that execute each in parallel. And an integration unit 23 that collectively compares and integrates the calculation results output from the final stage of the first-half division unit 21 for each calculation result output from each stage of the second-half division unit 22. .

  According to such a configuration, since a series of ACS arithmetic processing is divided into two and executed in parallel, a reduction in circuit delay or the like is expected compared to a case where a series of ACS arithmetic processing is sequentially processed. As a result, the time required for the arithmetic processing is reduced to about half. In addition to simply parallelizing a series of ACS calculation processes, since the integration unit 23 is provided, the calculation result in the first division unit 21 is also taken into account for the calculation result output from the second division unit 22. Therefore, there is no possibility that the calculation becomes inaccurate. Therefore, according to the present embodiment, it is possible to realize high-speed calculation while maintaining good calculation accuracy. Such an effect of speeding up the operation, that is, reducing the processing time, is more beneficial in an embedded environment such as a vehicle.

(Second Embodiment)
In the first embodiment, the cost correction processing circuit 12 divides a series of ACS arithmetic processing for a plurality of input data [1] to [N] into two parts, the first half and the second half, but this division number is three. That's all. In the present embodiment, two configuration examples obtained by dividing a series of ACS calculation processes into four will be described with reference to FIGS. 7 and 8.

<First configuration example>
As shown in FIG. 7, in the first configuration example, a series of ACS arithmetic processing is divided into four division units 31 to 34 in the order of the input data array and processed in parallel. Integrate the results. The dividing unit 31 includes ACS circuits 24 [2] to 24 [N / 4] that use the input data [2] to [N / 4] as input data, respectively. The dividing unit 32 includes ACS circuits 24 [N / 4 + 2] to 24 [N / 2] that use the input data [N / 4 + 2] to [N / 2] as input data, respectively.

  The dividing unit 33 includes ACS circuits 24 [N / 2 + 2] to 24 [3N / 4] that use the input data [N / 2 + 2] to [3N / 4] as input data, respectively. The dividing unit 34 includes ACS circuits 24 [3N / 4 + 2] to 24 [N] that use the input data [3N / 4 + 2] to [N] as input data, respectively.

  In such a configuration, the input data [1] becomes the output data [1] as it is, and the calculation results output from the ACS circuits 24 [2] to 24 [N / 4] included in the dividing unit 31 are output data [1]. 2] to [N / 4]. However, the calculation result output from the ACS circuit 24 [N / 4] is also given to the integration unit 35.

  The integration unit 35 includes a first integration block 35a, a second integration block 35b, and a third integration block 35c. The first integrated block 35a includes ACS circuits 27 [N / 4 + 1] to 27 [N / 2] that use the output of each stage of the dividing unit 32 as input data. The adders 28 of the ACS circuits 27 [N / 4 + 1] to 27 [N / 2] add α to the result of the final stage of the dividing unit 31, that is, the calculation result output from the ACS circuit 24 [N / 4]. It is like that. Therefore, the first integrated block 35a compares the data proportional to the calculation result of the final stage of the dividing unit 31 and the calculation result output from each stage of the dividing unit 32, and calculates the smaller value. Select and output as output data [N / 4 + 1] to [N / 2].

  The second integrated block 35b includes ACS circuits 27 [N / 2 + 1] to 27 [3N / 4] that use the output of each stage of the dividing unit 33 as input data. The adders 28 of the ACS circuits 27 [N / 2 + 1] to 27 [3N / 4] add α to the result of the final stage of the first integrated block 35a, that is, the operation result output from the ACS circuit 27 [N / 2]. It comes to add. Therefore, the second integrated block 35b is proportional to the output data [N / 2] that is the calculation result after being output from the final stage of the dividing unit 32 and being integrated via the first integrated block 35a. The data is compared with the calculation result output from each stage of the dividing unit 33, and the smaller value is selected and output as output data [N / 2 + 1] to [3N / 4].

  The third integrated block 35c includes ACS circuits 27 [3N / 4 + 1] to 27 [N] that use the output of each stage of the dividing unit 34 as input data. The adders 28 of the ACS circuits 27 [3N / 4 + 1] to 27 [N] add α to the result of the final stage of the second integrated block 35b, that is, the calculation result output from the ACS circuit 27 [3N / 4]. It is like that. Therefore, the third integrated block 35c is in a proportional relationship with the output data [3N / 4] that is the calculation result output from the final stage of the dividing unit 33 and integrated through the second integrated block 35b. The data is compared with the calculation result output from each stage of the dividing unit 34, and the smaller value is selected and output as output data [3N / 4 + 1] to [N].

  As described above, the integration unit 35 of the first configuration example performs the integration process by combining the first and second division units 31 and 32 in order, and each stage of the division units 33 and 34 in the third and subsequent orders. For each of the calculation results output from, the calculation results output from the division unit one order earlier than them and integrated after the integration processing are collectively compared and output as the final result It has become. In this case, the integration unit 35 has three stages in the order of “(1) integration by the first integration block 35a → (2) integration by the second integration block 35b → (3) integration by the third integration block 35c”. Integration processing will be performed.

<Second configuration example>
As shown in FIG. 8, in the second configuration example, as in the first configuration example, a series of ACS calculation processing is divided into four division units 31 to 34 in the order of the input data array, and is processed in parallel. Finally, the result of each stage is integrated by the integration unit 41. The integration unit 41 includes a first integration block 41a, a second integration block 41b, and a third integration block 41c.

  The first integrated block 41a has the same configuration as the first integrated block 35a of the first configuration example. Therefore, the first integrated block 41a compares the data proportional to the calculation result of the final stage of the dividing unit 31 and the calculation result output from each stage of the dividing unit 32, and calculates the smaller value. Select and output as output data [N / 4 + 1] to [N / 2].

  The second integrated block 41b includes ACS circuits 27 [3N / 4 + 1] to 27 [N] that use the output of each stage of the dividing unit 34 as input data. The adders 28 of the ACS circuits 27 [3N / 4 + 1] to 27 [N] add α to the result of the final stage of the dividing unit 33, that is, the calculation result output from the ACS circuit 24 [3N / 4]. It has become. Therefore, the second integrated block 41b compares the data proportional to the calculation result of the final stage of the dividing unit 33 and the calculation result output from each stage of the dividing unit 34, and calculates the smaller value. Select and output.

  The third integrated block 41c receives ACS circuits 27 [N / 2 + 1] to 27 [3N / 4] using the outputs of the respective stages of the dividing unit 33 as input data, and the outputs of the respective stages of the second integrated block 41b. ACS circuits 42 [3N / 4 + 1] to 42 [N] serving as input data are provided. Note that the ACS circuits 42 [3N / 4 + 1] to 42 [N] have the same configuration as the ACS circuit 27. Hereinafter, the ACS circuits 42 [3N / 4 + 1] to 42 [N] may be collectively referred to as the ACS circuit 42.

  The adders 28 of the ACS circuits 27 [N / 2 + 1] to 27 [3N / 4] and the ACS circuits 42 [3N / 4 + 1] to 42 [N] are the result of the final stage of the first integrated block 41a, that is, the ACS circuit 27. Α is added to the calculation result output from [N / 2]. Therefore, the third integrated block 41c is proportional to the output data [N / 2], which is the calculation result after being output from the final stage of the dividing unit 32 and integrated via the first integrated block 41a. The data is compared with the calculation result output from each stage of the dividing unit 33, and the smaller value is selected and output as output data [N / 2 + 1] to [3N / 4]. Further, the third integrated block 41c calculates data after being output from each stage of the dividing unit 34 and being integrated via the second integrated block 41b, with data proportional to the output data [N / 2]. The result is compared, and the smaller value is selected and output as output data [3N / 4 + 1] to [N].

  As described above, the integration unit 41 of the second configuration example performs integration processing by combining two division units 31 and 32 that are adjacent in order, and also sets two division units 33 and 34 that are adjacent in order. Perform integration processing. The integration unit 41 further performs integration processing on the two sets that have been subjected to integration processing, and outputs the result as a final result. In this case, the integration unit 41 performs integration processing in two stages in the order of “(1) integration by the first integration block 41a and integration by the second integration block 41b → (2) integration by the third integration block 41c”. Will be done.

  According to the present embodiment described above, as in the first embodiment, it is possible to realize high-speed calculation while maintaining good calculation accuracy. Each of the first configuration example and the second configuration example has merits. That is, the integration unit 35 of the first configuration example can reduce the number of ACS circuits as compared with the integration unit 41 of the second configuration example, and thus the circuit scale can be reduced. Further, the integration unit 41 of the second configuration example can suppress the number of stages passing through the ACS circuit to be smaller than that of the integration unit 35 of the first configuration example, so that the time required for the arithmetic processing can be further shortened. Therefore, when the number of divisions in a series of ACS calculation processes is set to 4 or more, an optimum configuration may be used so as to satisfy specifications such as a circuit scale and a processing time in consideration of such points.

(Other embodiments)
In addition, this invention is not limited to each embodiment described above and described in drawing, In the range which does not deviate from the summary, it can change, combine or expand arbitrarily.
In each of the above embodiments, the ACS operation is “addition → minimum comparison”, but may be “subtraction → maximum comparison”. That is, in each of the above embodiments, the constant λ is a positive value, but it may be a negative value. Then, the adders 25 and 28 substantially perform subtraction. In this case, the comparison selectors 26 and 29 may select the larger one of the two input values and output it as a calculation result. That is, in this case, the larger value is “a value that satisfies a predetermined condition”.
In each of the above embodiments, when dividing a series of ACS calculation processes, each division unit is equally divided, but it is not always necessary to equally divide. In each of the above embodiments, the number of data N in the input data array is an even number, but the number of data N may be an odd number.

In each of the embodiments described above, a series of ACS calculation processes are divided into a plurality along the order of the input data array. However, the present invention is not limited to this, and may be divided into a plurality according to a predetermined order.
Of the ACS circuits of the integration units 23, 35, and 41, it is possible to omit the subsequent stage portion. For example, if the data on the adder side is determined not to be the minimum value in the comparison and selection in the predetermined ACS circuit in the integration unit and is temporarily rejected, the data on the adder side is always used in the comparison and selection in the subsequent ACS circuit. Is rejected. Therefore, if it is known in advance through experiments or simulations that the data on the adder side is rejected with a very high probability at a certain point in the latter half of the integration unit, the ACS circuit is omitted thereafter, and It is also possible not to perform a process of collectively comparing the calculation results. In this way, it is possible to reduce the circuit scale. Even in such a case, the accuracy of the calculation is not greatly reduced.

  12 ... Cost correction processing circuit, 21, 22, 31-34 ... division unit, 23, 35, 41 ... integration unit.

Claims (4)

An arithmetic device (12) that executes arithmetic processing using a previous operation result according to a predetermined order for each of a plurality of input data,
The calculation process compares any one of the plurality of input data with data obtained by adding a predetermined constant to the previous calculation result, and sets a value satisfying a predetermined condition among the data. It is an addition comparison selection operation that is selected and output as the operation result.
A division unit (21, 22, 31 to 34) that divides a series of the arithmetic processing on the plurality of input data into a plurality of pieces along the order and executes them in parallel;
Comparing the operation results output from the last stage of the division unit with the previous order for each operation result output from each stage of the division unit with the next order among the two division units having the adjacent order. An integration unit (23, 35, 41) for executing an integration process of selecting and outputting values satisfying a predetermined condition ;
An arithmetic device comprising: The dividing unit (21, 22) divides a series of the arithmetic processing for the plurality of input data into two parts of the first half and the second half of the order, and executes each in parallel.
The integration unit (23) preliminarily compares a calculation result output from the final stage of the first half of the division unit with a predetermined condition for each of the calculation results output from the second stage of the division unit. The arithmetic unit according to claim 1, wherein a value satisfying the condition is selected and output . The division unit (31 to 34) divides a series of the arithmetic processing for the plurality of input data into three or more along the order, and executes each in parallel.
The integration unit (35) outputs the integration result output from the division unit one order earlier than the division unit with respect to each of the calculation results output from each stage of the division unit after the third order. The arithmetic unit according to claim 1, wherein the calculation results after the operation are performed are collectively compared and a value satisfying a predetermined condition is selected and output . The division unit (31 to 34) divides a series of the arithmetic processing for the plurality of input data into three or more along the order, and executes each in parallel.
The integration unit (41) performs the integration process on a group of two division units adjacent to each other in the order, and further performs a combination on two groups adjacent in the order among the groups on which the integration process is executed. The arithmetic device according to claim 1, wherein the integration process is executed.

Images