JP6584802B2 - Analog signal processor - Google Patents

Description

The present invention relates to an analog signal processing apparatus that receives analog signals of a plurality of channels, performs predetermined processing based on these signals, and outputs processing results to the outside.

  Patent Document 1 discloses an analog signal input device that controls an external device by calculating a control output (control signal) according to an analog signal captured from the outside and outputting the control output as a calculation result to the outside. Has been. This analog signal input device has a diagnostic function, and can diagnose a failure including an analog input circuit and an A / D converter with high accuracy and versatility.

JP 2012-39423 A

  However, the technique of Patent Document 1 is based on the premise that a single analog signal is input and processed, and it is necessary to input a plurality of channels of analog signals and perform predetermined arithmetic processing based on these signals. I can not cope with the case. Therefore, it is impossible to obtain a phase difference, a level difference, calculation data, and the like between analog signals of a plurality of channels and output the calculation result to an external device for control.

The present invention has been made in view of the circumstances as described above, and its object is to perform analog processing by inputting analog signals of a plurality of channels, and analog signal processing capable of diagnosing the calculation results. To provide an apparatus.

The analog signal processing apparatus of the present invention includes an arithmetic unit configured to perform predetermined arithmetic processing on an input analog signal, and outputs an arithmetic processing result to the outside. A processing device is provided that includes a diagnostic unit that performs a cross-system comparison of arithmetic processing and processing results executed in each system and diagnoses that the arithmetic unit is normal when they are consistent or within an allowable range . It is characterized by that.

In the present invention, in an analog signal processing device having a multiple system configuration composed of a plurality of systems, arithmetic processing executed in each system and inter-system verification of processing results are performed, and when they match or are within an allowable range In addition, it can be diagnosed that the computing means is operating normally.

It is a block diagram which shows the analog signal input device which concerns on embodiment of this invention. FIG. 2 is a waveform diagram of two analog signals input to the analog signal input device illustrated in FIG. 1 and a digital signal output from a CPU. 3 is a flowchart showing level detection operations of two analog signals in the analog signal input device shown in FIG. 1. 2 is a flowchart showing a phase difference detection operation of two analog signals in the analog signal input device shown in FIG. 1. It is a flowchart which shows the diagnostic operation | movement of the arithmetic circuit in the analog signal input device shown in FIG. It is a flowchart which shows the diagnostic operation | movement of the A / D converter in the analog signal input device shown in FIG. It is a flowchart which shows the diagnostic operation | movement of the system power supply in the analog signal input device shown in FIG. 2 is a flowchart showing a diagnosis operation of an inter-system level difference in the analog signal input device shown in FIG. 1.

Embodiments of the present invention will be described below with reference to the drawings.
The analog signal input device shown in FIG. 1 shows a specific example of an analog signal processing device, which corresponds to a 2-channel analog input and has a dual system configuration of an A system and a B system. Then, the levels of the analog signals A1 and A2 and the phase difference between the analog signals A1 and A2 are calculated and output to an external device. The analog signal input device is provided with various diagnostic functions. For example, high fail-safety is ensured so that the analog signal input device can be used when detecting the presence of a train in a track circuit.

  The A-system circuit unit 100 includes analog input circuits 1a and 2a, a multiplexer 3a, a power supply IC 4a, an MCU (Micro Controller Unit) 5a, an arithmetic circuit 6a, and the like. The MCU 5a functions as a determination control unit, and includes an A / D converter 7a, a CPU (Central Processing Unit) 8a, buffers 9a and 10a, and a D / A converter 11a. The B-system circuit unit 200 has a similar circuit configuration, and includes analog input circuits 1b and 2b, a multiplexer 3b, a power supply IC 4b, an MCU 5b, an arithmetic circuit 6b, and the like. The MCU 5b functions as a determination control unit, and includes an A / D converter 7b, a CPU 8b, buffers 9b and 10b, and a D / A converter 11b.

  The analog input signals A1 and A2 are input to the analog input circuits 1a and 2a of the A system circuit unit 100 and the analog input circuits 1b and 2b of the B system circuit unit 200, respectively. The analog input signals A1 and A2 input to the analog input circuits 1a and 2a are supplied to the multiplexer 3a, and the analog input signals A1 and A2 input to the analog input circuits 1b and 2b are supplied to the multiplexer 3b.

  In addition to the analog signals A1 and A2 output from the analog input circuits 1a and 2a, the multiplexer 3a includes the output signal of the arithmetic circuit 6a and the diagnostic signal of the A / D converter 7a output from the D / A converter 11a. And a system power supply diagnosis signal (power supply voltage Vcc) are supplied, and one of them is selected and supplied to the A / D converter 7a under the control of the CPU 8a. The A / D converter 7a is supplied with the reference voltage VREFa from the power supply IC 4a. Based on the reference voltage VREFa, the input is converted from analog to digital and supplied to the CPU 8a. As a result, the CPU 8a acquires signals obtained by analog / digital conversion of the signals selected by the multiplexer 3a in a time division manner.

  Similarly, in addition to the analog signals A1 and A2 output from the analog input circuits 1b and 2b, the multiplexer 3b includes the output signal of the arithmetic circuit 6b and the A / D converter 7b output from the D / A converter 11b. And a system power supply diagnosis signal (power supply voltage Vcc) are supplied, and one of them is selected by the control of the CPU 8b and supplied to the A / D converter 7b. The A / D converter 7b is supplied with the reference voltage VREFb from the power supply IC 4b. Based on the reference voltage VREFb, the input is converted from analog to digital and supplied to the CPU 8b. As a result, the CPU 8b acquires signals obtained by analog / digital conversion of the signals selected by the multiplexer 3b in a time division manner.

  The CPU 8a receives the digital signals D1 and D2 (the signals obtained by digitizing the analog signals A1 and A2, see FIGS. 2A and 2B) output from the A / D converter 7a through the buffers 9a and 10a, respectively. To the arithmetic circuit 6a. The arithmetic circuit 6a compares the phases of the input digital signals D1 and D2, for example, and supplies the comparison result to the multiplexer 3a. Alternatively, the level difference between the digital signals D1 and D2 and calculation data are obtained as necessary, and the calculation result is supplied to the multiplexer 3a. The CPU 8a supplies a known diagnostic signal (digital signal) to the D / A converter 11a. The D / A converter 11a is supplied with the reference voltage VREFa from the power supply IC 4a, and the diagnosis signal is digital / analog converted and supplied to the multiplexer 3a.

  On the other hand, the CPU 8b supplies the digital signals D1 and D2 (the signals obtained by digitizing the analog signals A1 and A2) output from the A / D converter 7b to the arithmetic circuit 6b via the buffers 9b and 10b, respectively. For example, the arithmetic circuit 6b compares the phases of the input digital signals D1 and D2, and supplies the comparison result to the multiplexer 3b. Alternatively, the level difference between the digital signals D1 and D2, the operation data, and the like are obtained as necessary, and the operation result is supplied to the multiplexer 3b. The CPU 8b supplies a known diagnostic signal (digital signal) to the D / A converter 11b. The D / A converter 11b is supplied with the reference voltage VREFb from the power supply IC 4b, and digital / analog converts the diagnostic signal and supplies it to the multiplexer 3b. The CPUs 8a and 8b output output signals OUTa and OUTb, respectively.

Next, in the above configuration, the detection operation will be described with reference to the flowcharts of FIGS.
[Level detection of two analog signals]
The detection of the levels of the analog signals A1 and A2 is performed as shown in FIG. First, under the control of the CPUs 8a and 8b, the multiplexers 3a and 3b respectively select the outputs of the analog input circuits 1a and 1b, that is, the analog signal A1 (step S1). As a result, the analog signal A1 is input to the A / D converters 7a and 7b, respectively, and subjected to analog / digital conversion (step S2). The outputs of the A / D converters 7a and 7b are supplied to and read from the CPUs 8a and 8b, respectively, and A / D conversion results are acquired (step S3). The value acquired by the CPUs 8a and 8b in step S3 is the voltage level of the analog signal A1.

Subsequently, under the control of the CPUs 8a and 8b, the multiplexers 3a and 3b respectively select the outputs of the analog input circuits 2a and 2b, that is, the analog signal A2 (step S4). As a result, the analog signal A2 is input to the A / D converters 7a and 7b, respectively, and subjected to analog / digital conversion (step S5). The outputs of the A / D converters 7a and 7b are supplied to and read from the CPUs 8a and 8b, respectively, and A / D conversion results are acquired (step S6). The value acquired by the CPUs 8a and 8b in step S6 is the voltage level of the analog signal A2.
In this way, the voltage levels of the analog signals A1 and A2 can be obtained.

[Detection of phase difference between two analog signals]
When detecting the phase difference between the analog signals A1 and A2, when the level of the analog signals A1 and A2 is acquired, information that exceeds (or falls below) a predetermined level is output from the CPUs 8a and 8b, and the MCUs 5a and 5b. Input to external arithmetic circuits (phase comparison) 6a and 6b. That is, as shown in the flowchart of FIG. 4, the outputs of the analog input circuits 1a and 1b, that is, the analog signal A1 are selected by the multiplexers 3a and 3b, respectively, under the control of the CPUs 8a and 8b (step S11).

  As a result, the analog signal A1 is input to the A / D converters 7a and 7b, respectively, and subjected to analog / digital conversion (step S12). The outputs of the A / D converters 7a and 7b are supplied to and read from the CPUs 8a and 8b, respectively, and an A / D conversion result is acquired (step S13). The CPUs 8a and 8b determine whether or not the acquired A / D conversion result exceeds a predetermined level, and output a result corresponding to the voltage level to the arithmetic circuit (step S14).

  Next, under the control of the CPUs 8a and 8b, the multiplexers 3a and 3b respectively select the outputs of the analog input circuits 2a and 2b, that is, the analog signal A2 (step S15). As a result, the analog signal A2 is input to the A / D converters 7a and 7b, respectively, and subjected to analog / digital conversion (step S16). The outputs of the A / D converters 7a and 7b are supplied to and read from the CPUs 8a and 8b, respectively, and an A / D conversion result is acquired (step S17). The CPUs 8a and 8b determine whether or not the acquired A / D conversion result exceeds a predetermined level, and output a result corresponding to the voltage level to the arithmetic circuit (step S18).

  Subsequently, under the control of the CPUs 8a and 8b, the multiplexers 3a and 3b respectively select the outputs of the arithmetic circuits 6a and 6b (step S19). The voltage levels output from the arithmetic circuits 6a and 6b in accordance with the phase difference between the analog signals A1 and A2 are input to the CPUs 8a and 8b via (through) the A / D converters 7a and 7b, respectively. Thus, the phase difference is acquired (step S20).

At this time, since the CPUs 8a and 8b perform only the output corresponding to the level threshold determination to the arithmetic circuits 6a and 6b, and it is not necessary to calculate the phase difference itself, the processing load can be reduced. .
CPU8a, 8b controls an external apparatus according to the level of analog signal A1, A2 acquired by the above, and the information of the phase difference of these signals.

  For example, when detecting the presence / absence of a train in the track circuit, the phase and amplitude (voltage level) of the power supply whose phase and amplitude change depending on whether the reference power supply in the equipment room and the train are present or not are correct. Check whether it is within the range or not, and determine whether it is present or absent.

In addition, this analog signal input device can be used not only for a track circuit but for various uses by comparing what the detected analog signal is with respect to a reference analog signal.
In the above-described embodiment, the case where the levels of the analog signals A1 and A2 and the phase difference between these signals A1 and A2 are detected has been described as an example. However, the signal A1 is output by the arithmetic circuits 6a and 6b. , A2 level difference, correlation between signals A1 and A2, and arithmetic data of signals A1 and A2.

Next, various diagnostic functions in the analog signal input device shown in FIG. 1 will be described with reference to the flowcharts of FIGS. These diagnostic operations may be performed at predetermined time intervals, or may be appropriately performed at a necessary timing.
<Diagnosis of arithmetic circuit>
In the diagnosis of the arithmetic circuits 6a and 6b, a negative mode failure in which the arithmetic result is fixed to a constant value is detected. As shown in the flowchart of FIG. 5, diagnostic signals are input from the CPUs 8a and 8b to the arithmetic circuits 6a and 6b at a constant cycle (step S31). Then, the outputs of the arithmetic circuits 6a and 6b are respectively selected by the multiplexers 3a and 3b under the control of the CPUs 8a and 8b (step S32). The outputs of the selected arithmetic circuits 6a and 6b are supplied to the CPUs 8a and 8b via the A / D converters 7a and 7b (through) (step S33). The processing value thus obtained is compared with the output value of the diagnostic signal output from the CPUs 8a and 8b, and the validity is confirmed by the CPUs 8a and 8b (step S34). In this way, it is possible to diagnose whether or not the arithmetic circuits 6a and 6b are operating normally by verifying the arithmetic processing result.

<Diagnosis of A / D converter>
As shown in the flowchart of FIG. 6, the diagnosis of the A / D converters 7a and 7b is performed by first outputting diagnostic signals from the CPUs 8a and 8b to the D / A converters 11a and 11b, respectively, for digital / analog conversion (step). S41). The diagnostic signal is a digital signal corresponding to a known voltage level, and an analog voltage corresponding to this signal is obtained. Next, the outputs of the D / A converters 11a and 11b are respectively selected by the multiplexers 3a and 3b under the control of the CPUs 8a and 8b (step S42). A diagnostic signal is input to the A / D converters 7a and 7b, subjected to analog / digital conversion (step S43), and supplied to the CPUs 8a and 8b (step S44). Then, the processing values read by the CPUs 8a and 8b are compared with the diagnostic signals (output values) output from the CPUs 8a and 8b to confirm the validity (step S45). Specifically, it is determined whether or not the comparison result between the processed value and the output value is smaller than a predetermined value. If the result is smaller, it is determined that the A / D converters 7a and 7b are operating normally. By performing such a diagnosis, it is possible to prevent an inappropriate conversion result from being used due to an abnormality in the A / D conversion system.

<System power supply diagnosis>
As shown in the flowchart of FIG. 7, the diagnosis of the system power supply is performed by selecting the power diagnosis signal (power supply voltage Vcc) by the multiplexers 3a and 3b under the control of the CPUs 8a and 8b (step S51). The A / D converters 7a and 7b perform analog / digital conversion of power supply diagnosis signals (step S52), and the CPUs 8a and 8b acquire and check the relationship between the reference voltages VREFa and VREFb and the power supply voltage Vcc (step S53). ).
As described above, by diagnosing the system power supply, it is possible to prevent the reference voltages VREFa and VREFb from fluctuating due to an abnormality in the power supply voltage Vcc and resulting in an invalid analog / digital conversion result.

<Diagnosis of various processing results of two systems>
Since the present embodiment has a dual system configuration, there is a discrepancy between the processing results of the CPU 8a of the A system circuit unit 100 and the CPU 8b of the B system circuit unit 200 when an abnormality occurs. Therefore, by comparing the various processing results of the CPU 8a with the various processing results of the CPU 8b, the analog input circuits 1a, 1b, 2a, 2b, multiplexers 3a, 3b, MCU (A / D converters 7a, 7b, CPUs 8a, 8b). D / A converters 11a, 11b, etc.) 5a, 5b and power supply ICs 4a, 4b can detect a single system abnormality.

  That is, inter-system collation is performed on the various processing results of the two systems. As shown in the flowchart of FIG. 8, the processing result of the own system is transferred to the other system (step S61), and the processing result of the other system is received (step S62). Then, the two are compared to confirm whether they match or whether the difference is within an allowable range (step S63). In this way, by comparing various processing results of the A system circuit unit 100 and the B system circuit unit 200, various faults, for example, fixed faults of the CPUs 8a and 8b, that is, faults in which the output level is fixed are diagnosed. it can. Therefore, when there is an error in the determination result, it is possible to detect the determination error by performing inter-system collation.

  As described above, according to the present invention, not only can the input of analog signals of a plurality of channels be supported, but also processing based on these analog signals can be diagnosed to ensure fail-safety. Further, by providing the arithmetic circuits 6a and 6b outside the MCUs 5a and 5b, it is possible to obtain data subjected to various calculations with a small processing load on the MCUs 5a and 5b. Since the processing load on the MCUs 5a and 5b is small, it is not necessary to prepare a high-performance MCU and the cost can be reduced. Furthermore, since the dual system configuration is used to compare the calculation results of the A system circuit unit 100 and the B system circuit unit 200 to diagnose whether a correct determination has been made, the reliability can be further increased. Thus, for example, the present invention can also be applied when detecting the presence of a train in a track circuit.

In addition, this invention is not limited to embodiment mentioned above and its modification, It is possible to implement in various deformation | transformation. For example, the case where two analog signals are input and the phase difference, level difference, calculation data, etc. between the signals are obtained has been described, but it is needless to say that three or more analog signals may be input.
In addition, although the detection operation and the diagnosis operation have been described independently, each detection operation and each diagnosis operation may be performed continuously in a predetermined order. For example, the detection operation and the detection operation correspond to this detection operation. The reliability can be further improved by alternately performing the diagnosis operation of the circuit unit to be performed.
Furthermore, although a dual system configuration of A system and B system is taken as an example, a single system configuration may be used when high reliability is not required.

  The circuit configuration, operation procedure, and the like described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

3a, 3b ... multiplexer (signal input switching means), 5a, 5b ... MCU (diagnostic means), 6a, 6b ... arithmetic circuit ( arithmetic means), 7a, 7b ... A / D converter, 8a, 8b ... CPU, 9a , 9b, 10a, 10b ... buffer, 11a, 11b ... D / A converter, 100 ... A system circuit unit, 200 ... B system circuit unit

Claims (7)

An analog signal processing apparatus having a multi-system configuration including a plurality of systems, including arithmetic means for performing predetermined arithmetic processing on an input analog signal and outputting the arithmetic processing results to the outside,
An analog signal processing apparatus provided with a diagnostic unit that performs arithmetic processing executed in each system and inter-system collation of processing results, and that the arithmetic unit diagnoses that it is normal when they match or are within an allowable range .   The analog signal processing apparatus according to claim 1, wherein the diagnosis unit further diagnoses the digitized analog signal.   3. The analog signal processing apparatus according to claim 1, further comprising a signal input switching unit that selects a signal and inputs the selected signal to the diagnosis unit. The diagnostic means includes an A / D converter that performs analog / digital conversion of the signal selected by the signal input switching means, a processing device that performs the predetermined processing based on the output of the A / D converter, and the processing A D / A converter for digital / analog conversion of the output of the device,
4. The analog signal processing apparatus according to claim 3, wherein the signal input switching means includes a multiplexer controlled to be switched by the processing apparatus.   The multiplexer selects one of the input multi-channel analog signals and supplies the selected analog signal to the A / D converter; and the non-selected one of the input multi-channel analog signals. A second operation mode in which two analog signals are selected and supplied to the A / D converter, and an arithmetic processing result for the two analog signals output from the arithmetic means are selected and supplied to the A / D converter. A third operation mode, a fourth operation mode for selecting a calculation output when the diagnostic signal is input to the calculation means and supplying the calculation output to the A / D converter, and a signal output from the processing device The analog signal according to claim 4, further comprising: a fifth operation mode in which another diagnostic signal analogized by the D / A converter is selected and supplied to the A / D converter. Processing equipment .   The processing device obtains the analog signal digitized in the first operation mode of the multiplexer, obtains the analog signal digitized in the second operation mode, and obtains the analog signal in the third operation mode. The calculation processing result by the calculation means is acquired, the calculation output of the diagnostic signal is acquired in the fourth operation mode, and the calculation means operates normally when the calculation processing result is within a predetermined range. And when another arithmetic signal digitized in the fifth operation mode is acquired and compared with another diagnostic signal output from the processing device, and the result of the arithmetic processing is within a predetermined range 6. The analog signal processing apparatus according to claim 5, wherein the A / D converter is determined to be operating normally.   The arithmetic means includes an arithmetic circuit that receives digitized analog signals of a plurality of channels and calculates at least one of a phase difference, a level difference, and arithmetic data of these signals. The analog signal processing device according to 1, 5, or 6.