JP6586765B2 - Access blocking circuit, semiconductor integrated circuit, and access blocking method - Google Patents

Description

  The embodiments referred to in this specification relate to an access blocking circuit, a semiconductor integrated circuit, and an access blocking method.

  In recent years, the system has become more complicated, and the number of modules to be mounted has become enormous. Among them, some modules in the system may become uncontrollable due to a program mistake or a malfunction of the opposite device.

  In recent years, for example, AMBA (registered trademark) (Advanced) is used as a bus standard used to connect various blocks in a system LSI (semiconductor integrated circuit) such as SoC (System-On-a-Chip). Microcontroller Bus Architecture) is known.

  Further, AMBA (registered trademark) has a plurality of buses such as AXI (registered trademark) (Advanced eXtensible Interface), AHB (registered trademark) (Advanced High-performance Bus), and APB (registered trademark) (Advanced Peripheral Bus). A standard is defined.

  Note that this embodiment described later is not limited to the AMBA (registered trademark) bus standards. For example, the present invention is applicable to semiconductor integrated circuits using various bus standards such as OCP (Open Core Protocol). Can be applied. Furthermore, the application of the present embodiment is not limited to a semiconductor integrated circuit, but can be widely applied to a system, a server, and the like using a plurality of semiconductor integrated circuits.

  By the way, conventionally, various proposals have been made as countermeasures when some modules in the system become uncontrollable.

JP 2013-205961 A JP 2002-31333 A JP 05-020290 A JP 2004-348719 A

  As described above, conventionally, various proposals have been made as countermeasures when some modules in the system become uncontrollable. Further, data transfer based on a bus standard such as AMBA (registered trademark) is performed in a handshake format in which a response to a transfer command is required in a master / slave relationship.

  Therefore, for example, when a master becomes uncontrollable due to a program mistake or a malfunction of the opposite device, the bus route is occupied or locked by the runaway of that master, and access from other masters is delayed. The entire system hangs up. In other words, even if one module in the system runs out of control, the effect extends to the entire system.

  Further, for example, in the case of a protocol that involves handshaking, it is not sufficient to simply immediately block access between the master and the bus, and data being transferred is required to complete handshaking.

  According to one embodiment, an access blocking circuit provided between a master and a bus to which at least one slave is connected, the access having an abnormality detection unit, an access blocking unit, and a protocol correction unit A breaker circuit is provided.

The abnormality detection unit detects an abnormality of the master, and the access blocking unit blocks the access of the master in which the abnormality is detected when the abnormality detection unit detects the abnormality of the master. The protocol correction unit corrects the protocol by the master whose access is blocked, and holds the slave in an idle state. The abnormality detection unit includes: a first monitor unit that monitors whether a data transfer rate between the master and the slave differs by a threshold value or more from a value based on the standard of the bus; and an output of the first monitor unit And a status receiving unit that detects an abnormality between the master and the slave.

  The disclosed access blocking circuit, semiconductor integrated circuit, and access blocking method have an effect that the entire system can be prevented from entering a hang-up state. Furthermore, according to the disclosed access blocking circuit, semiconductor integrated circuit, and access blocking method, only the master that has become uncontrollable needs to be initialized without initializing the entire system.

FIG. 1 is a diagram for explaining a case where some modules in the system have become uncontrollable. FIG. 2 is a flowchart for explaining an example of the operation of the system shown in FIG. FIG. 3 is a block diagram schematically showing a system to which the first embodiment of the access blocking circuit is applied. FIG. 4 is a flowchart for explaining an example of the operation of the system shown in FIG. FIG. 5 is a timing chart for explaining an example of processing when the read data channel is not completed in the system shown in FIG. FIG. 6 is a timing chart for explaining an example of processing when the write response channel is not completed in the system shown in FIG. FIG. 7 is a timing chart for explaining an example of processing when the write address channel is completed but the write data channel is not completed in the system shown in FIG. FIG. 8 is a timing chart for explaining an example of processing when the write data channel is completed but the write address channel is not completed in the system shown in FIG. FIG. 9 is a block diagram showing an access blocking circuit of the first embodiment in the system shown in FIG. FIG. 10 is a diagram (part 1) for explaining the state transition of the access blocking circuit shown in FIG. FIG. 11 is a diagram (No. 2) for explaining the state transition of the access blocking circuit shown in FIG. FIG. 12 is a block diagram schematically showing a system to which the second embodiment of the access blocking circuit is applied. FIG. 13 is a block diagram showing an access blocking circuit of the second embodiment in the system shown in FIG. FIG. 14 is a diagram (part 1) for explaining the state transition of the access blocking circuit shown in FIG. FIG. 15 is a diagram (part 2) for explaining the state transition of the access blocking circuit shown in FIG.

  First, before describing the access blocking circuit, the semiconductor integrated circuit, and the access blocking method of this embodiment in detail, referring to FIG. 1 and FIG. 2, when some modules in the system become uncontrollable and its problems Explain the point.

  FIG. 1 is a diagram for explaining a case where some modules in the system have become uncontrollable, and shows a case where a master 111 in a system LSI (semiconductor integrated circuit) 100 has become uncontrollable.

  In FIG. 1, reference numerals 111 to 113 denote masters (bus masters) such as a CPU (Central Processing Unit) and DMA (Direct Memory Access), 103 is an internal bus (bus), and 121 and 122 are For example, a slave (bus slave) such as a memory is shown.

  As shown in FIG. 1, the LSI 100 includes masters 111 to 113, a bus 103, and slaves 121 and 122, and exchanges data with an opposing device 200 provided outside the LSI to perform predetermined processing. .

  Incidentally, in the LSI 100, for example, data transfer based on a bus standard such as AMBA (registered trademark) is performed in a handshake format in which a response to a transfer command is required in a master / slave relationship.

  Therefore, for example, when a master 111 becomes uncontrollable due to a program mistake or a malfunction of the opposite device 200, the bus route is occupied or locked by the runaway of that master, and access from other masters Hangs and the entire system hangs up.

  FIG. 2 is a flowchart for explaining an example of the operation of the system shown in FIG. First, as shown in FIG. 2, for example, in step ST11, a watch dog timer (WDT) is started, the process proceeds to step ST12, and WDT is periodically initialized on the software. Note that the WDT is used to detect a CPU (for example, the master 111) that starts a malfunction (runaway) due to noise or the like and return it to a normal state.

  If it is determined in step ST12 that initialization of WDT is impossible (ST12: No), the process proceeds to step ST13, the entire system is reset, and further, the process proceeds to step ST14 to start the initialization routine and finish the process. . If it is determined in step ST12 that WDT can be initialized (ST12: No), the processing is continued until it is determined that initialization of WDT is impossible.

  Here, the reset process of the entire system in step ST13 and the activation process of the initialization routine in step ST14 have a great influence on the performance of the system.

  In other words, if some module in the system (for example, master 111) runs out of control (uncontrollable), the entire system will be reset and the initialization sequence will start over. Even if one module in the system runs out of control, the effect will be The whole system.

  Further, for example, in the case of a protocol involving handshake, it is not sufficient to simply immediately block access between the master and the bus. That is, the data being transferred is required to complete the handshake, and in particular, the bus-side interface (IF) is required to guarantee an idle (IDLE) state.

  Hereinafter, embodiments of an access blocking circuit, a semiconductor integrated circuit, and an access blocking method will be described in detail with reference to the accompanying drawings. In the following description, a semiconductor integrated circuit using AXI (registered trademark) of AMBA (registered trademark) will be mainly described as an example. The application of this embodiment is applied to a semiconductor using this AXI (registered trademark). It is not limited to integrated circuits.

  That is, the application of this embodiment is, for example, semiconductor integration using the above-mentioned AMBA (registered trademark) AHB (registered trademark) or APB (registered trademark), or AMBA (registered trademark) ACE (AXI Coherency Extensions). It may be a circuit.

  Furthermore, the application of the present embodiment is not limited to a semiconductor integrated circuit (system LSI, SoC), and can be widely applied to a system, a server, and the like using a plurality of semiconductor integrated circuits. For example, a method for mounting a protocol correction circuit and a pseudo transfer method described later depend on the standard (bus protocol) of each bus.

  FIG. 3 is a block diagram schematically showing a system to which the first embodiment of the access blocking circuit is applied. In FIG. 3, reference numeral 1 is a system LSI (semiconductor integrated circuit), 11 to 13 are masters, 21 and 22 are slaves, 3 is an internal bus (bus), 41 to 43 are access blocking circuits, and 5 is a system controller. (CPU etc.).

  As is clear from the comparison between FIG. 3 and FIG. 1 described above, in the first embodiment, access blocking circuits 41 to 41 are respectively connected between the masters 11 to 13 and the bus 3 to which the slaves 21 and 22 are connected. 43 is provided. The masters 11 to 13 are, for example, a CPU and a DMA, and the slaves 21 and 22 are, for example, a memory.

  The access blocking circuits 41 to 43 are controlled by the system controller 5, for example. Here, the system controller 5 is a module having a system control function in a SoC (semiconductor integrated circuit) typified by, for example, a clock reset generator and a power management unit.

  In addition, the system controller 5 may be configured such that any one of the higher-level arithmetic processing devices that control the masters 11 to 13 or the plurality of masters 11 to 13 directly plays a role.

  The system controller 5 receives the access blocking request signal ABRS and the access blocking completion (reset permission) signal ABCS from each of the access blocking circuits 41 to 43, and outputs an access blocking permission signal ABPS to each of the access blocking circuits 41 to 43. To do. Further, the system controller 5 outputs an individual reset signal IRST for individually resetting each of the masters 11 to 13 to each of the masters 11 to 13.

  Here, for example, when the master 11 runs away due to an unintended factor during the transfer from the master 11 to the slave 21, the transfer path between the master 11 and the slave 21 continues to be occupied by the runaway access.

  In such a case, in the semiconductor integrated circuit 100 shown in FIG. 1 described above, access from other masters (for example, the master 112) is waited indefinitely, and as described above, the system using the WDT or the like. Restore the entire reset process.

  On the other hand, in the semiconductor integrated circuit 1 according to the first embodiment, for example, the access blocking circuit 41 can temporarily block the runaway access from the master 11, and in that state, only the master 11 is reset. To do.

  Thereafter, normal access by the master 11 becomes possible by setting the access blocking circuit 41 to the normal state. As a result, the entire system can be recovered without being reset.

  FIG. 4 is a flowchart for explaining an example of the operation of the system shown in FIG. First, as shown in FIG. 4, for example, when the access blocking circuit 41 detects an exceptional case (a state that is not a normal operation) in step ST21, the process proceeds to step ST22.

  In step ST22, (a) a bus handshake factor and (b) a transfer performance factor are determined. In step ST22, for example, the access blocking circuit 41 monitors the transfer with the slave 21 via the bus (internal bus) 3 and (a) detects (determines) a bus handshake abnormality. Proceed to ST23. For example, if it is determined in step ST22 that the handshake with the slave 21 via the bus 3 has not been completed, the process proceeds to step ST23.

  In step ST22, for example, the handshake is completed, but (b) an abnormality in transfer performance, for example, an abnormality such that the data transfer rate differs by a predetermined threshold or more from the bus 3 standard. If detected, the process proceeds to step ST27.

  In step ST27, for example, if it is determined that the set number of times and the sampling result are not changed, that is, deviate from the original transfer performance (normal operation) (ST27: Yes), the process proceeds to step ST23. If it is determined in step ST27 that the set number of times and the sampling result are changed, that is, normal operation (ST27: No), the process returns to step ST21.

  In step ST23, the access of the master 11 is blocked, and the process further proceeds to step ST24 to determine whether or not there is an incomplete handshake. If it is determined in step ST24 that there is an incomplete handshake (ST24: No), the process proceeds to step ST28, performs pseudo transfer, and then proceeds to step ST25.

  If it is determined in step ST24 that there is no incomplete handshake (ST24: Yes), the process proceeds to step ST25 as it is. In step ST25, the target master (for example, master 11) is initialized, and the process proceeds to step ST26, where the access blocking is canceled and the process is terminated.

  Thus, according to the first embodiment, for example, when the master 11 is out of control (not controllable), only the master 11 is shut off and initialized, and for example, the bus 3 and the slave 21 are opened to enter an idle state. And avoid affecting the entire system.

  Next, an operation sequence when the present embodiment is applied will be described by taking the AMBA (registered trademark) AXI (registered trademark) protocol (bus standard) as an example. Here, in order to determine when access blocking is required (master runaway), for example, a factor that can be determined from the bus protocol and a factor that can be determined from the transfer rate can be considered.

  First, a factor that can be determined from the bus protocol is, for example, when the handshaking process specified by the protocol in the AXI (registered trademark) protocol is not possible ((a) bus handshake factor).

  The factor that can be determined from the transfer rate is that the master transfer performance can be specified in advance from the results of system simulation, etc., and the master behaves far from the specified transfer rate ((b) Transfer performance factor) It is.

  In the following description, signal names and terms (abbreviations) used represent the following contents (meanings). First, the meanings represented by abbreviations (ARch, Rch, RVALID, etc.) in FIGS. 5 to 8 are as follows.

  ARch (Read address channel) indicates a read address channel, Rch (Read data channel) indicates a read data channel, and AWch (Write address channel) indicates a write address channel. Wch (Write data channel) indicates a write data channel, and Bch (Write response channel) indicates a write response channel.

  Next, signal names RVALID, RREADY, BVALID, and the like are signal names defined by the AMBA (registered trademark) AXI (registered trademark) protocol, and have the following meanings, respectively. RVALID indicates that the read is valid, RREADY indicates that the read is ready, BVALID indicates that the write response is valid, and BREADY is ready for the write response WVALID indicates that the write data is valid.

  WID indicates an ID tag of write data, WSTRB indicates a strobe of write data, AWVALID indicates that the write address is valid, and AWID indicates an ID tag of the write address. Furthermore, AWLEN indicates the number of write data transfers (burst length), and AWADDR indicates a write address.

  First, factors that can be determined from the bus protocol will be described using the AXI (registered trademark) protocol (bus standard) of AMBA (registered trademark) as an example. If the master cannot handle the handshake specified in the protocol, for example, the VALID from the bus (slave) cannot return READY from the master within an arbitrary time, or there is a correlation between AWVALID and WVALID. This is the case when it collapses. The following four cases (P1) to (P4) can be considered.

  (P1) is a case where Rch (read data channel) is not completed, and (P2) is a case where Bch (write response channel) is not completed. (P3) is a case where AWch (write address channel) is completed but Wch (write data channel) is not completed. Further, (P4) is a case where Wch (write data channel) is completed but AWch (write address channel) is not completed.

  In these cases (P1) to (P4), it becomes a cause of a deadlock of the bus 3. Therefore, it is preferable that the access is cut off immediately after detection and the target master is reset. However, when the access is blocked, as described above, a predetermined number of READYs and VALIDs to the bus 3 (slaves 21 and 22) are pseudo-transferred from the access blocking circuits 41 to 43 instead of the masters 11 to 13 to shift to the idle state. After that, it will move to reset control.

  FIG. 5 is a timing chart for explaining an example of the process (P1) when the read data channel is not completed in the system shown in FIG. 3. For example, the master 11 is a slave (for example, a memory) 21. This shows a case where data is read out from.

  As shown in FIG. 5, when the master 11 reads data at a predetermined address from the memory 21, for example, the master 11 outputs a read address channel (read command) ARch to the memory 21.

  The memory 21 receives ARch via the access blocking circuit 41 and the bus 3, and starts asserting RVALID indicating that reading of the read data channel Rch is valid to the master 11. Here, if the master 11 runs out of control and becomes uncontrollable, for example, even if the master 11 receives RVALID, it does not return RREADY indicating that it is ready for reading.

  At this time, for example, the access blocking circuit 41 determines that the master 11 is out of control due to the elapse of a set cycle number (count of a preset number of clocks) in which the master 11 does not return RREADY after receiving RVALID. To block access.

  Further, the access blocking circuit 41 asserts RREADY to the memory 21 instead of the master 11 (pseudo-assertion: pseudo-transfer). That is, in the case of P1, the access blocking circuit 41 pseudo-asserts RREADY for RVALID from the bus 3 (memory 21). For example, the access blocking circuit 41 initializes only the master 11 that has become uncontrollable, and then enables the connection between the master 11 and the bus 3.

  FIG. 6 is a timing chart for explaining an example of the process (P2) when the write response channel is not completed in the system shown in FIG. 3. For example, the master 11 sends data to the memory 21. It shows the case of writing.

  As shown in FIG. 6, when the master 11 writes data to a predetermined address in the memory 21, for example, the master 11 sets a write address channel (write command) AWch and a write data channel Wch to the memory 21. Output.

  The memory 21 receives AWch and Wch via the access blocking circuit 41 and the bus 3, and starts asserting BVALID indicating that the write response of the write response channel Bch is valid to the master 11. Here, if the master 11 runs out of control and becomes uncontrollable, for example, even if the master 11 receives BALID, it does not return BREADY indicating that the write response is ready.

  At this time, for example, the access blocking circuit 41 determines that the master 11 is out of control due to the elapse of a set cycle number in which the master 11 does not return BEADY after receiving the BALID, and blocks the access.

  Further, the access blocking circuit 41 pseudo-asserts BREADY to the memory 21 instead of the master 11. That is, in the case of P2, the access blocking circuit 41 pseudo-asserts BREADY for BVALID from the bus 3 (memory 21). For example, the access blocking circuit 41 initializes only the master 11 that has become uncontrollable, and then enables the connection between the master 11 and the bus 3.

  FIG. 7 is a timing chart for explaining an example of the process (P3) when the write address channel is completed but the write data channel is not completed in the system shown in FIG.

  As shown in FIG. 7, when the master 11 writes data to a predetermined address in the memory 21, for example, the master 11 writes AWch (write address ID tag AWID-1) and write data to the memory 21. The ID tag WID is output.

  Here, when the master 11 does not output WVALID indicating that the write data of Wch is valid, the access blocking circuit 41 determines that the master 11 has runaway due to the elapse of the set number of cycles in which WVALID is not output. To block access.

  Further, the access blocking circuit 41 pseudo-asserts WVALID to the memory 21 instead of the master 11 to set the write data strobe WSTRB to “0” so that data is not written to the memory 21. Then, the access blocking circuit 41 pseudo-asserts BREADY indicating that the Bch write response is ready.

  That is, in the case of P3, the WSTRB having the ID value equivalent to the AWID (AWID-1) of the completed AWch as WID is set to “0”, and the pseudo Wch is handshaked. Further, BREADY is continuously asserted in preparation for the subsequent Bch. For example, the access blocking circuit 41 initializes only the master 11 that has become uncontrollable, and then enables the connection between the master 11 and the bus (internal bus) 3.

  FIG. 8 is a timing chart for explaining an example of the process (P4) when the write data channel is completed but the write address channel is not completed in the system shown in FIG.

  As shown in FIG. 8, when the master 11 writes data to a predetermined address of the memory 21, for example, the master 11 outputs the AWch AWID and the burst length AWLEN of the write data to the memory 21. Further, the master 11 outputs an AWch write address AWADDR and Wch write data ID tags WID (WID-2, WID-2) to the memory 21.

  Here, when the master 11 does not output AWVALID indicating that the write address of AWch is valid, the access blocking circuit 41 determines that the master 11 has runaway due to the elapse of the set number of cycles in which AWVALID is not output. To block access.

  Further, the access blocking circuit 41 pseudo-asserts AWVALID to the memory 21 instead of the master 11 and writes data to the reserved area set by AWADDR.

  That is, in the case of P4, handshaking is performed on a pseudo AWch having an ID value equivalent to the WID (WID-2) of the completed Wch as AWID. The address value at that time is issued to the reserved area set by AWADDR. Then, similarly to P3 described above, the access blocking circuit 41 continues to pseudo-assert BREADY in preparation for the subsequent Bch. For example, the access blocking circuit 41 initializes only the master 11 that has become uncontrollable, and then enables the connection between the master 11 and the bus 3.

  The factors that can be determined from the bus protocol have been described as P1 to P4 based on the AXI (registered trademark) protocol of AMBA (registered trademark). Next, the factors that can be determined from the transfer rate will be described.

  First, the transfer performance of the masters 11 to 13 can be recognized in advance from the result of a system simulation, for example. Accordingly, when the master behaves greatly deviating from the transfer rate recognized in advance, for example, it is determined that the master is out of control due to runaway.

  However, even if the transfer rate deviates significantly from the expected transfer rate, overshoot and undershoot can be considered for the transfer performance. It is preferable to initialize the master by shutting off.

  In this case, for example, it is preferable to detect a break in the transfer protocol, set the bus 3 (slaves 21 and 22) to a state that does not violate the protocol, and then block the access and move to reset control (master initialization). .

  In any case, as in the first embodiment, an access blocking process is performed via software by issuing an access blocking factor signal (including an interrupt signal) to the system controller (CPU, etc.) 5. It is possible.

  Alternatively, as in the second embodiment which will be described later with reference to FIGS. 12 to 15, the access blocking circuit (41 ′) blocks the access alone and generates a reset for the master (11). Is also possible.

  FIG. 9 is a block diagram showing an access blocking circuit of the first embodiment in the system shown in FIG. 9, reference symbols P11 to P17 and P11 'correspond to signals (information and processing) in the processing of the access blocking circuit 40 described with reference to FIGS.

  As shown in FIG. 9, the access blocking circuit 40 (41 to 43) includes a system IF unit 401, an access blocking unit 402, a protocol correction unit 403, a status reception unit 404, a protocol monitoring unit 405, and a performance monitoring unit 406. . Here, the status reception unit 404, the protocol monitor unit 405, and the performance monitor unit 406 function as an abnormality detection unit that detects an abnormality of the master.

  For example, the system IF unit 401 outputs an access blocking request signal ABRS and an access blocking completion (reset permission) signal ABCS to the system controller 5 and receives an access blocking permission signal ABPS from the system controller 5. The system IF unit 401 also receives a signal (processing) P16 from the protocol correction unit 403 and a signal P12 from the status reception unit 404.

  The access blocking unit 402 is provided on the master side, receives signals P13 and P17 from the system IF unit 401, and outputs a signal P14 to the protocol correction unit 403. The protocol correction unit 403 is provided on the slave (bus) side, and receives the signal P15 from the status reception unit 404 together with the signal P14 from the access blocking unit 402.

  The status receiving unit 404 receives the signal P11 from the protocol monitor unit 405 and the signal (cause information) P11 ′ from the performance monitor unit 406, and outputs a signal (notification of a cutoff request signal) P12 to the system IF unit 401. To do. Further, the status receiving unit 404 outputs a signal (correction information such as a target signal, various output IDs, and an access destination address) P15 to the protocol correction unit 403.

  The protocol monitor unit 405 constantly monitors the bus 3 to monitor the protocol, detects a behavior that deviates from the protocol, or causes the handshake timing of VALID and READY to exceed the preset number of cycles. Detects (master runaway).

  The performance monitor unit 406 continuously measures the transfer performance, and detects a factor (master runaway) by comparing with a preset assumed value. Each module function described above can be included in the protocol monitor unit 405 and the performance monitor unit 406, for example.

  10 and 11 are diagrams for explaining the state transition of the access blocking circuit shown in FIG. FIG. 11 is for explaining the access blocking process in FIG.

  As shown in FIG. 10, when the processing of the access blocking circuit 40 shown in FIG. 9 starts, in step ST31, the protocol monitor unit 405 monitors the transfer state of the bus 3 and determines whether it conforms to the bus protocol. To do. If the transfer state of the bus 3 deviates from the protocol, the protocol factor is detected (P11), and the process proceeds to step ST33.

  In step ST32, the performance monitor unit 406 measures the transfer performance of the bus 3 and determines whether it is within the performance threshold range. If the transfer performance of the bus 3 deviates from the performance threshold value, the process proceeds to step ST33 as performance threshold deviation (P11 ').

  In step ST33, the status receiving unit 404 receives the blocking factor (P11, P11 '), proceeds to step ST34, transmits a blocking request signal (P12) to the system IF unit 401, and proceeds to step ST35.

  In step ST35, it is determined whether an access blocking permission signal (ABPS) has been received from the system controller 5. If it is determined that ABPS has been received, a signal P13 is output to the access blocking unit 402, and the process proceeds to step ST36. That is, in step ST36, the access blocking unit 402 performs the access blocking process shown in FIG.

  As shown in FIG. 11, when the access blocking process starts, the access blocking unit 402 blocks the access of the master (11: 11-13), outputs an access blocking completion signal (P14), and proceeds to step ST61. .

  In step ST61, the status receiving unit 404 updates the blocking factor, outputs the updated information (P15), and proceeds to step ST62. Here, steps ST62 to ST67, ST62 'and ST67' indicate protocol processing by the protocol correction unit 403.

  In step ST62, it is determined whether or not the transfer is incomplete. If it is determined that the transfer is incomplete (Yes), the process proceeds to step ST62 ′, and P1 to P1 described above with reference to FIGS. The case of P4 is divided.

  That is, in the case of P1 where Rch is not completed, the process proceeds to step ST63, and RREADY is pseudo-asserted instead of the master. In the case of P2, where Bch is not completed, the process proceeds to step ST64 and BREADY is replaced in place of the master. Pseudo-assert and proceed to step ST67 ′.

  Further, in the case of P3 in which AWch is completed but Wch is not completed, the process proceeds to step ST65, and a handshake of a pseudo Wch of WSTROB = 0 with a specified WID (according to completed AWID) is performed. Proceed to ST67.

  Then, in the case of P4 in which Wch is completed but AWch is not completed, the process proceeds to step ST66, and a preset reserved area address is simulated with a prescribed AWID (according to the completed WID). Handshake AWch and proceed to step ST67.

  In step ST67, BREADY is pseudo-asserted in preparation for the subsequent Bch, and the process proceeds to step ST67 '. As described above, the process is divided into P1 to P4 by step ST62 ', and after corresponding processing is performed, the process proceeds to step ST67'.

  In step ST67 ′, for example, in step ST63 to ST67 described above, the master 11 that has runaway is shut off, the slaves 21 and 22 (bus 3) are transitioned to the idle state, and a transfer completion signal (P16) is output. Proceed to step ST68.

  If it is determined in step ST67 'that there is an incomplete transfer, the process returns to step ST61 and the same processing is repeated. If it is determined in step ST62 that the transfer is not incomplete (No), that is, it is determined that the transfer is complete, the process proceeds to step ST68.

  In step ST68, the system IF unit 401 asserts the access cutoff completion signal ABCS, and the process proceeds to step ST69. That is, the system controller 5 receives ABCS from the access blocking circuit 40 (for example, 41), and initializes the target master 11, for example.

  Here, for example, the runaway master 11 is disconnected from the bus 3 and the slaves 21 and 22 by the corresponding access blocking circuit 41, so that the other masters 12 and 13 and the slaves 21 and 23 are not affected. It can be initialized as it is.

  The initialization of the master 11 that has runaway is transmitted to the access blocking unit 402 by a signal P17 from the system IF unit 401, for example. As described above, for example, when access blocking and initialization of the runaway master (11) are completed, the access blocking by the access blocking circuit 40 (41) is released.

  FIG. 12 is a block diagram schematically showing a system to which the second embodiment of the access blocking circuit is applied, and the access blocking circuits 41 ′ to 43 ′ are accessed independently without using the system controller (CPU etc.) 5. Is shown, and the masters 11 to 13 are initialized.

  As is apparent from the comparison between FIG. 12 and FIG. 3 described above, in the second embodiment, each of the access blocking circuits 41 ′ to 43 ′ has a master reset signal MRST for initializing the corresponding masters 11 to 13. Is output.

  The MRST output from each of the access blocking circuits 41 'to 43' controls the corresponding masters 11 to 13 by taking predetermined logic with the system reset signal SRST, for example.

  FIG. 13 is a block diagram showing an access blocking circuit of the second embodiment in the system shown in FIG. As is clear from comparison between FIG. 13 and FIG. 9 described above, the access blocking circuit 40 ′ (41 ′ to 43 ′) of the second embodiment includes the system IF unit 401 in the access blocking circuit 40 of the first embodiment. Instead, a reset signal generation unit 407 is provided.

  That is, the access blocking circuit 40 ′ of the second embodiment generates a reset signal for generating a reset signal for initializing the master instead of generating an access blocking request signal ABRS and an access blocking completion signal ABCS for the system controller 5. The unit 407 is incorporated.

  The status receiving unit 404 receives the factor information P21 and P21 'from the protocol monitoring unit 405 and the performance monitoring unit 406, and outputs the blocking notification P22 for the access blocking unit 402' and the correction information P24 for the protocol correction unit 403. Here, the status reception unit 404, the protocol monitor unit 405, and the performance monitor unit 406 function as an abnormality detection unit that detects an abnormality of the master.

  The reset signal generation unit 407 receives the signal P25 from the protocol correction unit 403, generates and outputs a master reset signal MRST for initializing the master corresponding to its own access blocking circuit 40 '. In FIG. 13, signals (processing, information) P21, P21 'and P23 to P25 correspond to P11, P11' and P14 to P16 in FIG.

  14 and 15 are diagrams for explaining the state transition of the access blocking circuit shown in FIG. FIG. 15 is for explaining the access blocking process in FIG. In the following description, the description will be given mainly focusing on processing different from the first embodiment described with reference to FIGS. 10 and 11.

  As is clear from comparison between FIG. 14 and FIG. 10, the second embodiment shown in FIG. 14 is obtained by omitting steps ST34 and ST35 in the first embodiment shown in FIG. That is, when the processing of the access blocking circuit 40 ′ shown in FIG. 13 is started, the protocol factor (P21) in step ST31 and the performance threshold deviation (P21 ′) in step ST32 are processed by the status reception unit 404 in step ST33. .

  In step ST33, the status receiving unit 404 receives the blocking factor (P21, P21 '), transmits a blocking request signal (P22) to the access blocking unit 402, and proceeds to step ST37. That is, in step ST37, the access blocking unit 402 performs the access blocking process shown in FIG.

  As shown in FIG. 15, when the access blocking process starts, the access blocking unit 402 blocks the access of the master, outputs an access blocking completion signal (P23), and proceeds to step ST71.

  Here, as apparent from the comparison between FIG. 15 and FIG. 11 described above, steps ST71 to ST77 (ST72 ′, ST77 ′) in FIG. 15 are replaced with steps ST61 to ST67 (ST62 ′, ST67 ′) in FIG. Correspondingly, their description is omitted.

  As shown in FIG. 15, the process is divided into P1 to P4 by step ST72 ', and after corresponding processing is performed by steps ST73 to ST77, the process proceeds to step ST77'.

  In step ST77 ', for example, the runaway master 11 is shut off, the slaves 21 and 22 (bus 3) are shifted to the idle state, a transfer completion signal (P25) is output, and the process proceeds to step ST78. If it is determined in step ST77 'that there is an incomplete transfer, the process returns to step ST71 and the same processing is repeated.

  In step ST78, the reset signal generation unit 407 asserts the master reset signal MRST, proceeds to step ST79, and initializes the master to be provided with its own access blocking circuit 40 '.

  Here, for example, the runaway master 11 is disconnected from the bus 3 and the slaves 21 and 22 by the corresponding access blocking circuit 41, so that the other masters 12 and 13 and the slaves 21 and 23 are not affected. It can be initialized as it is.

  The initialization of the master 11 that has runaway is transmitted to the access blocking unit 402 ′ by, for example, a signal P26 from the reset signal generating unit 407. As described above, for example, when the access blocking and initialization of the runaway master (11) are completed, the access blocking by the access blocking circuit 40 '(41') is released.

  As described above in detail, according to the access blocking circuits of the first and second embodiments, for example, when the master runs away, the access between the master and the internal bus (slave) is blocked, and at the time of recovery, only the runaway master It becomes possible to restore the system by initializing the. When the master access is cut off, protocol correction is performed on the downstream internal bus (slave) and the idle state is maintained.

  As described above, the present embodiment has been described mainly using the AMXI (registered trademark) AXI (registered trademark) protocol as an example, but the present embodiment is not limited to this. The present embodiment includes, for example, the above-mentioned AMXI (registered trademark) AXI (registered trademark), AHB (registered trademark) and APB (registered trademark), as well as AMBA (registered trademark) ACE (registered trademark) ( AXI (registered trademark) Coherency Extensions).

  Further, the present embodiment can be applied to a semiconductor integrated circuit using a bus standard other than AMBA (registered trademark) such as OCP (Open Core Protocol) or PIF (Xtensa Processor Interface Protocol). Furthermore, the application of the present embodiment is not limited to a semiconductor integrated circuit, but can be widely applied to a system, a server, and the like using a plurality of semiconductor integrated circuits. Note that the protocol correction circuit mounting method and pseudo-transfer method depend on each bus protocol (bus standard).

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
An access blocking circuit provided between a master and a bus to which at least one slave is connected,
An abnormality detection unit for detecting an abnormality of the master;
When an abnormality of the master is detected by the abnormality detection unit, an access blocking unit that blocks the access of the master from which an abnormality has been detected;
A protocol correction unit that corrects a protocol by the master whose access is blocked and holds the slave in an idle state,
An access blocking circuit characterized by that.

(Appendix 2)
The abnormality detection unit
A first monitoring unit for monitoring a transfer state of the bus between the master and the slave;
A second monitor unit for monitoring the transfer performance of the bus between the master and the slave;
A status receiving unit that receives outputs of the first monitor unit and the second monitor unit and detects an abnormality between the master and the slave;
The access cut-off circuit according to appendix 1, wherein:

(Appendix 3)
further,
A system IF unit for exchanging signals with the system controller and controlling the access blocking unit;
When recovering the system, the system controller initializes only the master whose access is blocked,
The access cut-off circuit according to Supplementary Note 2, wherein

(Appendix 4)
The system IF unit is
To the system controller, an access blocking request signal for requesting access blocking and an access blocking completion signal indicating that the access blocking has been completed are output,
Receiving an access blocking permission signal indicating permission of access blocking from the system controller;
The access cut-off circuit according to appendix 3, wherein

(Appendix 5)
further,
Controlling the access blocking unit, and having a reset signal generating unit that generates a master reset signal that initializes only the master whose access is blocked when the system is restored,
The access cut-off circuit according to appendix 3, wherein

(Appendix 6)
The first monitor unit includes:
Monitoring whether the handshake between the master and the slave does not complete after a preset number of cycles based on the bus standard;
The access blocking circuit according to any one of Supplementary Note 2 to Supplementary Note 5, wherein:

(Appendix 7)
The second monitor unit includes
Monitoring whether the data transfer rate between the master and the slave differs by a threshold or more than a value based on the standard of the bus;
The access blocking circuit according to any one of appendix 2 to appendix 6, wherein

(Appendix 8)
A plurality of the masters are provided, and the access blocking circuit according to any one of appendix 1 to appendix 7 is provided between each master and the bus.
A semiconductor integrated circuit.

(Appendix 9)
An access blocking method for blocking access between a master and a bus to which at least one slave is connected,
Detecting an abnormality of the master,
Blocking access to the master where an abnormality is detected,
Correct the protocol by the master whose access is blocked, and keep the slave in an idle state;
An access blocking method characterized by the above.

(Appendix 10)
The abnormality detection of the master is
Monitor the transfer state of the bus between the master and the slave,
Monitor the transfer performance of the bus between the master and the slave,
Detecting an abnormality of the master based on the monitoring result of the transfer state of the bus and the monitoring result of the transfer performance of the bus;
The access blocking method according to appendix 9, characterized in that:

(Appendix 11)
further,
Interact with the system controller to control access blocking of the master,
When the system is restored, only the master whose access is blocked by the system controller is initialized.
The access blocking method according to Supplementary Note 10, wherein

(Appendix 12)
Control of access blocking of the master is as follows:
To the system controller, an access blocking request signal for requesting access blocking and an access blocking completion signal indicating that the access blocking has been completed are output,
An access blocking permission signal indicating permission of access blocking is received from the system controller.
The access blocking method according to Supplementary Note 11, wherein the access is blocked.

(Appendix 13)
further,
Controlling access blocking of the master,
When restoring the system, a master reset signal is generated that initializes only the master whose access has been blocked.
The access blocking method according to Supplementary Note 10, wherein

(Appendix 14)
The bus transfer status monitor is:
Monitoring whether the handshake between the master and the slave does not complete after a preset number of cycles based on the bus standard;
14. The access blocking method according to any one of supplementary note 10 to supplementary note 13, characterized by:

(Appendix 15)
The bus transfer performance monitor is:
Monitoring whether the data transfer rate between the master and the slave differs by a threshold or more than a value based on the standard of the bus;
The access blocking method according to any one of Supplementary Note 10 to Supplementary Note 14, wherein:

1,100 system LSI (semiconductor integrated circuit)
3,103 Internal bus (bus)
5 System controller 11-13, 111-113 Master 21, 22, 121, 122 Slave 40, 41-43, 40 ', 41'-43' Access cut-off circuit
200 Counter device
401 System IF
402, 402 'Access blocker
403 Protocol correction unit
404 status receiver
405 Protocol monitor
406 Performance monitor
407 Reset signal generator

Claims (7)

An access blocking circuit provided between a master and a bus to which at least one slave is connected,
An abnormality detection unit for detecting an abnormality of the master;
When an abnormality of the master is detected by the abnormality detection unit, an access blocking unit that blocks the access of the master from which an abnormality has been detected;
A protocol correction unit that corrects a protocol by the master whose access is blocked and holds the slave in an idle state,
The abnormality detection unit
A first monitor that monitors whether a data transfer rate between the master and the slave differs by a threshold or more from a value based on the standard of the bus;
A status receiving unit that receives an output of the first monitor unit and detects an abnormality between the master and the slave;
An access blocking circuit characterized by that. The abnormality detection unit further includes:
A second monitor unit for monitoring a transfer state of the bus between the master and the slave;
The status receiving unit receives outputs of the first monitor unit and the second monitor unit, and detects an abnormality between the master and the slave;
The access blocking circuit according to claim 1, wherein: further,
A system IF unit for exchanging signals with the system controller and controlling the access blocking unit;
When recovering the system, the system controller initializes only the master whose access is blocked,
The access blocking circuit according to claim 1 or 2, characterized in that further,
Controlling the access blocking unit, and having a reset signal generating unit that generates a master reset signal that initializes only the master whose access is blocked when the system is restored,
The access blocking circuit according to claim 3, wherein: A plurality of the masters are provided, and the access blocking circuit according to any one of claims 1 to 4 is provided between the masters and the buses.
A semiconductor integrated circuit. An access blocking method for blocking access between a master and a bus to which at least one slave is connected,
An access blocking circuit provided between the master and a bus to which at least one slave is connected;
Detecting an abnormality of the master,
Blocking access to the master where an abnormality is detected,
Correct the protocol by the master that has been blocked from access, and keep the slave in an idle state,
For detecting the abnormality of the master, the access blocking circuit
Monitoring whether the data transfer rate between the master and the slave differs by more than a threshold value from a value based on the standard of the bus;
Detecting an abnormality of the master based on a monitoring result of a data transfer rate between the master and the slave;
An access blocking method characterized by the above. The master abnormality detection is performed by the access blocking circuit,
Monitor the transfer state of the bus between the master and the slave,
Detecting an abnormality of the master based on the monitoring result of the transfer state of the bus and the monitoring result of the data transfer rate between the master and the slave;
The access blocking method according to claim 6.

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