JP6589320B2 - Nonvolatile storage device, driver, electro-optical device, electronic apparatus, and inspection method of nonvolatile storage device - Google Patents

Description

  The present invention relates to a nonvolatile memory device, a driver, an electro-optical device, an electronic apparatus, a method for inspecting the nonvolatile memory device, and the like.

  Among non-volatile storage devices (non-volatile memories) that can hold data when power is not supplied, for example, PROM (Programmable Read Only Memory), EPROM (Erasable PROM), EEPROM (Electrically Erasable PROM) Etc. are known. These nonvolatile storage devices are used in, for example, an OTP (One Time Programmable) memory that stores IC setting values, a storage device that stores programs and data, and the like.

  As a prior art of a nonvolatile memory device, for example, Patent Document 1 includes a memory cell array having first and second memory cells for storing complementary data, and a read circuit having a sense amplifier. A nonvolatile memory device is disclosed that reads data stored in the first and second memory cells by comparing the current flowing through the second memory cell with a reference current.

  The nonvolatile memory device disclosed in Patent Document 2 includes a plurality of memory cells, a reference current generation circuit having a plurality of reference current sources, a current of one reference current source among the plurality of reference current sources, and a plurality of memories. A read circuit for comparing a current flowing in a selected memory cell selected from the cells is included. As the one reference current source, a reference current source having a large read margin with respect to the selected memory cell is selectively selected from the plurality of reference current sources.

JP 2011-192329 A JP 2007-207343 A

  In the prior arts of Patent Documents 1 and 2, data is read by comparing the current flowing through the memory cell with the reference current. However, as a precondition, the reference current itself needs to be normal. However, in the prior art, the inspection of the reference current itself is insufficient.

  In the inspection of the reference current, the current flowing through the reference cell can be measured by a DC test or the like. However, the marginal read that determines whether the write level is necessary for the data retention characteristic is based on the premise that the current mirror circuit that current mirrors the current flowing through the reference cell is normal, and the current mirror circuit is abnormal. In some cases, correct judgment cannot be made.

  A non-volatile memory device, a driver, an electro-optical device, an electronic device, a non-volatile memory device inspection method, and the like that can inspect whether the marginal read is at an appropriate level by inspecting the reference current itself.

  One aspect of the present invention includes a plurality of nonvolatile memory cells, a reference cell for generating a reference current, a first reference test cell and a second reference test cell having different current supply capabilities, A read circuit for comparing the reference current with a current flowing in a selected memory cell among a plurality of memory cells, the read circuit including a first current flowing in the first reference test cell and the read current; The present invention relates to a nonvolatile memory device that performs a comparison process between a second current flowing in a second reference test cell and the reference current.

  According to one aspect of the present invention, a first reference inspection cell and a second reference inspection cell are provided, and a comparison process between the first current flowing in the first reference inspection cell and the reference current; Comparison processing between the second current flowing through the second reference test cell and the reference current is performed. By inspecting the reference current itself in this manner, it is possible to inspect whether the marginal read is at an appropriate level.

  In one embodiment of the present invention, when the target value of the reference current is IrefT, the current value of the first current is I1, and the current value of the second current is I2, I1 <IrefT <I2 It may be.

  By comparing the first current and the second current satisfying I1 <IrefT <I2 with the reference current, the current value of the reference current becomes the current value I1 of the first current and the current value of the second current. It can be checked whether or not it is between I2. Thereby, it can be checked that the reference current in the marginal read is at an appropriate level.

  In one embodiment of the present invention, a current mirror circuit that generates a reference current by performing a current mirror of a current from the reference cell may be included.

  For example, the same number of read circuits as the number of bits of one word of memory access are provided. Since a reference current is generated for each readout circuit, it takes time to DC test all the reference currents. For this reason, it is conceivable to reduce the time by performing a DC test on the current from the reference cell. However, if the current mirror circuit fails, the reference current becomes inaccurate. In this regard, according to one aspect of the present invention, the reference current itself can be inspected using the readout circuit, so that the reliability and efficiency of the inspection can be improved.

  In the aspect of the invention, each of the memory cells may be an OTP (One Time Programmable) memory cell.

  The OTP memory needs to be able to hold the data for a long time after writing the data once. Therefore, it is necessary to inspect the data retention characteristics by marginal read. However, if the reference current is not inspected, marginal read may not be performed at an appropriate level. In this regard, according to one embodiment of the present invention, the reference current can be inspected, so that the marginal read can be performed at an appropriate level.

  In the aspect of the invention, each of the memory cells, the first reference inspection cell, and the second reference inspection cell may be configured by transistors having the same structure.

  By configuring the memory cell and the first and second reference test cells with transistors having the same structure, they can be arranged in the same memory cell array, and the first read circuit for reading data from the memory cell array. The first and second currents from the second reference test cell can be compared with the reference current. As a result, the reference current can be inspected by the same read operation as the marginal read of the memory cell, and the reliability of the inspection can be improved.

  In one embodiment of the present invention, the third reference inspection cell and the fourth reference inspection cell having different current supply capacities are provided, and the readout circuit flows through the third reference inspection cell. A comparison process may be performed between the reference current and the fourth current flowing in the current and the fourth reference test cell.

  According to one aspect of the present invention, two sets of reference inspection cells, the first and second reference inspection cells, and the third and fourth reference inspection cells, are provided, and each set of reference inspection cells is used. The reference current is checked with the current from the cell. If the test results of the reference currents in each set do not match, there is a possibility that one of the reference test cells has failed. However, in one aspect of the present invention, the test is not performed in such a case. You can pass.

  In one embodiment of the present invention, the first reference test cell and the second reference test cell are provided for each read circuit of the plurality of read circuits. Also good.

  For example, the same number of read circuits as the number of bits of one word of memory access are provided. According to one embodiment of the present invention, a reference current can be inspected for each readout circuit of the plurality of readout circuits. Since the reference current can be inspected by the comparison process (function test) by the readout circuit, the inspection can be made more efficient than when the DC test is used.

  In one embodiment of the present invention, the reference current is input to the first input node of the readout circuit, and one ends of a plurality of column selection transistors are connected to the second input node of the readout circuit. The plurality of memory cells, the first reference inspection cell, and the second reference inspection cell may be connected to the other end of the plurality of column selection transistors.

  In this way, the first and second currents and the reference from the first and second reference test cells are turned on by turning on the column selection transistor connected to the first and second reference test cells. Comparison processing with current can be performed. That is, the reference current can be inspected by selecting the first and second reference inspection cells with the same address designation as the memory cell.

  Another embodiment of the present invention relates to a driver including any of the nonvolatile memory devices described above and a driving circuit that drives a display panel.

  Another aspect of the invention relates to an electro-optical device including the driver described above.

  Another embodiment of the present invention relates to an electronic device including the nonvolatile memory device described in any of the above.

  According to another aspect of the present invention, a plurality of nonvolatile memory cells, a reference cell for generating a reference current, a first reference inspection cell, a second reference inspection cell, In a test method for a nonvolatile memory device, comprising: a read circuit that compares a current flowing in a selected memory cell among memory cells and the reference current; and a first current flowing in the first reference test cell; A comparison process with a reference current is performed by the readout circuit, and a comparison process between the second current flowing in the second reference test cell having a current supply capability different from that of the first reference test cell and the reference current is performed. The present invention relates to a nonvolatile memory device inspection method performed by the reading circuit.

  In another aspect of the present invention, in the first comparison process and the second comparison process, a current value of the reference current is a current value of the first current and a current value of the second current. If it is determined that it is between, the reference current test may be determined to be acceptable.

  In this way, it is possible to check whether the current value of the reference current is between the current value of the first current and the current value of the second current, and the reference current in the marginal read is at an appropriate level. Can be inspected.

The comparative structural example of a non-volatile memory device. The flowchart which shows the test | inspection procedure of the comparative structural example of a non-volatile memory device. Explanatory drawing of marginal lead. 1 is a first configuration example of a nonvolatile memory device according to an embodiment. Explanatory drawing of a reference current test | inspection. 6 is a flowchart showing an inspection procedure of the nonvolatile memory device according to the embodiment. Explanatory drawing of a reference current test | inspection. 2 shows a second configuration example of the nonvolatile memory device according to the embodiment. A modification of the current mirror circuit. 3 is a detailed configuration example of a nonvolatile memory device according to the embodiment. 2 shows a detailed configuration example of a memory cell array. Example of driver configuration. Configuration examples of electro-optical devices and electronic devices.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

  For example, a description will be given below of a FAMOS (Floating Gate Avalanche Injection MOS) memory in which data is written by charge injection into the floating gate, but the present invention is also applicable to a nonvolatile memory other than the FAMOS memory. That is, the present invention can be applied to any nonvolatile memory that reads data by comparing the reference current and the cell current. For example, the present invention can be applied to a MONOS (Metal Oxide Nitride Oxide Silicon) memory for writing data by injecting charges into an insulating charge storage layer (for example, a silicon nitride film).

1. Comparative Example FIG. 1 shows a comparative configuration example of a nonvolatile memory device. The nonvolatile memory device includes a reference cell 10, a current mirror circuit 20, a memory cell array 30, a read circuit SA, switch elements SWR and SWC, and a reference cell selection transistor TR3.

  The memory cell array 30 includes a plurality of nonvolatile memory cells and a plurality of column selection transistors. One of the plurality of memory cells is selected by a word line and a column line, and the selected memory cell is connected to the bit line BL. FIG. 1 illustrates two memory cells MCA and MCB among a plurality of memory cells, and column selection transistors TCA and TCB corresponding to the memory cells MCA and MCB among a plurality of column selection transistors.

  Taking the memory cell MCA as an example, the memory cell MCA includes P-type MOS (Metal Oxide Semiconductor) transistors TFGA, TWA connected in series between the high potential side power supply VDD and one end (source) of the column selection transistor TCA. Including.

  The other end (drain) of the column selection transistor TCA is connected to the bit line BL. The transistor TFGA has a FAMOS structure and stores data (“0” or “1”) by electric charge accumulated in a gate in a floating state. The transistor TWA is turned on when the gate thereof is connected to the word line WLA and the logic level of the word line WLA is active (low level). The transistor TCA, which is a P-type MOS transistor, is turned on when its gate is connected to the column line CLA and the logical level of the column line CLA is active (low level). When both the transistors TWA and TCA are turned on, the memory cell MCA is selected, and the drain current of the transistor TFGA is output to the bit line BL as the cell current Icel.

  Similarly, the memory cell MCB includes a P-type FAMOS transistor TFGB and a P-type MOS transistor TWB whose gate is connected to the word line WLB. When both the transistors TWB and TCB are turned on, the memory cell MCB is selected. The

  The reference cell 10 is a cell that outputs a reference cell current IRC for generating a reference current Iref. The reference cell 10 includes P-type MOS (Metal Oxide Semiconductor) transistors TR1 and TR2 connected in series between the high-potential-side power supply VDD and one end (source) of the reference cell selection transistor TR3. The reference cell selection transistor TR3 is a P-type MOS transistor.

  The transistors TR1, TR2, and TR3 have the same structure and the same size as the transistors TFGA, TWA, and TCA of the memory cell MCA, respectively. The gate of the transistor TR1 is connected to a low potential side power source VSS (for example, ground), and is in an on state. A control signal SRC is input to the gates of the transistors TR2 and TR3. When the control signal SRC is active (low level), the drain current of the transistor TR1 is output as the reference cell current IRC from the other end (drain) of the transistor TR3.

  The current mirror circuit 20 is a circuit that generates a reference current Iref for determining data held in a memory cell by mirroring the reference cell current IRC. The current mirror circuit 20 includes P-type MOS transistors TA, TB1 to TB3, and N-type MOS transistors TB4 to TB7.

  The reference cell current IRC flows through the transistor TB6 to the drain of the transistor TB7, and the current IRC is mirrored from the transistor TB6 to the transistor TB5. The mirrored current flows through the transistors TB3 and TB4 to the drain of the transistor TB2, and is mirrored from the transistor TB2 to the transistor TA. The drain current of the transistor TA is output as a reference current Iref to the read circuit SA via the transistor TB1. When the control signal SRead becomes active (high level) and the transistors TB4 and TB6 are turned on, and when the control signal SRef becomes active (low level) and the transistors TB1 and TB3 are turned on, the above mirror is turned on. The reference current Iref is output.

  The read circuit SA compares the current Icel flowing through the selected memory cell among the plurality of memory cells with the reference current Iref. Specifically, the read circuit SA is composed of a sense amplifier, a reference current Iref is supplied to the first input node of the sense amplifier, a cell current Icel is supplied to the second input node, and the sense amplifier The result of comparing the magnitude relationship is output as read data from the memory cell. For example, when Icel> Iref, data “1” (first logic level) is output as a comparison result, and when Icel <Iref, data “0” (second logic level) is output as a comparison result. To do.

  As shown in FIG. 10, a read circuit SA is provided corresponding to the number of bits of one word in memory access. FIG. 10 shows a case where one word is 16 bits, and 16 read circuits SA1 to SA16 and 16 bit lines BL1 to BL16 are provided. Transistors TA1 to TA16 that output reference currents Iref1 to Iref16 by mirrors are provided corresponding to the read circuits SA1 to SA16, respectively, and the reference cell 10 and the bias generator 22 (transistors TB2 to TB7 in FIG. 1) are common. Is provided. In this case, the read data is 16 bits D1 to D16.

  FIG. 2 is a flowchart showing the inspection procedure of the nonvolatile memory device. In the inspection, first, the switch element SWR is turned on, the reference cell current IRC is output from the test terminal, and the reference cell current IRC is measured by the inspection device (tester) (step S1).

  Next, test data is written into the memory cell (charge is accumulated in the floating gate), the switch element SWC is turned on, the cell current Icel from the memory cell is output from the test terminal, and the cell is tested by the inspection device (tester). Current Icel is measured (step S2). This step is a sampling test, in which cell currents of several memory cells selected from the memory cell array 30 are measured.

  Next, test data is written in the memory cell, and marginal read is performed to read the data from the read circuit SA (step S5). This step is a function test (inspection by digital input / output between the inspection apparatus and the IC), and is performed for all memory cells included in the memory cell array 30, for example. Since the DC test in step S2 is a sampling test, a margin test is performed on all memory cells by the function test in step S5.

  In the marginal read, it is inspected whether or not electric charges are written to the floating gate of the memory cell with a sufficient margin. In other words, the nonvolatile memory may hold data for a long period of time (for example, an OTP memory that stores setting values at the time of manufacture), but checks whether or not charges that can hold the long-term data can be written. . In the marginal read, the cell current Icel and the reference current Iref are compared by the read circuit SA, and if Icel> Iref (that is, if data “1” is read), it is determined as a path.

  Now, by performing marginal read as described above, it is inspected whether the write level necessary for the data retention characteristic is reached, but the reference current Iref itself is not inspected. Therefore, when the reference current Iref is not a correct current value, there is a problem that correct determination cannot be performed by marginal read.

  For example, as shown in FIG. 3, it is assumed that the current level of the reference cell current IRC output from the reference cell 10 is 100% and the mirror ratio of the current mirror circuit 20 is 1/2. When the current mirror circuit 20 is normal, the current level of the reference current Iref is 50%. In the marginal read, if the current level of the cell current Icel is greater than 50%, the pass (pass) is passed, and if the current level is smaller, the pass (fail) is determined.

  On the other hand, when the current mirror circuit 20 has an abnormality (for example, a short circuit or an open transistor), the current level of the reference current Iref is smaller than 50% (for example, 30%) or larger (for example, 70%). To do. When the current level becomes small, the cell current Icel passes even if the current level is less than 50%, so that a memory cell with a shallow write level is regarded as a non-defective product, and the risk of data retention abnormality is increased. On the other hand, when the current level is increased, the cell current Icel is passed even if the current level is higher than 50%. Therefore, a deeply written memory cell is regarded as a defective product, and the inspection becomes excessive.

  As a method of inspecting the reference current Iref, for example, a method of inspecting by a DC test by providing a path for outputting the output of the current mirror circuit 20 to a test terminal is conceivable. However, since the DC test does not pass through the read circuit SA, the operation is different from that of the marginal read function test, which may reduce the reliability of the test. Further, as shown in FIG. 10, it is necessary to inspect the reference currents Iref1 to Iref16 corresponding to the number of bits of one word. Compared with the function test, the DC test is inefficient because it takes time, and the inspection time increases as the number of bits in one word increases.

  Alternatively, a slight charge write to the memory cell and measurement of the cell current Icel are repeated, the cell current Icel is adjusted to the marginal read current level, and the cell current Icel and the reference current Iref are compared by the read circuit SA. A method for inspecting the reference current Iref can be considered. However, since the DC test of the cell current Icel is repeated, it takes time and is not a practical method.

2. Nonvolatile Storage Device FIG. 4 shows a configuration example of the nonvolatile storage device of the present embodiment that can solve the above-described problems. The nonvolatile memory device includes a reference cell 10, a current mirror circuit 20, a memory cell array 30, a read circuit SA, switch elements SWR and SWC, and a reference cell selection transistor TR3. In addition, the same code | symbol is attached | subjected about the component already demonstrated and description is abbreviate | omitted suitably.

  The memory cell array 30 includes a plurality of nonvolatile memory cells, a first reference inspection cell ROMCA and a second reference inspection cell ROMCB having different current supply capabilities, and a plurality of column selection transistors. FIG. 4 shows two memory cells MCA and MCB among a plurality of memory cells, and columns corresponding to memory cells MCA and MCB and first and second reference test cells ROMCA and ROMCB among a plurality of column selection transistors. The selection transistors TCA to TCD are shown.

  The first and second reference inspection cells ROMCA and ROMCB and the memory cells MCA and MCB are composed of transistors having the same structure.

  Taking the first reference test cell ROMCA as an example, the first reference test cell ROMCA is a P-type MOS connected in series between the high potential side power supply VDD and one end (source) of the column selection transistor TCC. Includes transistors TROMA, TWC.

  The transistor TROMA is a transistor having the same structure as that of the floating gate transistor TFGA, but the gate is connected to the low-potential-side power source VSS and is in the on state. The transistors TWC and TCC have the same structure and the same size as the transistors TWA and TCA of the memory cell MCA. The transistor TWC has its gate connected to the word line WLC, and the transistor TCC has its gate connected to the column line CLC. When both the transistors TWC and TCC are turned on, the first reference test cell ROMCA is selected, and the drain current I1 of the transistor TROMA is output to the bit line BL as the cell current Icel.

  Similarly, the second reference test cell ROMCB has the same structure as the FAMOS transistor and has a P-type MOS transistor TROB whose gate is connected to the low-potential-side power source VSS and a P-type whose gate is connected to the word line WLD. MOS transistor TWD.

  The transistors TROMA and TRROM are different in size (gate width (channel width) and gate length (channel length)), whereby the current supply capability (for example, on-resistance) of the first and second reference test cells ROMCA and ROMCB. Is different. That is, the cell current Icel = I1 when the first reference test cell ROMCA is selected is different from the cell current Icel = I2 when the second reference test cell ROMCB is selected. The first and second reference inspection cells ROMCA and ROMCB may be arranged anywhere in the memory cell array (for example, cells MC11 to MC88 in FIG. 11) connected to the read circuit SA. For example, the word lines WLC and WLD may be the same word line and the column lines CLC and CLD may be different, or the word lines WLC and WLD may be different word lines and the column lines CLC and CLD may be the same column line. May be.

  The read circuit SA performs a comparison process of the reference current Iref with the first current I1 flowing through the first reference test cell ROMCA and the second current I2 flowing through the second reference test cell ROMCB.

  Specifically, the reference current Iref is input to the first input node of the read circuit SA, and one ends of the plurality of column selection transistors TCA to TCD are connected to the second input node of the read circuit SA. A plurality of memory cells MCA and MCB and first and second reference inspection cells ROMCA and ROMCB are connected to the other ends of the plurality of column selection transistors TCA to TCD. The read circuit SA compares the cell current Icel = I1 with the reference current Iref when the first reference test cell ROMCA is selected, and the cell current when the second reference test cell ROMCB is selected. Icel = I2 is compared with the reference current Iref, and the comparison result is output. When Icel> Iref, data “1” is output as a comparison result, and when Icel <Iref, data “0” is output as a comparison result.

  As described above, the first and second reference inspection cells ROMCA and ROMCB having different current supply capacities are provided, and the reference current Iref is compared with the currents I1 and I2 flowing through the cells ROMCA and ROMCB. The current level of Iref can be checked. Since the reference current Iref itself is inspected, it can be ensured that the marginal read is determined at an appropriate current level, and the risk of data retention abnormality and excessive inspection can be suppressed. In addition, since the reference current Iref can be inspected by the function test, it can be inspected by the same operation as the marginal read which is the function test, and the accuracy of the inspection is increased as compared with the method of DC testing the reference current Iref. In addition, the test can be performed at higher speeds than the method of DC testing the reference current Iref or the method of comparing the reference current Iref with a current level adjusted by repeating slight writing to the memory cell.

  As described above, the present invention is not limited to application to a FAMOS memory. The present invention can be applied to any nonvolatile memory (for example, a MONOS memory) that reads data by comparing a reference current and a cell current.

  When the target value of the reference current Iref is IrefT, the first current I1 that the first reference inspection cell ROMCA flows and the second current I2 that the second reference inspection cell ROMCB flows are I1 <IrefT <I2 is satisfied. For simplicity, the code indicating the current and the code indicating the current value of the current are the same.

  For example, when the current level of the reference cell current IRC flowing through the reference cell 10 is 100% and the mirror ratio of the current mirror circuit 20 is 1/2, the current level of the target value IrefT is 50%. In this case, for example, the current level of the first current I1 is set to 30% to 45%, and the current level of the second current I2 is set to 70% to 55%. As shown in FIG. 5, it is assumed that the current level of the first current I1 is set to 45% and the current level of the second current I2 is set to 55%. When I1 <Iref <I2 with respect to the actual reference current Iref, data “0” is read by comparison with the first current I1 (determination of whether or not I1> Iref), and the second current I2 The data “1” is read out by comparison with (determination of whether or not I2> Iref), and the inspection is determined to be a pass. On the other hand, when data of other patterns is read, since I1 <Iref <I2 is not satisfied, the inspection is determined to fail. In this way, it is checked that the reference current Iref is within ± 5% of the current level 50% of the target value IrefT.

  As described above, in this embodiment, when it is determined that the current value of the reference current Iref is between the current value of the first current I1 and the current value of the second current I2, the reference current Iref is inspected. Is determined to be acceptable. This ensures that the current value of the reference current in the marginal read is between the current value of the first current I1 and the current value of the second current I2, so that the marginal read is performed at an appropriate level. Can be inspected.

3. Inspection Flow FIG. 6 is a flowchart showing the inspection procedure of the nonvolatile memory device of this embodiment. Note that the steps already described are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In the inspection, first, the reference cell current IRC is measured (step S1). Next, the cell current Icel is measured (step S2).

  Next, the switch element SWC is turned on, and the first and second currents I1 and I2 from the first and second reference test cells ROMCA and ROMCB are output from the test terminal, and the test device (tester) performs the first operation. 1. First and second currents I1 and I2 are measured (step S3). This step is, for example, a sampling inspection. As shown in FIG. 10, read circuits are provided for the number of bits of one word, and first and second reference inspection cells ROMCA and ROMCB are provided corresponding to each read circuit. In the example of FIG. 10, 16 bits × 2 reference test cells are provided. A DC test is performed on some of the 32 reference inspection cells.

  Next, the first current I1 from the first reference test cell ROMCA and the reference current Iref are compared by the read circuit SA (first comparison process), and the second current from the second reference test cell ROMCB is then compared. The current I2 and the reference current Iref are compared by the readout circuit SA (second comparison process) (step S4). This step is a function test. As a comparison result, as described with reference to FIG. 5, data “0” or “1” is output for each of the currents I1 and I2. As shown in FIG. 7, when eight read circuits are provided, read data for one word is 8-bit D1 to D8. For example, if D1 to D8 are all “0” in the determination of I1> Iref, and D5 is “0” and D1 to D4 and D6 to D8 are “1” in the determination of I2> Iref, D5 is a failure. The entire inspection in step S4 also fails.

  Next, marginal read is performed with the reference current Iref inspected in step S4 (step S5).

4). Second Configuration Example FIG. 8 shows a second configuration example of the nonvolatile memory device of this embodiment. The nonvolatile memory device includes a reference cell 10, a current mirror circuit 20, a memory cell array 30, a read circuit SA, switch elements SWR and SWC, and a reference cell selection transistor TR3. In addition, the same code | symbol is attached | subjected about the component already demonstrated and description is abbreviate | omitted suitably.

  The memory cell array 30 includes a plurality of nonvolatile memory cells, a first reference test cell ROMCA and a second reference test cell ROMCB having different current supply capabilities, and a third reference test cell having different current supply capabilities. A ROMCC and a fourth reference test cell ROMCD, and a plurality of column selection transistors are included. FIG. 8 shows four memory cells MCA to MCD among a plurality of memory cells, and columns corresponding to memory cells MCA to MCD and first to fourth reference test cells ROMCA to ROMCD among a plurality of column selection transistors. The selection transistors TCA to TCD are shown.

  The third reference test cell ROMCC includes a P-type MOS transistor TRMC whose gate is connected to the low-potential-side power supply VSS and a P-type MOS transistor TWG whose gate is connected to the word line WLG. The transistors TROMAC and TWG have the same structure and the same size as the transistors TROMA and TWC of the first reference test cell ROMCA, respectively. The fourth reference test cell ROMCD includes a P-type MOS transistor TROMD whose gate is connected to the low-potential-side power source VSS, and a P-type MOS transistor TWH whose gate is connected to the word line WLH. The transistors TROMD and TWH have the same structure and the same size as the transistors TROMB and TWD of the second reference test cell ROMCB, respectively.

  The read circuit SA performs a comparison process of the reference current Iref with the third current I3 flowing through the third reference inspection cell ROMCC, the fourth current I4 flowing through the fourth reference inspection cell ROMCD, and the reference current Iref.

  As described above, the third and fourth reference inspection cells ROMCC and ROMCD similar to the first and second reference inspection cells ROMCA and ROMCB are provided, and the currents I1 to I4 flowing through these cells ROMCA to ROMCD are provided. By comparing the reference current Iref, the abnormality of the reference inspection cells ROMCA to ROMCD can be inspected. That is, when the comparison results of the first and third currents I1 and I3 and the reference current Iref are different, it can be estimated that either the first or third reference inspection cell ROMCA or ROMCC is abnormal. When the comparison results of the second and fourth currents I2 and I4 and the reference current Iref are different, it can be estimated that either the second or fourth reference test cell ROMCB or ROMCD is abnormal.

  In the above description, the first and third reference inspection cells ROMCA and ROMCC are selected with the same column address, and the second and fourth reference inspection cells ROMCB and ROMCD are selected with the same column address. As described above, the relationship between the reference test cell and the column address is not limited to this. That is, the first and third reference test cells ROMCA and ROMCC may be selected with different column addresses, and the second and fourth reference test cells ROMCB and ROMCD may be selected with different column addresses. .

5. FIG. 9 shows a modification of the current mirror circuit 20. The current mirror circuit 20 includes P-type MOS transistors TA and TB1 to TB3, and N-type MOS transistors TB6 and TB7. The mirror ratio switching transistors include N-type MOS transistors TTA1 to TTAn (n is an integer of 2 or more) and TTB1 to TTBn.

  Control signals Test1 to Testn are input to the gates of the transistors TTA1 to TTAn. The transistor TTAi (i is an integer of 1 to n) is turned on when the control signal Testi is active (high level), and mirrors the reference cell current IRC. The mirror ratio is set depending on which of the control signals Test1 to Testn is active. The number of signals to be activated may be one or more.

  For example, when there are a plurality of test modes, the mirror ratio may be changed in each test mode, or the mirror ratio may be changed between marginal read and normal data reading. For example, in an acceleration test in which deterioration with time is accelerated by baking, data written before baking is read after baking. The charge accumulated in the floating gate has been reduced by baking, and since the function should be normal in the accelerated test, the mirror ratio in reading after baking is made smaller than the mirror ratio in marginal reading.

6). Detailed Configuration Example FIG. 10 shows a detailed configuration example of the nonvolatile memory device of the present embodiment. The nonvolatile memory device includes a reference cell 10, a current mirror circuit 20, read circuits SA1 to SA16, and a memory cell array 30. In addition, the same code | symbol is attached | subjected about the component already demonstrated and description is abbreviate | omitted suitably.

  Memory cell array 30 includes memory cell arrays MA1 to MA16 connected to bit lines BL1 to BL16. Cell currents Icel1 to Icel16 are output from the memory cell arrays MA1 to MA16 to the bit lines BL1 to BL16.

  The current mirror circuit 20 includes a bias generation unit 22 and P-type MOS transistors TA1 to TA16 provided corresponding to the read circuits SA1 to SA16. The bias generation unit 22 corresponds to the transistors TB2 to TB7 in FIGS. The transistors TA1 to TA16 respectively output reference currents Iref1 to Iref16 in which the reference cell current IRC is mirrored.

  The read circuits SA1 to SA16 compare the cell currents Icel1 to Icel16 with the reference currents Iref1 to Iref16, and output the comparison results as data D1 to D16.

  FIG. 11 shows a detailed configuration example of each memory cell array of the memory cell arrays MA1 to MA16. The memory cell array of FIG. 11 includes memory cells MC11 to MC88 of 8 rows and 8 columns, and column selection transistors TC1 to TC8.

  Memory cells having the same column address are connected to the same column selection transistor. For example, the output (the drain of the word selection transistor) of the memory cells MC11 to MC18 selected by the column line CL1 is connected to the source of the column selection transistor TC1. Memory cells with the same row address are connected to the same word line. For example, the gates of the word selection transistors of the memory cells MC11 to MC81 selected by the word line WL1 are connected to the word line WL1.

  For example, when the word line WL1 and the column line CL1 are selected, the memory cell MC11 is selected in each of the memory cell arrays MA1 to MA16. Then, the current from the memory cell MC11 is compared by the read circuits SA1 to SA16 as cell currents Icel1 to Icel16, and the data held in the memory cell MC11 is read as data D1 to D16.

  The reference test cells are arranged in the memory cell of FIG. 11 as follows, for example. For example, memory cells MC11 to MC81 connected to the word line WL1 are provided as test cells (cells not used for normal data holding), and for example, the first and second references are the memory cells MC11 and MC21. Inspection cells ROMCA and ROMCB are provided. Alternatively, the memory cells MC12 to MC82 connected to the word line WL2 are provided as test cells, and for example, the third and fourth reference test cells ROMCC and ROMCD are provided as the memory cells MC12 and MC22, for example. These reference test cells are provided in each of the memory cell arrays MA1 to MA16.

7). Driver FIG. 12 shows a configuration example of a driver (display driver) to which the nonvolatile memory device of this embodiment is applied. The driver includes a CPU side write / read circuit 112, a CPU side column decoder 114, a RAM cell array 120 (RAM: Random Access Memory), a panel side read circuit 132, a panel side column decoder 134, a drive circuit 140, a control circuit 150, a read / write It includes a write control circuit 160, a row decoder 170, and an OTP memory 180 (nonvolatile storage device). The driver is configured as an integrated circuit device, for example.

  The OTP memory 180 includes the reference cell 10, the current mirror circuit 20, the memory cell array 30 (OTP cell array), the read circuit SA, and the switch elements SWR and SWC described with reference to FIG. Also, a row address decoder that decodes a row address into a word line address of the memory cell array 30, a column address decoder that decodes a column address into a column line address of the memory cell array 30, and a control that controls read / write to the memory cell array 30. Circuit.

  The OTP memory 180 is a memory that stores the setting value of the driver in a nonvolatile manner, and the setting value is written at the time of manufacture, for example. The setting value to be written is a setting value according to the user's usage environment (for example, a setting according to the type of display panel to be connected, etc.), or a setting value according to the electrical characteristics of the driver (for example, a correction value for manufacturing variation). ) Etc. are assumed.

  The control circuit 150 performs interface processing with an external processing unit and controls each unit of the driver. For example, display data is transferred to the read / write control circuit 160, display data read by the read / write control circuit 160 is transferred to the processing unit 400, and column addresses are supplied to the write circuit 110 and the read circuit 130. The mode setting signal is supplied to the reading circuit 130, the drive timing is controlled, and the like. It also controls data transfer with the OTP memory 180.

  The read / write control circuit 160 controls access to the RAM cell array 120. For example, control of write timing and read timing, control of ports (CPU side port, panel side port), supply of row address corresponding to write data to the row decoder 170, row decoder 170 of row address corresponding to read data Supply to

  The row decoder 170 performs a decoding process for converting a row address (logical address) into an address (physical address) of a word line in the RAM cell array 120. When accessing the CPU side port, the row address for the CPU side port is designated, and when accessing the panel side port, the row address for the panel side port is designated.

  The CPU side column decoder 114 performs a decoding process in which the CPU side column address is associated with the bit line address of the RAM cell array 120. The CPU side write / read circuit 112 writes data to the bit line selected by the CPU side column decoder 114 using the write buffer. Further, data is read from the selected bit line by the sense amplifier.

  The panel side column decoder 134 performs a decoding process for converting the panel side column address into the address of the bit line of the RAM cell array 120. The panel side read circuit 132 reads data from the bit line selected by the panel side column decoder 134 by the sense amplifier.

  The drive circuit 140 includes a data driver 142 (source driver) and a gate driver 144 (scan driver). The data driver 142 includes, for example, a gradation voltage generation circuit, a D / A conversion circuit, and an amplifier circuit (source amplifier). Then, the D / A conversion circuit selects a voltage corresponding to the display data read by the panel side read circuit 132 from the plurality of voltages generated by the gradation voltage generation circuit. The amplifier circuit amplifies the selected voltage and drives the data line of the display panel 200. The gate driver 144 includes, for example, a buffer circuit (gate buffer). Then, the buffer circuit drives (selects) the gate line of the display panel 200 based on the timing control from the control circuit 150.

8). Electro-Optical Device and Electronic Device FIG. 13 shows a configuration example of an electro-optical device and an electronic device to which the driver of this embodiment can be applied. As the electronic device of the present embodiment, various electronic devices equipped with a display device such as a projector, a television device, an information processing device (computer), a portable information terminal, a car navigation system, and a portable game terminal are assumed. it can.

  The electronic device illustrated in FIG. 13 includes an electro-optical device 350, a display controller 300 (host controller, first processing unit), a CPU 310 (second processing unit), a storage unit 320, a user interface unit 330, and a data interface unit 340. The electro-optical device 350 includes a driver 100 and a display panel 200.

  The display panel 200 is, for example, a matrix type liquid crystal display panel. Alternatively, the display panel 200 may be an EL (Electro-Luminescence) display panel using self-luminous elements. For example, the electro-optical device 350 is configured by connecting a flexible substrate to the display panel 200 and mounting the driver 100 (integrated circuit device) on the flexible substrate. Note that the driver 100 and the display panel 200 may not be configured as the electro-optical device 350 but may be incorporated into an electronic apparatus as individual components. For example, a flexible substrate for drawing out wiring is connected to the display panel 200, the driver 100 is mounted on a rigid substrate together with the display controller 300 and the like, and the display panel 200 is mounted by connecting the flexible substrate to the rigid substrate. Good.

  The user interface unit 330 is an interface unit that accepts various operations from the user. For example, it includes a button, a mouse, a keyboard, a touch panel mounted on the display panel 200, and the like. The data interface unit 340 is an interface unit that inputs and outputs image data and control data. For example, a wired communication interface such as a USB or a wireless communication interface such as a wireless LAN. The storage unit 320 stores the image data input from the data interface unit 340. Alternatively, the storage unit 320 functions as a working memory for the CPU 310 and the display controller 300. The CPU 310 performs control processing of various parts of the electronic device and various data processing. The display controller 300 performs control processing for the driver 100. For example, the display controller 300 converts the image data transferred from the data interface unit 340 or the storage unit 320 into a format that can be accepted by the driver 100, and outputs the converted image data to the driver 100. The driver 100 drives the display panel 200 based on the image data transferred from the display controller 300.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. In addition, the configuration and operation of the reference cell, current mirror circuit, readout circuit, memory cell array, nonvolatile storage device, driver, electro-optical device, and electronic device are not limited to those described in this embodiment, and various modifications may be made. Is possible.

10 reference cells, 20 current mirror circuit, 22 bias generator,
30 memory cell array, 100 drivers,
112 CPU side write / read circuit, 114 CPU side column decoder,
120 RAM cell array, 132 panel side lead circuit,
134 Panel side column decoder, 140 drive circuit,
142 data driver, 144 gate driver, 150 control circuit,
160 read / write control circuit, 170 row decoder, 180 storage device,
200 display panel, 300 display controller, 310 CPU,
320 storage unit, 330 user interface unit,
340 data interface unit, 350 electro-optical device,
BL bit line, BL1 bit line, I1-I4 first to fourth currents,
Icel cell current, IRC reference cell current,
Iref reference current, MCA memory cell, MC11 memory cell,
ROMCA to ROMCD first to fourth reference inspection cells,
SA readout circuit, SA1 readout circuit, TCA column selection transistor

Claims (13)

A plurality of non-volatile memory cells;
A reference cell for generating a reference current;
A first reference test cell and a second reference test cell having different current supply capabilities;
A read circuit that compares a current flowing in a selected memory cell among the plurality of memory cells and the reference current;
Including
The first reference inspection cell includes a first reference inspection transistor and a first word line selection transistor connected in series between a first power supply node and one end of a first column selection transistor.
The first reference test transistor has a gate connected to a second power supply node, and has the same structure as the data storage transistor of each memory cell,
The second reference test cell includes a second reference test transistor and a second word line selection transistor connected in series between the first power supply node and one end of a second column selection transistor.
The second reference test transistor has a gate connected to the second power supply node and has the same structure as the data storage transistor of each memory cell,
The readout circuit is
A non-volatile memory device, wherein the reference current is compared with the first current output from the first reference inspection transistor and the second current output from the second reference inspection transistor . In claim 1,
When the target value of the reference current is IrefT, the current value of the first current is I1, and the current value of the second current is I2,
A nonvolatile memory device, wherein I1 <IrefT <I2. In claim 1 or 2,
A non-volatile memory device comprising: a current mirror circuit that generates a reference current by performing a current mirror of a current from the reference cell. In any one of Claims 1 thru | or 3,
Each memory cell is
A non-volatile memory device characterized by being a cell of an OTP (One Time Programmable) memory. In any one of Claims 1 thru | or 4,
Each of the memory cells, the first reference inspection cell, and the second reference inspection cell are:
A nonvolatile memory device comprising transistors having the same structure. In any one of Claims 1 thru | or 5,
A third reference test cell and a fourth reference test cell having different current supply capabilities;
The readout circuit is
A non-volatile memory device characterized in that the reference current is compared with a third current flowing through the third reference test cell and a fourth current flowing through the fourth reference test cell. In any one of Claims 1 thru | or 6.
Including a plurality of the readout circuits;
The nonvolatile memory device, wherein the first reference test cell and the second reference test cell are provided for each of the plurality of read circuits. In any one of Claims 1 thru | or 7,
The reference current is input to a first input node of the readout circuit,
One end of a plurality of column selection transistors is connected to the second input node of the readout circuit,
The nonvolatile memory device, wherein the plurality of memory cells, the first reference inspection cell, and the second reference inspection cell are connected to the other end of the plurality of column selection transistors. A nonvolatile memory device according to any one of claims 1 to 8,
A drive circuit for driving the display panel;
A driver characterized by including:   An electro-optical device comprising the driver according to claim 9.   An electronic apparatus comprising the nonvolatile memory device according to claim 1. A plurality of nonvolatile memory cells, a reference cell for generating a reference current, a first reference test cell, and a second reference test cell having a current supply capability different from that of the first reference test cell And a reading circuit that compares the reference current with a current that flows through a selected memory cell among the plurality of memory cells.
The first reference inspection cell includes a first reference inspection transistor and a first word line selection transistor connected in series between a first power supply node and one end of a first column selection transistor. The reference test transistor has a gate connected to a second power supply node and has the same structure as the data storage transistor of each memory cell, and the second reference test cell includes the first power supply node and a second column. A second reference inspection transistor and a second word line selection transistor connected in series between one end of the selection transistor, the second reference inspection transistor having a gate connected to the second power supply node; The same structure as the data storage transistor of each memory cell Come,
A first comparison process between the first current output from the first reference inspection transistor and the reference current is performed by the readout circuit;
A test method for a nonvolatile memory device, wherein a second comparison process between a second current output from the second reference test transistor and the reference current is performed by the read circuit. In claim 12,
When it is determined in the first comparison process and the second comparison process that the current value of the reference current is between the current value of the first current and the current value of the second current A test method for a nonvolatile memory device, wherein the test for the reference current is determined to be acceptable.

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