JP6593208B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  2. Description of the Related Art A semiconductor device is known in which a semiconductor element and a mounting portion such as a substrate or another semiconductor element are flip-chip connected. In such a semiconductor device, a method for improving the reliability of bonding between a semiconductor element and a mounting portion has been proposed. For example, it is known to improve the reliability of bonding by providing a barrier layer smaller than the electrode body on the electrode body (for example, Patent Document 1). It is known that the reliability of bonding is improved by providing an electrode configuration in which a protrusion extending from one end of the columnar portion to the other end is provided on the columnar portion (for example, Patent Document 2).

JP 2010-56191 A JP 2014-17454 A

  However, the conventional method leaves room for improvement in terms of the reliability of bonding between the semiconductor element and the mounting portion. An object of the present semiconductor device and the method for manufacturing the semiconductor device is to improve reliability.

The semiconductor device includes a mounting portion including a first pillar, a semiconductor element in which a second pillar is bonded to the first pillar, and is flip-chip mounted on the mounting portion, and the first pillar and the second pillar. A barrier layer provided on at least one of the first pillar and the second pillar; and at least one of the first pillar and the second pillar includes the first columnar portion and the second pillar. A second columnar portion that is narrower than the first columnar portion, and the barrier layer is provided on a surface of the second columnar portion where the first pillar and the second pillar face each other, The joining member is provided in contact with the barrier layer and covering the barrier layer, and is in contact with a side surface of the second columnar portion and the opposing surfaces of the first pillar and the second pillar, and 1 pillar and 2nd pillar The composed of an intermetallic compound of a metal element joining member constituting the pillars in contact with the metal elements constituting the solder.

The manufacturing method of the semiconductor device includes a step of preparing a mounting portion including a first pillar, a step of preparing a semiconductor element including a second pillar, and a barrier layer on at least one of the first pillar and the second pillar. A step of forming, a step of forming solder on the barrier layer, a step of causing the mounting portion and the semiconductor element to face each other, and bonding the first pillar and the second pillar with the solder, and the bonding After the step, the metal element constituting the pillar in contact with the solder of the first pillar and the second pillar is alloyed with the metal element constituting the solder, and all of the solder is converted into an intermetallic compound. And at least one of the step of preparing the mounting portion and the step of preparing the semiconductor element includes a first columnar portion and a second columnar portion that is narrower than the first columnar portion. First The step of preparing the pillar and the second pillar and forming the barrier layer includes the step of forming the first pillar and the second pillar when the mounting portion and the semiconductor element are opposed to each other in the second columnar portion. Forming the barrier layer on the surface facing each other and forming the intermetallic compound is in contact with the barrier layer and covering the barrier layer, the side surface of the second columnar portion, the first pillar, and the second pillar. The intermetallic compound in contact with the mutually opposing surfaces is formed.

  According to the semiconductor device and the method for manufacturing the semiconductor device described in this specification, reliability can be improved.

FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the first embodiment. FIG. 3A to FIG. 3D are cross-sectional views illustrating a first method for manufacturing a semiconductor device according to the first embodiment. FIG. 4A to FIG. 4D are cross-sectional views illustrating a second manufacturing method of the semiconductor device according to the first embodiment. 5A to 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. FIG. 6A to 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 2. FIG. 7 is a cross-sectional view illustrating the vicinity of a microbump in the semiconductor device according to the second embodiment. FIG. 8A to FIG. 8D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a cross-sectional view illustrating the vicinity of a microbump in the semiconductor device according to the first modification of the second embodiment. FIG. 10 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the third embodiment. FIG. 11A to FIG. 11D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 12A to FIG. 12D are cross-sectional views showing simulation results. FIG. 13 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the first modification of the third embodiment. FIG. 14 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the second modification of the third embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 100 according to the first embodiment includes a package substrate 10 on which wiring is formed, an intermediate semiconductor element 20 on which a through-silicon via (TSV) is formed, and an upper semiconductor. And an element 30. The semiconductor element 20 is mounted on the package substrate 10 by bumps 40. The semiconductor element 30 is flip-chip mounted on the semiconductor element 20 by micro bumps 42. The semiconductor element 30 is electrically connected to the package substrate 10 via the semiconductor element 20. The pitch of the bumps 40 is about 180 μm, for example, and the pitch of the micro bumps 42 is about 45 μm, for example. High integration can be achieved by stacking the semiconductor element 20 and the semiconductor element 30. Further, the semiconductor element 20 converts the high-density electrode array made of the micro bumps 42 into the electrode array made of the lower density bumps 40.

  FIG. 2 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the first embodiment. As shown in FIG. 2, the semiconductor element 20 includes a first pillar 22 on a surface facing the semiconductor element 30. The first pillar 22 is electrically connected to the bump 40 via a silicon through electrode formed in the semiconductor element 20. The semiconductor element 30 includes a second pillar 32 on the surface facing the semiconductor element 20. The second pillar 32 is electrically connected to a functional unit such as a transistor formed in the semiconductor element 30 through a wiring. The size (area) of the facing surface 24 facing the second pillar 32 of the first pillar 22 is smaller than the facing surface 34 facing the first pillar 22 of the second pillar 32. The first pillar 22 and the second pillar 32 are, for example, copper (Cu) pillars.

  A barrier layer 44 is provided on the facing surface 34 of the second pillar 32. The barrier layer 44 is provided, for example, on the entire facing surface 34 of the second pillar 32. The barrier layer 44 is made of a material that hardly reacts with the solder as compared with the second pillar 32, and plays a role of suppressing the reaction between the solder and the second pillar 32. The barrier layer 44 is a layer containing, for example, nickel (Ni) as a main component, and a Ni layer, a nickel phosphorus (NiP) layer, a nickel vanadium (NiV) layer, a nickel boron (NiB) layer, or the like can be used. Note that a seed layer may be provided between the second pillar 32 and the barrier layer 44 in order to improve adhesion.

The first pillar 22 and the second pillar 32 are joined by a joining member 46. As a result, the semiconductor element 30 is flip-chip mounted on the semiconductor element 20. The bonding member 46 is in contact with the barrier layer 44 and the facing surface 24 and the side surface 26 of the first pillar 22. The joining member 46 is made of an intermetallic compound (for example, Cu ₃ Sn and Cu ₆ Sn ₅ ) of a main metal element (for example, Sn) constituting solder and a metal element (for example, Cu) constituting the first pillar 22.

  Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Here, the process of mounting the semiconductor element 30 on the semiconductor element 20 will be described, and the description of the other processes will be omitted. FIG. 3A to FIG. 3D are cross-sectional views illustrating a first method for manufacturing a semiconductor device according to the first embodiment.

  As shown in FIG. 3A, the semiconductor element 20 including the first pillar 22 and the semiconductor element 30 including the second pillar 32 are prepared. A barrier layer 44 is formed on the second pillar 32. A solder 48 made of, for example, tin-silver (SnAg) is formed on the barrier layer 44. The first pillar 22, the second pillar 32, the barrier layer 44, and the solder 48 can be formed by a general method using, for example, an electrolytic plating method.

  As shown in FIG. 3B, the first pillar 22 of the semiconductor element 20 and the second pillar 32 of the semiconductor element 30 are opposed to each other. As shown in FIG. 3C, the solder 48 is heated to a temperature equal to or higher than the melting point, and the semiconductor element 30 is pressed against the semiconductor element 20 for a predetermined time (for example, at 300 ° C. for 10 seconds). The pillar 32 is joined.

As shown in FIG. 3D, heat treatment is performed on the solder 48 at a temperature equal to or higher than the melting point of the solder 48 in a reducing atmosphere or an inert atmosphere. Since the solder 48 contacts the first pillar 22, the metal element (Sn) constituting the solder 48 and the metal element (Cu) constituting the first pillar 22 can be alloyed by the heat treatment. In the heat treatment, all of the solders 48 are made of an intermetallic compound (Cu ₃ Sn and Cu ₆ Sn ₅ ) of a metal element (Sn) constituting the solder 48 and a metal element (Cu) constituting the first pillar 22. This is repeated until the member 46 is changed. For example, the heat treatment is performed at 240 ° C. for 1 minute. For example, formic acid or hydrogen can be used as the reducing gas, and nitrogen or argon can be used as the inert gas, for example.

  FIG. 4A to FIG. 4D are cross-sectional views illustrating a second manufacturing method of the semiconductor device according to the first embodiment. As shown in FIG. 4A, the semiconductor element 20 including the first pillar 22 and the semiconductor element 30 including the second pillar 32 are prepared. A barrier layer 44 is formed on the second pillar 32. The solder 48 is formed on the barrier layer 44 and the solder 48 is directly formed on the first pillar 22. Since FIG. 4B to FIG. 4D are the same as FIG. 3B to FIG. By providing the solder 48 on both the first pillar 22 and the second pillar 32 as in the second manufacturing method, compared to the case where the solder 48 is provided only on the second pillar 32 as in the first manufacturing method, It becomes easy to adjust the amount of solder provided in one pillar.

  Here, in describing the effect of the semiconductor device 100 of the first embodiment, a semiconductor device according to a comparative example will be described. 5A to 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 1. FIG. As shown in FIG. 5A, the semiconductor element 20 including the first pillar 22 and the semiconductor element 30 including the second pillar 32 are prepared. The solder 48 is directly formed on the first pillar 22 and the second pillar 32. That is, the solder 48 is in contact with the first pillar 22 or the second pillar 32.

As shown in FIG. 5B, the first pillar 22 of the semiconductor element 20 and the second pillar 32 of the semiconductor element 30 are opposed to each other. Thereafter, the solder 48 is heated to a temperature equal to or higher than the melting point to join the first pillar 22 and the second pillar 32. When the solder 48 is thin or when high-temperature heat is applied to the solder 48 before joining, FIG. As shown in c), the metal element of the solder 48 and the metal elements of the first pillar 22 and the second pillar 32 are alloyed before bonding, and the intermetallic compound layer 50 is formed. For example, when the solder 48 is made of SnAg solder and the first pillar 22 and the second pillar 32 are made of Cu pillar, an intermetallic compound layer 50 of Cu ₃ Sn and Cu ₆ Sn ₅ is applied by applying a temperature of about 150 ° C. Is formed. The melting point of Cu ₃ Sn is as high as 675 ° C., and the melting point of Cu ₆ Sn ₅ is as high as 435 ° C. For this reason, if the solder 48 is changed to the intermetallic compound layer 50 before the first pillar 22 and the second pillar 32 are joined, a joint failure between the first pillar 22 and the second pillar 32 occurs.

  6A to 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to Comparative Example 2. As shown in FIG. 6A, the semiconductor element 20 including the first pillar 22 and the semiconductor element 30 including the second pillar 32 are prepared. A barrier layer 44 is formed on the first pillar 22 and the second pillar 32. A solder 48 is formed on the barrier layer 44.

  As shown in FIG. 6B, the first pillar 22 of the semiconductor element 20 and the second pillar 32 of the semiconductor element 30 are opposed to each other. As shown in FIG. 6C, the solder 48 is heated to a temperature equal to or higher than the melting point, and the semiconductor element 30 is pressed toward the semiconductor element 20 to join the first pillar 22 and the second pillar 32.

  In Comparative Example 2, a barrier layer 44 is provided between the first pillar 22 and the solder 48 and between the second pillar 32 and the solder 48. As described above, since the barrier layer 44 is made of a material that does not easily react with solder, the solder 48 is suppressed from being changed to an intermetallic compound. Therefore, it is suppressed that the joining failure like the comparative example 1 arises.

  However, as shown in FIG. 6C, the solder 48 remains even after the first pillar 22 and the second pillar 32 are joined. Since the solder 48 has a low melting point (for example, SnAg solder has a melting point of 220 ° C.), electromigration is likely to occur. In addition, if the solder 48 having a low melting point remains, reliability against heat generation due to current flowing through the pillar, current resistance characteristics, and the like also deteriorate.

On the other hand, according to the first embodiment, as shown in FIG. 2, the joining member 46 that joins the first pillar 22 and the second pillar 32 includes the metal element (Cu) of the first pillar 22 and the metal element (Sn) of solder. And an intermetallic compound (Cu ₃ Sn and Cu ₆ Sn ₅ ). As described above, the intermetallic compounds (Cu ₃ Sn and Cu ₆ Sn ₅ ) have a high melting point, so that the degradation of reliability, withstand current characteristics, etc. due to electromigration as in Comparative Example 2 and heat generation in the pillar is suppressed. it can. Further, since the barrier layer 44 is provided on the second pillar 32, the solder 48 is formed on the second pillar 32 via the barrier layer 44 as shown in FIGS. 3 (a) and 4 (a). Can do. For this reason, it is possible to suppress poor bonding due to the solder 48 changing to an intermetallic compound before the first pillar 22 and the second pillar 32 are joined. Therefore, according to the first embodiment, the reliability can be improved. In FIG. 4A, the solder 48 formed on the first pillar 22 may be changed to an intermetallic compound, but the solder 48 formed on the second pillar 32 via the barrier layer 44 is Since the change to the intermetallic compound is suppressed, bonding failure can be suppressed.

  Further, according to the first embodiment, as illustrated in FIG. 2, the bonding member 46 is in contact with the opposing surface 24 and the side surface 26 of the first pillar 22 where the barrier layer 44 is not provided. As a result, the contact area between the solder 48 and the first pillar 22 increases as shown in FIGS. 3C and 4C, so that the metal element of the solder 48 and the metal element of the first pillar 22 are alloyed. It becomes easy to proceed and the joining member 46 made of an intermetallic compound is easily formed.

  In addition, according to the first embodiment, the metal element of the solder 48 and the metal element of the first pillar 22 are alloyed to change all of the solder 48 into an intermetallic compound in a reducing atmosphere or an inert atmosphere. Performed by heat treatment. If the surface of the solder 48 is oxidized, the alloying of the solder 48 does not proceed. However, the oxidation of the solder 48 can be suppressed by performing a heat treatment in a reducing atmosphere or an inert atmosphere.

Furthermore, according to the first embodiment, the first pillar 22 and the second pillar 32 is composed of Cu pillar, the bonding member 46 is made of at least one of _Cu 3 Sn and _Cu 6 Sn _5. Since the alloying speed of CuSn is fast, the joining member 46 made of an intermetallic compound can be formed in a short time. Further, as described above, since the joining member 46 is made of at least one intermetallic compound of Cu ₃ Sn and Cu ₆ Sn ₅ , the melting point of the joining member 46 is increased, and the reliability can be improved.

  In the first embodiment, the barrier layer 44 is provided on the second pillar 32 and not provided on the first pillar 22, but the barrier layer 44 is provided on the first pillar 22 and the first pillar 22 is provided. The two pillars 32 may not be provided. In this case, it is preferable to make the size of the facing surface 34 of the second pillar 32 smaller than the facing surface 24 of the first pillar 22. As described above, the barrier layer 44 is provided only on one of the first pillars 22 and the second pillar 32 and may not be provided on the other pillar.

  In the first embodiment, the solder 48 is made of SnAg. However, the solder 48 may be made of Sn, SnAgCu, SnAgZn, SnZn, SnBiIn, SnIn, SnAu, SnCu, or SnZnIn. The barrier layer 44 is preferably composed mainly of Ni, but may be composed mainly of tantalum (Ta) or titanium (Ti). The first pillar 22 and the second pillar 32 are not limited to being made of Cu, and may be made of, for example, gold (Au). The first pillar 22 and the second pillar 32 are preferably made of a material in which the melting point of the joining member 46 made of an intermetallic compound of the solder metal element and the pillar metal element is higher than that of the solder.

  In the first embodiment, the case where the facing surface 24 of the first pillar 22 not provided with the barrier layer 44 is smaller than the facing surface 34 of the second pillar 32 provided with the barrier layer 44 is described as an example. The sizes may be approximately the same. In this case, the joining member 46 may be in contact with only the facing surface 24 of the first pillar 22 and not in contact with the side surface 26.

  FIG. 7 is a cross-sectional view illustrating the vicinity of a microbump in the semiconductor device according to the second embodiment. As shown in FIG. 7, the facing surface 24 of the first pillar 22 and the facing surface 34 of the second pillar 32 have substantially the same size. A barrier layer 44 a is provided on both the first pillar 22 and the second pillar 32. The barrier layer 44 a is smaller than the facing surface 24 of the first pillar 22 and the facing surface 34 of the second pillar 32. The bonding member 46 covers the barrier layer 44 a while being in contact with the opposing surface 24 of the first pillar 22 and the opposing surface 34 of the second pillar 32. Since other configurations are the same as those of the first embodiment, the description thereof is omitted.

  FIG. 8A to FIG. 8D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. Here, the process of mounting the semiconductor element 30 on the semiconductor element 20 will be described, and the description of the other processes will be omitted.

  As shown in FIG. 8A, the semiconductor element 20 including the first pillar 22 and the semiconductor element 30 including the second pillar 32 are prepared. A barrier layer 44 a having a smaller width than the first pillar 22 is formed on the first pillar 22. Similarly, a barrier layer 44 a having a smaller width than the second pillar 32 is formed on the second pillar 32. In the first pillar 22 and the second pillar 32, the solder 48 is formed on the barrier layer 44a. The first pillar 22, the second pillar 32, the barrier layer 44a, and the solder 48 can be formed by a general method using, for example, an electrolytic plating method.

  As shown in FIG. 8B, the first pillar 22 of the semiconductor element 20 and the second pillar 32 of the semiconductor element 30 are opposed to each other. As shown in FIG. 8C, the first pillar 22 and the second pillar 32 are joined by heating the solder 48 to a temperature equal to or higher than the melting point and pressing the semiconductor element 30 against the semiconductor element 20 for a predetermined time.

  As shown in FIG. 8D, heat treatment is performed on the solder 48 in a reducing atmosphere or an inert atmosphere. By the heat treatment, the metal element (Sn) of the solder 48 and the metal element (Cu) of the first pillar 22 and the second pillar 32 can be alloyed. The heat treatment is performed until all of the solder 48 changes to the joining member 46 made of an intermetallic compound of the metal element of the solder 48 and the metal elements of the first pillar 22 and the second pillar 32.

  According to the second embodiment, as illustrated in FIG. 7, the barrier layer 44 a has a smaller width than the first pillar 22 and the second pillar 32. The joining member 46 covers the barrier layer 44 a and is in contact with the facing surface 24 of the first pillar 22 and the facing surface 34 of the second pillar 32. Thereby, since the interface between the barrier layer 44a and the bonding member 46 is not exposed to the outside, the bonding strength can be improved.

  Further, according to the second embodiment, as shown in FIG. 8A, since the barrier layer 44a is smaller in width than the first pillar 22 and the second pillar 32, the solder 48 formed on the barrier layer 44a is also small. Become. For this reason, it can suppress that the joining member 46 is formed in the side surface of the 1st pillar 22 and / or the 2nd pillar 32 like FIG. Thereby, it can suppress that adjacent bumps short-circuit.

  FIG. 9 is a cross-sectional view illustrating the vicinity of a microbump in the semiconductor device according to the first modification of the second embodiment. As shown in FIG. 9, the barrier layer 44 a is provided only on the second pillar 32 and is not provided on the first pillar 22. Since other configurations are the same as those of the second embodiment, the description thereof is omitted.

  As in the first modification of the second embodiment, the barrier layer 44a may be provided only on one of the first pillars 22 and the second pillar 32 and may not be provided on the other pillar.

  FIG. 10 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the third embodiment. As shown in FIG. 10, the first pillar 22 includes a first columnar portion 22a and a second columnar portion 22b having a smaller width than the first columnar portion 22a. Similarly, the second pillar 32 includes a first columnar portion 32a and a second columnar portion 32b having a smaller width than the first columnar portion 32a. The barrier layer 44b is provided on the entire surface of the opposing surfaces 24a and 34a of the second columnar portions 22b and 32b. The bonding member 46 is in contact with the side surfaces 26a and 36a of the second columnar portions 22b and 32b and the opposing surfaces 24b and 34b of the first columnar portions 22a and 32a while covering the barrier layer 44b. Since other configurations are the same as those of the first embodiment, the description thereof is omitted.

  FIG. 11A to FIG. 11D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the third embodiment. Here, the process of mounting the semiconductor element 30 on the semiconductor element 20 will be described, and the description of the other processes will be omitted.

  As shown in FIG. 11A, the semiconductor element 20 including the first pillar 22 having the first columnar portion 22a and the second columnar portion 22b, and the second pillar 32 having the first columnar portion 32a and the second columnar portion 32b. The semiconductor element 30 provided with is prepared. A barrier layer 44b is formed on the second columnar portions 22b and 32b. Solder 48 is formed on the barrier layer 44b. The first pillar 22, the second pillar 32, the barrier layer 44b, and the solder 48 can be formed by a general method using, for example, an electrolytic plating method.

  As shown in FIG. 11B, the second columnar portion 22 b of the first pillar 22 of the semiconductor element 20 and the second columnar portion 32 b of the second pillar 32 of the semiconductor element 30 are opposed to each other. As shown in FIG. 11C, the first pillar 22 and the second pillar 32 are joined by heating the solder 48 to a temperature equal to or higher than the melting point and pressing the semiconductor element 30 toward the semiconductor element 20.

  As shown in FIG. 12D, heat treatment is performed on the solder 48 in a reducing atmosphere or an inert atmosphere. By the heat treatment, the metal element (Sn) of the solder 48 and the metal element (Cu) of the first pillar 22 and the second pillar 32 can be alloyed. The heat treatment is performed until all of the solder 48 changes to the joining member 46 made of an intermetallic compound of the metal element of the solder 48 and the metal elements of the first pillar 22 and the second pillar 32.

  According to the third embodiment, as shown in FIG. 10, the first pillar 22 and the second pillar 32 include the first columnar portions 22a and 32a and the second columnar portion 22b having a smaller width than the first columnar portions 22a and 32a. , 32b. The barrier layer 44b is provided on the opposing surfaces 24a and 34a of the second columnar portions 22b and 32b. The bonding member 46 covers the barrier layer 44b and is in contact with the side surfaces 26a and 36a of the second columnar portions 22b and 32b and the opposing surfaces 24b and 34b of the first columnar portions 22a and 32a. As a result, the contact area between the solder and the pillar is increased, so that the alloying of the metal element of the solder and the metal element of the pillar easily proceeds, and the joining member 46 made of an intermetallic compound is easily formed. Further, since the first columnar portions 22a and 32a having a larger width than the second columnar portions 22b and 32b provided with the barrier layer 44b are provided, the joining member 46 (solder 48) is connected to the first pillar 22 and the second pillar 22b. Spilling from the two pillars 32 can be suppressed.

  Here, an experiment conducted by the inventor will be described. In the experiment, the first columnar portions 22a and 32a are Cu pillars having a diameter of 30 μm, the second columnar portions 22b and 32b are Cu pillars having a diameter of 20 μm and a height of 5 μm, and the barrier layer 44b is a Ni layer having a thickness of 1 μm. It was. In this structure, the solder 48 shown in FIG. 11A is used as SnAg solder, and the amount of the solder 48 is varied to examine how the state after joining the first pillar 22 and the second pillar 32 changes. It was.

  FIG. 12A to FIG. 12D are cross-sectional views showing simulation results. 12A shows a thickness of the solder 48 of 7.5 μm, FIG. 12B shows a thickness of the solder 48 of 11.25 μm, FIG. 12C shows a thickness of the solder 48 of 15 μm, and FIG. ) Is a simulation result when the thickness of the solder 48 is 3.75 μm. When the volume of the solder 48 with respect to the volume of the stepped portion formed by the first columnar portions 22a and 32a and the second columnar portions 22b and 32b is a specific volume of the solder 48, the solder 48 has a thickness of 7.5 μm. The specific volume of 48 is 100%. When the thickness of the solder 48 is 11.25 μm, the specific volume of the solder 48 is 150%. When the thickness of the solder 48 is 15 μm, the specific volume of the solder 48 is 200%. When the thickness of the solder 48 is 3.75 μm, the specific volume of the solder 48 is 50%.

  As shown in FIG. 12A, when the thickness of the solder 48 is 7.5 μm (that is, the specific volume of the solder 48 is 100%), the thickness of the bonding member 46 between the barrier layers 44b in many bumps is 0 μm. Not very thin. As shown in FIG. 12B, when the thickness of the solder 48 is 11.25 μm (that is, the specific volume of the solder 48 is 150%), the thickness t of the bonding member 46 between the barrier layers 44b is about 3.3 μm. became. As shown in FIG. 12C, when the thickness of the solder 48 is 15 μm (that is, the specific volume of the solder 48 is 200%), the thickness t of the bonding member 46 between the barrier layers 44b is about 6.6 μm. . As shown in FIG. 12D, when the thickness of the solder 48 is 3.75 μm (that is, the specific volume of the solder 48 is 50%), the thickness of the bonding member 46 between the barrier layers 44b is 0 μm for all the bumps. Not very thin. In addition, the shape of the bonding member 46 at the step portion formed by the first columnar portions 22a and 32a and the second columnar portions 22b and 32b is curved so that the central portion is thin in the height direction.

  As shown in FIGS. 12A to 12C, the joining member 46 between the barrier layers 44b becomes thicker as the solder 48 becomes thicker (that is, the specific volume of the solder 48 becomes larger). The thicker the joining member 46 between the barrier layers 44b, the greater the electrical resistance. Further, when the joining member 46 between the barrier layers 44b becomes thick, there is a possibility that the solder 48 that is not alloyed remains between the barrier layers 44b. Therefore, the specific volume of the solder 48 is preferably 200% or less, more preferably 175% or less, and further preferably 150% or less. On the other hand, as shown in FIG. 12D, when the solder 48 becomes too thin (that is, when the specific volume of the solder 48 becomes too small), the joining member 46 is formed at the step portion formed by the first columnar portion and the second columnar portion. There is a possibility that a thinned portion will be formed, resulting in poor bonding. Therefore, the specific volume of the solder 48 is preferably 100% or more, more preferably 125% or more, and further preferably 150% or more.

  FIG. 13 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the first modification of the third embodiment. As shown in FIG. 13, the barrier layer 44 b is provided only on the second columnar portion 32 b of the second pillar 32, and is not provided on the second columnar portion 22 b of the first pillar 22. Since other configurations are the same as those of the third embodiment, the description thereof is omitted.

  As in the first modification of the third embodiment, the barrier layer 44b is provided on at least one of the second columnar portion 22b of the first pillar 22 and the second columnar portion 32b of the second pillar 32, and is provided on the other. There may be no case.

  FIG. 14 is a cross-sectional view illustrating the vicinity of the microbump in the semiconductor device according to the second modification of the third embodiment. As shown in FIG. 14, the second pillar 32 includes a first columnar portion 32a and a second columnar portion 32b having a smaller width than the first columnar portion 32a. On the other hand, the first pillar 22 is formed by only a columnar portion having the same and constant width as the first columnar portion 32 a of the second pillar 32. Since other configurations are the same as those of the third embodiment, the description thereof is omitted.

  As in Modification 2 of Example 3, at least one of the first pillar 22 and the second pillar 32 may include a first columnar part and a second columnar part having a smaller width than the first columnar part.

  In the first to third embodiments, the semiconductor element 30 is flip-chip mounted on the semiconductor element 20 as a mounting portion. However, the semiconductor element 30 may be flip-chip mounted on a wiring board or the like. . Since a large current flows through the microbumps connecting the semiconductor elements, it is preferable to improve the current resistance by forming the bonding member of an intermetallic compound in such a microbump.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Appendix 1) A mounting portion including a first pillar, a semiconductor element in which a second pillar is bonded to the first pillar, and flip-chip mounted on the mounting portion, and at least one of the first pillar and the second pillar A barrier layer provided on one side, and a joining member that joins the first pillar and the second pillar, wherein the joining member includes at least one of the first pillar and the second pillar and the barrier layer. A semiconductor device made of an intermetallic compound of a metal element constituting the pillar that is in contact with the joining member of the first pillar and the second pillar and a metal element constituting the solder.
(Supplementary Note 2) The barrier layer is smaller in width than the first pillar and the second pillar, and the joining member is provided so as to cover the barrier layer, and the first pillar and the second pillar are mutually connected. The semiconductor device according to appendix 1, in contact with the opposing surface.
(Supplementary Note 3) At least one of the first pillar and the second pillar has a first columnar portion and a second columnar portion having a width smaller than that of the first columnar portion, and the barrier layer includes the second pillar A columnar portion provided on a surface of the first pillar and the second pillar facing each other; the joining member is provided to cover the barrier layer; and a side surface of the second columnar portion; The semiconductor device according to appendix 1 or 2, which is in contact with the opposing surfaces of the first pillar and the second pillar.
(Additional remark 4) The said barrier layer is provided only in one pillar of the said 1st pillar and the said 2nd pillar, and is not provided in the other pillar, The said joining member is the said pillar of the said other pillar. 4. The semiconductor device according to claim 1, wherein the semiconductor device is in contact with a surface facing one pillar and a side surface of the other pillar.
(Supplementary note 5) The semiconductor device according to supplementary note 4, wherein the other pillar has a smaller width than the one pillar.
(Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the first pillar and the second pillar are made of Cu, and the joining member is made of at least one of Cu ₃ Sn and Cu ₆ Sn ₅ .
(Additional remark 7) The process of preparing the mounting part provided with a 1st pillar, The process of preparing a semiconductor element provided with a 2nd pillar, The process of forming a barrier layer in at least one of the said 1st pillar and the said 2nd pillar, After the step of forming solder on the barrier layer, the step of facing the mounting part and the semiconductor element, and joining the first pillar and the second pillar with the solder, and the step of joining, A step of alloying a metal element constituting the pillar of the first pillar and the second pillar with which the solder is in contact with a metal element constituting the solder to make all of the solder an intermetallic compound; A method for manufacturing a semiconductor device.
(Supplementary note 8) The method of manufacturing a semiconductor device according to supplementary note 7, wherein the step of forming the intermetallic compound includes performing heat treatment on the solder in a reducing atmosphere or an inert atmosphere.
(Supplementary note 9) The method for manufacturing a semiconductor device according to supplementary note 7 or 8, wherein the solder includes tin, and the first pillar and the second pillar are made of copper.

DESCRIPTION OF SYMBOLS 10 Package substrate 20 Semiconductor element 22 1st pillar 22a 1st columnar part 22b 2nd columnar part 24 Opposite surface of 1st pillar 24a Opposite surface of 2nd columnar part 24b Opposite surface of 1st columnar part 26 Side surface of 1st pillar 26a Side surface of second columnar portion 30 Semiconductor element 32 Second pillar 32a First columnar portion 32b Second columnar portion 34 Opposing surface of second pillar 34a Opposing surface of second columnar portion 34b Opposing surface of first columnar portion 36a Second columnar shape Side surface 40 Bump 42 Micro bump 44, 44a, 44b Barrier layer 46 Joining member 48 Solder

Claims (5)

A mounting section comprising a first pillar;
A semiconductor element in which a second pillar is bonded to the first pillar and is flip-chip mounted on the mounting portion;
A barrier layer provided on at least one of the first pillar and the second pillar;
A joining member that joins the first pillar and the second pillar,
At least one of the first pillar and the second pillar has a first columnar portion and a second columnar portion that is narrower than the first columnar portion,
The barrier layer is provided on a surface of the second columnar portion where the first pillar and the second pillar are opposed to each other,
The joining member is provided in contact with the barrier layer and covering the barrier layer, and is in contact with a side surface of the second columnar portion and the opposing surfaces of the first pillar and the second pillar, and The semiconductor device which consists of an intermetallic compound of the metal element which comprises the pillar which the said joining member contacts among the 1 pillar and the said 2nd pillar, and the metal element which comprises solder. The barrier layer is provided only on one of the first pillar and the second pillar, and is not provided on the other pillar.
The joining member is in contact with the surface facing the one of the pillars of the other pillar and the side surface of the other pillars, the semiconductor device according to claim 1, wherein. The first pillar and the second pillar are made of Cu,
The joining member is made of at least one of _Cu 3 Sn and _Cu 6 Sn _5, the semiconductor device according to claim 1 or 2 wherein. Preparing a mounting portion including a first pillar;
Preparing a semiconductor element including a second pillar;
Forming a barrier layer on at least one of the first pillar and the second pillar;
Forming solder on the barrier layer;
The mounting portion and the semiconductor element are opposed to each other, and the first pillar and the second pillar are joined with the solder;
After the joining step, the metal element that constitutes the pillar that contacts the solder of the first pillar and the second pillar is alloyed with the metal element that constitutes the solder, and all of the solder is made of metal. A step of making an intermetallic compound,
At least one of the step of preparing the mounting portion and the step of preparing the semiconductor element includes the first pillar and the second pillar having a first columnar portion and a second columnar portion that is narrower than the first columnar portion. Prepare the pillar,
The step of forming the barrier layer includes forming the barrier layer on a surface of the second columnar portion where the first pillar and the second pillar face each other when the mounting portion and the semiconductor element are opposed to each other. And
The step of forming the intermetallic compound includes contacting the barrier layer and covering the barrier layer, and contacting the side surface of the second columnar portion and the opposing surfaces of the first pillar and the second pillar. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 4 , wherein the step of forming the intermetallic compound includes performing heat treatment on the solder in a reducing atmosphere or an inert atmosphere.

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