JP6607069B2 - MEMORY ACCESS CONTROL DEVICE, MEMORY ACCESS CONTROL METHOD, PROGRAM - Google Patents

Description

  The present invention relates to a memory access control device, a memory access control method, and a program, and more particularly to a memory access control device, a memory access control method, and a program that suppress latency.

  A shared memory system in which a plurality of processors share a memory is known. In such a shared memory system, latency (delay) may occur due to a plurality of instructions competing. Therefore, various countermeasures against the above latency are considered.

  For example, Patent Document 1 describes a system having an access arbitration unit in which priorities among groups are set in advance when a data processing unit is divided into a plurality of groups. According to Patent Literature 1, the access arbitration unit performs access arbitration according to priority when a conflict occurs. In addition, when an access request exceeding the allowable access count occurs, the access arbitration unit transmits a wait command signal to the data processing unit with a low priority. According to Patent Document 1, such a configuration can suppress an increase in response time.

  Further, for example, Patent Literature 2 describes a latency shortening system including a storage unit, a registration unit, and a transmission unit. According to Patent Document 2, when a request is issued at the same time to the same address in the shared memory, the registration unit stores control information for specifying an issuer that issued the request in the storage unit. In addition, when sending data to the issuer of the request with respect to the request issued first among the requests transmitted at the same time, the transmission unit determines the issuer based on the control information. According to Patent Document 2, with such a configuration, predetermined requests from a plurality of processors can be processed simultaneously, and as a result, latency can be shortened.

JP-A-2005-242408 JP 2011-002986 A

  In the case of the technique described in Patent Document 1, a plurality of data processing units permitted to access as a result of access arbitration may access the same address (or the same address range). In such a case, access concentration to the same address occurs, and as a result, it takes time for coherency processing and the like, and load and store instructions may be significantly delayed than usual. Thus, in the case of the technique described in Patent Document 1, there is a possibility that latency may occur due to concentration of accesses to the same address.

  The technique described in Patent Document 2 suppresses latency by processing predetermined requests simultaneously. Therefore, it has not always been sufficient for requests that cannot be processed simultaneously. Thus, even in the case of the technique described in Patent Document 2, it may be difficult to suppress latency due to concentration of accesses to the same address.

  As described above, in a system having a shared memory, there is a problem that it is difficult to suppress latency due to concentration of accesses to the same address.

  Therefore, an object of the present invention is to provide a memory access control device that solves the problem that it is difficult to suppress latency due to concentration of accesses to the same address in a system having a shared memory.

In order to achieve such an object, a memory access control device according to one aspect of the present invention provides:
Accepting means for accepting an access request to a memory address;
An issuing unit that issues an access instruction to instruct the memory access unit to access a memory address in response to the access request received by the receiving unit;
A control unit that refers to status information indicating a status of access by the memory access unit with respect to a memory address to which the access request requests access, and suppresses issuance of the access command by the issuing unit for a predetermined time based on the status information; ,
It has a configuration of having

In addition, a memory access control method according to another aspect of the present invention includes:
Accept access request to memory address,
In response to the received access request, issue an access instruction to instruct the memory access means to access the memory address,
The access request refers to status information indicating a status of access by the memory access means for a memory address that requests access, and based on the status information, issuance of the access command is suppressed for a predetermined time.
The structure is taken.

Moreover, the program which is the other form of this invention is:
In the information processing device,
Accepting means for accepting an access request to a memory address;
An issuing unit that issues an access instruction to instruct the memory access unit to access a memory address in response to the access request received by the receiving unit;
A control unit that refers to status information indicating a status of access by the memory access unit with respect to a memory address to which the access request requests access, and suppresses issuance of the access command by the issuing unit for a predetermined time based on the status information; ,
It is a program for realizing.

  The present invention is configured as described above to provide a memory access control device that solves the problem that it is difficult to suppress latency due to concentration of accesses to the same address in a system having a shared memory. It becomes possible.

It is a block diagram which shows an example of a structure of the memory access control apparatus in the 1st Embodiment of this invention. It is a block diagram which shows an example of a structure of a memory access control apparatus. It is a figure which shows an example of a structure of the delay prediction table shown in FIG. It is a figure which shows an example of a structure of a memory access request | requirement mechanism and a memory access means. It is a flowchart which shows an example of operation | movement of a memory access request control mechanism. It is a flowchart which shows an example of operation | movement of a memory access request control mechanism. It is a flowchart which shows an example of operation | movement of a memory access request | requirement mechanism. It is a flowchart which shows an example of operation | movement of a memory access management mechanism. It is a block diagram which shows the example of mounting of a memory access request control mechanism. It is an example of the pseudo code describing an example of the operation of the memory access request control mechanism. It is a figure which shows an example of the whole structure of the NUMA type | system | group system in the 2nd Embodiment of this invention. It is a figure which shows an example of the flow of the memory access in the NUMA type | system | group system shown in FIG. It is a figure which shows an example of the flow of the memory access in the NUMA type | system | group system shown in FIG. It is a figure which shows an example of a structure of the delay prediction table in the 2nd Embodiment of this invention. It is a schematic block diagram which shows an example of a structure of the memory access control apparatus in the 3rd Embodiment of this invention.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are block diagrams showing an example of the configuration of the memory access control device 1. FIG. FIG. 3 is a diagram illustrating an example of the configuration of the delay prediction table 42. FIG. 4 is a diagram showing an example of the configuration of the memory access request mechanism 3 and the memory access means 43. 5 and 6 are flowcharts showing an example of the operation of the memory access request control mechanism 2. FIG. 7 is a flowchart showing an example of the operation of the memory access request mechanism 3. FIG. 8 is a flowchart showing an example of the operation of the memory access management mechanism 4. FIG. 9 is a block diagram illustrating an implementation example of the memory access request control mechanism 2. FIG. 10 is an example of pseudo code describing an example of the operation of the memory access request control mechanism 2.

  In the first embodiment of the present invention, a memory access control device 1 that suppresses latency caused by concentration of accesses to the same address range will be described. As will be described later, the memory access control device 1 in this embodiment measures a queue length indicating the number of requests being processed for each address range. When it is determined that accesses to the same address range are concentrated, the memory access control device 1 is configured to temporarily suppress issuance of memory access instructions. With such a configuration, the memory access control device 1 can refrain from memory access in a situation where a memory access delay is predicted. As a result, deterioration of delay can be prevented. That is, the latency can be suppressed.

  In the present embodiment, the same address range means that values from the first to a predetermined number of memory addresses match. The granularity of the address range (how many the predetermined number is set) may be arbitrarily set according to the system using the memory access control device 1.

  Referring to FIG. 1, a memory access control device 1 according to the present embodiment includes a memory access request control mechanism 2 that receives a memory access request, and memory access request mechanisms 3a, 3b, 3c, 3d, 3e, and 3f (hereinafter, particularly The memory access request mechanism 3 and the memory access management mechanism 4 are provided.

  As shown in FIG. 1, the memory access request control mechanism 2 and the memory access request mechanism 3 are connected so as to communicate with each other. Similarly, the memory access request mechanism 3 and the memory access management mechanism 4 and the memory access management mechanism 4 and the memory access request control mechanism 2 are also connected so as to be communicable.

  The memory access request control mechanism 2 receives a memory access request (access request) to a specific memory address from the outside. Then, in response to the accepted memory access request, the memory access request control mechanism 2 issues a memory access command (access command) that instructs access to the memory address requested by the memory access request. Further, the memory access request control mechanism 2 in this embodiment issues a memory access instruction when it is determined that accesses to the same address range are concentrated based on a delay prediction table 42 (status information) described later. Is temporarily suppressed. In other words, the memory access request control mechanism 2 temporarily suppresses the issuance of a memory access instruction for the memory address when it is determined that access to the memory address that requests access is delayed due to concentration of access.

  Referring to FIG. 2, the memory access request control mechanism 2 in this embodiment includes a delay recognition unit 21, a delay prediction flag 22, a memory access instruction issue preparation unit 23, a delay address confirmation unit 24, and a delay suppression unit 25. And a memory access instruction issuing means 26. The memory access request control mechanism 2 includes, for example, an arithmetic device and a storage device (not shown), and the arithmetic device executes the program stored in the storage device, thereby realizing each of the above means.

  The delay recognition unit 21 updates the delay prediction flag 22. For example, the delay recognition unit 21 receives a delay prediction notification for predicting a delay in the address range managed by the memory access management mechanism 4 from the delay prediction notification unit 47 of the memory access management mechanism 4. Further, the delay recognizing unit 21 receives from the delay prediction notifying unit 47 a delay cancellation notification for canceling the delay prediction in the address range managed by the memory access management mechanism 4. Then, the delay recognizing means 21 updates the delay prediction flag 22 based on the received delay prediction notification and delay cancellation notification.

  Specifically, the delay prediction flag 22 is implemented as a counter, and the delay recognition unit 21 increments (increases by 1) the delay prediction flag 22 when receiving the delay prediction notification. Further, when the delay recognizing unit 21 receives the delay cancellation notification, the delay recognizing unit 21 decrements the delay prediction flag 22 (decreases it by 1). As described above, the delay recognition unit 21 updates the delay prediction flag 22 in accordance with the notification received from the delay prediction notification unit 47.

  The delay prediction flag 22 indicates information indicating whether or not there is a possibility that a delay has occurred in the memory access management mechanism 4. As described above, the delay prediction flag 22 is implemented as a counter, for example. When the value of the delay prediction flag 22 is 0, it indicates that no delay has occurred, and when the value of the delay prediction flag 22 is 1 or more, it indicates that a delay may have occurred. ing.

  Based on the delay prediction flag 22, the memory access command issue preparation unit 23 (accepting unit) determines whether or not to transmit the received memory access request to the delay address confirmation unit 24. For example, the memory access command issuance preparation unit 23 receives a memory access request from the outside. Then, the memory access instruction issuance preparation means 23 refers to the delay prediction flag 22 and determines whether or not a delay is predicted for the latest access in the address range managed by the memory access management mechanism 4. When the delay prediction flag 22 is set (when the value is 1 or more and a delay is predicted), the memory access instruction issuance preparation means 23 transmits a memory access request to the delay address confirmation means 24. On the other hand, when the delay prediction flag 22 is not set (when the value is 0 and the delay is not predicted), the memory access instruction issue preparing unit 23 transmits a memory access request to the memory access instruction issuing unit 26.

  The delay address confirmation unit 24 (a part of the suppression unit) determines whether or not an entry corresponding to the memory address requested by the memory access request exists in the delay prediction table 42 of the memory access management mechanism 4 described later. Check whether there is an alert in the entry. For example, the delay address confirmation unit 24 receives a memory access request from the memory access instruction issue preparation unit 23. Then, the delay address confirmation unit 24 refers to the delay prediction table 42 and confirms whether or not an entry corresponding to the memory address at which the received memory access request requests access exists in the delay prediction table 42. In other words, the delay address confirmation unit 24 confirms whether or not an entry in the address range including the memory address requested by the memory access request exists in the delay prediction table 42. Further, when there is a corresponding entry, the delay address confirmation unit 24 confirms whether or not an alert is set for the entry. When the corresponding entry exists and an alert is set for the entry, the delay address confirmation unit 24 transmits a memory access request to the delay suppression unit 25. On the other hand, when the corresponding entry does not exist or when no alert is raised in the entry, the delay address confirmation unit 24 transmits a memory access request to the memory access instruction issue unit 26.

  The delay suppression unit 25 (a part of the suppression unit) suppresses access to the corresponding memory address for a predetermined time (delay suppression time). For example, the delay suppression unit 25 receives a memory access request from the delay address confirmation unit 24. Then, the delay suppression unit 25 waits for a predetermined time. Thereafter, the delay suppressing unit 25 transmits the received memory access request to the memory access command issuing unit 26. The delay suppression unit 25, for example, issues a memory access instruction by the memory access instruction issuing unit 26 by transmitting a memory access request to the memory access instruction issuing unit 26 after waiting for a predetermined time in this way. Is suppressed for a predetermined time.

  Based on the received memory access request, the memory access command issuing unit 26 (issuing unit) issues to the memory access request mechanism 3 a memory access command that instructs access to the memory address indicated by the memory access request. For example, the memory access instruction issue unit 26 receives a memory access request from the memory access instruction issue preparation unit 23, the delay address confirmation unit 24, and the delay suppression unit 25. Then, the memory access command issuing means 26 issues a memory access command to the memory access request mechanism 3 based on the received memory access request.

  As shown in FIG. 2, the memory access request mechanism 3 includes a memory access determination unit 31 and a cache 32. The memory access request mechanism 3 is a mechanism that can be realized by the existing technology, and is a mechanism such as a processor.

  The memory access determination unit 31 determines whether to use the cache 32 or to actually perform memory access according to the memory access command. For example, the memory access determining unit 31 receives a memory access command from the memory access command issuing unit 26. Then, the memory access determination unit 31 interprets the received memory access command. Then, the memory access determination unit 31 determines whether to use the cache 32 or to actually perform the memory access according to the interpretation result. Further, when it is determined that the memory access is actually performed, the memory access determination unit 31 transmits a memory access command to the memory access monitoring unit 41 of the memory access management mechanism 4.

  The memory access management mechanism 4 accesses the memory 44 in response to the received memory access command. The memory access management mechanism 4 detects concentration of access to a specific address range and notifies the memory access request control mechanism 2 of a delay prediction notification. In addition, the memory access management mechanism 4 notifies the memory access request control mechanism 2 of a delay cancellation notification when the possibility of occurrence of delay is low.

  Referring to FIG. 2, the memory access management mechanism 4 in this embodiment includes a memory access monitoring unit 41, a delay prediction table 42, a memory access unit 43, a memory 44, a delay occurrence prediction unit 45, a delay elimination prediction unit 46, and a delay prediction. Notification means 47. The memory access management mechanism 4 includes, for example, an arithmetic device and a storage device (not shown), and the arithmetic device executes the program stored in the storage device, thereby realizing each of the above means. The memory access management mechanism 4 has a storage device such as a memory, and stores the delay prediction table 42 in the storage device.

  The memory access monitoring unit 41 receives a memory access command from the memory access request mechanism 3 and transmits the received memory access command to the memory access unit 43. Further, the memory access monitoring unit 41 manages the delay prediction table 42. As will be described later, the memory access monitoring unit 41 measures the queue length by managing the delay prediction table 42.

  For example, the memory access monitoring unit 41 receives a memory access command from the memory access request mechanism 3. Then, the memory access monitoring unit 41 updates the delay prediction table 42 based on the received memory access command. For example, when the memory access monitoring unit 41 receives a memory access command, the memory access monitoring unit 41 checks whether an entry for the address range to which the memory address requested by the received memory access command belongs already exists in the delay prediction table 42. If a corresponding entry exists, the memory access monitoring unit 41 increments the queue length corresponding to the corresponding memory address. On the other hand, when there is no corresponding entry, the memory access monitoring unit 41 registers the corresponding entry as a new entry in the delay prediction table 42. At this time, the queue length of the newly registered entry is 1. The memory access monitoring means 41 transmits a memory access command to the memory access means 43 and activates the delay occurrence prediction means 45 as necessary. For example, the memory access monitoring unit 41 activates the delay occurrence prediction unit 45 when no alert is raised in the entry with the queue length incremented.

  When the memory access monitoring unit 41 is notified of the completion of the memory access from the memory access unit 43, the memory access monitoring unit 41 updates the delay prediction table 42. For example, when the memory access monitoring unit 41 receives a notification that the memory access is completed, the memory access monitoring unit 41 decrements the queue length of the corresponding entry. As a result, when the queue length becomes 0, the memory access monitoring unit 41 deletes the corresponding entry from the delay prediction table 42. Further, the memory access monitoring unit 41 activates the delay elimination prediction unit 46 as necessary. For example, the memory access monitoring unit 41 activates the delay elimination prediction unit 46 when an alert is set for the entry decremented by the queue length.

  The delay prediction table 42 (status information) indicates the status of access by the memory access means 43, for example, the number of accesses to the memory address. Specifically, the delay prediction table 42 indicates the queue length for each address range (number of requests being processed. For example, the number of memory access instructions received after the memory access unit 43 (memory access management mechanism 4) has received and before execution is completed. ).

  FIG. 3 is an example of the configuration of the delay prediction table 42. Referring to FIG. 3, the delay prediction table 42 includes an address range, a queue, a queue length, an H-WM (High Watermark) (delay threshold), an L-WM (Low Watermark) (resolution threshold), an alert. Are associated with each other. In the delay prediction table 42, a request (memory access instruction) being monitored by the memory access monitoring unit 41 is registered by the memory access monitoring unit 41.

  As described above, the queue length indicates the number of requests being processed. The queue length is managed by the memory access monitoring means 41 so that it increases by 1 every time one memory access command is transmitted to the memory access means 43. The queue length is managed by the memory access monitoring means 41 so that the queue length is decreased by 1 every time the execution of the memory access instruction is completed.

  H-WM is a threshold value used to determine whether or not access to an address range is concentrated. The H-WM is compared with the queue length by the delay occurrence prediction unit 45, and when the queue length becomes equal to or greater than H-WM, an alert for the corresponding entry is set. L-WM is a value smaller than, for example, H-WM, and is a threshold value used to determine whether or not concentration of access to the address range has been eliminated. The L-WM is compared with the queue length by the delay elimination prediction means 46, and when the queue length becomes equal to or less than L-WM, the alert of the corresponding entry is overwritten (deleted). As described above, the alert is set when the queue length is equal to or greater than H-WM, and is overwritten when the queue length is equal to or less than L-WM. Due to such a configuration, the delay address confirmation unit 24 has a queue length greater than that of the H-WM in a state in which the memory access instruction issuance unit 26 suppresses the issuance of the memory access instruction for a predetermined time (in an alert state). Until the value becomes less than L-WM, which is a small value, the state in which the issue of the memory access instruction is suppressed for a predetermined time is maintained.

  Note that the values of H-WM and L-WM are, for example, predetermined values. The values of H-WM and L-WM are predetermined as system-specific values based on, for example, system specifications and empirical rules.

  The memory access unit 43 performs memory access to the memory 44 and operates to maintain consistency and coherency of the contents of the cache 32 included in the memory access request mechanism 3. Various existing technologies can be employed for the memory access means 43.

  The memory 44 is a storage device such as a hard disk or a memory. As described above, the memory 44 is accessed by the memory access means 43.

  The delay occurrence prediction unit 45 performs delay occurrence prediction using the delay prediction table 42 as an information source. Specifically, as described above, the delay occurrence prediction unit 45 is activated by the memory access monitoring unit 41. Then, the delay occurrence prediction unit 45 refers to the delay prediction table 42 and confirms whether or not the queue length of the corresponding entry (for example, the entry causing the activation) is equal to or greater than H-WM. When the queue length is equal to or greater than H-WM, the delay occurrence prediction unit 45 raises an alert for the corresponding entry. Further, the delay occurrence prediction unit 45 notifies the delay prediction notification unit 47 that an alert has been set. On the other hand, when the queue length is smaller than H-WM, the delay occurrence predicting unit 45 ends the process.

  The delay elimination prediction means 46 performs delay elimination prediction using the delay prediction table 42 as an information source. Specifically, as described above, the delay elimination prediction unit 46 is activated by the memory access monitoring unit 41. Then, the delay elimination prediction unit 46 refers to the delay prediction table 42 and confirms whether or not the queue length of the corresponding entry (for example, the entry causing the activation) is equal to or less than L-WM. When the queue length is equal to or shorter than L-WM, the delay elimination prediction unit 46 defeats the alert for the corresponding entry. Further, the delay elimination prediction means 46 notifies the delay prediction notification means 47 that the alert has been defeated. On the other hand, when the queue length is larger than L-WM, the delay cancellation prediction unit 46 ends the process.

  The delay prediction notification unit 47 (transmission unit) transmits a delay prediction notification and a delay cancellation notification to the memory access request control mechanism 2. For example, the delay prediction notification unit 47 receives a notification from the delay occurrence prediction unit 45 that an alert has been raised. Then, the delay prediction notification unit 47 transmits a delay prediction notification for predicting the delay according to the received notification. Further, the delay prediction notification unit 47 receives a notification that the alert has been defeated from the delay cancellation prediction unit 46. Then, the delay prediction notification unit 47 transmits a delay cancellation notification for canceling the delay prediction in response to the received notification.

  The above is an example of the configuration of the memory access control device 1.

  Note that the memory access means 43 of the memory access request mechanism 3 and the memory access management mechanism 4 are means that can be realized by, for example, existing technology. For example, in the system 5 (5a, 5b) as shown in FIG. 4, the memory access request mechanism 3 and the memory access means 43 are respectively similar to a general processor 51 (CPU (Central Processing Unit)) and a memory controller 52. Operate.

Further, the system 5 as described above has, for example, the following characteristics.
Features 1. A memory access instruction (an instruction requesting access to the memory 53) can be issued simultaneously from each processor 51 to the memory controller 52.
Feature 2. When the request from each processor 51 is an access to a different address range, the processing of the memory controller 52 can be performed in parallel in many cases. Therefore, in such a case, the delay is small (see the system 5a in FIG. 4).
Feature 3. When the request from each processor 51 is an access to the same address range, it is necessary to maintain the coherency of the memory and the cache in each processor 51, and the processing is serialized (serialized). For this reason, when a large number of processors 51 continue to access the same memory address, the corresponding memory address is stored in a cache on the large number of processors 51, so that update processing and synchronization processing for maintaining coherency become heavy. . As a result, the delay increases (see the system 5b in FIG. 4).

  FIG. 4 shows a very simple example of the system in which the memory access control device 1 in this embodiment is used. The memory access control device 1 in the present embodiment can be used, for example, to improve the performance of a relatively large-scale system having the above-described characteristics, but is applied to other devices and systems. It doesn't matter.

  Next, an example of the operation of the memory access control device 1 will be described with reference to FIGS. First, an example of the operation of the memory access request control mechanism 2 when a memory access request is received will be described with reference to FIG.

  Referring to FIG. 5, the memory access command issuance preparation means 23 receives a memory access request from an external device or external software (step S001). Then, the memory access instruction issuance preparation unit 23 refers to the delay prediction flag 22 and determines whether or not a delay is predicted in the memory access management mechanism 4.

  When the value of the delay prediction flag 22 is 1 or more (when a delay is predicted) (step S002, True), the memory access instruction issue preparation unit 23 transmits a memory access request to the delay address confirmation unit 24. On the other hand, when the value of the delay prediction flag 22 is 0 (when the delay is not predicted) (step S002, False), the memory access instruction issue preparation unit 23 transmits a memory access request to the memory access instruction issue unit 26. To do.

  The delay address confirmation unit 24 receives the memory access request from the memory access instruction issue preparation unit 23. Then, the delay address confirmation unit 24 refers to the delay prediction table 42 of the memory access management mechanism 4 and an entry corresponding to the memory address requested by the received memory access request exists in the delay prediction table 42. Check if there is an alert on the entry.

  When the corresponding entry exists and an alert is raised (step S003, True), the delay address confirmation unit 24 transmits a memory access request to the delay suppression unit 25. On the other hand, when there is no corresponding entry or when no alert is raised in the entry (step S003, False), the delay address confirmation unit 24 transmits a memory access request to the memory access instruction issue unit 26.

  The delay suppression unit 25 receives the memory access request from the delay address confirmation unit 24. Then, the delay suppression unit 25 waits for a predetermined time. That is, the delay suppression unit 25 performs a delay suppression process (step S004). Thereafter, the delay suppressing unit 25 transmits the received memory access request to the memory access command issuing unit 26.

  Based on the received memory access request, the memory access command issuing means 26 issues a memory access command for instructing access to the memory address indicated by the memory access request to the memory access request mechanism 3 (step S005).

  The above is an example of the operation of the memory access request control mechanism 2 when a memory access request is received. Next, an example of the operation of the memory access request control mechanism 2 when the delay prediction flag 22 is updated will be described with reference to FIG.

  Referring to FIG. 6, the delay recognition unit 21 of the memory access request control mechanism 2 receives a delay prediction notification and a delay cancellation notification from the delay prediction notification unit 47 of the memory access management mechanism 4 (step S101).

  Then, the delay recognition unit 21 performs an update according to the notification. Specifically, when a delay prediction notification is received (step S102, delay prediction notification), the delay recognition unit 21 increments the delay prediction flag 22 (step S103). On the other hand, when a delay cancellation notification is received (step S102, delay cancellation notification), the delay recognizing means 21 decrements the delay prediction flag 22 (step S104). The delay recognizing means 21 updates the delay prediction flag 22 according to the notification received in this way, for example.

  The above is an example of the operation of the memory access request control mechanism 2 when the delay prediction flag 22 is updated. Next, an example of the operation of the memory access request mechanism 3 will be described with reference to FIG.

  Referring to FIG. 7, the memory access request mechanism 3 receives a memory access command from the memory access command issuing unit 26 (step S201). Specifically, the memory access determination unit 31 of the memory access request mechanism 3 receives a memory access command.

  The memory access determination means 31 interprets the received memory access instruction, confirms the cache 32, updates the cache 32 if necessary, or makes a memory access request to the memory access management mechanism 4. (Step S202).

  The above is an example of the operation of the memory access request mechanism 3. Next, an example of the operation of the memory access management mechanism 4 will be described with reference to FIG.

  Referring to FIG. 8, the memory access monitoring unit 41 of the memory access management mechanism 4 receives a memory access command (step S301). Then, the memory access monitoring unit 41 checks whether or not an entry for the address range to which the memory address requested by the received memory access instruction belongs already exists in the delay prediction table 42 (step S302).

  If there is a corresponding entry (step S302, True), the memory access monitoring unit 41 increments the queue length of the corresponding memory address (step S303). On the other hand, if there is no corresponding entry (step S302, False), the memory access monitoring unit 41 registers the corresponding entry as a new entry in the delay prediction table 42 (step S304). At this time, the queue length of the newly registered entry is 1.

  The memory access monitoring unit 41 confirms whether an alert is set in the corresponding entry as a process capable of parallel operation (step S305), and transmits the received memory access command to the memory access unit 43.

  If an alert is set (step S305, False), one of the parallel processes of the memory access monitoring unit 41 is terminated. On the other hand, if no alert is raised (step S305, True), the memory access monitoring unit 41 activates the delay occurrence prediction unit 45.

  The delay occurrence prediction unit 45 refers to the delay prediction table 42 and confirms whether or not the queue length of the entry that caused the activation is equal to or greater than H-WM (step S306). If the queue length is equal to or longer than H-WM (step S306, True), the delay occurrence prediction unit 45 raises an alert for the corresponding entry (step S307). Further, the delay occurrence prediction unit 45 notifies the delay prediction notification unit 47 that an alert has been set. After that, the delay prediction notifying unit 47 that has received the notification notifies the memory access request control mechanism 2 of the delay prediction notification based on the received notification (step S308). On the other hand, when the queue length is smaller than H-WM (step S306, False), the delay occurrence prediction unit 45 ends the process.

  The memory access means 43 that has received the memory access instruction adds a request to a queue corresponding to the access range to which the memory access instruction requests access, for example, and performs memory access (step S309). This process is performed by, for example, an existing technique.

  When the memory access is completed, the memory access unit 43 notifies the memory access monitoring unit 41 that the memory access is completed. When the notification indicating that the memory access is completed is received, the memory access monitoring unit 41 decrements the queue length of the corresponding entry (step S310). If the queue length becomes 0 as a result of the decrement (step S311, True), the memory access monitoring unit 41 deletes the corresponding entry from the delay prediction table 42 (step S312). On the other hand, when the queue length does not become 0 (step S311, False), the memory access monitoring unit 41 confirms whether an alert is set in the corresponding entry (step S313). Note that this processing is guaranteed to be executed after step S307 in the same access request due to synchronization of parallel processing.

  If no alert is raised (step S313, True), the memory access monitoring unit 41 ends the process. On the other hand, when an alert is raised (step S313, False), the memory access monitoring unit 41 activates the delay elimination prediction unit 46.

  The delay elimination prediction means 46 refers to the delay prediction table 42 and confirms whether or not the queue length of the entry that caused the activation is equal to or less than L-WM (step S314). When the queue length is equal to or shorter than L-WM (step S314, True), the delay elimination prediction unit 46 defeats the alert of the corresponding entry (step S315). Further, the delay elimination prediction means 46 notifies the delay prediction notification means 47 that the alert has been defeated. After that, the delay prediction notification unit 47 that has received the notification notifies the memory access request control mechanism 2 of a delay cancellation notification based on the received notification (step S316). On the other hand, when the queue length is larger than L-WM (step S314, False), the delay elimination prediction unit 46 ends the process.

  The above is an example of the operation of the memory access management mechanism 4.

  As described above, the memory access control device 1 according to the present embodiment includes the delay address confirmation unit 24 and the delay suppression unit 25. In addition, a delay prediction table 42 is provided. With this configuration, the delay address confirmation unit 24 refers to the delay prediction table 42 and confirms whether or not the memory access request is concentrated in the address range to which the memory address requesting access belongs. I can do it. In addition, the delay suppression unit 25 can refrain from memory access in a situation where memory access delay is predicted due to concentration of access based on the confirmation result by the delay address confirmation unit 24. As a result, deterioration of delay can be prevented. That is, the latency can be suppressed.

  Further, the memory access control device 1 in the present embodiment has a delay prediction notification means 47. With such a configuration, the memory access management mechanism 4 can inform the memory access request control mechanism 2 that there is a possibility that a delay has occurred. As a result, the memory access request control mechanism 2 determines whether or not to issue a memory access instruction according to the possibility of occurrence of delay (or whether or not to confirm information for determination). Judgment).

  Further, according to the memory access control device 1 of the present embodiment, it is possible to efficiently control memory access and efficiently suppress the occurrence of delay. Therefore, it is possible to efficiently prevent an increase in delay when the number of CPUs mounted in the system is increased. As a result, it becomes easy to easily increase the number of CPUs. Further, by utilizing the delay prediction table 42, it is possible to easily determine whether or not the cause of the problem occurring in the system is due to a memory access delay.

  Note that the memory access instruction issuance preparation unit 23 in the present embodiment uniformly checks the delay prediction flag 22 when a memory access request is received. However, the memory access instruction issuance preparation unit 23 does not necessarily have to check the delay prediction flag 22 for all received memory access requests. For example, the memory access instruction issue preparation means 23 may be configured to omit the confirmation of the delay prediction flag 22 when all the memory access requests received at the same time are load requests. As described above, the memory access instruction issuance preparation means 23 can be configured to determine whether or not to confirm the delay prediction flag 22 according to the content or type of the received memory access request. Further, the memory access instruction issue preparation means 23 may be configured to confirm the delay prediction flag 22 only for a memory access instruction issued from predetermined software, for example.

  Further, the memory access request control mechanism 2 in the present embodiment may be implemented by software realized by reading a program into hardware such as a CPU as shown in FIG. The interrupt handler 61 in FIG. 9 updates the delay flag 62 in response to the interrupt. Further, the process 63 applies the present invention only to a process that can significantly delay the delay by using, for example, the delay prediction information (delay flag 62, delay prediction table 64), and the delay flag 62 ( 2) and a delay prediction table 64 (corresponding to the delay prediction table 42) are confirmed. The processing content may be system processing or user application processing.

  Further, for example, software implementation realized by loading a program such as the pseudo code in FIG. 10 into hardware may be performed. Here, the is_delay function in FIG. 10 corresponds to the delay address confirmation unit 24, and the lazy_spinlock function corresponds to the delay suppression unit 25. According to FIG. 10, when the delay is predicted by the is_delay function, the lazy_spinlock function is used instead of the normal spinlock function. The lazy_spinlock function achieves the suppression of access to the memory address pointed to by useless lock-> next_ticket that worsens the delay for a certain period by repeating the lock-> nop_times number of instructions that do nothing, such as the nop instruction. .

  In the case described above, the lock time can be dynamically changed using a specific algorithm by using lock-> nop_times indicating how much access is suppressed as a variable. As described above, the time during which the delay suppression unit 25 suppresses access may be configured to change dynamically. Further, for example, it is possible to add the suppression time as a new item in the delay prediction table 42 and acquire the suppression time from the memory access management mechanism 4.

  Further, in the present embodiment, the memory access management mechanism 4 has the global delay prediction table 42 in which the target is the entire address range. In the delay prediction table 42, H-WM and L-WM are fixed values, and the delay suppression time is set in advance in the memory access request control mechanism 2. However, the configuration of the memory access management mechanism 4 is not limited to the above case. For example, the address range stored in one delay prediction table 42 is divided and distributed to a plurality of delay prediction tables 42, and the delay prediction flags 22 are configured by the number of delay prediction tables 42, or some memory addresses You may use only the range delay prediction table. Further, the H-WM and L-WM may be configured to be dynamically changeable depending on, for example, the load status on the system having the memory access control device 1. The delay suppression time may be configured to be controllable by the memory access management mechanism 4. For example, the delay suppression time may be included in the delay prediction table 42. The delay suppression time may be dynamically controlled by, for example, the memory access monitoring unit 41, for example, as the queue length becomes longer.

  In the present embodiment, the memory access management mechanism 4 predicts the occurrence of delay based on the queue length. However, the memory access management mechanism 4 may predict the occurrence of delay based on other than the queue length. For example, the memory access management mechanism 4 may be configured to measure the time required for memory access and predict the occurrence of delay based on the measurement result. As described above, the memory access management mechanism 4 may be configured to predict the occurrence of delay based on other than the queue length and transmit the delay prediction notification.

[Second Embodiment]
Subsequently, in the second embodiment, the memory access control device 1 described in the first embodiment is replaced with the node controller 71 (node controllers 71a and 71b) of the NUMA type system 7 having a NUMA (Non-Uniform Memory Access) configuration. 71c, 71d, unless otherwise distinguished, will be referred to as a node controller 71. Hereinafter, an example in the case of application to the same will be described. In the following description, descriptions overlapping with those of the first embodiment are omitted.

  Referring to FIG. 11, the NUMA type system 7 in the present embodiment has, for example, four nodes, and four node controllers 71 (71a, 71b, 71c, 71d) corresponding to the respective nodes; Four CPUs 72 (72a, 72b, 72c, 72d) composed of a plurality of CPUs, four memory controllers 73 (73a, 74b, 73c, 73d), and 16 memories 74 (74a, 74b, 74c, 74d) 4). Further, as described above, each node controller 71 has the configuration of the memory access control device 1 described in the first embodiment.

  In such a system, when accessing via the node controller 71 (in the case of via C01, via the node controllers 71a and 71b) as in the path C01 shown in FIG. 12, the path from the CPU 72 to the memory 74 ( In the case of the via C01, the memory 74b) becomes longer from the CPU 72a, so that the latency is increased. For this reason, as shown in FIG. 13, when accesses to the same memory address from many CPUs 72 are concentrated, that is, for example, when there are many accesses to the same memory address via the node controller 71b, memory access via the node controller 71b is performed. Therefore, latency is likely to occur in all paths. Therefore, it is considered that by applying the present invention to the node controller 71, it is possible to monitor memory access via a route passing through the node controller 71, and a great effect can be obtained.

  Further, the delay due to the concentration of access to the same memory address using the path not passing through the node controller 71 such as the path C02 and the path C03 shown in FIG. 12 is compared with the delay occurring when passing through the node controller 71. It is considered relatively small. Therefore, each node controller 71 manages, for example, only the load status of the memory controller 73 that is directly managed by itself (for example, the node controller 71a manages the load status of the memory controller 73a) as shown in FIG. . Thereby, efficient management can be performed. FIG. 14 shows that the node controller 71a manages the load status of the memory controller 73a (MC1). 14 shows an example of the delay prediction table 42 in each node controller 71 where the queue shown in FIG. 3 is a queue for each memory controller and the queue length is the number of accesses to each memory controller 73. . Also, the case where the H-WM and L-WM are dynamically changed (for example, dynamically changed according to the load on each node, etc.) is shown, and the delay suppression time is dynamically controlled Is shown.

[Third Embodiment]
Next, a third embodiment will be described with reference to FIG. In the third embodiment, a memory access control device 8 that suppresses latency caused by concentration of accesses to the same address range will be described. In the present embodiment, an outline of the configuration of the memory access control device 8 will be described.

  Referring to FIG. 15, the memory access control device 8 in the present embodiment includes an accepting unit 81, an issuing unit 82, a suppressing unit 83, and a memory access unit 84.

  The accepting unit 81 accepts an access request to a memory address. In response to the access request received by the receiving unit 81, the issuing unit 82 issues an access command that instructs the memory access unit 84 to access the memory address.

  The suppression unit 83 refers to the status information indicating the status of access by the memory access unit 84 to the memory address requested by the access request, and suppresses the issue of the access command by the issuing unit 82 based on the status information for a predetermined time. .

  As described above, the memory access control device 8 according to the present embodiment includes the issuing unit 82 and the suppressing unit 83. With such a configuration, the suppressing unit 83 can refer to the situation information and suppress the issuance of the access command by the issuing unit 82 for a predetermined time based on the situation information. That is, based on the status information, for example, when the access request determines that access to the memory address requesting access is delayed, the suppression unit 83 issues an access command requesting access to the memory address. Time can be suppressed. Thereby, it is possible to refrain from memory access in a situation where memory access delay is predicted. As a result, deterioration of delay can be prevented. That is, the latency can be suppressed.

  The memory access control device 8 can be realized by incorporating a predetermined program into the memory access control device 8. Specifically, a program according to another embodiment of the present invention includes: a receiving unit that receives an access request to a memory address in an information processing device; and a memory that is stored in the memory access unit according to the access request received by the receiving unit. Issuing means for issuing an access instruction for instructing access to an address, and status information indicating the status of access by the memory access means for the memory address to which the access request requests access, and by issuing means based on the status information And a suppressor that suppresses issuance of an access command for a predetermined time.

  The memory access control method executed by the operation of the memory access control device 8 described above accepts an access request to a memory address, and responds to the memory address with respect to the memory access means according to the accepted access request. An access instruction for instructing access is issued, the access request refers to the status information indicating the status of access by the memory access means for the memory address requesting access, and the issuance of the access command is suppressed for a predetermined time based on the status information This is the method.

  Even the invention of the program or the memory access control method having the above-described configuration can achieve the above-described object of the present invention because it has the same operation as the memory access control device 8.

<Appendix>
Part or all of the above-described embodiment can be described as in the following supplementary notes. The outline of the memory access control device and the like in the present invention will be described below. However, the present invention is not limited to the following configuration.

(Appendix 1)
Accepting means for accepting an access request to a memory address;
An issuing unit that issues an access instruction to instruct the memory access unit to access a memory address in response to the access request received by the receiving unit;
A control unit that refers to status information indicating a status of access by the memory access unit with respect to a memory address to which the access request requests access, and suppresses issuance of the access command by the issuing unit for a predetermined time based on the status information; ,
A memory access control device.

  According to this configuration, the memory access control device has the issuing unit and the suppressing unit. With such a configuration, the suppression unit can refer to the situation information and suppress the issuance of the access command by the issuing unit for a predetermined time based on the situation information. Thereby, it is possible to refrain from memory access in a situation where memory access delay is predicted. As a result, deterioration of delay can be prevented. That is, the latency can be suppressed.

(Appendix 2)
The memory access control device according to attachment 1, wherein
The suppression means refers to information indicating the number of accesses to a memory address to which the access request requests access as the status information.

  According to this configuration, the suppression unit refers to information indicating the number of accesses to the memory address requested by the access request as the status information. Thereby, the suppression means can suppress the issue of the access command by the issuing means for a predetermined time, for example, when it is determined that the number of accesses is large and the access is concentrated. As a result, it is possible to suppress latency caused by concentration of accesses to memory addresses.

(Appendix 3)
The memory access control device according to appendix 1 or 2,
The memory unit is a memory access control device that refers to information indicating a queue length that is the number of the access instructions after the memory access unit receives and before the execution completion as the status information.

  According to this configuration, the suppression unit refers to information indicating the queue length as the status information. As a result, when it is determined that access to the corresponding memory address is concentrated based on the number of access instructions being executed (processing) by the memory access means, the issuing means issues the access instructions in a predetermined manner. Time can be suppressed.

(Appendix 4)
The memory access control device according to attachment 3, wherein
The memory access control device that suppresses issuance of the access command that instructs access to a corresponding memory address for a predetermined time when the queue length is equal to or greater than a predetermined delay threshold.

(Appendix 5)
The memory access control device according to appendix 3 or 4,
In a state where the issuing unit suppresses the issuing of the access command for a predetermined time, the suppressing unit issues the access command until the queue length becomes equal to or less than a cancellation threshold that is smaller than the delay threshold. A memory access control device that maintains a state of being suppressed for a predetermined time.

(Appendix 6)
The memory access control device according to any one of appendices 3 to 5,
The queue length is measured for each address range in which values up to a predetermined number of memory addresses coincide with each other.

(Appendix 7)
The memory access control device according to any one of appendices 1 to 6,
The suppressing means is configured to transmit the received access request to the issuing means after receiving the access request from the accepting means, and for the access request that is determined to be delayed based on the status information Then, after receiving the access request from the accepting unit, the memory access control device transmits the received access request to the issuing unit after waiting for a predetermined time.

(Appendix 8)
The memory access control device according to appendix 7,
When it is determined that a delay occurs based on the situation information, the transmission unit has a transmission unit that transmits the delay prediction information for predicting the occurrence of the delay to the reception unit,
The accepting unit is a memory access control device that transmits the memory access request to the suppressing unit when occurrence of a delay is predicted based on the delay prediction information.

(Appendix 9)
Accept access request to memory address,
In response to the received access request, issue an access instruction to instruct the memory access means to access the memory address,
The access request refers to status information indicating a status of access by the memory access means for a memory address that requests access, and based on the status information, issuance of the access command is suppressed for a predetermined time.
Memory access control method.

(Appendix 9-1)
A memory access control method according to attachment 9, wherein
A memory access control method for referring to information indicating the number of accesses to a memory address to which the access request requests access as the status information.

(Appendix 9-2)
A memory access control method according to appendix 9 or 9-1,
The memory control method according to claim 1, wherein the suppression unit refers to information indicating a queue length that is the number of the access instructions after the memory access unit has received and before completion of execution as the status information.

(Appendix 10)
In the information processing device,
Accepting means for accepting an access request to a memory address;
An issuing unit that issues an access instruction to instruct the memory access unit to access a memory address in response to the access request received by the receiving unit;
A control unit that refers to status information indicating a status of access by the memory access unit with respect to a memory address to which the access request requests access, and suppresses issuance of the access command by the issuing unit for a predetermined time based on the status information; ,
A program to realize

(Appendix 10-1)
The program according to attachment 10, wherein
The suppression unit refers to information indicating the number of accesses to a memory address to which the access request requests access as the status information.

(Appendix 10-2)
The program according to appendix 10 or 10-1,
The control unit refers to information indicating a queue length, which is the number of the access instructions after the memory access unit receives and before the execution is completed, as the status information.

  The programs described in the above embodiments and supplementary notes are stored in a storage device or recorded on a computer-readable recording medium. For example, the recording medium is a portable medium such as a flexible disk, an optical disk, a magneto-optical disk, and a semiconductor memory.

  Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Memory access control apparatus 2 Memory access request control mechanism 21 Delay recognition means 22 Delay prediction flag 23 Memory access instruction issue preparation means 24 Delay address confirmation means 25 Delay suppression means 26 Memory access instruction issue means 3 Memory access request mechanism 31 Memory access judgment Means 32 Cache 4 Memory access management mechanism 41 Memory access monitoring means 42 Delay prediction table 43 Memory access means 44 Memory 45 Delay occurrence prediction means 46 Delay elimination prediction means 47 Delay prediction notification means 5 System 51 Processor 52 Memory controller 53 Memory 61 Interrupt handler 62 Delay flag 63 Processing 64 Delay prediction table 7 NUMA system 71 Node controller 72 CPU
73 memory controller 74 memory 8 memory access control device 81 receiving means 82 issuing means 83 suppressing means 84 memory access means

Claims (7)

Accepting means for accepting an access request to a memory address;
An issuing unit that issues an access instruction to instruct the memory access unit to access a memory address in response to the access request received by the receiving unit;
A control unit that refers to status information indicating a status of access by the memory access unit with respect to a memory address to which the access request requests access, and suppresses issuance of the access command by the issuing unit for a predetermined time based on the status information; ,
Have a,
The suppression means refers to information indicating a queue length that is the number of the access instructions after the memory access means has received and before execution completion as the status information,
The queue length is a memory access control device that is measured for each address range in which values up to a predetermined number of memory addresses match . The memory access control device according to claim 1 ,
The memory access control device that suppresses issuance of the access command that instructs access to a corresponding memory address for a predetermined time when the queue length is equal to or greater than a predetermined delay threshold. The memory access control device according to claim 2 ,
In a state where the issuing unit suppresses the issuing of the access command for a predetermined time, the suppressing unit issues the access command until the queue length becomes equal to or less than a cancellation threshold that is smaller than the delay threshold. A memory access control device that maintains a state of being suppressed for a predetermined time. A memory access control device according to any one of claims 1 to 3 ,
The suppressing means is configured to transmit the received access request to the issuing means after receiving the access request from the accepting means, and for the access request that is determined to be delayed based on the status information Then, after receiving the access request from the accepting unit, the memory access control device transmits the received access request to the issuing unit after waiting for a predetermined time. The memory access control device according to claim 4 ,
When it is determined that a delay occurs based on the situation information, the transmission unit has a transmission unit that transmits the delay prediction information for predicting the occurrence of the delay to the reception unit,
It said accepting means, when the occurrence of the delay based on the delay prediction information is predicted, before a memory access controller for transmitting Kia access request to the suppressing means. Accept access request to memory address,
In response to the received access request, issue an access instruction to instruct the memory access means to access the memory address,
With reference to status information indicating the status of access by the memory access means for the memory address to which the access request requests access, issuance of the access command is suppressed for a predetermined time based on the status information ,
As the status information, refer to information indicating a queue length which is the number of the access instructions after the access instruction is received and before the execution is completed,
The queue length is a memory access control method measured for each address range in which values up to a predetermined number of memory addresses match . In the information processing device,
Receiving means for receiving an access request to the memory address;
An issuing unit that issues an access instruction to instruct the memory access unit to access a memory address in response to the access request received by the receiving unit;
A control unit that refers to status information indicating a status of access by the memory access unit with respect to a memory address to which the access request requests access, and suppresses issuance of the access command by the issuing unit for a predetermined time based on the status information; ,
Realized ,
The suppression unit refers to information indicating a queue length that is the number of the access instructions after the memory access unit has received and before execution completion as the status information,
The queue length is measured for each address range in which values up to a predetermined number of memory addresses match .

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