JP6609926B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a compound semiconductor device and a method for manufacturing the same, for example, a compound semiconductor transistor using a high dielectric constant insulating film such as an Al ₂ O ₃ film as a gate insulating film and a method for manufacturing the same.

  A transistor using a nitride semiconductor typified by AlGaN / GaN-HEMT can apply a gate voltage positively by adopting a MIS (Metal Insulator Semiconductor) structure using a gate insulating film. Moreover, high output can be realized thereby.

However, the transconductance g _m for the distance between the gate electrode and the channel With the gate insulating film is increased is lowered. Therefore, it is important to shorten the distance between the gate electrode and the channel by using a recess structure directly under the gate electrode, and the gate recess MIS structure is a promising structure for high output (for example, see Patent Document 1 or Patent Document 2). .

In GaN-based semiconductors, Al ₂ O ₃ is most used as a material for the gate insulating film. This is because Al ₂ O ₃ has a wider band gap and higher breakdown voltage than SiO ₂ , has a relatively high dielectric constant, and has a large ΔE _c with GaN. Here, a conventional AlGaN / GaN gate recess MISFET will be described with reference to FIG.

  FIG. 29 is a schematic cross-sectional view of a conventional AlGaN / GaN gate recess MISFET, in which an i-type GaN electron transit layer 103, an n-type AlGaN electron supply layer 104, and an n-type are disposed on an SiC substrate 101 via an AlN buffer layer 102. A GaN cap layer 105 is sequentially formed. A two-dimensional electron gas layer 106 is formed at the interface between the i-type GaN electron transit layer 103 and the n-type AlGaN electron supply layer 104.

Next, a gate electrode 114 is provided through an Al ₂ O ₃ film 111 formed as a gate insulating film by forming a gate recess region. On the other hand, an ohmic recess region is formed on both sides away from the gate electrode 114 to provide a source electrode 118 and a drain electrode 119. Thus, since the right under the gate electrode 114 is made shorter the distance between the gate electrode 114 and the two-dimensional electron gas layer 106 as a recess structure, it is possible to increase the mutual conductance g _m.

  Such a manufacturing method of the recess MIS structure can be roughly divided into two processes. One is a gate first process, which is a method of forming an ohmic electrode after providing a gate insulating film and a gate electrode. The other is an ohmic first process in which an ohmic electrode is formed and then a gate insulating film is formed.

  Comparing the two methods, the gate-first process can reduce the level of the gate insulating film / semiconductor interface. Therefore, electron traps at the insulating film / semiconductor interface can be suppressed, and threshold voltage shift and current collapse can be suppressed. Here, a manufacturing process of the AlGaN / GaN gate recess MISFET by the conventional gate first process will be described with reference to FIGS.

  First, as shown in FIG. 30A, an AlN buffer layer 102, an i-type GaN electron transit layer 103, an n-type AlGaN electron supply layer 104, and an n-type GaN cap layer 105 are sequentially formed on the SiC substrate 101. . Next, as shown in FIG. 30B, the n-type GaN cap layer 105 is etched using the resist pattern 107 as a mask, and the n-type AlGaN electron supply layer 104 is etched halfway to form an ohmic recess region 108.

Next, as shown in FIG. 30C, after removing the resist pattern 107, a new resist pattern 109 is provided, and the surface side of the n-type GaN cap layer 105 and the n-type AlGaN electron supply layer 104 is etched. A gate recess region 110 is formed. Next, as shown in FIG. 31D, after the resist pattern 109 is removed, an Al ₂ O ₃ film 111 to be a gate insulating film is formed on the entire surface.

  Next, as shown in FIG. 31E, after providing a resist pattern 112, a Ni film and an Au film are sequentially deposited to form a Ni / Au film 113. At this time, the Ni / Au film deposited in the gate recess region 110 becomes the gate electrode 114. Next, the Ni / Au film 113 deposited on the resist pattern 112 together with the resist pattern 112 is lifted off.

Next, as shown in FIG. 31F, a new resist pattern 115 is provided, and the Al ₂ O ₃ film 111 exposed in the ohmic recess region 108 is removed by etching using the resist pattern 115 as a mask.

  Next, as shown in FIG. 32G, after removing the resist pattern 115, a new resist pattern 116 is provided, and a Ti film and an Al film are sequentially formed to form a Ti / Al film 117. Next, as shown in FIG. 32H, the Ti / Al film 117 deposited on the resist pattern 116 together with the resist pattern 116 is lifted off. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film 117 is in ohmic contact with the n-type AlGaN electron supply layer 104 to form the source electrode 118 and the drain electrode 119. Thus, the basic structure of the AlGaN / GaN gate recess MISFET is completed. Actually, the source electrode 118 and the drain electrode 119 are alternately arranged with the gate electrode 114 interposed therebetween, and the gate electrode 114 has a comb-like electrode structure.

JP 2008-098455 A JP 2012-089677 A

However, when the gate recess MIS structure using the Al ₂ O ₃ film as the gate insulating film is manufactured by the gate first process, the Al ₂ O ₃ film in the ohmic electrode formation scheduled region is opened as shown in FIG. It is necessary to do. As a means for opening the Al ₂ O ₃ film, wet etching can be considered first, but the wet etching of the Al ₂ O ₃ film is concerned with the progress of etching in the lateral direction, and it is difficult to apply it to a device having a small size.

In addition, although the opening can be formed in the Al ₂ O ₃ film by dry etching using a gas containing BCl ₃ , it is necessary to etch with low power in consideration of damage to the underlying AlGaN. However, when etching is performed at a low power, there is a problem that the periphery of the etching bottom is deepened to form a micro-trench (sub-trench) due to the influence of ions wrapping around due to the etching mask and side wall charging.

FIG. 33 is an explanatory diagram of problems in the manufacturing process of the conventional AlGaN / GaN gate recess MISFET, and shows a diagram corresponding to the above-described FIG. 31 (f). When the exposed portion of the Al ₂ O ₃ film 111 is dry-etched with BCl ₃ using the resist pattern 115 as a mask, the n-type AlGaN electron supply layer 104 under the Al ₂ O ₃ film 111 is also etched. Therefore, the micro-trench 120 generated during the etching of the Al ₂ O ₃ film 111 has a history in the etching shape of the n-type AlGaN electron supply layer 104 (and the i-type GaN electron transit layer 103), and the source electrode 118 provided in this region. In addition, the contact resistance of the drain electrode 119 is increased. The generation of micro-trench accompanying the etching of the Al ₂ O ₃ film occurs regardless of the gate recess structure or the ohmic recess structure, and becomes a cause of increasing the contact resistance of the ohmic electrode.

Therefore, when a MIS structure using a high dielectric constant insulating film such as Al ₂ O ₃ as a gate insulating film is manufactured by a gate first process, the generation of a micro-trench shape is suppressed and an increase in resistance of the ohmic electrode is suppressed. With the goal.

From a disclosed aspect, a nitride semiconductor carrier travel layer is formed on a substrate, a nitride semiconductor carrier supply layer is formed on the carrier travel layer, and Si is contained on the carrier supply layer. Forming a first insulating film; removing a part of the first insulating film; and covering a part of the first insulating film from which the first insulating film has been removed. And covering a part of the second insulating film where the two-dimensional electron gas layer is present at a position away from the first insulating film, from which the first insulating film is removed. A gate electrode is formed in a portion, the first insulating film and the second insulating film are spaced apart from the gate electrode, and the first opening and the second opening are located at positions sandwiching the gate electrode. Forming a source electrode and a drain electrode in the first opening and the second opening In the formation of the first opening and the second opening, the second insulating film is etched with the first gas, and the etching rate of the nitride semiconductor is lower than that of the first gas. There is provided a method of manufacturing a compound semiconductor device, wherein the first insulating film is etched with a second gas.

From another viewpoint to be disclosed, a substrate, a nitride semiconductor carrier travel layer formed on the substrate, a nitride semiconductor carrier supply layer formed on the carrier travel layer, and A second insulating film formed on the carrier supply layer; a gate electrode formed in a region where a two-dimensional electron gas layer exists through the second insulating film; and a position sandwiching the gate electrode. Further, the source electrode and the drain electrode are formed on the carrier supply layer, are separated from the gate electrode, and the source electrode and the drain electrode are disposed on the gate electrode side of the source electrode and the gate electrode side of the drain electrode. There is provided a compound semiconductor device comprising: a first insulating film containing Si that is in contact with the first insulating film; and the second insulating film extends to the top of the first insulating film. The

According to the disclosed compound semiconductor device and manufacturing method thereof, generation of a micro-trench shape is suppressed when a MIS structure using a high dielectric constant insulating film such as Al ₂ O ₃ as a gate insulating film is manufactured by a gate first process. It becomes possible. This also makes it possible to suppress an increase in resistance of the ohmic electrode.

It is explanatory drawing of the manufacturing process of the compound semiconductor device of embodiment of this invention. It is explanatory drawing of the manufacturing process of the other compound semiconductor device of embodiment of this invention. It is explanatory drawing to the middle of the manufacturing process of AlGaN / GaNMISFET of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 3 of the manufacturing process of AlGaN / GaNMISFET of Example 1 of this invention. It is explanatory drawing after FIG. 4 of the manufacturing process of AlGaN / GaNMISFET of Example 1 of this invention. It is explanatory drawing of the modification of AlGaN / GaNMISFET of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of AlGaN / GaNMISFET of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 7 of the manufacturing process of AlGaN / GaNMISFET of Example 2 of this invention. It is explanatory drawing to the middle after FIG. 8 of the manufacturing process of AlGaN / GaNMISFET of Example 2 of this invention. It is explanatory drawing after FIG. 9 of the manufacturing process of AlGaN / GaNMISFET of Example 2 of this invention. It is principal part explanatory drawing of the manufacturing process of AlGaN / GaNMISFET of Example 3 of this invention. It is explanatory drawing to the middle of the manufacturing process of AlGaN / GaNMISFET of Example 4 of this invention. It is explanatory drawing to the middle after FIG. 12 of the manufacturing process of AlGaN / GaNMISFET of Example 4 of this invention. It is explanatory drawing to the middle after FIG. 13 of the manufacturing process of AlGaN / GaNMISFET of Example 4 of this invention. FIG. 15 is an explanatory view after FIG. 14 of the manufacturing process of the AlGaN / GaN MISFET of Example 4 of the present invention. It is explanatory drawing to the middle of the manufacturing process of AlGaN / GaNMISFET of Example 5 of this invention. It is explanatory drawing to the middle after FIG. 16 of the manufacturing process of AlGaN / GaNMISFET of Example 5 of this invention. It is explanatory drawing to the middle after FIG. 17 of the manufacturing process of AlGaN / GaNMISFET of Example 5 of this invention. FIG. 19 is an explanatory view of FIG. 18 and subsequent drawings showing a manufacturing process of an AlGaN / GaN MISFET of Example 5 of the present invention. It is explanatory drawing to the middle of the manufacturing process of AlGaN / GaNMISFET of Example 6 of this invention. It is explanatory drawing to the middle after FIG. 20 of the manufacturing process of AlGaN / GaNMISFET of Example 6 of this invention. It is explanatory drawing to the middle after FIG. 21 of the manufacturing process of AlGaN / GaNMISFET of Example 6 of this invention. It is explanatory drawing after FIG. 22 of the manufacturing process of AlGaN / GaNMISFET of Example 6 of this invention. It is explanatory drawing to the middle of the manufacturing process of AlGaN / GaNMISFET of Example 7 of this invention. It is explanatory drawing to the middle after FIG. 24 of the manufacturing process of AlGaN / GaNMISFET of Example 7 of this invention. It is explanatory drawing to the middle after FIG. 25 of the manufacturing process of AlGaN / GaNMISFET of Example 7 of this invention. It is explanatory drawing after FIG. 26 of the manufacturing process of AlGaN / GaNMISFET of Example 7 of this invention. It is principal part explanatory drawing of the manufacturing process of AlGaN / GaNMISFET of Example 8 of this invention. It is a schematic sectional view of a conventional AlGaN / GaN gate recess MISFET. It is explanatory drawing to the middle of the manufacturing process of the conventional AlGaN / GaN gate recess MISFET. It is explanatory drawing to the middle after FIG. 30 of the manufacturing process of the conventional AlGaN / GaN gate recess MISFET. It is explanatory drawing after FIG. 31 of the manufacturing process of the conventional AlGaN / GaN gate recess MISFET. It is explanatory drawing of the problem of the manufacturing process of the conventional AlGaN / GaN gate recess MISFET.

  Here, with reference to FIG. 1 and FIG. 2, the compound semiconductor device of the embodiment of the present invention will be described. FIG. 1 is an explanatory diagram of a manufacturing process of a compound semiconductor device according to an embodiment of the present invention. Here, a process after forming a gate electrode is illustrated. First, as shown in FIG. 1A, at least a nitride carrier traveling layer 12 and a nitride carrier supply layer 13 are sequentially formed on a substrate 11. A two-dimensional carrier gas layer 15 is formed at the interface between the nitride carrier running layer 12 and the nitride carrier supply layer 13.

  Next, after depositing the first insulating film 16 over the entire surface, the first insulating film 16 deposited in the region including the gate formation region is selectively removed to expose the region including the gate formation region. Next, a second insulating film 17 having a dielectric constant higher than that of the first insulating film 16 is deposited so as to cover the region including the gate formation region and the remaining first insulating film 16. Next, the gate electrode 18 is provided in the gate formation region.

As the second insulating film 17, a high dielectric constant, and, using Delta] E _c is greater aluminum oxide film or a high dielectric constant of aluminum oxide insulating film to the nitride semiconductor, for example, hafnium oxide with (HfO ₂₎ .

In addition, the condition of the first insulating film 16 is as follows:
(1) A film can be formed with almost no damage to the nitride semiconductor.
(2) Patterning (processing) is possible.
(3) The etching rate by BCl ₃ is equal to or smaller than that of Al ₂ O ₃ or HfO ₂ used as the second insulating film 18.
(4) Etching can be performed using a fluorine-based gas that does not etch the nitride semiconductor. Typically, any one of a silicon nitride film (SiN film), a silicon oxide film (SiO ₂ film), or a silicon oxynitride film (SiON film) is used.

  Next, as shown in FIG. 1B, using the resist pattern 19 as a mask, the second insulating film 17 covering the electrode formation region 20 for forming the source electrode / drain electrode is dry-etched. Next, as shown in FIG. 1C, the first insulating film 16 covering the electrode formation region 20 is selectively etched. Note that the electrode formation region 20 may be dug in advance before the step of depositing the first insulating film 16. Alternatively, the electrode forming region 20 may be dug down after the step of selectively removing the first insulating film 16 covering the electrode forming region 20.

In the step of dry etching the second insulating film 17, the nitride semiconductor is etched because the first insulating film 16 is provided in the lower layer even if a material containing boron trichloride (BCl ₃ ) is used. There is nothing. Further, in the step of selectively etching the first insulating film 16, by using dry etching using a gas containing a fluorine-based gas, even if a micro trench is generated in the etching step of the second insulating film 17. The underlying nitride semiconductor layer is not etched.

  As the substrate 11, a SiC substrate, a sapphire substrate, a GaN substrate, or a Si substrate can be used. Further, a buffer layer may be provided between the substrate 11 and the nitride carrier transit layer 12, and an AlN buffer layer, a GaN buffer layer, an AlN low temperature buffer layer, or a GaN low temperature buffer layer can be used as the buffer layer.

  The nitride carrier running layer 12 is typically an i-type GaN layer, but may be i-type InGaN or the like. The nitride carrier supply layer 13 is typically an n-type AlGaN layer. However, when the nitride carrier running layer 12 is an i-type InGaN layer, an n-type GaN layer may be used. Furthermore, when holes are used as carriers, Mg may be doped instead of Si as a dopant to make it p-type.

  Further, a cap layer 14 such as an n-type GaN layer may be provided in advance on the growth surface side of the nitride carrier supply layer 13, and by providing the cap layer 14, oxidation of the surface of the nitride carrier supply layer 13 is prevented. be able to.

  In the case of growing the above nitride semiconductor layer, metal organic vapor phase epitaxy (MOVPE) is used. Alternatively, a molecular beam epitaxy (MBE) method or the like may be used instead of the metal organic chemical vapor deposition method.

In the case of using a metal organic chemical vapor deposition method, trimethylaluminum gas (TMAl) or the like is used as an Al source, trimethylgallium gas (TMGa) or the like is used as a Ga source, and ammonia (NH ₃ ) is used as an N source. . The flow rate of the ammonia gas is about 100 sccm to 10,000 sccm, the growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° to 1200 °. The doping concentration of Si is about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

  In the embodiment of the present invention shown in FIG. 1, the gate recess structure and the ohmic recess structure are not used, but one or both of the structures may be employed together. The structure adopted will be described with reference to FIG. FIG. 2 is an explanatory diagram of another manufacturing process of the compound semiconductor device according to the embodiment of the present invention, and again shows the process after the formation of the gate electrode. First, as shown in FIG. 2A, at least a nitride carrier traveling layer 12 and a nitride carrier supply layer 13 are sequentially formed on the substrate 11. A two-dimensional carrier gas layer 15 is formed at the interface between the nitride carrier running layer 12 and the nitride carrier supply layer 13. Next, a gate recess region is formed in the nitride carrier supply layer 13.

  Next, after the first insulating film 16 is deposited on the entire surface, the first insulating film 16 deposited in the region including the gate recess region is selectively removed to expose the region including the gate recess region. Next, a second insulating film 17 having a dielectric constant higher than that of the first insulating film 16 is deposited so as to cover the region including the gate recess region and the remaining first insulating film 16. Next, the gate electrode 18 is provided so as to cover the gate recess region and its vicinity.

  Next, as shown in FIG. 2B, using the resist pattern 19 as a mask, the second insulating film 17 covering the electrode formation region 20 for forming the source electrode / drain electrode is dry etched. Next, as shown in FIG. 2C, the first insulating film 16 covering the electrode formation region 20 is selectively etched. Note that the electrode formation region 20 may be dug in advance before the step of depositing the first insulating film 16. Alternatively, the electrode forming region 20 may be dug down after the step of selectively removing the first insulating film 16 covering the electrode forming region 20.

As described above, even when the gate recess structure and the ohmic recess structure are employed, the first insulating film 16 is provided in the lower layer in the step of dry-etching the second insulating film 17 with BCl _3. It is not etched. Further, in the step of selectively etching the first insulating film 16, by using dry etching using a gas containing a fluorine-based gas, even if a micro trench is generated in the etching step of the second insulating film 17. The underlying nitride semiconductor layer is not etched.

In the embodiment of the present invention, since the first insulating film 16 is interposed under the second insulating film 17 at the location where the ohmic electrode is formed, even if a micro-trench is generated, the shape is The nitride semiconductor layer is not taken over. As a result, the contact resistance (Ωcm ² ) can be reduced by an order of magnitude compared to a conventional gate first process in which microtrench is introduced into a nitride semiconductor layer.

  Next, with reference to FIGS. 3 to 5, the manufacturing process of the AlGaN / GaN MISFET of Example 1 of the present invention will be described. First, as shown in FIG. 3A, an AlN buffer layer 22 having a thickness of 100 nm is grown on a SiC substrate 21 as a growth substrate by metal organic vapor phase epitaxy. Subsequently, an i-type GaN electron transit layer 23 having a thickness of 300 nm, an n-type AlGaN electron supply layer 24 having a thickness of 20 nm and an Al composition ratio of 0.2, and an n-type GaN cap layer having a thickness of 5 nm are sequentially grown. Let At this time, a two-dimensional electron gas layer 26 is generated at the interface between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24. Next, an element isolation region (not shown) that reaches the SiC substrate 21 is formed by ion implantation of Ar.

Note that a mixed gas of trimethylaluminum gas (TMAl), trimethylgallium gas (TMGa), and ammonia gas is used as a source gas in the growth conditions. For example, when growing a GaN layer, TMGa is 200 sccm, ammonia gas is 4000 sccm, the growth pressure is 100 Torr, and the growth temperature is 1100 ° C. Further, SiH ₄ is used as an n-type impurity source for growing the n-type layer, the Si concentration of the n-type AlGaN electron supply layer 24 is 5 × 10 ¹⁸ cm ^−3, and the Si of the n-type GaN cap layer 25 is used. The concentration is 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 3B, a SiN film 27 having a thickness of 50 nm is deposited on the entire surface by using a CVD (chemical vapor deposition) method. Next, as shown in FIG. 3C, a resist pattern 28 having an opening corresponding to the gate opening is provided, and the exposed portion of the SiN film 27 is removed using CF ₄ gas using the resist pattern 28 as a mask. A gate opening 29 is formed.

Next, as shown in FIG. 4D, after the resist pattern 28 is removed, an Al ₂ O ₃ film 30 serving as a gate insulating film is provided on the entire surface by using an ALD (Atomic Layer Deposition) method. If the thickness of the Al ₂ O ₃ film 30 is increased, a positive voltage can be applied by the gate electrode, but g _m is lowered. Therefore, the thickness is determined by the required specification of the device, but here it is 20 nm.

  Next, as shown in FIG. 4E, a resist pattern 31 that opens the gate formation region is provided, and an Ni film with a thickness of 50 nm and an Au film with a thickness of 150 nm are sequentially formed by vapor deposition. Then, the Ni / Au film 32 is formed. At this time, the Ni / Au film deposited in the gate formation region becomes the gate electrode 33.

Next, as shown in FIG. 4F, after the Ni / Au film 32 deposited on the resist pattern 31 is lifted off together with the resist pattern 31, a resist pattern 34 that opens the ohmic electrode formation region is provided. Next, the exposed Al ₂ O ₃ film 30 is removed using BCl ₃ using the resist pattern 34 as a mask. At this time, a micro trench may be generated in the SiN film 27 in some cases.

Subsequently, as shown in FIG. 5G, the exposed SiN film 27 is selectively removed using CF ₄ gas using the resist pattern 34 as it is as a mask. At this time, since AlGaN or GaN is not etched by the fluorine-based gas, it stops at the surface of the n-type GaN cap layer 25.

  Next, as shown in FIG. 5 (h), after removing the resist pattern 34, a new resist pattern 35 is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film 36 is formed by film formation.

  Next, as shown in FIG. 5I, the Ti / Al film 36 deposited on the resist pattern 35 is lifted off together with the resist pattern 35. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film 36 is brought into ohmic contact with the n-type GaN cap layer 25 to form a source electrode 37 and a drain electrode 38. Thus, the basic structure of the AlGaN / GaN MISFET of Example 1 of the present invention is completed. In practice, the source electrode 37 and the drain electrode 38 are alternately arranged with the gate electrode 33 interposed therebetween, and the gate electrode 33 has a comb-like electrode structure.

In Example 1 of the present invention, when the source electrode and the drain electrode are formed after the gate electrode is formed, since the SiN film is provided under the Al ₂ O ₃ film serving as the gate insulating film, a micro trench is generated. Is also generated in the SiN film. When the SiN film in which the micro-trench is generated is etched with CF ₄ , the shape of the micro-trench is not inherited by GaN and AlGaN because GaN and AlGaN are not etched. As a result, an increase in ohmic resistance due to the microtrench can be prevented. In addition, since the gate first process is applied, the threshold voltage shift can be reduced as compared with the transistor manufactured by the ohmic first process.

  FIG. 6 is a cross-sectional view of a modification of the AlGaN / GaN gate recess MISFET according to the first embodiment of the present invention. In this modification, the n-type GaN cap layer is omitted. Other structures and manufacturing processes are the same as those of the AlGaN / GaN MISFET of Example 1.

  Next, the manufacturing process of the AlGaN / GaN MISFET according to the second embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 7A, similarly to Example 1, an AlN buffer layer 22 having a thickness of 100 nm is grown on a SiC substrate 21 as a growth substrate by metal organic vapor phase epitaxy. Subsequently, an i-type GaN electron transit layer 23 having a thickness of 300 nm, an n-type AlGaN electron supply layer 24 having a thickness of 20 nm and an Al composition ratio of 0.2, and an n-type GaN cap layer having a thickness of 5 nm are sequentially grown. Let At this time, a two-dimensional electron gas layer 26 is generated at the interface between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24. Next, an element isolation region (not shown) that reaches the SiC substrate 21 is formed by ion implantation of Ar.

Note that a mixed gas of TMAl, TMGa, and ammonia gas is used as a raw material gas under the growth conditions. For example, when growing a GaN layer, TMGa is 200 sccm, ammonia gas is 4000 sccm, the growth pressure is 100 Torr, and the growth temperature is 1100 ° C. Further, SiH ₄ is used as an n-type impurity source for growing the n-type layer, the Si concentration of the n-type AlGaN electron supply layer 24 is 5 × 10 ¹⁸ cm ^−3, and the Si of the n-type GaN cap layer 25 is used. The concentration is 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 7B, a resist pattern 39 having an opening corresponding to the ohmic recess region 40 is provided, and the exposed portion is etched using Cl ₂ gas using the resist pattern 39 as a mask. 40 is formed.

Next, as shown in FIG. 7C, after removing the resist pattern 39, a SiN film 41 having a thickness of 50 nm is deposited on the entire surface by CVD. Next, as shown in FIG. 8D, a resist pattern 42 is provided so as to completely cover the ohmic recess region 40, and the exposed portion of the SiN film 41 is removed using CF ₄ gas using the resist pattern 42 as a mask. Thus, the gate opening 43 is formed.

Next, as shown in FIG. 8E, after removing the resist pattern 42, an Al ₂ O ₃ film 44 serving as a gate insulating film is provided on the entire surface by using the ALD method. The thickness of the Al ₂ O ₃ film 44, because positive is the the voltage can be applied to g _m by thickly the gate electrode decreases, the thickness is determined by the required specification of the device, also made in consideration of the gate recess depth However, in this case, it is 20 nm.

  Next, as shown in FIG. 8F, a resist pattern 45 that opens the gate formation region is provided, and a 50 nm thick Ni film and a 150 nm thick Au film are sequentially formed by vapor deposition. Then, the Ni / Au film 46 is formed. At this time, the Ni / Au film deposited in the gate formation region becomes the gate electrode 47.

Next, as shown in FIG. 9G, after the Ni / Au film 46 deposited on the resist pattern 45 is lifted off together with the resist pattern 45, a resist pattern 48 that opens the ohmic recess region (40) is provided. Next, the exposed Al ₂ O ₃ film 44 is removed using BCl ₃ using the resist pattern 48 as a mask. At this time, a micro trench may be generated in the SiN film 41.

Subsequently, as shown in FIG. 9H, the exposed SiN film 41 is selectively removed using CF ₄ gas using the resist pattern 48 as it is as a mask. At this time, since AlGaN is not etched by the fluorine-based gas, the etching stops at the surface of the n-type AlGaN electron supply layer 24 exposed at the bottom surface of the ohmic recess region (40).

  Next, as shown in FIG. 10 (i), after removing the resist pattern 48, a new resist pattern 49 is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film 50 is formed by film formation.

  Next, as shown in FIG. 10 (j), the Ti / Al film 50 deposited on the resist pattern 49 is lifted off together with the resist pattern 49. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film 50 is brought into ohmic contact with the n-type AlGaN electron supply layer 24 to form the source electrode 51 and the drain electrode 52. Thus, the basic structure of the AlGaN / GaN MISFET of Example 2 of the present invention is completed. In this case as well, in practice, the source electrode 51 and the drain electrode 52 are alternately arranged with the gate electrode 47 interposed therebetween, and the gate electrode 47 has a comb-like electrode structure.

Even in Example 2 of the present invention, since the SiN film is provided under the Al ₂ O ₃ film serving as the gate insulating film, even if the micro-trench is generated, the SiN film is generated. When the SiN film in which the microtrench is generated is etched with CF ₄ , AlGaN is not etched, so that the shape of the microtrench is not inherited by AlGaN. As a result, an increase in ohmic resistance due to the microtrench can be prevented. In addition, since the gate first process is applied, the threshold voltage shift can be reduced as compared with the transistor manufactured by the ohmic first process. In the second embodiment, since the ohmic recess structure is employed, the resistance can be reduced by the thickness of the n-type AlGaN electron supply layer 24. In Example 2, the n-type GaN cap layer may be omitted.

  Next, the AlGaN / GaN MISFET of Example 3 of the present invention will be described with reference to FIG. 11. However, the basic manufacturing process is the same as that of Example 2 except that the source electrode and the drain electrode are provided. Only the difference in the manufacturing process will be described. FIG. 11 is an explanatory view of the main part of the manufacturing process of the AlGaN / GaN MISFET of Example 3 of the present invention.

As shown in FIG. 11A, the gate electrode 47 is formed in the same process from FIG. 7A to FIG. 8F of the second embodiment. Next, a resist pattern 48 opening the ohmic recess region (40) is provided. At this time, by increasing the size of the resist pattern 48 as compared with Example 1, was etched an _Al 2 _{O 3} film 40 with BCl ₃ using the resist pattern 48 as a mask, _Al 2 O adhering to the side wall at the end _Three films 40 are left.

Subsequently, as shown in FIG. 11B, the exposed SiN film 41 is selectively removed using CF ₄ gas using the resist pattern 48 as it is as a mask. At this time, since AlGaN is not etched by the fluorine-based gas, the etching stops at the bottom surface of the ohmic recess region (40) even if the microtrench is generated.

  Thereafter, as shown in FIG. 11C, after removing the resist pattern 48, a new resist pattern is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film is formed by film formation. Next, the Ti / Al film deposited on the resist pattern is lifted off together with the resist pattern. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film is brought into ohmic contact with the n-type AlGaN electron supply layer 24 to form the source electrode 51 and the drain electrode 52. Thus, the basic structure of the AlGaN / GaN MISFET of Example 3 of the present invention is completed. In this case as well, in practice, the source electrode 51 and the drain electrode 52 are alternately arranged with the gate electrode 47 interposed therebetween, and the gate electrode 47 has a comb-like electrode structure.

  In the third embodiment, since it is not necessary to strictly align the resist pattern 48 with the ohmic recess region (40) dug down first, a manufacturing margin can be increased as compared with the second embodiment. In Example 3, the n-type GaN cap layer may be omitted.

  Next, with reference to FIGS. 12 to 15, a manufacturing process of the AlGaN / GaN MISFET of Example 4 of the present invention will be described. First, as shown in FIG. 12A, similarly to Example 1, an AlN buffer layer 22 having a thickness of 100 nm is grown on a SiC substrate 21 as a growth substrate by metal organic vapor phase epitaxy. Subsequently, an i-type GaN electron transit layer 23 having a thickness of 300 nm, an n-type AlGaN electron supply layer 24 having a thickness of 20 nm and an Al composition ratio of 0.2, and an n-type GaN cap layer having a thickness of 5 nm are sequentially grown. Let At this time, a two-dimensional electron gas layer 26 is generated at the interface between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24. Next, an element isolation region (not shown) that reaches the SiC substrate 21 is formed by ion implantation of Ar.

Note that a mixed gas of TMAl, TMGa, and ammonia gas is used as a raw material gas under the growth conditions. For example, when growing a GaN layer, TMGa is 200 sccm, ammonia gas is 4000 sccm, the growth pressure is 100 Torr, and the growth temperature is 1100 ° C. Further, SiH ₄ is used as an n-type impurity source for growing the n-type layer, the Si concentration of the n-type AlGaN electron supply layer 24 is 5 × 10 ¹⁸ cm ^−3, and the Si of the n-type GaN cap layer 25 is used. The concentration is 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 12B, a SiN film 27 having a thickness of 50 nm is deposited on the entire surface by CVD. Next, as shown in FIG. 12C, a resist pattern 28 having an opening corresponding to the gate opening is provided, and the exposed portion of the SiN film 27 is removed using CF ₄ gas using the resist pattern 28 as a mask. A gate opening 29 is formed.

Next, as shown in FIG. 13D, after the resist pattern 28 is removed, an Al ₂ O ₃ film 30 serving as a gate insulating film is provided on the entire surface by using the ALD method. If the thickness of the Al ₂ O ₃ film 30 is increased, a positive voltage can be applied by the gate electrode, but g _m is lowered. Therefore, the thickness is determined by the required specification of the device, but here it is 20 nm.

  Next, as shown in FIG. 13E, a resist pattern 31 opening the gate formation region is provided, and a 50 nm thick Ni film and a 150 nm thick Au film are sequentially formed by vapor deposition. Then, the Ni / Au film 32 is formed. At this time, the Ni / Au film deposited in the gate formation region becomes the gate electrode 33.

Next, as shown in FIG. 13 (f), after the Ni / Au film 32 deposited on the resist pattern 31 is lifted off together with the resist pattern 31, a resist pattern 34 that opens an ohmic electrode formation region is provided. Next, the exposed Al ₂ O ₃ film 30 is removed using BCl ₃ using the resist pattern 34 as a mask. At this time, a micro trench may be generated in the SiN film 27 in some cases.

Subsequently, as shown in FIG. 14G, the exposed SiN film 27 is selectively removed using CF ₄ gas using the resist pattern 34 as it is as a mask. At this time, since AlGaN or GaN is not etched by the fluorine-based gas, it stops at the surface of the n-type GaN cap layer 25. The steps up to here are the same as in the first embodiment.

Subsequently, as shown in FIG. 14H, the resist pattern 34 is directly used as a mask to etch the n-type GaN cap layer 25 and part of the n-type AlGaN electron supply layer 24 using BCl ₃ gas, thereby forming an ohmic recess. Region 53 is formed.

  Next, as shown in FIG. 15 (i), after removing the resist pattern 34, a new resist pattern 54 is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film 55 is formed by film formation.

  Next, as shown in FIG. 15 (j), the Ti / Al film 55 deposited on the resist pattern 54 is lifted off together with the resist pattern 54. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film is brought into ohmic contact with the n-type AlGaN electron supply layer 24 to form a source electrode 56 and a drain electrode 57. Thus, the basic structure of the AlGaN / GaN MISFET of Example 4 of the present invention is completed. In practice, the source electrode 56 and the drain electrode 57 are alternately arranged with the gate electrode 33 interposed therebetween, and the gate electrode 33 has a comb-like electrode structure.

Also in Example 4 of the present invention, when forming the source electrode and the drain electrode after forming the gate electrode, the SiN film is provided under the Al ₂ O ₃ film serving as the gate insulating film, so that a micro-trench is generated. Is also generated in the SiN film. When the SiN film in which the micro-trench is generated is etched with CF ₄ , the shape of the micro-trench is not inherited by GaN and AlGaN because GaN and AlGaN are not etched. As a result, an increase in ohmic resistance due to the microtrench can be prevented. In addition, since the gate first process is applied, the threshold voltage shift can be reduced as compared with the transistor manufactured by the ohmic first process.

  Also in the fourth embodiment, as in the second embodiment, since the ohmic recess structure is adopted, the resistance can be reduced as much as the n-type AlGaN electron supply layer 24 is thinned. In Example 4, the n-type GaN cap layer may be omitted.

  Next, with reference to FIGS. 16 to 19, the manufacturing process of the AlGaN / GaN MISFET of Example 5 of the present invention will be described. First, as shown in FIG. 16A, similarly to Example 1, an AlN buffer layer 22 having a thickness of 100 nm is grown on a SiC substrate 21 as a growth substrate by metal organic vapor phase epitaxy. Subsequently, an i-type GaN electron transit layer 23 having a thickness of 300 nm, an n-type AlGaN electron supply layer 24 having a thickness of 20 nm and an Al composition ratio of 0.2, and an n-type GaN cap layer having a thickness of 5 nm are sequentially grown. Let At this time, a two-dimensional electron gas layer 26 is generated at the interface between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24. Next, an element isolation region (not shown) that reaches the SiC substrate 21 is formed by ion implantation of Ar.

Note that a mixed gas of TMAl, TMGa, and ammonia gas is used as a raw material gas under the growth conditions. For example, when growing a GaN layer, TMGa is 200 sccm, ammonia gas is 4000 sccm, the growth pressure is 100 Torr, and the growth temperature is 1100 ° C. Further, SiH ₄ is used as an n-type impurity source for growing the n-type layer, the Si concentration of the n-type AlGaN electron supply layer 24 is 5 × 10 ¹⁸ cm ^−3, and the Si of the n-type GaN cap layer 25 is used. The concentration is 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 16B, a resist pattern 58 having an opening corresponding to the gate recess region 59 is provided, and the exposed portion is etched using Cl ₂ gas using the resist pattern 58 as a mask to form the gate recess region 59. Form. Note that, since the etching amount leads to the threshold voltage and high frequency characteristics of the device, the etching depth is determined in accordance with the required specification of the device, but here it is 20 nm.

Next, as shown in FIG. 16C, after the resist pattern 58 is removed, a 50 nm thick SiN film 60 is deposited on the entire surface by CVD. Next, as shown in FIG. 17D, a resist pattern 61 having an opening corresponding to the gate opening is provided, and the exposed portion of the SiN film 60 is removed using CF ₄ gas using the resist pattern 61 as a mask. A gate opening 62 is formed.

Next, as shown in FIG. 17E, after removing the resist pattern 61, an Al ₂ O ₃ film 63 serving as a gate insulating film is provided on the entire surface by using the ALD method. The thickness of the Al ₂ O ₃ film 63, because positive is the the voltage can be applied to g _m by thickly the gate electrode decreases, the thickness is determined by the required specification of the device, also made in consideration of the gate recess depth However, in this case, it is 20 nm.

  Next, as shown in FIG. 17 (f), a resist pattern 64 that opens in the vicinity of the gate recess region (59) is provided, and an Ni film with a thickness of 50 nm and an Au film with a thickness of 150 nm are formed by vapor deposition. A Ni / Au film 65 is formed sequentially. At this time, the Ni / Au film deposited in the vicinity of the gate recess region becomes the gate electrode 66.

Next, as shown in FIG. 18G, after the Ni / Au film 65 deposited on the resist pattern 64 is lifted off together with the resist pattern 64, a resist pattern 67 that opens the source electrode formation region and the drain electrode formation region is provided. . Next, the exposed Al ₂ O ₃ film 63 is removed using BCl ₃ using the resist pattern 67 as a mask. At this time, a micro trench 68 may be generated in the SiN film 60.

Subsequently, as shown in FIG. 18H, the exposed SiN film 60 is selectively removed using CF ₄ gas using the resist pattern 67 as it is as a mask. At this time, since GaN is not etched by the fluorine-based gas, the etching stops at the surface of the n-type GaN cap layer 25 in the source electrode formation region and the drain electrode formation region.

  Next, as shown in FIG. 19 (i), after removing the resist pattern 67, a new resist pattern 69 is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film 70 is formed by film formation.

  Next, as shown in FIG. 19 (j), the Ti / Al film 70 deposited on the resist pattern 69 is lifted off together with the resist pattern 69. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film is brought into ohmic contact with the n-type GaN cap layer 25 to form the source electrode 71 and the drain electrode 72. Thus, the basic structure of the AlGaN / GaN MISFET of Example 5 of the present invention is completed. In this case as well, in practice, the source electrode 71 and the drain electrode 72 are alternately arranged with the gate electrode 66 in between, and the gate electrode 66 has a comb-like electrode structure.

In Example 5 of the present invention, since the Al ₂ O ₃ film is etched in the flat portion, the accuracy of alignment of the ohmic recess region is not required as compared with Example 2, but compared with Example 2. Micro-trench is likely to occur. However, in this case as well, since the SiN film is provided under the Al ₂ O ₃ film serving as the gate insulating film, even if a micro trench is generated, it occurs in the SiN film. When the SiN film in which the micro-trench is generated is etched with CF ₄ , GaN is not etched, so that the shape of the micro-trench is not inherited by GaN. As a result, an increase in ohmic resistance due to the microtrench can be prevented.

Further, since the right under the gate electrode is made shorter the distance between the gate electrode and the channel as recess structure, it is possible to suppress a decrease in mutual conductance g _m. In addition, since the gate first process is applied, the threshold voltage shift can be reduced as compared with the transistor manufactured by the ohmic first process. In Example 5, the n-type GaN cap layer may be omitted.

  Next, with reference to FIGS. 20 to 24, description will be made on a manufacturing process of the AlGaN / GaN MISFET of Example 6 of the present invention. First, as shown in FIG. 20A, similarly to Example 1, an AlN buffer layer 22 having a thickness of 100 nm is grown on a SiC substrate 21 as a growth substrate by metal organic vapor phase epitaxy. Subsequently, an i-type GaN electron transit layer 23 having a thickness of 300 nm, an n-type AlGaN electron supply layer 24 having a thickness of 20 nm and an Al composition ratio of 0.2, and an n-type GaN cap layer having a thickness of 5 nm are sequentially grown. Let At this time, a two-dimensional electron gas layer 26 is generated at the interface between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24. Next, an element isolation region (not shown) that reaches the SiC substrate 21 is formed by ion implantation of Ar.

Note that a mixed gas of TMAl, TMGa, and ammonia gas is used as a raw material gas under the growth conditions. For example, when growing a GaN layer, TMGa is 200 sccm, ammonia gas is 4000 sccm, the growth pressure is 100 Torr, and the growth temperature is 1100 ° C. Further, SiH ₄ is used as an n-type impurity source for growing the n-type layer, the Si concentration of the n-type AlGaN electron supply layer 24 is 5 × 10 ¹⁸ cm ^−3, and the Si of the n-type GaN cap layer 25 is used. The concentration is 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 20B, a resist pattern 58 having an opening corresponding to the gate recess region 59 is provided, and the exposed portion is etched using Cl ₂ gas using the resist pattern 58 as a mask to form the gate recess region 59. Form. Note that, since the etching amount leads to the threshold voltage and high frequency characteristics of the device, the etching depth is determined in accordance with the required specification of the device, but here it is 20 nm.

Next, as shown in FIG. 20C, after removing the resist pattern 58, a 50 nm thick SiN film 60 is deposited on the entire surface by CVD. Next, as shown in FIG. 21D, a resist pattern 61 having an opening corresponding to the gate opening is provided, and the exposed portion of the SiN film 60 is removed using CF ₄ gas using the resist pattern 61 as a mask. Thus, the gate opening 62 is formed.

Next, as shown in FIG. 21E, after the resist pattern 61 is removed, an Al ₂ O ₃ film 63 serving as a gate insulating film is provided on the entire surface by using the ALD method. The thickness of the Al ₂ O ₃ film 63, because positive is the the voltage can be applied to g _m by thickly the gate electrode decreases, the thickness is determined by the required specification of the device, also made in consideration of the gate recess depth However, in this case, it is 20 nm.

  Next, as shown in FIG. 21 (f), a resist pattern 64 opening in the vicinity of the gate recess region (59) is provided, and an Ni film having a thickness of 50 nm and an Au film having a thickness of 150 nm are formed by vapor deposition. A Ni / Au film 65 is formed sequentially. At this time, the Ni / Au film deposited in the vicinity of the gate recess region becomes the gate electrode 66.

Next, as shown in FIG. 22G, after the Ni / Au film 65 deposited on the resist pattern 64 is lifted off together with the resist pattern 64, a resist pattern 67 that opens the source electrode formation region and the drain electrode formation region is provided. . Next, the exposed Al ₂ O ₃ film 63 is removed using BCl ₃ using the resist pattern 67 as a mask. At this time, a micro trench 68 may be generated in the SiN film 60.

Subsequently, as shown in FIG. 22H, the exposed SiN film 60 is selectively removed using CF ₄ gas using the resist pattern 67 as it is as a mask. At this time, since GaN is not etched by the fluorine-based gas, the etching stops at the surface of the n-type GaN cap layer 25 in the source electrode formation region and the drain electrode formation region. Subsequently, as shown in FIG. 22 (i), the resist pattern 67 is used as it is as a mask, and the n-type GaN cap layer 25 and a part of the n-type AlGaN electron supply layer 24 are etched using BCl ₃ gas to form an ohmic recess. Region 74 is formed.

  Next, as shown in FIG. 23 (j), after removing the resist pattern 67, a new resist pattern 75 is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film 76 is formed by film formation.

  Next, as shown in FIG. 23 (k), the Ti / Al film 76 deposited on the resist pattern 75 is lifted off together with the resist pattern 75. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film is brought into ohmic contact with the n-type AlGaN electron supply layer 24 to form the source electrode 77 and the drain electrode 78. Thus, the basic structure of the AlGaN / GaN MISFET of Example 6 of the present invention is completed. In this case as well, in practice, the source electrode 77 and the drain electrode 78 are alternately arranged with the gate electrode 66 interposed therebetween, and the gate electrode 66 has a comb-like electrode structure.

Also in Example 6 of the present invention, since the Al ₂ O ₃ film is etched in the flat portion, the accuracy of the alignment of the ohmic recess region is not required as compared with Example 1, but compared with Example 1. Micro-trench is likely to occur. However, in this case as well, since the SiN film is provided under the Al ₂ O ₃ film serving as the gate insulating film, even if a micro trench is generated, it occurs in the SiN film. When the SiN film in which the micro-trench is generated is etched with CF ₄ , GaN is not etched, so that the shape of the micro-trench is not inherited by GaN. As a result, an increase in ohmic resistance due to the microtrench can be prevented. In addition, since the gate first process is applied, the threshold voltage shift can be reduced as compared with the transistor manufactured by the ohmic first process.

Also, in Example 6, as in Example 2, the ohmic recess structure is adopted, so that the resistance can be reduced by the thickness of the n-type AlGaN electron supply layer 24 as compared with Example 5. . Further, since the right under the gate electrode is made shorter the distance between the gate electrode and the channel as recess structure, it is possible to suppress a decrease in mutual conductance g _m. In Example 6, the n-type GaN cap layer may be omitted.

  Next, with reference to FIGS. 24 to 27, a manufacturing process of the AlGaN / GaN MISFET of Example 7 of the present invention will be described. First, as shown in FIG. 24A, similarly to Example 1, an AlN buffer layer 22 having a thickness of 100 nm is grown on a SiC substrate 21 as a growth substrate by metal organic vapor phase epitaxy. Subsequently, an i-type GaN electron transit layer 23 having a thickness of 300 nm, an n-type AlGaN electron supply layer 24 having a thickness of 20 nm and an Al composition ratio of 0.2, and an n-type GaN cap layer having a thickness of 5 nm are sequentially grown. Let At this time, a two-dimensional electron gas layer 26 is generated at the interface between the i-type GaN electron transit layer 23 and the n-type AlGaN electron supply layer 24. Next, an element isolation region (not shown) that reaches the SiC substrate 21 is formed by ion implantation of Ar.

Note that a mixed gas of TMAl, TMGa, and ammonia gas is used as a raw material gas under the growth conditions. For example, when growing a GaN layer, TMGa is 200 sccm, ammonia gas is 4000 sccm, the growth pressure is 100 Torr, and the growth temperature is 1100 ° C. Further, SiH ₄ is used as an n-type impurity source for growing the n-type layer, the Si concentration of the n-type AlGaN electron supply layer 24 is 5 × 10 ¹⁸ cm ^−3, and the Si of the n-type GaN cap layer 25 is used. The concentration is 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 24B, a resist pattern 39 having openings for opening the source electrode formation region and the drain electrode formation region is provided, and the exposed portion is etched using Cl ₂ gas using the resist pattern 39 as a mask. Thus, the ohmic recess region 40 is formed.

Next, as shown in FIG. 24C, after removing the resist pattern 39, a new resist pattern 79 having an opening corresponding to the gate recess region 80 is provided. Next, the exposed portion is etched using Cl ₂ gas using the resist pattern 79 as a mask to form a gate recess region 80. Note that, since the etching amount leads to the threshold voltage and high frequency characteristics of the device, the etching depth is determined in accordance with the required specification of the device, but here it is 20 nm.

Next, as shown in FIG. 25D, after removing the resist pattern 79, a SiN film 81 having a thickness of 50 nm is deposited on the entire surface by CVD. Next, as shown in FIG. 25E, a resist pattern 82 is provided so as to completely cover the ohmic recess region 40, and the exposed portion of the SiN film 81 is removed using CF ₄ gas using the resist pattern 82 as a mask. A gate opening 83 is formed.

Next, as shown in FIG. 25F, after the resist pattern 82 is removed, an Al ₂ O ₃ film 84 serving as a gate insulating film is provided on the entire surface by using the ALD method. The thickness of the Al ₂ O ₃ film 84, because positive is the the voltage can be applied to g _m by thickly the gate electrode decreases, the thickness is determined by the required specification of the device, also made in consideration of the gate recess depth However, in this case, it is 20 nm.

  Next, as shown in FIG. 26 (g), a resist pattern 85 opening in the vicinity of the gate recess region (80) is provided, and an Ni film having a thickness of 50 nm and an Au film having a thickness of 150 nm are formed by vapor deposition. A Ni / Au film 86 is formed by sequentially forming films. At this time, the Ni / Au film deposited in the vicinity of the gate recess region becomes the gate electrode 87.

Next, as shown in FIG. 26H, after the Ni / Au film 86 deposited on the resist pattern 85 is lifted off together with the resist pattern 85, a resist pattern 88 that opens the ohmic recess region 40 is provided. Next, the exposed Al ₂ O ₃ film 84 is removed using BCl ₃ using the resist pattern 88 as a mask.

Subsequently, as shown in FIG. 26I, the exposed SiN film 81 is selectively removed using CF ₄ gas using the resist pattern 88 as it is as a mask. At this time, since AlGaN is not etched with the fluorine-based gas, the etching stops at the bottom surface of the ohmic recess region 40. Subsequently, as shown in FIG. 27J, the ohmic recess region 40 is dug using Cl ₂ gas using the resist pattern 88 as a mask.

  Next, as shown in FIG. 27 (k), after removing the resist pattern 88, a new resist pattern 89 is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film 90 is formed by film formation.

  Next, as shown in FIG. 27L, the Ti / Al film 90 deposited on the resist pattern 89 is lifted off together with the resist pattern 89. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film is brought into ohmic contact with the n-type AlGaN electron supply layer 24 to form the source electrode 91 and the drain electrode 92. Thus, the basic structure of the AlGaN / GaN MISFET of Example 7 of the present invention is completed. In practice, the source electrode 91 and the drain electrode 92 are alternately arranged with the gate electrode 87 interposed therebetween, and the gate electrode 87 has a comb-like electrode structure.

Also in Example 7 of the present invention, when the source electrode and the drain electrode are formed after the gate electrode is formed, since the SiN film is provided under the Al ₂ O ₃ film serving as the gate insulating film, a micro trench is generated. Is also generated in the SiN film. When the SiN film in which the microtrench is generated is etched with CF ₄ , AlGaN is not etched, so that the shape of the microtrench is not inherited by AlGaN. As a result, an increase in ohmic resistance due to the microtrench can be prevented. In addition, since the gate first process is applied, the threshold voltage shift can be reduced as compared with the transistor manufactured by the ohmic first process.

Also in Example 7, since the ohmic recess structure is employed, the resistance can be reduced by the thickness of the n-type AlGaN electron supply layer 24. Further, since the right under the gate electrode is made shorter the distance between the gate electrode and the channel as recess structure, it is possible to suppress a decrease in mutual conductance g _m. In Example 7, the n-type GaN cap layer may be omitted.

  Next, an AlGaN / GaN MISFET according to an eighth embodiment of the present invention will be described with reference to FIG. 28. However, the basic manufacturing process is the same as that of the seventh embodiment except that the positions where the source electrode and the drain electrode are provided are different. Only the difference in the manufacturing process will be described. FIG. 28 is an explanatory view of the essential part of the manufacturing process of the AlGaN / GaN MISFET of Example 8 of the present invention.

As shown in FIG. 28A, the gate electrode 87 is formed in the same process from FIGS. 24A to 26G of the seventh embodiment. Next, a resist pattern 88 opening the ohmic recess region 40 is provided. At this time, by increasing the size of the resist pattern 88 as compared to Example 7, an _Al 2 _{O 3} film 84 is etched using BCl ₃ using the resist pattern 88 as a mask, _Al 2 O adhering to the side wall at the end _{The three} films 84 are left.

Subsequently, as shown in FIG. 28B, the exposed SiN film 81 is selectively removed using CF ₄ gas using the resist pattern 88 as it is as a mask. At this time, since AlGaN is not etched by the fluorine-based gas, the etching stops at the bottom surface of the ohmic recess region 40 even if a micro trench is generated.

  Thereafter, as shown in FIG. 28C, after removing the resist pattern 88, a new resist pattern is provided, and a Ti film having a thickness of 20 nm and an Al film having a thickness of 200 nm are sequentially formed by vapor deposition. A Ti / Al film is formed by film formation. Next, the Ti / Al film deposited on the resist pattern is lifted off together with the resist pattern. Next, heat treatment is performed at about 550 ° C. in a nitrogen atmosphere, and the Ti / Al film is brought into ohmic contact with the n-type AlGaN electron supply layer 24 to form the source electrode 91 and the drain electrode 92. Thus, the basic structure of the AlGaN / GaN MISFET of Example 8 of the present invention is completed. In this case as well, in practice, the source electrode 91 and the drain electrode 92 are alternately arranged with the gate electrode 87 interposed therebetween, and the gate electrode 87 has a comb-like electrode structure. In the eighth embodiment, since it is not necessary to strictly align the resist pattern 88 with the ohmic recess region, a manufacturing margin can be increased as compared with the seventh embodiment.

Here, the following additional notes are attached to the embodiment of the present invention including Examples 1 to 8.
(Appendix 1) A nitride semiconductor carrier travel layer is formed on a substrate, a nitride semiconductor carrier supply layer is formed on the carrier travel layer, and a Si-containing first insulation is formed on the carrier supply layer. Forming a film, removing a part of the first insulating film, and covering the first insulating film on the part of the first insulating film; In a portion covering a part of the second insulating film where the first insulating film in which the two-dimensional electron gas layer is present is removed from the second insulating film at a position away from the first insulating film, A gate electrode is formed, and a first opening and a second opening are formed in the first insulating film and the second insulating film, spaced apart from the gate electrode and sandwiching the gate electrode. Forming a source electrode and a drain electrode in the first opening and the second opening; In the formation of the first opening and the second opening, the second insulating film is etched with the first gas, and the second gas has a lower nitride semiconductor etching rate than the first gas. A method of manufacturing a compound semiconductor device, comprising: etching the first insulating film.
(Supplementary note 2) The method of manufacturing a compound semiconductor device according to supplementary note 1, wherein a gate recess region is formed in the carrier supply layer before the first insulating film is formed.
(Supplementary note 3) The method for manufacturing a compound semiconductor device according to supplementary note 1 or 2, wherein a recess region is formed in a region where the source electrode and the drain electrode are formed before the gate electrode is formed.
(Additional remark 4) After forming the said gate electrode, a recess area | region is formed in the area | region which forms the said source electrode and drain electrode, The manufacturing method of the compound semiconductor device of Additional remark 1 or Additional remark 2 characterized by the above-mentioned.
(Supplementary note 5) The method of manufacturing a compound semiconductor device according to any one of supplementary notes 1 to 4, wherein a dielectric constant of the second insulating film is higher than a dielectric constant of the first insulating film. .
(Supplementary note 6) The compound semiconductor device according to any one of supplementary notes 1 to 5, wherein the first insulating film is formed of any one of silicon nitride, silicon oxide, and silicon oxynitride. Production method.
(Supplementary note 7) The method of manufacturing a compound semiconductor device according to any one of supplementary notes 1 to 6, wherein the second insulating film is formed of aluminum oxide or hafnium oxide.
(Supplementary note 8) The method of manufacturing a compound semiconductor device according to any one of supplementary notes 1 to 7, wherein the first gas is a gas containing chlorine.
(Supplementary note 9) The method for manufacturing a compound semiconductor device according to any one of supplementary notes 1 to 8, wherein the second gas is a gas containing fluorine.
(Supplementary note 10) The method for manufacturing a compound semiconductor device according to any one of supplementary notes 1 to 9, wherein the substrate is any one of a SiC substrate, a sapphire substrate, a GaN substrate, and a Si substrate.
(Additional remark 11) The manufacturing method of the compound semiconductor device of Additional remark 10 characterized by the said carrier running layer being an i-type GaN layer, and the said carrier supply layer being an n-type AlGaN layer.
(Supplementary Note 12) A substrate, a nitride semiconductor carrier travel layer formed on the substrate, a nitride semiconductor carrier supply layer formed on the carrier travel layer, and formed on the carrier supply layer A second insulating film formed, a gate electrode formed in a region where a two-dimensional electron gas layer exists via the second insulating film, and a source electrode and a drain formed at positions sandwiching the gate electrode An electrode and Si formed on the carrier supply layer, separated from the gate electrode, and in contact with the source electrode and the drain electrode on the gate electrode side of the source electrode and the gate electrode side of the drain electrode; A compound semiconductor device comprising: a first insulating film contained therein, wherein the second insulating film extends over the first insulating film.
(Supplementary note 13) The compound semiconductor device according to supplementary note 12, wherein the gate electrode is provided with a gate recess region and its vicinity.
(Supplementary note 14) The compound semiconductor device according to supplementary note 12 or supplementary note 13, wherein a dielectric constant of the second insulating film is higher than a dielectric constant of the first insulating film.

DESCRIPTION OF SYMBOLS 11 Substrate 12 Nitride carrier travel layer 13 Nitride carrier supply layer 14 Cap layer 15 Two-dimensional carrier gas layer 16 First insulating film 17 Second insulating film 18 Gate electrode 19 Resist pattern 20 Electrode forming region 21, 101 SiC substrate 22, 102 AlN buffer layer 23, 103 i-type GaN electron transit layer 24, 104 n-type AlGaN electron supply layer 25, 105 n-type GaN cap layer 26, 106 Two-dimensional electron gas layers 27, 41, 60, 81 SiN film 28 , 42, 61, 82 Resist patterns 29, 43, 62, 83 Gate openings 30, 44, 63, 84, 111 Al ₂ O ₃ films 31, 45, 64, 85, 112 Resist patterns 32, 46, 65, 86 113 Ni / Au films 33, 47, 66, 87, 114 Gate electrodes 34, 48, 67, 88 115 resist pattern 35, 49, 54, 69, 75, 89, 116 resist pattern 36, 50, 55, 70, 76, 90, 117 Ti / Al film 37, 51, 56, 71, 77, 91, 118 source electrode 38, 52, 57, 72, 78, 92, 119 Drain electrode 39, 107 Resist pattern 40, 53, 74, 108 Ohmic recess region 58, 79, 109 Resist pattern 59, 80, 110 Gate recess region 68, 120 Micro trench

Claims (7)

A nitride semiconductor carrier travel layer is formed on the substrate,
Forming a nitride semiconductor carrier supply layer on the carrier running layer;
Forming a first insulating film containing Si on the carrier supply layer;
Removing a partial region of the first insulating film;
Forming a second insulating film on the first insulating film to cover a part of the region from which the first insulating film has been removed;
A gate electrode is formed in a portion covering the first part of the region where the insulating film is removed to the two-dimensional electron gas layer is present of the second insulating film at a position apart from the first insulating film ,
Forming a first opening and a second opening in the first insulating film and the second insulating film, spaced apart from the gate electrode and sandwiching the gate electrode;
Forming a source electrode and a drain electrode in the first opening and the second opening;
In the formation of the first opening and the second opening, the second insulating film is etched with a first gas, and a second etching rate of the nitride semiconductor is lower than that of the first gas. A method of manufacturing a compound semiconductor device, comprising etching the first insulating film with a gas. The method of manufacturing a compound semiconductor device according to claim 1, wherein a dielectric constant of the second insulating film is higher than a dielectric constant of the first insulating film. 3. The method of manufacturing a compound semiconductor device according to claim 1, wherein the first insulating film is formed of any one of silicon nitride, silicon oxide, and silicon oxynitride. Said second insulating film is an aluminum oxide, a manufacturing method of a compound semiconductor device according to any one of claims 1 to 3, characterized in that it is formed by any one of hafnium oxide. The first gas is characterized in that it is a gas containing chlorine, the production method of a compound semiconductor device according to any one of claims 1 to 4. The second gas is characterized in that it is a gas containing fluorine, a manufacturing method of a compound semiconductor device according to any one of claims 1 to 5. A substrate,
A nitride semiconductor carrier travel layer formed on the substrate;
A nitride semiconductor carrier supply layer formed on the carrier running layer;
A second insulating film formed on the carrier supply layer;
A gate electrode formed in a region where a two-dimensional electron gas layer exists via the second insulating film;
A source electrode and a drain electrode formed at positions sandwiching the gate electrode;
A Si-containing first electrode formed on the carrier supply layer, separated from the gate electrode, and in contact with the source electrode and the drain electrode on the gate electrode side of the source electrode and the gate electrode side of the drain electrode. 1 insulating film,
The compound semiconductor device, wherein the second insulating film extends to the top of the first insulating film.

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