JP6623745B2 - Control method of electronic circuit and oscillator - Google Patents

Description

  The present disclosure relates to a control method for an electronic circuit and an oscillator.

  Since a digital circuit of an LSI (Large Scale Integrated Circuit) operates in synchronization with a clock signal, when a circuit scale is large, a large current is consumed at a clock transition timing, and power supply noise called IR drop occurs in a power supply voltage. appear. Due to the IR drop, the power supply voltage shows a voltage change in a frequency band determined by the impedance of the power supply wiring and the stabilizing capacitance. Generally, this variation has a frequency band on the order of 50 MHz to 150 MHz.

  When the power supply voltage decreases, the change speed of a signal propagating through a signal path in an LSI decreases, and data may not be transferred properly on a critical path or the like having a small signal transmission timing margin. In order to avoid such timing errors, some LSIs such as processors control the operating frequency adaptively according to the voltage drop. More specifically, the voltage is measured, an increase in the delay of the data path due to the voltage drop is estimated, and the clock cycle is lengthened so as to offset the increase in the delay.

  As a method of changing a clock cycle, a method of switching a frequency division ratio of a PLL (Phase Locked Loop) circuit is generally known. In this method, the influence of the voltage drop on the timing is measured, the frequency division ratio of the PLL circuit is changed based on the measured value, and the adaptive frequency control is realized by lowering the oscillation frequency of the PLL circuit.

  In the above adaptive frequency control, since the oscillation frequency is changed using the control system of the PLL circuit, it takes a very long time until the oscillation frequency of the PLL circuit reaches the target value after switching the frequency division ratio. Specifically, a time of, for example, 200 cycles or more in terms of the number of cycles of the reference clock is required. If the voltage drop is a slow change (change of about several tens of kHz in frequency), even with the above control, the change in the clock frequency can sufficiently follow the voltage drop.

  However, the IR drop that occurs when, for example, the operation rate increases in the processor is a high-speed change having a frequency band of about 50 MHz to 150 MHz as described above. Therefore, in the adaptive frequency control in which the frequency division ratio is changed in the PLL circuit, the change in the clock frequency cannot keep up with the speed of the voltage drop, and the timing error cannot be avoided.

JP-A-11-288325 JP-A-2002-202829

Dong Jiao, Bongjin Kim, and Chris H. Kim, "Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation," The Journal of Solid-state Circuits, VOL. 47, NO. 10, October 2012, pp 2505-2012 MS Floyd, et al., "Runtime power reduction capability of the IBM POWER7 + chip," IBM J. RES. & DEV. VOL. 57, NO. 6, PAPER 2, November / December 2013, pp 2: 1-2: 17

  In view of the above, an electronic circuit capable of changing the oscillation frequency at high speed following power supply noise is desired.

The electronic circuit includes an oscillator that generates an oscillation signal having a cycle corresponding to the input signal, a voltage detector that outputs a detection signal corresponding to a power supply voltage, and a frequency division ratio corresponding to a signal obtained by time-averaging the detection signal. A frequency divider for dividing the oscillation signal to generate a frequency-divided signal; a sum of a first signal corresponding to a phase difference between the frequency-divided signal and a reference signal and a second signal corresponding to the detection signal And an adder that supplies a signal corresponding to the sum to the oscillator as the input signal.

  According to at least one embodiment, in an electronic circuit, an oscillation frequency can be changed at a high speed following power supply noise.

FIG. 9 is a diagram illustrating an example of an embodiment of an electronic circuit that can change an oscillation frequency according to power supply noise. FIG. 2 is a diagram illustrating an example of an operation of the PLL circuit illustrated in FIG. 1 with respect to a rapid change in a power supply voltage VDD. FIG. 2 is a diagram illustrating an example of an operation of the PLL circuit illustrated in FIG. 1 with respect to a continuous fluctuation of a power supply voltage VDD. FIG. 2 is a diagram for explaining an operation of the PLL circuit shown in FIG. 1 with respect to a continuous fluctuation of a power supply voltage VDD. FIG. 2 is a diagram for explaining an operation of the PLL circuit shown in FIG. 1 with respect to a continuous fluctuation of a power supply voltage VDD. FIG. 9 is a diagram illustrating an example of an embodiment of an electronic circuit capable of changing an oscillation frequency following a power supply noise based on a circuit delay measurement. FIG. 7 is a diagram showing a modification of the electronic circuit shown in FIG. 6. FIG. 3 is a diagram illustrating an example of a configuration of a delay monitor circuit. FIG. 3 is a diagram illustrating an example of a configuration of a variable delay line. FIG. 4 is a diagram illustrating a code conversion unit that performs code conversion for a variable delay line. FIG. 3 is a diagram illustrating an example of a configuration of a mask circuit. 4 is a flowchart illustrating an example of a setting operation by a control circuit. FIG. 9 is a diagram illustrating another example of an electronic circuit according to an embodiment in which the oscillation frequency can be changed according to power supply noise based on a circuit delay measurement. FIG. 14 is a diagram illustrating a modification of the electronic circuit illustrated in FIG. 13. FIG. 3 is a diagram illustrating an example of a configuration of a critical path monitor & delay monitor circuit. FIG. 3 is a diagram illustrating an example of a configuration of a pseudo critical path circuit. FIG. 9 is a diagram illustrating another example of the configuration of the pseudo critical path circuit. FIG. 9 is a diagram illustrating another example of the configuration of the pseudo critical path circuit. FIG. 9 is a diagram illustrating another example of the configuration of the pseudo critical path circuit. 4 is a flowchart illustrating an example of a setting operation by a control circuit. FIG. 4 is a timing chart illustrating an example of a setting operation by a control circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of an embodiment of an electronic circuit capable of changing an oscillation frequency according to power supply noise. The electronic circuit shown in FIG. 1 includes a PLL circuit 10, an AD converter 11, an averaging unit 12, a code conversion unit 13, and a logic circuit 14. The PLL circuit 10 includes a digitally controlled oscillator (DCO) 20, a frequency divider 21, a phase comparator 22, a loop filter 23, a normalizing unit 24, and an adder 25. The logic circuit 14 includes a data path 30, and the data path 30 includes flip-flops 31 and 32 and a circuit element group 33. Oscillation signals (clock signals) generated by the PLL circuit 10 are applied to clock input terminals of the flip-flops 31 and 32.

  In FIG. 1, the boundary between each circuit or function block indicated by each box and another circuit or function block basically indicates a functional boundary, such as separation of physical positions, electrical It does not always correspond to signal separation, control logical separation, and the like. Each circuit or function block may be a single hardware module physically separated to some extent from another block, or one function in a hardware module physically integrated with another block. May be indicated.

  The power supply voltage VDD is supplied to the logic circuit 14, and each circuit element in the logic circuit 14 is driven using the power supply voltage VDD as a power supply. The power supply voltage VDD is further applied to the AD converter 11. The AD converter 11 functions as a voltage detector and generates a detection signal Q corresponding to the applied power supply voltage. The detection signal Q may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1. The detection signal Q output from the AD converter 11 is supplied to the averaging unit 12 and also to the adder 25 of the PLL circuit 10.

The averaging unit 12 takes the time average of the detection signal Q and generates an average signal Q _avr . When the detection signal Q is a digital code, the average value signal Q _avr is generated by adding the value of the detection signal Q over a predetermined number of clock cycles of 2 or more and dividing the addition result by the predetermined number. May be. The average signal Q _avr generated by the averaging unit 12 is supplied to the code conversion unit 13.

The code conversion unit 13 generates a frequency division ratio setting code according to the average signal _Qavr . The frequency division ratio setting code generated by the code conversion unit 13 is supplied to the frequency divider 21 of the PLL circuit 10 as a control signal for setting the frequency division ratio.

  The digital control oscillator 20 of the PLL circuit 10 generates an oscillation signal having a cycle (or frequency) according to an input signal to the digital control oscillator 20. The oscillation signal oscillated by the digitally controlled oscillator 20 is supplied to a frequency divider 21 which oscillates at a frequency division rate corresponding to the frequency division rate setting code (that is, a frequency division rate corresponding to the detection signal Q). The signal is divided to generate a divided signal.

  The phase comparator 22 generates a phase detection signal corresponding to the phase difference between the frequency-divided signal output from the frequency divider 21 and the reference signal REF. When the phase of the divided signal is later than the phase of the reference signal REF, the phase detection signal becomes, for example, a negative value (or a value smaller than a predetermined reference value), and when the phase of the divided signal is earlier than the phase of the reference signal REF. May be, for example, a plus value (or a value larger than a predetermined reference value). The phase detection signal may have a value (or a difference from a predetermined reference value) corresponding to a difference between the phase of the frequency-divided signal and the phase of the reference signal REF. The phase detection signal may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1.

  The loop filter 23 is a low-pass filter that passes a low-frequency component of the phase detection signal output from the phase comparator 22 and blocks or suppresses a high-frequency component, and may be implemented by, for example, a digital filter. The loop filter 23 performs low-pass filtering on the phase detection signal to generate phase difference information indicating a tendency of the phase difference over a relatively long period of time without being affected by temporary small fluctuations. The information is supplied to the normalization unit 24. The phase difference information may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1.

  The normalizing unit 24 generates a phase difference code having an appropriate value as an input signal of the digitally controlled oscillator 20 by multiplying the supplied phase difference information by a predetermined coefficient. In the digitally controlled oscillator 20, the magnitude (sensitivity) of the change of the oscillation frequency with respect to one bit change of the LSB (Least Significant Bit) of the input signal differs depending on the oscillation frequency. By multiplying the phase difference information by a coefficient that cancels out the difference in sensitivity according to the oscillation frequency of the digitally controlled oscillator 20 by the normalization unit 24, it is possible to eliminate the frequency-dependent influence of the sensitivity of the digitally controlled oscillator 20. it can. If the influence of the frequency dependence of the sensitivity of the digitally controlled oscillator 20 can be neglected, the normalizing unit 24 need not be provided. The phase difference code generated by the normalization unit 24 is supplied to the adder 25. The phase difference code may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1.

  The adder 25 calculates the sum of the phase difference code corresponding to the phase difference between the frequency-divided signal and the reference signal REF and the signal corresponding to the detection signal Q output from the AD converter 11, and calculates the sum. Is supplied to the digitally controlled oscillator 20 as an input signal. The signal to be added to the phase difference code by the adder 25 may be the detection signal Q itself, which is the output of the AD converter 11, or the detection signal Q may be appropriately sized as an input to the digitally controlled oscillator 20. The signal may be normalized by multiplying by a constant.

  Alternatively, for example, if the design is such that the value of the detection signal Q increases in response to a decrease in the power supply voltage VDD, the detection signal Q equal to or less than the predetermined value is discarded by cutting off the detection signal Q equal to or less than the predetermined value. A signal adjusted so that the value becomes the predetermined value may be used. By using the signal adjusted in this way, for example, when the power supply voltage VDD becomes higher than a desired value, a control operation that does not execute the frequency adjustment operation by the PLL circuit 10 can be realized. That is, the frequency may be adjusted for a decrease in the power supply voltage VDD from a desired level, but the frequency adjustment may not be performed for a rise in the power supply voltage VDD to a desired level or higher.

  In the example illustrated in FIG. 1, the signal added by the adder 25 to the phase difference code output from the normalization unit 24 is the detection signal Q itself output from the AD converter 11. However, by providing a lower limit value to the output of the AD converter 11, for example, as described above, the frequency is adjusted with respect to a decrease in the power supply voltage VDD from a desired level, but is adjusted to a desired level or more. The frequency adjustment may not be performed for the rise of the power supply voltage VDD.

  The input signal of the digitally controlled oscillator 20 may be, for example, a digital code represented by a plurality of bits in which each bit takes a value of 0 or 1. The digitally controlled oscillator 20 may be, for example, an LC oscillator. A plurality of variable capacitance elements such as varactors may be connected in parallel to form a parallel capacitance, and a corresponding bit of the input signal may be applied to each of the control terminals of the plurality of variable capacitance elements. The magnitude of the parallel capacitance may be controlled by setting each bit of the input signal to 0 or 1, and the digital control oscillator 20 may oscillate at a cycle (or frequency) according to the controlled parallel capacitance.

  The oscillation signal oscillated by the digital control oscillator 20 of the PLL circuit 10 is supplied to the logic circuit 14 as a clock signal. As described above, the logic circuit 14 is driven by the power supply voltage VDD. The clock signal is applied to a clock terminal of a flip-flop in the logic circuit 14.

  In the electronic circuit shown in FIG. 1, when the value of the input signal of the digitally controlled oscillator 20 increases, the length of the period of the oscillation signal of the digitally controlled oscillator 20 may increase. Conversely, when the value of the input signal of the digitally controlled oscillator 20 decreases, the length of the cycle of the oscillation signal of the digitally controlled oscillator 20 may decrease. In this case, when the power supply voltage VDD decreases, the value of the detection signal Q that is the output of the AD converter 11 may increase. If the relationship between the increase and decrease in the value of the input signal of the digitally controlled oscillator 20 and the increase and decrease in the cycle length of the oscillation signal of the digitally controlled oscillator 20 is opposite to the above, the AD is responded to the fall of the power supply voltage VDD. The value of the detection signal Q output from the converter 11 may be small.

The value of the detection signal Q increases in response to the fall of the power supply voltage VDD, and when this state continues for a long time, the value of the average signal Q _avr output from the averaging unit 12 also increases. The code conversion unit 13 changes the frequency division ratio setting code so that the frequency division ratio decreases when the value of the average signal _Qavr increases. As a result, the oscillation frequency of the PLL circuit 10 becomes lower, and the oscillation cycle of the oscillation signal becomes longer. As described above, when the power supply voltage VDD is lowered as determined by averaging over a long period of time, the value of the average value signal Q _avr output from the averaging unit 12 increases, and the clock signal Becomes longer.

  In the logic circuit 14 driven by the power supply voltage VDD, when the power supply voltage VDD decreases, the driving force for changing the output signal of each circuit element decreases, and the signal propagation speed between the circuit elements, and thus the signal propagation speed between the flip-flops. Decreases. For example, in the logic circuit 14 shown in FIG. 1, for example, among the data paths included in the logic circuit 14, the data path 30 is a critical path having a small timing margin. In the data path 30, data output from the flip-flop 31 propagates through the circuit element group 33 and is taken into the flip-flop 32. The data capture by the flip-flop 32 is performed in synchronization with a clock signal (oscillation signal) generated by the PLL circuit 10. If the time required for signal propagation between the flip-flops 31 and 32 of the data path 30 increases due to a decrease in the power supply voltage VDD, the reception-side flip-flop 32 may fail to capture data.

  As described above, when the power supply voltage VDD is reduced based on an average over a long period of time, the frequency of the clock signal oscillated by the PLL circuit 10 is increased by setting the frequency division ratio small. As a result, it is possible to avoid data transfer failure in a data path such as the data path 30 included in the logic circuit 14.

  When the logic circuit 14 operates in synchronization with the clock signal of the PLL circuit 10, a current is consumed at a clock transition timing, and an IR drop may occur in the power supply voltage VDD. A remarkable IR drop does not occur when the normal logic circuit 14 operates, but the IR drop that occurs when the logic circuit 14 is, for example, a processor and a transition occurs in the operation mode thereof is not negligible. Become. In this case, as described above, the power supply voltage VDD having a frequency band of about 50 MHz to 150 MHz fluctuates sharply.

  When such a rapid fluctuation of the power supply voltage VDD occurs, the cycle of the clock signal oscillated by the digitally controlled oscillator 20 can be obtained simply by changing the frequency division ratio of the frequency divider 21 by the code conversion unit 13 as described above. Does not change fast enough. In the first place, the instantaneous fluctuation of the power supply voltage VDD is ignored by the averaging operation by the averaging unit 12, but the averaging unit 12 is not provided, and the frequency divider 21 is changed according to the instantaneous fluctuation of the power supply voltage VDD. Even if the division ratio is changed, the cycle of the clock signal does not change at a sufficient speed. This is because, as described above, when changing the oscillation frequency using the control system of the PLL circuit, it takes a long time until the oscillation frequency of the PLL circuit reaches the target value after switching the frequency division ratio. It is.

  In the electronic circuit shown in FIG. 1, the detection signal Q, which is the output signal of the AD converter 11, is added to the input signal to the digitally controlled oscillator 20 via the adder 25, so that the power supply voltage VDD can be rapidly changed. On the other hand, the oscillation frequency of the PLL circuit 10 can be changed instantaneously. That is, in the PLL circuit 10, since the digital code corresponding to the detection signal Q is added to the digital code input to the digital control oscillator 20, when the value of the detection signal Q increases due to the decrease in the power supply voltage VDD, the digital The input value to the control oscillator 20 increases. The digitally controlled oscillator 20 is designed to oscillate at an oscillation cycle corresponding to an input value. As the input value increases, the length of the oscillation cycle increases. Since the control of the oscillation cycle is realized by directly adjusting the input of the digitally controlled oscillator 20, the oscillation cycle fluctuates quickly in response to the fluctuation of the power supply voltage VDD. That is, it is possible to realize a change in the oscillation cycle that follows the change in the power supply voltage VDD.

  FIG. 2 is a diagram illustrating an example of the operation of the PLL circuit illustrated in FIG. 1 with respect to a rapid change in the power supply voltage VDD. 2A shows the voltage value of the power supply voltage VDD. (B) shows the oscillation cycle of the PLL circuit 10. (C) shows the average value of the oscillation cycle of the PLL circuit 10. (D) shows a timing margin of the data path 30 which is a critical path of the logic circuit 14. The horizontal axis in each waveform diagram is time. Voltage V1 is a desired voltage level of power supply voltage VDD supplied to the electronic circuit shown in FIG. The oscillation cycle T1 is a desired oscillation cycle of the PLL circuit 10 corresponding to the power supply voltage VDD.

  First, as shown in FIG. 2A, a fluctuation shown by a waveform 41 occurs in the power supply voltage VDD due to, for example, an IR drop. This voltage fluctuation is a high-speed change having a frequency band of about 50 MHz to 150 MHz. The power supply voltage VDD drops from the desired voltage V1 due to the IR drop, and then the voltage is recovered by the current supply through the stabilizing capacitor or the power supply wiring. Voltage VDD is temporarily higher than desired voltage V1.

  The digital code input to the digitally controlled oscillator 20 increases in response to the voltage drop of the waveform 41, and the oscillation cycle of the digitally controlled oscillator 20 changes as shown by the waveform 42 in FIG. The average value of the oscillation cycle in consideration of the averaging or integration function of the PLL control loop (phase locked loop) by the loop filter 23 changes as shown by a waveform 43 in FIG.

  The contribution of the fluctuation of the power supply voltage VDD in the timing margin of the data path 30 changes similarly to the waveform 41 of the fluctuation of the power supply voltage VDD shown in FIG. The contribution of the adjustment of the clock cycle to the timing margin of the data path 30 changes in the same manner as the clock cycle change waveform 42 shown in FIG. 2B. Accordingly, the timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 41 of FIG. 2A and the waveform 42 of FIG. For example, a waveform 44 shown in FIG. As shown by a waveform 44 in FIG. 2D, a state where the timing margin is equal to or higher than zero (that is, a state in which a certain timing margin exists) is maintained, and the logic circuit 14 appropriately operates without a timing error. Can work.

  FIG. 3 is a diagram illustrating an example of an operation of the PLL circuit illustrated in FIG. 1 with respect to a continuous fluctuation of the power supply voltage VDD. FIG. 3A shows the voltage value of the power supply voltage VDD. (B) is an oscillation cycle that is a target of the control loop of the PLL, and indicates an oscillation cycle corresponding to the frequency division ratio set in the frequency divider 21. (C) shows the oscillation cycle of the PLL circuit 10. (D) shows the average value of the oscillation cycle of the PLL circuit 10. (E) shows a timing margin of the data path 30 which is a critical path of the logic circuit 14. The horizontal axis in each waveform diagram is time. Voltage V1 is a desired voltage level of power supply voltage VDD supplied to the electronic circuit shown in FIG. The oscillation cycle C1 is a target oscillation cycle of the PLL circuit 10 corresponding to the power supply voltage VDD. The oscillation cycle T1 is a desired oscillation cycle of the PLL circuit 10 corresponding to the power supply voltage VDD.

  In the example shown in FIG. 3A, a periodic change shown by a waveform 51 occurs in the power supply voltage VDD due to the IR drop. This voltage fluctuation is a high-speed change having a frequency band of about 50 MHz to 150 MHz. For example, when the operation mode of an LSI such as a processor periodically transitions from the standby mode to the operation mode, the power supply voltage VDD changes as shown in FIG. In the waveform 51 of FIG. 3A, the upper waveform of the desired voltage V1 and the lower waveform of the voltage V1 are shown as having substantially the same amplitude. However, actually, the waveform 51 is formed by the decrease in the power supply voltage VDD due to the IR drop and the subsequent increase in the power supply voltage VDD due to the overshoot, so that the upper waveform of the voltage V1 is larger than the lower waveform of the voltage V1. Also have a small amplitude.

  In the waveform 51 of the power supply voltage VDD shown in FIG. 3A, the state where the power supply voltage VDD is lower than the desired voltage V1 on average continues, so that the target oscillation cycle of the PLL control loop, that is, the target oscillation cycle, The length of the oscillation cycle corresponding to the frequency division ratio set in frequency divider 21 increases. Therefore, as shown by the waveform 52 in FIG. 3B, the oscillation cycle that is the target of the PLL control loop increases.

  In addition, the digital code input to the digitally controlled oscillator 20 increases in response to the voltage drop of the waveform 41 shown in FIG. 3A, and the oscillation cycle of the digitally controlled oscillator 20 is changed to a waveform 53 in FIG. Changes as shown. Further, the average value of the oscillation period in consideration of the averaging or integration function of the PLL control loop (phase locked loop) by the loop filter 23 changes as shown by a waveform 54 in FIG.

  Further, the timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 51 of FIG. 3A and the waveform 53 of FIG. For example, a waveform 55 shown in FIG. As shown by the waveform 55 in FIG. 3E, the state where the timing margin is equal to or higher than zero (that is, a state where a certain timing margin exists) is maintained, and the logic circuit 14 appropriately operates without the timing error. Can work.

  In the operation examples shown in FIGS. 3A to 3E, the average value of the oscillation period (FIG. 3D) in consideration of the averaging or integration function of the PLL control loop by the loop filter 23 is shown in FIG. 3 (FIG. 3B). This is because the average value of the oscillation period does not follow the target oscillation period due to the operation of the control loop of the PLL, but rather the average value of the oscillation period obtained by adding the detection signal Q to the input of the digital control oscillator 20. The increase corresponds to the result of the increase of the target oscillation period. The increase in the average value of the oscillation period due to the addition of the detection signal Q coincides with the increase in the target oscillation period. As a result, a stable state (phase locked state) of the PLL control loop is realized, and the waveform 52 in FIG. And the waveform 54 in FIG. 3D is kept in agreement.

  FIG. 4 is a diagram for explaining an operation of the PLL circuit shown in FIG. 1 with respect to a continuous fluctuation of the power supply voltage VDD. When the addition operation of the adder 25 for adding the detection signal Q of the AD converter 11 to the input signal of the digital control oscillator 20 is stopped in the PLL circuit shown in FIG. It shows how the PLL circuit operates in response to the continuous fluctuation of the voltage VDD. The signals shown in FIGS. 4A to 4E are the same as the signals shown in FIGS. 3A to 3E.

  In the power supply voltage VDD waveform 61 shown in FIG. 4A, the state in which the power supply voltage VDD is lower than the desired voltage V1 on average continues, so the target oscillation period of the control loop of the PLL, that is, The length of the oscillation cycle corresponding to the frequency division ratio set in frequency divider 21 increases. Therefore, as shown by the waveform 62 in FIG. 4B, the oscillation cycle that is the target of the PLL control loop increases.

  By increasing the target oscillation cycle of the PLL control loop as shown in FIG. 4B, the oscillation cycle of the digitally controlled oscillator 20 changes as shown by a waveform 63 in FIG. Further, the average value of the oscillation period in consideration of the averaging or integration function of the PLL control loop (phase locked loop) by the loop filter 23 changes as shown by a waveform 64 in FIG.

  In this operation example, the average value of the oscillation period (FIG. 4D) in consideration of the averaging or integration function of the PLL control loop by the loop filter 23 is the target oscillation period of the PLL control loop (FIG. 4B). ) To gradually increase. This is because the oscillation cycle changes by the operation of the control loop of the PLL such that the average value of the oscillation cycle follows the target oscillation cycle. As described above, in the operation examples shown in FIGS. 4A to 4E, the addition operation of the adder 25 that adds the detection signal Q of the AD converter 11 to the input signal of the digitally controlled oscillator 20 is stopped. This is an example showing how the PLL circuit operates in such a case. The oscillation cycle of the PLL circuit 10 shown in FIG. 4C does not show a fast change in response to a steep power supply voltage change, unlike the oscillation cycle shown in FIG.

  The timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 61 in FIG. 4A and the waveform 63 in FIG. A waveform 65 shown in FIG. As shown by the waveform 65 in FIG. 4E, for a while after the power supply voltage VDD starts to fluctuate, the oscillation cycle cannot respond to the fluctuation of the power supply voltage VDD at high speed, and the timing margin is increased. A state of dropping below zero occurs. Therefore, the logic circuit 14 of the electronic circuit illustrated in FIG. 1 may not be able to operate properly due to a timing error. Thereafter, when the oscillation cycle of the PLL circuit 10 gradually increases due to the control operation of the PLL control loop, the timing margin also gradually increases, and the state where the timing margin is equal to or higher than zero is maintained.

  As shown in FIGS. 4A to 4E, a sharp change in the power supply voltage VDD is caused only by changing the frequency division ratio of the frequency divider 21 in accordance with the detection signal Q output from the AD converter 11. When there is, the oscillation cycle cannot be changed at high speed in accordance with the fluctuation. As a result, there is no timing margin, and a timing error occurs in the data path of the logic circuit 14. Therefore, as in the PLL circuit 10 shown in FIG. 1, in addition to the operation of controlling the frequency division ratio, the detection signal Q of the AD converter 11 is further added to the input signal of the digitally controlled oscillator 20 by the adder 25. Preferably, the oscillation cycle of the digitally controlled oscillator 20 is directly changed.

  FIG. 5 is a diagram for explaining an operation of the PLL circuit shown in FIG. 1 with respect to a continuous fluctuation of the power supply voltage VDD. Each waveform shown in FIG. 5 indicates the continuation of the power supply voltage VDD when the operation of adjusting the frequency division ratio of the frequency divider 21 in accordance with the detection signal Q of the AD converter 11 is stopped in the PLL circuit shown in FIG. It shows how the PLL circuit operates in response to a typical fluctuation. The signals shown in FIGS. 5A to 5E are the same as the signals shown in FIGS. 3A to 3E.

  In the waveform 71 of the power supply voltage VDD shown in FIG. 5A, the state where the power supply voltage VDD is lower than the desired voltage V1 on average is maintained. However, in the operation shown in FIGS. 5A to 5E, it is assumed that the operation of adjusting the target oscillation cycle of the control loop of the PLL is stopped, so that the waveform 72 is shown in FIG. As shown, the target oscillation cycle of the PLL control loop maintains the same value C1.

  In addition, in response to the voltage drop of the waveform 71 shown in FIG. 5A, the digital code input to the digitally controlled oscillator 20 is increased by the addition operation of the adder 25, and the oscillation cycle of the digitally controlled oscillator 20 is increased. The waveform changes as shown as a waveform 73 in FIG. Furthermore, the average value of the oscillation cycle in consideration of the averaging or integration function of the PLL control loop (phase locked loop) by the loop filter 23 changes as shown by a waveform 74 in FIG.

  In this operation example, the oscillation period increases in response to the power supply fluctuation at a high speed as shown by a waveform 73 in FIG. 5C, so that the oscillation in consideration of the averaging or integration function by the loop filter 23 of the PLL control loop is performed. The average value of the period (FIG. 5 (d)) also initially shows an increase. However, thereafter, as shown as a waveform 74 in FIG. 5D, the average of the oscillation periods is approximated to approach a period T1 corresponding to a constant value C1 of the target oscillation period (FIG. 5B) of the PLL control loop. The value is gradually decreasing. This is because the oscillation cycle changes by the operation of the control loop of the PLL so that the average value of the oscillation cycle approaches the target oscillation cycle.

  The timing margin in which the fluctuation of the power supply voltage VDD is offset by the adjustment of the clock cycle is the sum of the waveform 71 in FIG. 5A and the waveform 73 in FIG. A waveform 75 shown in FIG. As shown by the waveform 75 in FIG. 5E, for a while after the power supply voltage VDD starts to fluctuate, the oscillation cycle responds to the fluctuation of the power supply voltage VDD at high speed, so that the timing margin is zero. The state that is equal to or higher than the level is maintained. However, thereafter, when the oscillation cycle of the PLL circuit 10 gradually decreases due to the control operation of the PLL control loop, the timing margin also gradually decreases, and a state below the level where the timing margin is zero occurs. Therefore, the logic circuit 14 of the electronic circuit shown in FIG. 1 may not operate properly due to a timing error.

  As shown in FIGS. 5A to 5E, the target oscillation is not obtained only by directly adding the signal to the input signal of the digitally controlled oscillator 20 from the outside of the PLL loop to directly change the oscillation cycle of the digitally controlled oscillator 20. The period and the average oscillation period are different. As a result, in the case where the power supply voltage VDD fluctuates as shown in FIG. 5A, if a long time equal to or more than a certain period elapses after the fluctuation has occurred, a timing error occurs due to a decrease in the oscillation cycle due to the operation of the PLL control loop. Can occur. Therefore, in addition to the operation of adding the signal to the input signal of the digitally controlled oscillator 20 from the outside of the PLL loop and directly changing the oscillation cycle of the digitally controlled oscillator 20 as in the PLL circuit 10 shown in FIG. It is preferable to execute an operation for controlling the frequency division ratio.

  As described above, in the electronic circuit shown in FIG. 1, when the value of the digital code of the detection signal Q output from the AD converter 11 increases due to a decrease in the power supply voltage VDD, the oscillation of the digital control oscillator 20 increases. The period length increases. At this time, it is assumed that the digital code of the detection signal Q, which is the output of the AD converter 11, increases by 1 LSB and the oscillation cycle length increases by ΔTo with respect to the decrease of ΔV of the power supply voltage VDD. It is also assumed that the signal propagation time in the data path 30 of the logic circuit 14 increases by ΔTp due to the decrease in ΔV of the power supply voltage VDD. In this case, it is preferable that the increase ΔTo of the oscillation cycle in response to the increase of 1 LSB of the detection signal Q is greater than or equal to the increase ΔTp of the signal propagation time of the data path 30. In order to realize the fastest operation speed while avoiding the timing error, it is preferable that the increase ΔTo of the oscillation cycle in response to the increase of 1 LSB of the detection signal Q is equal to the increase ΔTp of the signal propagation time of the data path 30. . Therefore, it is preferable to adjust the change in the oscillation cycle of the digitally controlled oscillator 20 (that is, the sensitivity of the oscillation cycle control) with respect to a 1 LSB change in the input digital code so as to satisfy these conditions.

  In the configuration shown in FIG. 1, the AD converter 11 functioning as a voltage detector outputs the detection signal Q. However, as the voltage detector for generating the detection signal Q, an analog power supply voltage is converted to a digital detection signal Q The conversion is not limited to the one based on the AD conversion function. The voltage detector may measure a circuit delay caused by a voltage change of the power supply voltage and output a measured value indicating the circuit delay as the detection signal Q.

  FIG. 6 is a diagram illustrating an example of an electronic circuit according to an embodiment in which an oscillation frequency can be changed by following a power supply noise by using a voltage detector that generates a detection signal Q based on a circuit delay measurement. 6, the same or corresponding components as those of FIG. 1 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate.

  The electronic circuit shown in FIG. 6 includes a control circuit 80, a delay monitor circuit (DDM) 81, a mask circuit (MASK) 82, and a PLL circuit 83 instead of the AD converter 11 shown in FIG. The control circuit 80, the delay monitor circuit 81, and the mask circuit 82 correspond to a voltage detector.

  The control circuit 80 is a circuit that controls the delay monitor circuit 81 and the mask circuit 82. The control circuit 80 supplies the first control signal C and the second control signal R of k bits (k is an integer of 2 or more) to the delay monitor circuit 81, and 2n bits (n is an integer of 1 or more). Is supplied to the mask circuit 82. The delay monitor circuit 81 measures, based on a clock signal, a circuit delay difference between two variable delay lines whose delay times are set by the first and second control signals C and R, respectively, and determines a result of the measurement. Output as circuit delay measurement value. These two variable delay lines are driven by the power supply voltage VDD and the reference voltage VREF, respectively, and a change in the circuit delay difference between the two variable delay lines indicates a change in the power supply voltage VDD. The mask circuit 82 masks the 2n-bit circuit delay measurement value output from the delay monitor circuit 81 for each bit based on the mask signal M, and outputs the 2n-bit masked circuit delay measurement value. The measured circuit delay value after the masking is supplied to the PLL circuit 10 and the averaging unit 12 as a detection signal Q.

  The clock signal used by the delay monitor circuit 81 may be supplied from the PLL circuit 83 to the clock input terminal CK of the delay monitor circuit 81. Hereinafter, this clock signal is referred to as a clock signal CK. The delay monitor circuit 81 measures a circuit delay based on a time difference when one clock pulse passes through the two variable delay lines. At this time, of the series of clock pulses in the clock signal CK, only one clock pulse is used to measure the circuit delay once, and if the circuit delay is measured only once, a single pulse is used. A signal may be supplied to the delay monitor circuit 81. By continuously supplying a plurality of clock pulses to the delay monitor circuit 81, a plurality of circuit delay measurements are continuously performed. Therefore, the circuit delay measurement value itself does not depend on the frequency of the clock signal CK, and the frequency of the clock signal CK may be set as appropriate as defining the sampling period for measuring the circuit delay.

  FIG. 7 is a modification of the electronic circuit shown in FIG. In the electronic circuit shown in FIG. 7, the clock signal CK used by the delay monitor circuit 81 is supplied from the PLL circuit 10. That is, the clock signal generated by the digitally controlled oscillator 20 of the PLL circuit 10 and supplied to the logic circuit 14 is also applied to the clock input terminal CK of the delay monitor circuit 81. As described above, the measured circuit delay value output by the delay monitor circuit 81 does not depend on the frequency of the clock signal applied to the clock input terminal CK. Therefore, even when the oscillation frequency of the PLL circuit 10 whose frequency changes as the control target is applied to the clock input terminal CK, the result of the circuit delay measurement by the delay monitor circuit 81 may change with the control of the PLL circuit 10. There is no. That is, the delay monitor circuit 81 can detect only a change in the power supply voltage VDD without being affected by a change in the oscillation frequency of the PLL circuit 10. With the configuration of the electronic circuit in FIG. 7, the number of PLL circuits can be reduced as compared with the configuration of the electronic circuit in FIG.

  FIG. 8 is a diagram illustrating an example of the configuration of the delay monitor circuit 81. The delay monitor circuit 81 shown in FIG. 8 includes a first variable delay line 90, a second variable delay line 91, and a time difference measurement circuit 92.

  The first variable delay line 90 receives the power supply voltage VDD and outputs a first delayed oscillation signal obtained by delaying the clock signal CK based on the first control signal C. The second variable delay line 91 receives the reference voltage VREF and outputs a second delayed oscillation signal obtained by delaying the clock signal CK based on the second control signal R.

  The time difference measurement circuit 92 includes a plurality of delay circuits 101, a plurality of delay circuits 102, n first flip-flops 103, and n second flip-flops 104. In the first flip-flop 103, a second delayed oscillation signal output from the second variable delay line 91 is supplied to each clock terminal. Further, a first delayed oscillation signal output from the first variable delay line 90, which is delayed by a first predetermined delay from the data input of the first flip-flop 103 in the preceding stage by the delay circuit 101, is output to each of the respective circuits. Input to the data input terminal.

  In the second flip-flop 104, the first delayed oscillation signal output from the first variable delay line 90 is input to each data input terminal. Further, a second delayed oscillation signal output from the second variable delay line 91, which is delayed by a second predetermined delay from the clock input of the second flip-flop 104 in the preceding stage by the delay circuit 102, is applied to each clock terminal. Supplied to Note that each delay time (delay) of the delay circuit 101 and each delay time (delay) of the delay circuit 102 may be equal. That is, the first predetermined delay and the second predetermined delay may be equal.

  The 2n-bit circuit delay measurement value Q [2n-1: 0] output from the time difference measurement circuit 92 is based on the n-bit output data of the n second flip-flops 104 as lower n bits and the n second The output data of n bits of the flip-flop 104 is the lower n bits. When the delay time of the first variable delay line 90 is equal to the delay time of the second variable delay line 91, the circuit delay measurement value Q [2n-1: 0] is such that the upper n bits are all 0 and the lower n bits are 0. All become 1. The circuit delay measurement value Q [2n-1: 0] having this value is expressed as {n′b00... 00, n′b11. When n is 4, for example, the circuit delay measurement value Q [7: 0] is “000011111”.

  When the circuit delay of the first variable delay line 90 is longer than the circuit delay of the second variable delay line 91, the first delayed oscillation signal output from the first variable delay line 90 is changed to the second variable delay line. This is behind the second delayed oscillation signal transmitted by the line 91. In this case, of the n second flip-flops 104, for example, the second flip-flop 104 located at the leftmost position in the drawing is the first delayed oscillation signal before the first delayed oscillation signal becomes HIGH. As data input. As a result, some of the n-bit output data of the n second flip-flops 104 become 0 instead of 1. When the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, three or four of the predetermined delays, a circuit in the case of n = 4 The measured delay value Q [7: 0] is “00000001”. Further, when the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, between two and three of the predetermined delays, n = 4 Circuit delay measurement value Q [7: 0] is “00000011”.

  When the circuit delay of the first variable delay line 90 is shorter than the circuit delay of the second variable delay line 91, the first delayed oscillation signal output from the first variable delay line 90 is changed to the second variable delay line. This is earlier than the second delayed oscillation signal transmitted by the line 91. In this case, of the n first flip-flops 103, for example, the second flip-flop 104 located at the leftmost position in the drawing is the first delayed oscillation signal after the first delayed oscillation signal becomes HIGH. As data input. As a result, some bits of the n-bit output data of the n first flip-flops 103 become 1 instead of 0. When the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, three or four of the predetermined delays, a circuit in the case of n = 4 The delay measurement value Q [7: 0] is “01111111”. Further, when the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 corresponds to, for example, between two and three of the predetermined delays, n = 4 Circuit delay measurement value Q [7: 0] is “00111111”.

  In the circuit configuration shown in FIG. 8, the output of the first variable delay line 90 is applied to the data input terminals of the flip-flops 103 and 104, and the output of the second variable delay line 91 is applied to the clock terminals of the flip-flops 103 and 104. Is applied. Conversely, the output of the first variable delay line 90 is applied to the clock terminals of the flip-flops 103 and 104, and the output of the second variable delay line 91 is applied to the data input terminals of the flip-flops 103 and 104. Good. In this case, the increase or decrease of the circuit delay measurement value Q [2n−1: 0] according to the change in the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 is opposite to the above. In consideration of this, the control operation based on the measured circuit delay value Q may be appropriately designed.

  In this way, the delay monitor circuit 81 outputs the circuit delay measurement value Q [2n-1: 0] which is a thermometer code indicating the circuit delay difference between the first variable delay line 90 and the second variable delay line 91. Output. The first variable delay line 90 is driven by the power supply voltage VDD, and the second variable delay line 91 is driven by the reference voltage VREF. Here, the reference voltage VREF is a power supply voltage supplied from outside separately from the power supply voltage VDD, and is not used in other circuit parts of the electronic circuit shown in FIG. 6 or FIG. 7 and is mixed with noise. It is a voltage that does not fluctuate and is maintained at a constant voltage. Therefore, the measured circuit delay value Q [2n-1: 0] indicating the circuit delay difference between the first variable delay line 90 and the second variable delay line 91 uniquely reflects the value of the power supply voltage VDD. It becomes. When the power supply voltage VDD decreases, the circuit delay of the first variable delay line 90 increases, and when the power supply voltage VDD increases, the circuit delay of the first variable delay line 90 decreases. Therefore, when the power supply voltage VDD decreases, the number of bits of the value 0 in the circuit delay measurement value Q [2n-1: 0] increases, and when the power supply voltage VDD increases, the circuit delay measurement value Q [2n-1: 0]. ] Has more bits.

  Even if it is desired to manufacture a circuit so that the circuit delay of the first variable delay line 90 and the circuit delay of the second variable delay line 91 have the same length, the circuit delay must be the same due to the effects of process variations and wiring variations. It is difficult. Therefore, it is desirable to set the circuit delay of the first variable delay line 90 and the circuit delay of the second variable delay line 91 to have the same length by the initialization operation performed in advance. This initial setting operation will be described later.

FIG. 9 is a diagram illustrating an example of the configuration of the variable delay line. Each of the first variable delay line 90 and the second variable delay line 91 shown in FIG. 8 may include the circuit configuration of the variable delay line shown in FIG. Variable delay line shown in FIG. 9 includes a plurality of inverters 111,2 ^k-number of switching circuits 112 and a plurality of capacitive elements 113,. Inverters 111 are cascaded to form a delay line. Switch control codes T [0] to T [2 ^k -1] are applied to each of the 2 ^k switch circuits 112. Each of the switch circuits 112 is turned on (conducted) when the corresponding bit value of the applied switch control code is 1, and the capacitance element 113 connected in series to the switch circuit 112 is connected to the output of the inverter 111. Is done. Each of the switch circuits 112 is further turned off (cut off) when the corresponding bit value of the applied switch control code is 0, and the capacitance element 113 connected in series to the switch circuit 112 is connected to the output of the inverter 111 from the output of the inverter 111. Separated.

As the number of bits of the value 1 of the switch control codes T [0] to T [2 ^k -1] increases, the number of the capacitive elements 113 connected to the delay line illustrated in FIG. 9 increases, and the delay time increases. Further, as the number of bits of the value 0 of the switch control codes T [0] to T [2 ^k -1] increases, the number of the capacitive elements 113 connected to the delay line illustrated in FIG. 9 decreases, and the delay time decreases. .

FIG. 10 is a diagram illustrating a code conversion unit that performs code conversion for a variable delay line. Each of the first variable delay line 90 and the second variable delay line 91 shown in FIG. 8 may include the code conversion unit shown in FIG. For example, a k-bit first control signal C [k−1: 0] corresponding to the first variable delay line 90 is supplied to the code conversion unit 115 illustrated in FIG. The code conversion unit 115 generates a thermocouple of 2 ^k bits such that the number of bits equal to one of the values of 0 to 2 ^k -1 indicated by the first control signal C [k-1: 0] is the value 1. Generate a meter code. That is, for example, when the first control signal C [3: 0] indicates “1011” and indicates the decimal value 11, the outputs T [0] to T [15] of the code conversion unit 115 are 11 out of all 16 bits. The number of bits becomes the thermometer code "1111111111100000" having the value 1. The second variable delay line 91, similar code conversion unit, a second control signal R [k-1: 0] and may be similarly converted to the thermometer code of 2 ^k bits.

  FIG. 11 is a diagram showing an example of the configuration of the mask circuit 82 shown in FIG. 6 or FIG. 6 or 7 receives the 2n-1 bit circuit delay measurement value Q [2n-1: 0] from the delay monitor circuit 81 at the A input, and receives the 2n-1 bit from the control circuit 80. At the B input. In FIG. 11, 2n-1 bit signals received at the A input are shown as A [0] to A [2n-1], and 2n-1 bit signals received at the B input are B [0] to B [2n- 1].

  The mask circuit illustrated in FIG. 11 includes 2n−1 OR circuits 120. Outputs X [0] to X [2n-1] of the 2n-1 OR circuits 120 are output from the mask circuit as masked circuit delay values of 2n-1 bits. Each OR circuit 120 performs an OR operation on the corresponding one bit of A [0] to A [2n-1] and the corresponding one bit of B [0] to B [2n-1]. , OR operation result is output as a corresponding one bit of X [0] to X [2n-1]. In this way, of the 2n-1 bit circuit delay measurement values Q [2n-1: 0], the bit corresponding to the value 1 bit of the 2n-1 bit mask signal M is masked, and the masked circuit The delay measurement is output.

  FIG. 12 is a flowchart illustrating an example of the setting operation by the control circuit. Before the electronic circuit shown in FIG. 6 or 7 starts execution of the original intended routine processing, the electronic circuit performs the initial setting procedure shown in the flowchart of FIG. For example, when the electronic circuit is a communication circuit, before the execution of the communication processing by the electronic circuit is started, the initial setting procedure shown in the flowchart of FIG. 12 is executed. After the initialization is performed, the electronic circuit executes the routine processing, and the adaptive frequency control that controls the oscillation frequency of the PLL circuit 10 according to the change in the power supply voltage VDD is executed.

  In step S1, the reference voltage VREF and the power supply voltage VDD are set to the same voltage, and all bits of the mask signal M are set to 1 by the control circuit 80. As for the voltage setting, the above-described voltage setting may be performed by, for example, transmitting a voltage setting command to the external voltage source by the control circuit 80. Here, the same set voltage for setting the reference voltage VREF and the power supply voltage VDD is a voltage lower than the rated voltage at which the power supply voltage VDD is set when the electronic circuit executes the routine processing, and triggers the adaptive frequency control. It may be a voltage. That is, when the power supply voltage VDD decreases from the rated voltage and reaches a predetermined voltage during execution of the routine processing, an operation of lowering the oscillation frequency of the PLL circuit 10 by the adaptive frequency control is desired to be started (triggering is desired). Case), the set voltage may be equal to the predetermined voltage. Also, by setting all bits of the mask signal M to 1, all bits of the output of the mask circuit 82 are fixed to the value 1, and all bits of the detection signal Q supplied to the PLL circuit 10 and the averaging unit 12 The value is fixed at 1. Thereby, the adaptive frequency control for controlling the oscillation frequency of the PLL circuit 10 is stopped.

In step S2, the control circuit 80 sets each of the first control signal C and the second control signal R to 2 ^k−1 −1. As a result, each of the first variable delay line 90 and the second variable delay line 91 of the delay monitor circuit 81 is set to an intermediate delay length between the maximum delay length and the minimum delay length. In step S3, the control circuit 80 acquires the circuit delay measurement value Q output from the delay monitor circuit 81.

  In step S4, the control circuit 80 determines whether the circuit delay measurement value Q acquired in step S3 is smaller than {n'b00 ... 00, n'b11 ... 11}. That is, it is determined whether the circuit delay of the first variable delay line 90 is greater than the circuit delay of the second variable delay line 91. When the determination result is Yes, the processing procedure proceeds to Step S5, and when the determination result is No, the processing procedure proceeds to Step S7.

  In step S5, the control circuit 80 increases the second control signal R by 1 when the first control signal C is 0, and increases the first control signal R when the first control signal C is not 0. Decrease C by one. That is, the control circuit 80 first changes the control signal so as to shorten the circuit delay of the first variable delay line 90, and after the circuit delay of the first variable delay line 90 becomes the shortest, the second variable delay line The control signal is changed so as to increase the circuit delay of the delay line 91. In step S6, the control circuit 80 outputs the changed first and second control signals C and R to the delay monitor circuit 81. Thereafter, the processing procedure returns to step S3, and the subsequent processing is repeated.

  In step S7, the control circuit 80 determines whether the circuit delay measurement value Q acquired in step S3 is larger than {n'b00 ... 00, n'b11 ... 11}. That is, it is determined whether the circuit delay of the first variable delay line 90 is smaller than the circuit delay of the second variable delay line 91. When the determination result is Yes, the processing procedure proceeds to Step S8, and when the determination result is No, the processing procedure proceeds to Step S9.

In step S8, the control circuit 80, when the first control signal C is 2 ^k -1 reduces the second control signal R by one, when the first control signal C is not a 2 ^k -1 Increases the first control signal C by one. That is, the control circuit 80 first changes the control signal so as to lengthen the circuit delay of the first variable delay line 90, and after the circuit delay of the first variable delay line 90 becomes the shortest, the second variable delay line The control signal is changed so as to shorten the circuit delay of the delay line 91. Thereafter, in step S6, the control circuit 80 outputs the changed first and second control signals C and R to the delay monitor circuit 81. Thereafter, the processing procedure returns to step S3 and repeats the subsequent processing.

  When the processing procedure reaches step S9, the measured circuit delay value Q is equal to {n′b00... 00, n′b11. That is, the circuit delay of the first variable delay line 90 is equal to the circuit delay of the second variable delay line 91. In this state, in step S9, the power supply voltage VDD is set to the rated voltage. As for the voltage setting, the above-described voltage setting may be performed by, for example, transmitting a voltage setting command to the external voltage source by the control circuit 80.

  In step S10, the control circuit 80 outputs a mask signal M in which all the bits are not 1, and starts adaptive frequency control. Here, the value of the mask signal M is a value obtained by shifting {n′b11... 11, n′b00.

  Here, TH is a threshold value set to provide a time margin in anticipation of the time required for the oscillation frequency of the PLL circuit 10 to actually change by the adaptive frequency control. If no time margin is considered, TH may be equal to zero. That is, the value of the mask signal M may be equal to {n'b11 ... 11, n'b00 ... 00}. When the power supply voltage VDD is equal to the reference voltage VREF (= trigger voltage), the circuit delays of the first variable delay line 90 and the second variable delay line 91 become equal by the above-described initial setting operation of FIG. At this time, the measured circuit delay value Q becomes equal to {n′b00... 00, n′b11. Therefore, when the power supply voltage VDD set to the rated voltage (> trigger voltage) decreases to the reference voltage VREF (= trigger voltage), the circuit delay measurement value Q becomes {n′b00... 00, n′b11 ·・ ・ It becomes 11｝. If the value of the mask signal M is {n′b11... 11, n′b00... 00}, the circuit delay measurement value Q is {n′b00... 00, n′b11. When it becomes smaller, the detection signal Q output from the mask circuit 82 changes for the first time. In the electronic circuit shown in FIG. 6 or FIG. 7, when the value of the input signal of the digitally controlled oscillator 20 decreases, the length of the period of the oscillation signal of the digitally controlled oscillator 20 may increase. Conversely, when the value of the input signal of the digitally controlled oscillator 20 increases, the period of the oscillation signal of the digitally controlled oscillator 20 may decrease. Since the frequency adjustment operation is performed by the PLL circuit 10 according to the change in the value of the detection signal Q generated as described above, when the power supply voltage VDD set to the rated voltage falls below the reference voltage VREF, The frequency adjustment operation by the PLL circuit 10 is started.

  However, it usually takes some time from the start of the frequency adjustment operation by the PLL circuit 10 until the clock frequency reaches an appropriate frequency. If it takes time for the clock frequency to reach an appropriate frequency, a data transfer error may occur in the critical path of the logic circuit 14. Therefore, in practice, it is preferable to provide a time margin in anticipation of the time required for the control. In consideration of the above, by shifting the mask signal M to the left by TH bits, the number of upper bits to be masked is reduced, and the value of the detection signal Q is changed earlier. Assuming that the control delay is Dc [nsec], the gradient of the voltage drop is Sn [mV / nsec], and the change of the power supply voltage VDD corresponding to the change of 1 LSB of the output of the delay monitor circuit 81 is h [mV], TH is as follows. It suffices to satisfy the equation.

Dc < (h / Sn) .TH
Therefore, TH is a positive integer satisfying the following equation.

TH > (Dc · Sn) / h
The threshold value TH is stored in a memory of the electronic circuit, and may be supplied to the control circuit 80 from the memory.

  FIG. 13 is a diagram showing another example of the embodiment of the electronic circuit capable of changing the oscillation frequency following the power supply noise based on the circuit delay measurement. 13, the same or corresponding components as those in FIG. 6 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate.

  In the electronic circuit shown in FIG. 13, a control circuit 80A is provided instead of the control circuit 80 shown in FIG. 6, and a critical path monitor & delay monitor circuit (CPM / DDM) 81A instead of the delay monitor circuit 81 shown in FIG. Is provided. Control circuit 80A includes a register QM and a state machine FSM. The register QM stores a circuit delay measurement value Q of the pseudo critical path circuit measured by the critical path monitor & delay monitor circuit 81A. The state machine FSM controls the operation performed by the control circuit 80A. The critical path monitor & delay monitor circuit 81A is a circuit having both a function of monitoring a pseudo critical path and a function of monitoring a circuit delay, and is hereinafter simply referred to as a delay monitor circuit 81A. The control circuit 80A, the delay monitor circuit 81A, and the mask circuit 82 correspond to a voltage detector.

  The delay monitor circuit 81A measures a circuit delay difference between the variable delay line whose delay time is set by the control signal R and the pseudo critical path based on the clock signal CK, and outputs a result of the measurement as a circuit delay measurement value. I do. The pseudo critical path and the variable delay line are driven by the power supply voltage VDD and the reference voltage VREF, respectively, and a change in a circuit delay difference between the pseudo critical path and the variable delay line indicates a change in the power supply voltage VDD. The configuration and operation of the delay monitor circuit 81A will be described later. In the delay monitor circuit 81A, similarly to the case of the delay monitor circuit 81, the measured circuit delay value itself does not depend on the frequency of the clock signal CK.

  FIG. 14 is a diagram showing a modification of the electronic circuit shown in FIG. In the electronic circuit shown in FIG. 14, the clock signal CK used by the delay monitor circuit 81A is supplied from the PLL circuit 10. As described above, the circuit delay measurement value output from the delay monitor circuit 81A does not depend on the frequency of the clock signal applied to the clock input terminal CK. Therefore, even when the oscillation frequency of the PLL circuit 10 whose frequency changes as a control target is applied to the clock input terminal CK, the result of the circuit delay measurement by the delay monitor circuit 81A may change with the control of the PLL circuit 10. There is no. That is, the delay monitor circuit 81A can detect only a change in the power supply voltage VDD without being affected by a change in the oscillation frequency of the PLL circuit 10. With the configuration of the electronic circuit in FIG. 14, the number of PLL circuits can be reduced as compared with the configuration of the electronic circuit in FIG.

  FIG. 15 is a diagram illustrating an example of the configuration of the delay monitor circuit 81A. The delay monitor circuit 81A shown in FIG. 15 includes a pseudo critical path circuit 131, a delay control circuit 132, and a time difference measurement circuit 92. The delay control circuit 132 includes a variable delay line 141 and a selection circuit 142.

  The pseudo critical path circuit 131 receives the power supply voltage VDD and outputs a first delayed oscillation signal obtained by delaying the clock signal CK. The variable delay line 141 receives the reference voltage VREF and outputs a second delayed oscillation signal obtained by delaying the clock signal CK based on the control signal R. The selection circuit 142 selects and outputs a third delayed oscillation signal, which is either the clock signal CK or the second delayed oscillation signal, based on the input selection signal S.

  In the first flip-flop 103 included in the time difference measurement circuit 92, the third delayed oscillation signal output from the selection circuit 142 is supplied to each first input terminal (a clock terminal in this example). The first output, which is the output of the pseudo critical path circuit 131, is delayed by the delay circuit 101 from the second input terminal (data input terminal in this example) of the preceding first flip-flop 103 by the first predetermined delay. The delayed oscillation signal is input to each second input terminal.

  In the second flip-flop 104, the first delayed oscillation signal output from the pseudo critical path circuit 131 is input to each second input terminal (data input terminal in this example). Further, a third delayed oscillation output from the selection circuit 142, which is delayed from the first input terminal (the clock input terminal in this example) of the second flip-flop 104 at the preceding stage by the second predetermined delay by the delay circuit 102, respectively. A signal is supplied to each first input terminal. Note that each delay time (delay) of the delay circuit 101 and each delay time (delay) of the delay circuit 102 may be equal. That is, the first predetermined delay and the second predetermined delay may be equal.

  During a routine process for activating the adaptive frequency control, the selection circuit 142 selects and outputs the output of the variable delay line 141. In this state, when the delay times of the pseudo critical path circuit 131 and the variable delay line 141 are equal, the upper n bits of the circuit delay measurement value Q [2n-1: 0] are all 0 and the lower n bits are all It becomes 1. That is, the measured circuit delay value Q [2n−1: 0] is {n′b00... 00, n′b11.

  When the circuit delay of the pseudo critical path circuit 131 is longer than the circuit delay of the variable delay line 141, some of the n-bit output data of the n second flip-flops 104 are not 1, but 0. become. That is, the measured circuit delay value Q [2n−1: 0] is smaller than {n′b00... 00, n′b11.

  When the circuit delay of the pseudo critical path circuit 131 is shorter than the circuit delay of the variable delay line 141, some bits of the n-bit output data of the n first flip-flops 103 are not 0 but 1 instead of 0. become. That is, the measured circuit delay value Q [2n−1: 0] is larger than {n′b00... 00, n′b11.

  In this way, the delay monitor circuit 81A outputs a circuit delay measurement value Q [2n-1: 0] which is a thermometer code indicating a circuit delay difference between the pseudo critical path circuit 131 and the variable delay line 141. The pseudo critical path circuit 131 is driven by the power supply voltage VDD, and the variable delay line 141 is driven by the reference voltage VREF. Here, the reference voltage VREF is a power supply voltage supplied from outside separately from the power supply voltage VDD, and is not used in other circuit parts of the electronic circuit shown in FIG. 6 or FIG. 7 and is mixed with noise. It is a voltage that does not fluctuate and is maintained at a constant voltage.

  The variable delay line 141 is designed to have a delay time equivalent to one clock cycle of an operation clock signal at the time of routine processing of an electronic circuit, and to have a delay time length equivalent to a critical path in the logic circuit 14. The pseudo critical path circuit 131 is designed. With this design, if the circuit delay of the pseudo critical path circuit 131 is shorter than one clock cycle, the circuit delay measurement value Q becomes {n′b00... 00, n′b11. It is a state larger than. On the other hand, when the circuit delay of the pseudo critical path circuit 131 is longer than one clock cycle, the measured circuit delay Q becomes smaller than {n′b00... 00, n′b11. Therefore, if the value of the mask signal M is set to {n′b11... 11, n′b00... 00}, when the circuit delay of the pseudo critical path circuit 131 becomes longer than one clock cycle, The detection signal Q output from the mask circuit 82 changes (decreases) for the first time. The frequency adjustment operation of the PLL circuit 10 is performed according to this change. Actually, it is preferable to provide a time margin in anticipation of the time required for the control. Therefore, by shifting the mask signal M to the left by TH bits, the number of upper bits to be masked is reduced, and the value of the detection signal Q changes earlier.

  Even if it is desired to manufacture a circuit so that the circuit delay of the variable delay line 141 is equal to one clock cycle, it is difficult to realize a circuit delay equal to one clock cycle due to the influence of process variations and wiring variations. Therefore, it is desirable to set the circuit delay of the variable delay line 141 to be equal to one clock cycle by an initialization operation performed in advance. This initial setting operation will be described later.

  FIG. 16 is a diagram illustrating an example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 16 realizes a desired delay time by cascading a plurality of even-numbered inverters 151. In this circuit configuration, a pseudo-critical path circuit in which gate delay is dominant can be realized by a relatively simple circuit.

  FIG. 17 is a diagram illustrating another example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 17 includes an inverter 152, a plurality of NOR circuits 153, a plurality of AND circuits 154, and a plurality of NAND circuits 155. Here, the logic circuit formed by one NOR circuit 153 and two AND circuits 154 is a composite logic circuit of 2AND-2OR inverter output. These logic gates are appropriately combined and cascade-connected to realize a desired delay time. In this circuit configuration, a pseudo-critical path circuit in which gate delay is dominant is realized by combining various logic gates as in the actual critical path, and a circuit delay that behaves closer to the actual critical path circuit delay is realized. can do.

  FIG. 18 is a diagram showing another example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 18 realizes a desired delay time by alternately cascading a plurality of even-numbered inverters 156 and a plurality of resistance elements 157. In this circuit configuration, a pseudo-critical path circuit in which wiring delay is dominant can be realized by a relatively simple circuit.

  FIG. 19 is a diagram showing another example of the configuration of the pseudo critical path circuit. The pseudo critical path circuit shown in FIG. 19 includes an inverter 158, a plurality of NOR circuits 159, a plurality of AND circuits 160, a NAND circuit 161, and a plurality of resistance elements 162. Here, the logic circuit formed by one NOR circuit 159 and two AND circuits 160 is a composite logic circuit of 2AND-2OR inverter output. A desired delay time is realized by appropriately combining these logic gates and resistance elements and cascade-connecting them. In this circuit configuration, a pseudo-critical path circuit where the wiring delay is dominant is realized by combining various logic gates like the actual critical path, and a circuit delay that shows behavior closer to the actual critical path circuit delay is realized. can do.

  FIG. 20 is a flowchart illustrating an example of a setting operation by the control circuit. Before the electronic circuit shown in FIG. 13 or FIG. 14 starts execution of the original intended routine processing, the electronic circuit performs the initialization procedure shown in the flowchart of FIG. For example, when the electronic circuit is a communication circuit, before the execution of the communication processing by the electronic circuit is started, the initial setting procedure shown in the flowchart of FIG. 12 is executed. After the initialization is performed, the electronic circuit executes the routine processing, and the adaptive frequency control that controls the oscillation frequency of the PLL circuit 10 according to the change in the power supply voltage VDD is executed.

  In step S21, all bits of the mask signal M are set to 1 by the control circuit 80A, and the selection signal S and the control signal R are set to 0. By setting all the bits of the mask signal M to 1, all the bits of the output of the mask circuit 82 are fixed at the value 1, and all the bits of the detection signal Q supplied to the PLL circuit 10 and the averaging unit 12 are set to the values. Fixed to 1. Thereby, the adaptive frequency control for controlling the oscillation frequency of the PLL circuit 10 is stopped.

  In step S22, the control circuit 80A acquires the circuit delay measurement value Q output from the delay monitor circuit 81A. At this time, since the selection signal S is 0, the selection circuit 142 shown in FIG. 15 selects and outputs the clock signal CK directly input without passing through the variable delay line 141. Therefore, the circuit delay measurement value Q output from the delay monitor circuit 81A is a value indicating the time difference between the clock signal CK without delay and the clock signal CK delayed by the pseudo critical path circuit 131, and the circuit of the pseudo critical path circuit 131 The value represents the delay itself. If the delay time length of the pseudo critical path circuit 131 is set to be substantially equal to the delay time length of the critical path of the logic circuit 14, the clock signal CK is used when the electronic circuit performs routine processing. Preferably, the frequency is the same as that of the clock signal. The delay time length of the pseudo critical path circuit 131 is usually designed to be slightly shorter than one clock cycle of the clock signal. The circuit delay measurement value Q is a time difference between a pulse in which a certain pulse of the clock signal CK is delayed by the pseudo critical path circuit 131 and a pulse in which the next pulse of the clock signal CK is output from the selection circuit 142 as it is. Is the measured value. If the delay time length of the pseudo critical path circuit 131 is set to, for example, N times the delay time length of the critical path of the logic circuit 14, the clock signal CK is used as an operation clock during execution of a routine process of the electronic circuit. Preferably, the frequency is N times the frequency of the signal.

  In step S23, the control circuit 80A stores the measured circuit delay value Q in the register QM. In step S24, the control circuit 80A sets the selection signal S to 1 and sets the control signal R to 0. Since the control signal R is 0, the variable delay line 141 of the delay monitor circuit 81A has the shortest delay time.

  In step S25, the control circuit 80A acquires the circuit delay measurement value Q output from the delay monitor circuit 81A. At this time, since the selection signal 1 is 0, the selection circuit 142 shown in FIG. 15 selects and outputs the clock signal CK delayed by the variable delay line 141. Therefore, the circuit delay measurement value Q output from the delay monitor circuit 81A is a value indicating the time difference between the clock signal CK delayed by the variable delay line 141 and the clock signal CK delayed by the pseudo critical path circuit 131. That is, the circuit delay measurement value Q is a time difference between a pulse in which a certain pulse of the clock signal CK is delayed by the pseudo critical path circuit 131 and a pulse in which the pulse of the clock signal CK is delayed by the variable delay line 141. Is the measured value.

  In step S26, the control circuit 80A determines whether the circuit delay measurement value Q acquired in step S3 is smaller than the circuit delay measurement value Q stored in the register QM (that is, the circuit delay measurement value acquired in step S22). Is determined. When the determination result is Yes, the processing procedure proceeds to Step S27, and when the determination result is No, the processing procedure proceeds to Step S28.

  In step S27, the control circuit 80A increases the control signal R by 1 and outputs the increased control signal R to the delay monitor circuit 81A. That is, the control circuit 80A increases the delay time length of the variable delay line 141 of the delay monitor circuit 81A by the minimum change. Thereafter, the processing procedure returns to step S25, and the subsequent processing is repeated.

  When the processing procedure reaches step S28, the measured circuit delay value Q according to the current control signal R is equal to the measured circuit delay value Q stored in the register QM. That is, the time difference between the clock pulse delayed by the pseudo critical path circuit 131 and the clock pulse in the next cycle without delay is equal to the difference between the delay time of the pseudo critical path circuit 131 and the delay time of the variable delay line 141. Has become. This means that the delay time length of the variable delay line 141 in this state is equal to one clock cycle of the clock signal CK. In this state, in step S28, the control circuit 80A determines the control signal R and outputs the determined control signal R to the delay monitor circuit 81A.

  In step S29, the control circuit 80A outputs a mask signal M in which all the bits are not 1, and starts adaptive frequency control. Here, the value of the mask signal M is a value obtained by shifting {n′b11... 11, n′b00.

  As described above, by the initial setting operation shown in FIG. 20, the variable delay line 141 can be set to have a delay time length equal to one clock cycle of the operation clock signal at the time of the routine processing of the electronic circuit. With this setting, when the circuit delay of the pseudo critical path circuit 131 becomes longer than one clock cycle, the measured circuit delay value Q becomes smaller than {n′b00... 00, n′b11. Therefore, if the value of the mask signal M is set to {n′b11... 11, n′b00... 00}, when the circuit delay of the pseudo critical path circuit 131 becomes longer than one clock cycle, The detection signal Q output from the mask circuit 82 changes (decreases) for the first time. However, by shifting the mask signal M to the left by TH bits in anticipation of the time required for the control, the number of upper bits to be masked is reduced, and the value of the detection signal Q is changed earlier.

  In the case where initialization is performed on the electronic circuit shown in FIG. 6 or 7 by the initialization operation shown in FIG. 12, an operation of changing the power supply voltage VDD is performed. On the other hand, in the case where the electronic circuit shown in FIG. 13 or FIG. 14 is initialized by the initialization operation shown in FIG. 20, the operation of changing the power supply voltage is not included. These initialization operations are usually performed at the time of the rising operation immediately after the power supply of the electronic circuit is turned on. However, there are cases where it is desired to avoid performing the operation of changing the power supply voltage at the time of such a rising operation. The electronic circuit shown in FIG. 13 or FIG. 14 is preferable in that point because it is not necessary to change the power supply voltage during the initialization operation.

  FIG. 21 is a timing chart showing an example of the setting operation by the control circuit. For example, FIG. 21 shows an example of a change in each signal value when the initial setting operation shown in FIG. 20 is executed when n = 4. In this example, TH = 2 is fixed. In the initial state, by executing step S21 shown in FIG. 20, the selection signal S is set to 0, all bits of the mask signal M are set to the value 1, and the control signal R is set to 0. I have.

  At the timing T1 shown in FIG. 21, the operations of steps S22 and S23 shown in FIG. 20 are executed, and the circuit delay measurement value Q output from the delay monitor circuit 81A with the selection signal S = 0 is stored in the register QM. You. In this example, the circuit delay measurement value Q stored in the register QM is 8b'0111_1111. That is, the measured circuit delay value Q is 8-bit data, and its value is “01111111”.

  Thereafter, at timing T2, the operations of steps S24 and S25 shown in FIG. 20 are performed. Thus, a circuit delay measurement value Q indicating the time difference between the clock signal CK delayed by the variable delay line 141 and the clock signal CK delayed by the pseudo critical path circuit 131 is obtained with the selection signal S = 1. In this example, the circuit delay measurement value Q obtained first is 8b′0000 — 0111, which is smaller than the stored value 8b′0111 — 1111 of the register QM. Therefore, the control signal R is increased by the operation of step S27 shown in FIG. As the control signal R is sequentially increased, the measured circuit delay value Q output from the delay monitor circuit 81A is also gradually increased.

  Thereafter, in response to the fact that the measured circuit delay value Q has become equal to the value stored in the register QM, the operation of step S28 shown in FIG. 28 is executed at timing T3, and the value of the control signal R is fixed at 15. . Further, at a timing T4, a value 8b'1100_0000 obtained by shifting 8b'1111_0000 to the left by TH bits (that is, 2 bits) is output as a mask signal M, and adaptive frequency control is started.

  As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the claims.

Reference Signs List 10 PLL circuit 11 AD converter 12 Averaging unit 13 Code conversion unit 14 Logic circuit 20 Digitally controlled oscillator (DCO)
Reference Signs List 21 frequency divider 22 phase comparator 23 loop filter 24 normalizer 25 adder 30 data paths 31, 32 flip-flop 33 circuit element group

Claims (11)

An oscillator for generating an oscillation signal having a cycle according to the input signal;
A voltage detector that outputs a detection signal according to the power supply voltage,
A frequency divider that generates a frequency-divided signal by dividing the frequency of the oscillation signal at a frequency division ratio corresponding to a signal obtained by time-averaging the detection signal;
A sum of a first signal corresponding to the phase difference between the frequency-divided signal and the reference signal and a second signal corresponding to the detection signal are obtained, and a signal corresponding to the sum is supplied to the oscillator as the input signal. An electronic circuit including an adder.   2. The electronic circuit according to claim 1, wherein the detection signal and the input signal are a digital code represented by a plurality of bits, and the oscillator is a digitally controlled oscillator.   2. The electronic circuit according to claim 1, further comprising a logic circuit driven by the power supply voltage, wherein the oscillation signal is applied to a clock input terminal of a flip-flop in the logic circuit. The voltage detector,
A first variable delay line for outputting a first delayed oscillation signal obtained by applying a first voltage and delaying the oscillation signal based on a first control signal, and applying a second voltage; A second variable delay line that outputs a second delayed oscillation signal obtained by delaying the oscillation signal based on a second control signal; and a second delay oscillation signal that is supplied to each clock terminal and is connected to a preceding stage. N first flip-flops, each of which receives a first delayed oscillation signal delayed by a first predetermined delay from the data input of the first flip-flop, and inputs the first delayed oscillation signal to the data input; Are respectively supplied to respective clock terminals, and the first delayed oscillation signal is respectively delayed by a second predetermined delay. A delay monitor circuit comprising n number of the second flip-flop input to the data input,
A mask circuit for outputting 2n masked output signals obtained by masking the 2n output signals output from the delay monitor circuit based on the input 2n mask signals as the detection signal;
The outputs said first control signal and a second control signal based on the detection signal, the 2n pieces of claims 1 to 3 electronic circuit according to any one claim comprises a control circuit for outputting a mask signal . The voltage detector,
A pseudo critical path circuit for applying the power supply voltage and outputting a first delayed oscillation signal obtained by delaying the oscillation signal, and a pseudo critical path circuit for applying a reference voltage and delaying the oscillation signal based on a control signal; A variable delay line that outputs a second delayed oscillation signal, and a selector that selects and outputs a third delayed oscillation signal that is either the oscillation signal or the second delayed oscillation signal based on an input selection signal. The first delayed oscillation signal is supplied to each first input terminal and the first delayed oscillation signal is delayed by a first predetermined delay from the second input terminal of the preceding first flip-flop. Delayed by a second predetermined delay from each of the n first flip-flops input to the second input terminal and the first input terminal of the preceding second flip-flop. A delay monitor circuit delays the oscillation signal of 3 and an n-number of the second flip-flop in which the first delay oscillation signal is input to the second input terminal respectively is supplied to the first input terminal, respectively,
A mask circuit for outputting 2n masked output signals obtained by masking the 2n output signals output from the delay monitor circuit based on the input 2n mask signals as the detection signal;
The outputs of the control signal based on the detection signal, the 2n pieces of claims 1 to 3 electronic circuit according to any one claim comprises a control circuit for outputting a mask signal. 6. The electronic circuit according to claim 5 , wherein the pseudo critical path circuit has a delay corresponding to a maximum operating frequency of the electronic circuit. An oscillation signal having a cycle according to the input signal to the oscillator is generated by the oscillator,
Generates a detection signal according to the power supply voltage,
Performing a frequency-divided signal generation process of generating a frequency-divided signal by frequency-dividing the oscillation signal at a frequency division ratio corresponding to a signal obtained by time-averaging the detection signal;
A sum of a first signal corresponding to the phase difference between the frequency-divided signal and the reference signal and a second signal corresponding to the detection signal are obtained, and a signal corresponding to the sum is supplied to the oscillator as the input signal. Execute input signal supply processing;
An oscillator control method including each step. Setting the first drive voltage applied to the first variable delay line and the second drive voltage applied to the second variable delay line to be equal;
With the first drive voltage and the second drive voltage being equal, a circuit delay difference between the circuit delay of the first variable delay line and the circuit delay of the second variable delay line becomes zero. Execute the adjustment process to
Applying the power supply voltage to the first variable delay line after performing the adjusting process, wherein the first variable delay line is driven by the power supply voltage and the second variable delay line is 8. The oscillator according to claim 7 , wherein a signal corresponding to said circuit delay difference is generated as said detection signal while driving with said second drive voltage to execute said divided signal generation processing and said input signal supply processing. Control method. Apply the power supply voltage and a predetermined drive voltage to the pseudo critical path circuit and the variable delay line, respectively,
Performing a process of adjusting a delay time length of the variable delay line to a length equal to one cycle of a clock signal;
Each step of measuring a circuit delay difference between the circuit delay of the pseudo critical path circuit and the circuit delay of the variable delay line after performing the adjusting process, and using a signal corresponding to the circuit delay difference as the detection signal. 8. The method of controlling an oscillator according to claim 7 , wherein the oscillator generates the divided signal and performs the input signal supply processing. The adjusting process includes:
Inputting the clock signal to the pseudo critical path circuit ,
Measuring a time difference between a first pulse of the clock signal delayed by the pseudo critical path circuit and a second pulse immediately after the first pulse of the clock signal;
10. The oscillator according to claim 9 , further comprising adjusting a delay time length of the variable delay line such that a circuit delay difference between a circuit delay of the pseudo critical path circuit and a circuit delay of the variable delay line is equal to the time difference. Control method. Said clock signal control method of an oscillator according to claim 9 or 10 wherein said oscillation signal.

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