JP6637353B2 - Pixel clock generation circuit and pixel clock generation method - Google Patents

Description

  The present invention relates to a pixel clock generation circuit that generates a pixel clock serving as a timing signal for processing each pixel of an image corresponding to image data transmitted from a transmission circuit to a reception circuit via a transmission path, and a pixel. The present invention relates to a clock generation method.

  FIG. 3A is a block diagram illustrating an example of a configuration of a receiver that is a part of a timing controller to which a conventional pixel clock generation circuit is applied. The receiver 40 shown in FIG. 3A receives image data transmitted from a transmission side circuit via a main link (Main Link) in accordance with a display port standard, and receives an image corresponding to the received image data. Is a receiving-side circuit that performs control for displaying on the image display device.

  The receiving side circuit includes a clock data recovery circuit (hereinafter, also referred to as a CDR (Clock Data Recovery) circuit) 12, a serial / parallel conversion circuit (hereinafter, also referred to as an S2P (Serial to Parallel) conversion circuit) 14, and a data extraction circuit 16. A serial-parallel and parallel-serial conversion circuit (hereinafter also referred to as S2P, P2S (Parallel to Serial) conversion circuit) 18, a control data holding circuit 20, a pixel clock generation circuit 50, an image memory 24, a display control circuit 26.

In the receiving side circuit, the CDR circuit 12 generates a recovery clock synchronized with the phase of the serial data transmitted from the transmitting side circuit via the main link.
The recovery clock is a clock having a frequency that is 1/10 of a link rate that indicates a transmission frequency of serial data transmitted from the transmission side circuit via the main link.

  Subsequently, the S2P conversion circuit 14 converts serial data transmitted from the transmission side circuit via the main link into parallel data in synchronization with the recovery clock generated by the CDR circuit 12.

Subsequently, the data extraction circuit 16 performs processing such as decoding on the parallel data converted by the S2P conversion circuit 14 in synchronization with the recovery clock, and converts the processed parallel data into image data and attribute data. Is extracted.
The attribute data includes data for determining the frequency of the pixel clock.

  The image data extracted by the data extraction circuit 16 is held in the image memory 24 in synchronization with the recovery clock.

The S2P, P2S conversion circuit 18 converts the control data transmitted from the transmission side circuit via the auxiliary channel (AUX) from serial data to parallel data.
The control data includes link rate data and the like.

  The control data of the parallel data converted by the S2P / P2S conversion circuit 18 is held in the control data holding circuit 20.

  Subsequently, based on the attribute data for determining the frequency of the pixel clock extracted by the data extraction circuit 16 by the pixel clock generation circuit 50 and the link rate control data held by the control data holding circuit 20. , A pixel clock is generated in synchronization with the recovery clock generated by the CDR circuit 12.

The frequency of the pixel clock is determined by the refresh rate and size of the image displayed on the image display device. As attribute data for determining the frequency of the pixel clock, variables M and N satisfying the relationship shown in Expression (1) are transmitted from the transmitting circuit to the receiving circuit via the main link.
Pixel clock frequency (MHz) = Link rate (MBps) * M / N Equation (1)

  The image data held in the image memory 24 is sequentially read at a timing displayed on the image display device in synchronization with the pixel clock.

  Subsequently, the display control circuit 26 generates a synchronization signal for displaying an image corresponding to the image data read from the image memory 24 on the image display device in synchronization with the pixel clock, and generates the image data and the synchronization signal. Is output.

  The image data, the pixel clock and the synchronization signal are sent to the image display device, and an image corresponding to the image data is displayed on the image display device in synchronization with the pixel clock and the synchronization signal.

Next, the pixel clock generation circuit will be described.
As an example, a case where a pixel clock is generated from a main link, M, N, and a recovery clock generated by the CDR circuit 12 as shown in FIG. 3B will be described.

  FIG. 4 is a block diagram illustrating an example of a configuration of the pixel clock generation circuit illustrated in FIG. 3B. The pixel clock generation circuit 42 shown in FIG. 4 generates a pixel clock based on a recovery clock, and includes a 1 / N frequency divider 44, a 1 / M frequency divider 46, and a phase locked loop circuit (hereinafter, referred to as a phase locked loop circuit). , And a PLL (Phase Locked Loop) circuit) 48).

In the pixel clock generation circuit 42, the recovery clock is frequency-divided into a clock having a frequency of 1 / N by a 1 / N frequency divider 44, and the pixel clock generated by the PLL circuit 48 is generated by a 1 / M frequency divider 46. Divided into 1 / M frequency clock. Then, the phase of the clock divided by the 1 / N divider 44 and the phase of the clock divided by the 1 / M divider 46 are synchronized by the PLL circuit 48. A pixel clock of the calculated frequency is generated.
Pixel clock frequency (MHz) = Recovery clock (MBps) * 10 * M / N Equation (2)
In the equation (2), the reason why the recovery clock frequency is multiplied by 10 is that the recovery clock is a clock having a frequency that is 1/10 of the link rate.

  However, since the values of M and N are very large values represented by 24 bits such as, for example, 8192, 32768, 5242898, etc., if the circuit shown in FIG. As the frequency becomes very large, the frequency of the input clock to the PLL circuit 48 may not satisfy the input frequency range of the PLL circuit 48 in some cases. Therefore, as shown in FIG. 5, a method is generally used in which a multiplication factor applied to the clock multiplication circuit is calculated in advance outside the clock multiplication circuit, and the calculated multiplication factor is applied to the clock multiplication circuit.

  FIG. 5 is a block diagram illustrating an example of a configuration of the pixel clock generation circuit illustrated in FIG. 3A. The pixel clock generation circuit 50 shown in FIG. 5 includes a link rate selection circuit 52, a multiplication rate calculation circuit 54, an input clock frequency divider 56, and a clock multiplication circuit 32.

  The control data holding circuit 20 shown in FIG. 5 has one or a plurality of registers in which a link rate that can be received by the receiving side circuit is written. The transmitting side circuit reads out these from the auxiliary channel (AUX), selects a link rate for transmission, and writes the number of the register from which the link rate has been read out to the link rate selection register via the auxiliary channel.

  Based on the control data held in the link rate selection register of the control data holding circuit 20, the link rate selection circuit 52 selects one link that is actually used from the data of the register in which the receivable link rate is written. The rate is selected. Then, the frequency division ratio L of the input clock in the input clock frequency divider 56 is determined based on the selected one actually used link rate.

Subsequently, the multiplication rate calculating circuit 54 multiplies the result of multiplying the M extracted by the data extracting circuit 16 and the L determined by the link rate selecting circuit 52 by a data extracting circuit as shown in Expression (3). By dividing by N extracted by 16, a multiplication rate to be applied to the clock multiplication circuit 32 is calculated.
Multiplier = M * L / N Equation (3)

  The input clock divider 56 divides the recovery clock into a clock having a frequency of 1 / L based on the division ratio L.

  The recovery clock is a clock having a frequency that is 1/10 of the link rate, and the higher the link rate, the higher the frequency of the recovery clock. Since the clock multiplying circuit 32 has an input frequency range, if the link rate increases and the frequency of the recovered clock becomes higher than the input frequency range of the clock multiplying circuit 32, the input clock divider 56 Thus, the recovery clock is divided into a clock having a frequency of 1 / L so that the frequency of the recovery clock falls within the input frequency range of the clock multiplication circuit 32.

  Subsequently, the clock multiplying circuit 32 multiplies the clock divided by the input clock divider 56 based on the multiplication rate calculated by the multiplication rate calculation circuit 54 to generate a pixel clock.

However, since M and N are both variables, a very large 48-bit divider is required, for example, to obtain a multiplication factor with an accuracy of 24 bits after the decimal point.
As described above, the clock multiplication circuit 32 has an input frequency range. Therefore, it is necessary to correct the recovery clock according to the link rate so that the recovery clock falls within the input frequency range of the clock multiplication circuit 32. Further, in order to calculate the multiplication rate, it is necessary to correct M and N according to the link rate.
Further, the circuit shown in FIG. 5 is based on the assumption that a recovery clock is used. Therefore, even when frames of the same image are continuously displayed, serial data must be continuously transmitted from the transmitting circuit via the main link.

  As a countermeasure, as shown in FIG. 6, as the input clock of the clock multiplying circuit 32, a fixed clock having a fixed frequency falling within the input frequency range of the clock multiplying circuit 32 is used by using an oscillator or the like without using a recovery clock. There is a way.

  FIG. 6 is a block diagram illustrating an example of a configuration of the pixel clock generation circuit illustrated in FIG. 3C. The pixel clock generation circuit 58 shown in FIG. 6 includes a link rate selection circuit 52, a multiplication rate calculation circuit 60, a fixed clock generation circuit 28, and a clock multiplication circuit 32.

  In the pixel clock generation circuit 58, the operations of the data extraction circuit 16, the control data holding circuit 20, and the link rate selection circuit 52 are the same as those of the pixel clock generation circuit 50 shown in FIG.

In the pixel clock generation circuit 58, the multiplication ratio calculation circuit 60 calculates the multiplication result obtained by multiplying one actually used link rate LINK_RATE by M by N and the fixed clock generation circuit 28 as shown in Expression (4). By dividing by a multiplication result obtained by multiplying the generated fixed clock by Y (MHz), which is a fixed frequency, a multiplication factor to be given to the clock multiplication circuit 32 is calculated.
Multiplication rate = (LINK_RATE * M) / (N * Y) ... Equation (4)

  The fixed clock generation circuit 28 generates a fixed clock having a fixed frequency.

  Subsequently, the clock multiplication circuit 32 multiplies the fixed clock generated by the fixed clock generation circuit 28 based on the multiplication ratio calculated by the multiplication ratio calculation circuit 60 to generate a pixel clock.

In the pixel clock generation circuit 58, the input clock divider 56 shown in FIG. 5 is not required, and it is not necessary to correct the recovery clock according to the link rate. Further, since the recovery clock is not used, it is not necessary to continuously transmit serial data from the transmission side circuit when displaying frames of the same image continuously.
However, since M and N are used to calculate the multiplication factor, a very large divider is also required. Further, since the fixed frequency of the fixed clock is not related to the link rate, it is necessary to correct the multiplication rate according to the fixed frequency of the fixed clock, and the calculation for that becomes complicated.

  Further, there are Patent Documents 1 to 5 as prior art documents relevant to the present invention.

JP 2000-276092 A JP 2001-92423 A JP-A-2002-305752 JP 2003-131634 A JP 2007-225863A

  An object of the present invention is to provide a pixel clock generation circuit and a pixel clock generation method that can simplify a circuit configuration and reduce the circuit scale.

In order to achieve the above object, the present invention generates a pixel clock serving as a timing signal for processing each pixel of an image corresponding to image data transmitted from a transmitting circuit to a receiving circuit via a transmission path. A pixel clock generation circuit,
A fixed clock generation circuit that generates a fixed clock of a fixed frequency;
Attribute data representing the frequency of the pixel clock itself transmitted from the transmitting side circuit to the receiving side circuit via the transmission path, and the frequency of the pixel clock based on data representing the fixed frequency of the fixed clock. Is divided by the fixed frequency of the fixed clock, thereby multiplying the fixed clock and calculating a multiplication factor for generating the pixel clock.
And a clock multiplying circuit for generating the pixel clock by multiplying the fixed clock based on the multiplication factor.

  Here, it is preferable that the attribute data representing the frequency of the pixel clock itself is real number data including an integer part and a decimal part each having a fixed bit length.

  Further, it is preferable that the attribute data representing the frequency itself of the pixel clock is serial data packetized by the transmission-side circuit.

  The attribute data representing the frequency of the pixel clock itself is converted from the serial data transmitted from the transmitting circuit to the receiving circuit via the transmission path to parallel data by a serial / parallel conversion circuit, The data is preferably extracted from the parallel data converted by the serial / parallel conversion circuit by the extraction circuit.

Further, the present invention is a pixel clock generation method for generating a pixel clock serving as a timing signal for processing each pixel of an image corresponding to image data transmitted from a transmission side circuit to a reception side circuit via a transmission path. hand,
A step of converting serial data including attribute data representing the frequency itself of the pixel clock transmitted from the transmitting circuit to the receiving circuit via the transmission path to parallel data,
Extracting attribute data representing the frequency itself of the pixel clock from the parallel data converted by the step of converting the serial data into parallel data,
Generating a fixed clock with a fixed frequency;
The fixed clock is multiplied by dividing the frequency of the pixel clock by the fixed frequency of the fixed clock based on attribute data representing the frequency itself of the pixel clock and data representing the fixed frequency of the fixed clock. Calculating a multiplication factor for generating the pixel clock;
Generating the pixel clock by multiplying the fixed clock based on the multiplication factor.

According to the present invention, it is not necessary to consider the link rate and the input frequency range of the clock multiplication circuit, so that the circuit configuration can be simplified.
Further, since the attribute data representing the frequency of the pixel clock itself is a real number and the data of the frequency of the fixed clock is fixed, the multiplication factor calculation circuit can calculate the multiplication factor by dividing the divisor by a fixed value. it can. For this reason, the circuit scale of the divider included in the multiplication rate calculation circuit can be reduced, and as a result, the circuit scale of the pixel clock generation circuit can be reduced.

FIG. 2 is a block diagram of an embodiment showing a configuration of a receiver which is a part of a timing controller to which the pixel clock generation circuit of the present invention is applied. FIG. 2 is a block diagram of an embodiment illustrating a configuration of a pixel clock generation circuit illustrated in FIG. 1. FIG. 11 is a block diagram illustrating an example of a configuration of a receiver, which is a part of a timing controller to which a conventional pixel clock generation circuit is applied. FIG. 11 is a block diagram illustrating another example of a configuration of a receiver, which is a part of a timing controller to which a conventional pixel clock generation circuit is applied. FIG. 11 is a block diagram illustrating another example of a configuration of a receiver, which is a part of a timing controller to which a conventional pixel clock generation circuit is applied. FIG. 3B is a block diagram illustrating an example of a configuration of a pixel clock generation circuit illustrated in FIG. 3B. FIG. 3B is a block diagram illustrating an example of a configuration of a pixel clock generation circuit illustrated in FIG. 3A. FIG. 3C is a block diagram illustrating an example of a configuration of a pixel clock generation circuit illustrated in FIG. 3C.

  Hereinafter, a pixel clock generation circuit and a pixel clock generation method of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block diagram of an embodiment showing a configuration of a receiver which is a part of a timing controller to which the pixel clock generation circuit of the present invention is applied. The receiver 10 shown in FIG. 1 receives image data transmitted from a transmission side circuit such as a video device via a transmission line in accordance with a display port standard, and converts an image corresponding to the received image data into a liquid crystal display. This is a receiving side circuit that performs control for displaying on an image display device such as a display.

  The display port is one of interface standards for connecting a video device or the like to an image display device, and has been formulated by a standardization organization VESA (Video Electronics Standards Association) for interface standards of video signals. In the display port, the transmission side circuit and the reception side circuit are connected by a transmission path including a main link (Main Link) of up to four lanes and an auxiliary channel (AUX).

The main link transmits, from the transmitting circuit to the receiving circuit, image data and attribute data representing the frequency itself of a pixel clock serving as a timing signal for processing each pixel of the image corresponding to the image data. Channel for
The auxiliary channel is a channel for transmitting and receiving control data for controlling a connection (link) between the transmission side circuit and the reception side circuit between the transmission side circuit and the reception side circuit in two directions.

  Serial data in which image data, attribute data, control data, and the like are packetized are transmitted and received between the transmission side circuit and the reception side circuit.

  The receiving-side circuit shown in FIG. 1 includes a pixel clock generating circuit 22 instead of the pixel clock generating circuit 58 in the conventional receiving-side circuit shown in FIG. 3C. That is, the receiving side circuit includes the CDR circuit 12, the S2P conversion circuit 14, the data extraction circuit 16, the S2P / P2S conversion circuit 18, the control data holding circuit 20, the pixel clock generation circuit 22, and the image memory 24. , A display control circuit 26.

The CDR circuit 12 detects the phase of the serial data transmitted from the transmitting side circuit via the main link, and generates a recovery clock synchronized with the detected phase of the serial data.
The recovery clock is a clock having a frequency that is 1/10 of the link rate.

  Subsequently, the S2P conversion circuit 14 converts serial data transmitted from the transmission side circuit via the main link into parallel data in synchronization with the recovery clock generated by the CDR circuit 12.

  Subsequently, the data extraction circuit 16 performs processing such as decoding on the parallel data converted by the S2P conversion circuit 14 in synchronization with the recovery clock, and converts image data, attribute data, and the like from the processed parallel data. Extract.

Subsequently, the S2P, P2S conversion circuit 18 converts the control data transmitted from the transmission side circuit via the auxiliary channel from serial data to parallel data, and converts the control data output from the control data holding circuit 20 into parallel data. Convert data to serial data.
The control data includes link rate data and the like. However, control data is not used in the present invention.

  Subsequently, the control data holding circuit 20 is, for example, a DPCD (Display Port Configuration Data) register corresponding to the display port standard, and holds the control data of the parallel data converted by the S2P / P2S conversion circuit 18. However, control data is not used in the present invention.

  Next, the pixel clock generation circuit 22 generates a pixel clock based on the attribute data extracted by the data extraction circuit 16 and representing the pixel clock frequency itself and the data representing the fixed frequency of the fixed clock.

  Subsequently, the image memory 24 holds the image data extracted by the data extraction circuit 16 in synchronization with the recovery clock, and holds the held image data in synchronization with the pixel clock generated by the pixel clock generation circuit 22. Output data.

  Subsequently, the display control circuit 26 generates a synchronization signal for displaying an image corresponding to the image data input from the image memory 24 on the image display device in synchronization with the pixel clock, and outputs the image data and the synchronization signal. Output.

  Next, FIG. 2 is a block diagram of one embodiment showing a configuration of the pixel clock generation circuit shown in FIG. The pixel clock generation circuit 22 shown in FIG. 2 includes a fixed clock generation circuit 28, a multiplication ratio calculation circuit 30, and a clock multiplication circuit 32.

  The fixed clock generation circuit 28 generates a fixed clock having a fixed frequency.

Subsequently, the multiplication rate calculation circuit 30 calculates the fixed frequency based on the attribute data representing the pixel clock frequency itself and the data representing the fixed frequency of the fixed clock generated by the fixed clock generation circuit 28, as shown in Expression (5). Then, by dividing the frequency of the pixel clock by the fixed frequency of the fixed clock, the multiplication factor for generating the pixel clock by multiplying the fixed clock is calculated.
Multiplication rate = pixel clock frequency / fixed clock fixed frequency Equation (5)

  In the case of the present embodiment, it is assumed that the data representing the fixed frequency of the fixed clock is set in advance inside the multiplication factor calculation circuit 30.

  Subsequently, the clock multiplication circuit 32 generates a pixel clock by multiplying the fixed clock generated by the fixed clock generation circuit 28 based on the multiplication factor calculated by the multiplication ratio calculation circuit 30.

  In the receiving circuit shown in FIG. 1, the operations of the CDR circuit 12, the S2P conversion circuit 14, the data extraction circuit 16, the S2P / P2S conversion circuit 18, the control data holding circuit 20, the image memory 24, and the display control circuit 26 are shown in FIG. This is the same as the case of the conventional receiving side circuit shown in FIG.

  That is, in the receiving circuit shown in FIG. 1, the CDR circuit 12 generates a recovery clock synchronized with the phase of the serial data transmitted from the transmitting circuit via the main link.

  Subsequently, the S2P conversion circuit 14 converts serial data transmitted from the transmission side circuit via the main link into parallel data in synchronization with the recovery clock.

Subsequently, the data extraction circuit 16 performs processing such as decoding on the parallel data converted by the S2P conversion circuit 14 in synchronization with the recovery clock, and performs processing such as image data and attribute data from the processed parallel data. Is extracted.
In the case of the present embodiment, the attribute data includes data representing the frequency of the pixel clock itself.

  The image data extracted by the data extraction circuit 16 is held in the image memory 24 in synchronization with the recovery clock.

  Conventionally, as shown in Table 1, 24-bit attribute data M [23: 0] and N [23: 0] respectively corresponding to the attribute data M and N for determining the frequency of the pixel clock are transmitted on the transmitting side. The signal is transmitted from the circuit to the receiving circuit via the main link. Table 1 shows the attribute data M [23: 0] and N [23: 0] transmitted from the transmitting circuit to the receiving circuit via the four lanes Lane0-3 of the main link.

  Before transmitting the attribute data, a preset 8-bit code SS is transmitted twice consecutively from the transmitting circuit to the receiving circuit via the main link. That is, in each of the four lanes Lane0-3, when the code SS is transmitted twice consecutively, it means that the attribute data is transmitted following the code SS transmitted second time.

  In Table 1, the attribute data M [23: 0] is received from the transmission side circuit via the lane Lane0 after the code SS is transmitted twice consecutively from the transmission side circuit to the reception side circuit via the lane Lane0. It is sequentially transmitted to the side circuit. In the case of Table 1, attribute data M [23:16], M [15: 8] and M [7: 0] of 8-bit parallel data are sequentially transmitted. The same applies to lanes Lane1-3.

  After the attribute data M [7: 0] is transmitted, the 24-bit attribute data N [23: 0] is sequentially transmitted from the transmitting circuit to the receiving circuit via the lane Lane3. In the case of Table 1, 8-bit attribute data N [23:16], N [15: 8] and N [7: 0] are sequentially transmitted.

  In the present embodiment, as shown in Table 2, the 24-bit attribute data representing the pixel clock frequency itself is 12-bit INTE [11: 0] and FRAC representing the integer part and the decimal part of the pixel clock frequency, respectively. [11: 0]. That is, the attribute data representing the frequency of the pixel clock itself is real data including an integer part and a decimal part each having a fixed bit length.

  In the present embodiment, as shown in Table 3, the attribute data INTE [11: 0] and FRAC [11: 0] representing the pixel clock frequency itself are replaced with the conventional attribute data M [23: 0], The data is transmitted from the transmitting circuit to the receiving circuit via the main link. Table 3 shows attribute data INTE [11: 0] and FRAC [11: 0] transmitted from the transmitting circuit to the receiving circuit via the four lanes Lane0-3 of the main link.

  Similarly, before transmitting the attribute data, a preset 8-bit code SS is transmitted twice consecutively from the transmitting circuit to the receiving circuit via the main link.

  In Table 3, after the code SS is transmitted twice consecutively from the transmission side circuit to the reception side circuit via the lane Lane0, the attribute data INTE [11: 0] and FRAC [11: 0] are transmitted to the transmission side circuit. Are sequentially transmitted to the receiving side circuit via the lane Lane0. In the case of Table 3, attribute data INTE [11: 4], INTE [3: 0], FRAC [11: 8], and FRAC [7: 0] of 8-bit parallel data are sequentially transmitted. The same applies to lanes Lane1-3.

  Note that even if the conventional attribute data M [23: 0] is transmitted and the attribute data INTE [11: 0] and the FRAC [11: 0] are transmitted separately from the attribute data M [23: 0]. Good. Further, the conventional attribute data M [23: 0] and N [23: 0] need not be transmitted. Furthermore, the number of lanes used when transmitting the attribute data INTE and FRAC, the bit length of the attribute data INTE and FRAC, and the like can be changed as necessary.

Further, the control data transmitted from the transmission side circuit via the auxiliary channel is converted from serial data to parallel data by the S2P / P2S conversion circuit 18.
The control data includes link rate data and the like. However, control data is not used in the present invention.

  The control data of the parallel data converted by the S2P / P2S conversion circuit 18 is held in the control data holding circuit 20. However, control data is not used in the present invention.

  Subsequently, the pixel clock generation circuit 22 generates a pixel clock based on the attribute data extracted by the data extraction circuit 16 and representing the pixel clock frequency itself and the data representing the fixed frequency of the fixed clock.

  In the pixel clock generation circuit 22, the multiplication factor calculation circuit 30 determines the pixel clock based on the attribute data representing the frequency of the pixel clock itself and the data representing the fixed frequency of the fixed clock generated by the fixed clock generation circuit 28. By dividing the frequency by the fixed frequency of the fixed clock, a multiplication factor for generating the pixel clock by multiplying the fixed clock is calculated.

The multiplication rate can be calculated by equation (6).
Multiplication rate = (INTE * 4096 + FRAC) / (Y * 4096)… Equation (6)
Y (MHz) is data representing the fixed frequency of the fixed clock.
In Equation (6), the reason why each of INTE and Y is multiplied by 4096 is that the calculation is performed by converting the 12-bit FRAC representing the fractional part of the frequency of the pixel clock into an integer.

When the frequency of the pixel clock is, for example, 148.5 MHz, INTE [11: 0] representing the integer part 148 and FRAC [11: 0] representing the decimal part 0.5 are expressed by the following equation (7). ) And equation (8).
INTE [11: 0] = 000010010100 ... Equation (7)
FRAC [11: 0] = 100000000000… Equation (8)

When the fixed frequency Y of the fixed clock is, for example, 50 MHz, the multiplication rate is calculated by Expression (9).
Multiplication rate = (148 * 4096 + 2048) / (50 * 4096) = 2.97… Equation (9)
In Expression (9), the value corresponding to FRAC in Expression (6) is 2048 because, similarly, a 12-bit FRAC representing the fractional part of the frequency of the pixel clock is converted into an integer to perform the operation. It is.

  Subsequently, the clock multiplication circuit 32 multiplies the fixed clock generated by the fixed clock generation circuit 28 based on the multiplication ratio calculated by the multiplication ratio calculation circuit 30 to generate a pixel clock.

In the pixel clock generation circuit 22 of the present embodiment, since it is not necessary to consider the link rate and the input frequency range of the clock multiplication circuit 32, the circuit configuration can be simplified.
Also, since the attribute data representing the frequency of the pixel clock itself is a real number and the data of the frequency of the fixed clock is fixed, the multiplication factor calculation circuit 30 calculates the multiplication factor by dividing the divisor by a fixed value. Can be. For this reason, the circuit scale of the divider included in the multiplication rate calculation circuit 30 can be reduced, and as a result, the circuit scale of the pixel clock generation circuit 22 can be reduced.

  The image data held in the image memory 24 is sequentially read at a timing displayed on the image display device in synchronization with the pixel clock.

  Subsequently, the display control circuit 26 generates a synchronization signal for displaying an image corresponding to the image data read from the image memory 24 on the image display device in synchronization with the pixel clock, and generates the image data and the synchronization signal. Is output.

  The image data, the pixel clock and the synchronization signal are sent to the image display device, and an image corresponding to the image data is displayed on the image display device in synchronization with the pixel clock and the synchronization signal.

  The present invention is not limited to the generation of the pixel clock conforming to the display port standard, and processes each pixel of the image corresponding to the image data transmitted from the transmitting circuit to the receiving circuit via the transmission path. Is applicable when generating a pixel clock for use.

  As described above, the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention.

10, 40 receiver 12 Clock data recovery circuit (CDR circuit)
14. Serial-to-parallel converter (S2P converter)
16 Data extraction circuit 18 Serial-parallel and parallel-serial conversion circuit (S2P, P2S conversion circuit)
Reference Signs List 20 control data holding circuit 22, 42, 50, 58 pixel clock generation circuit 24 image memory 26 display control circuit 28 fixed clock generation circuit 30, 54, 60 multiplication factor calculation circuit 32 clock multiplication circuit 44 1 / N divider 46 1 / M frequency divider 48 Phase locked loop circuit (PLL circuit)
52 Link rate selection circuit 56 Input clock divider

Claims (5)

A pixel clock generation circuit that generates a pixel clock serving as a timing signal for processing each pixel of an image corresponding to image data transmitted from the transmission circuit to the reception circuit via the transmission path,
A fixed clock generation circuit that generates a fixed clock of a fixed frequency;
Attribute data representing the frequency of the pixel clock itself transmitted from the transmitting side circuit to the receiving side circuit via the transmission path, and the frequency of the pixel clock based on data representing the fixed frequency of the fixed clock. Is divided by the fixed frequency of the fixed clock, thereby multiplying the fixed clock and calculating a multiplication factor for generating the pixel clock.
A clock multiplying circuit that generates the pixel clock by multiplying the fixed clock based on the multiplying factor.   2. The pixel clock generation circuit according to claim 1, wherein the attribute data representing the frequency itself of the pixel clock is real data including an integer part and a decimal part each having a fixed bit length.   3. The pixel clock generation circuit according to claim 1, wherein the attribute data representing the frequency itself of the pixel clock is serial data packetized by the transmission-side circuit.   The attribute data representing the frequency of the pixel clock itself is converted by the serial-parallel conversion circuit from the serial data transmitted from the transmission-side circuit to the reception-side circuit via the transmission path into parallel data, and the data extraction circuit 4. The pixel clock generation circuit according to claim 3, wherein the data is data extracted from the parallel data converted by the serial / parallel conversion circuit. A pixel clock generation method for generating a pixel clock serving as a timing signal for processing each pixel of an image corresponding to image data transmitted from a transmission circuit to a reception circuit via a transmission path,
A step of converting serial data including attribute data representing the frequency itself of the pixel clock transmitted from the transmitting circuit to the receiving circuit via the transmission path to parallel data,
Extracting attribute data representing the frequency itself of the pixel clock from the parallel data converted by the step of converting the serial data into parallel data,
Generating a fixed clock with a fixed frequency;
The fixed clock is multiplied by dividing the frequency of the pixel clock by the fixed frequency of the fixed clock based on attribute data representing the frequency itself of the pixel clock and data representing the fixed frequency of the fixed clock. Calculating a multiplication factor for generating the pixel clock;
Generating the pixel clock by multiplying the fixed clock based on the multiplication factor.