JP6637394B2 - Test item generation method, arithmetic unit - Google Patents

Description

  The present invention relates to a test item generation method and an arithmetic device.

2. Description of the Related Art In recent years, the operation amount of electronic devices has been increasing year by year due to multifunctionalization, and the performance of CPUs required for electronic devices has been increasing. To cope with this, the number of CPUs mounted on the electronic device is increased, and the number of CPU cores built in the CPU is increased. That is, in any case, the processing capability is improved by mounting a plurality of CPU cores on the electronic device (multi-core). When the electronic device includes a plurality of CPU cores, the operation becomes more complicated than when the electronic device includes only a single CPU core, and it is not easy to create a test item for verifying the operation.
U.S. Pat. No. 6,086,086 discloses a method for verifying a design, which extracts the resources required to execute a discrete test case or a set of related test cases for a design. Including steps. The method further includes constructing a simulation model based on the extracted resources, and executing the simulation model using only the extracted resources rather than the entire design, thereby providing a discrete test model. Testing a particular function or a group of interrelated functions represented by the case or set of related test cases to verify the design.

JP 2007-164780 A

  In the invention described in Patent Document 1, it is not possible to create an appropriate test item corresponding to a multi-core.

A test item generation method according to a first aspect of the present invention is a test item generation method for generating a test item in an arithmetic device including a plurality of CPU cores executing a plurality of tasks and a shared resource accessed by the plurality of CPU cores. Wherein the computer specifies, among the plurality of tasks, a task that accesses the shared resource; the computer classifies the plurality of tasks for each CPU core to be executed; and Specifying the execution order of the plurality of classified tasks in the CPU core; and causing the computer to execute the plurality of tasks in the specified CPU core in accordance with the execution order of the plurality of tasks and to execute the tasks on different CPU cores. Task execution in which the execution order of two or more tasks accessing the shared resource is interchanged By creating multiple columns, and generating a said test items.
An operation device according to a second aspect of the present invention includes a storage unit that stores a test item generated by the test item generation method according to the first aspect and check logic for confirming the test item.

  According to the present invention, an appropriate test item corresponding to a multicore can be created.

Diagram showing the hardware configuration of the test item generation device Diagram showing the functional configuration of the test item generation device Diagram showing the hardware configuration of the ECU Diagram showing the functional configuration of the ECU Diagram showing overview of test item generation The figure which shows an example of operation | movement of a test item generation part. Flow chart showing the operation of the test item generation unit The figure which shows the functional structure of the test item generation apparatus in the modification 2.

(First Embodiment)
Hereinafter, a first embodiment of a test item generation device 100 using a test item generation method according to the present invention will be described with reference to FIGS. The test item generation device 100 generates test items used in a test executed by the ECU 200 described later. In the present embodiment, the components of the computer program are called “tasks”. A task is composed of one or more CPU instructions. A task is executed by any one of the CPU cores, and some tasks require access to a shared resource 203 described later. The order in which a plurality of tasks are executed is referred to as a “task execution sequence”. In the present embodiment, the test item is composed of two or more task execution permutations. That is, the test executed in ECU 200 is to execute predetermined tasks in a predetermined order according to the generated test items.

(Hardware configuration of test item generation device)
FIG. 1 is a diagram illustrating a hardware configuration of the test item generation device 100. The test item generation device 100 includes a CPU 101, a ROM 102, a RAM 103, and an interface 104. The CPU 101 controls the operation of the test item generation device 100. The CPU 101 realizes functions described later by expanding a program (not shown) stored in the ROM 102 into the RAM 103 and executing the program. The RAM 103 is used for storing a working area when the above-described program is executed and a generated test item. The interface 104 is an input / output port for electronic data, and exchanges information between the test item generation device 100 and another device. The test item generation device 100 acquires input information 6 necessary for generating a test item via the interface 104. The input information 6 is a source code of a program, a design document, reverse engineering information of a CPU that executes the program, a test document, and the like, and includes a plurality of tasks executed by the CPU core of the ECU 200.

(Functional configuration of test item generation device)
FIG. 2 is a diagram illustrating a functional configuration of the test item generation device 100. Each function illustrated in FIG. 2 is realized by the CPU 101 executing a program stored in the ROM 102. The test item generation device 100 includes, as its functions, a correspondence information unit 111, a specific information unit 112, an order information unit 113, and a test item generation unit 114. In the RAM 103, a correspondence information storage area 121, a specific information storage area 122, an order information storage area 123, and a test item storage area 124 are provided. Here, an outline of each function will be described, and details of each function will be described later.

The correspondence information storage area 121, the specific information storage area 122, the order information storage area 123, and the test item storage area 124 are storage areas provided in the RAM 103.
The correspondence information unit 111 analyzes the input information 6 read from the interface 104, specifies which CPU core of the ECU 200 executes each of the plurality of tasks included in the input information 6, and executes the CPU to be executed. Classify tasks by core. Then, correspondence information indicating the task classification result is generated. The correspondence information generated by the correspondence information unit 111 is stored in the correspondence information storage area 121. The specific information unit 112 analyzes the input information 6 and specifies which of the tasks included in the input information 6 is a task that accesses a shared resource 203 described later. Then, specific information indicating the specified task is generated. The specific information generated by the specific information section 112 is stored in the specific information storage area 122.

The order information unit 113 analyzes the input information 6 and specifies the execution order of the tasks executed by the same CPU core. Then, it generates order information indicating the execution order of the tasks executed by the same CPU core, which is the specified information. The order information generated by the order information unit 113 is stored in the order information storage area 123. The order information may indicate an execution order of tasks for each CPU core, or may indicate a mixture of tasks executed by a plurality of CPU cores.
The test item generation unit 114 generates test items based on the information generated by the correspondence information unit 111, the specific information unit 112, and the order information unit 113, and stores the generated test items in the test item storage area 124. The test items generated by the test item generation unit 114 are output to the ECU 200 via the interface 104.

All of the correspondence information section 111, the specific information section 112, and the order information section 113 are easy to process when the source code is the input information 6. When a design document or a test document is used as the input information 6, the correspondence information section 111, the specific information section 112, and the order information section 113 perform a search equivalent to the source code by utilizing lexical analysis or the like. Further, in the analysis of the document, the lexical analysis can be made unnecessary according to the specification of the document format.
The specific information unit 112 analyzes the source code and specifies a task that accesses the shared resource 203. The specific information unit 112 recursively searches not only the task that directly accesses the shared resource 203 but also the call of the task. A task that indirectly accesses 203 is also specified. For indirect access, the range of search may be limited by designating the number of task calls.

(ECU hardware configuration)
FIG. 3 is a diagram illustrating a hardware configuration of the ECU 200. The ECU 200 includes a first core 201, a second core 202, a shared resource 203, a ROM 204, a RAM 205, and a test item input unit 206. The first core 201 and the second core 202 are CPU cores provided in the ECU 200. ECU 200 may include a plurality of CPUs having a single core, or may include a CPU having a plurality of cores. The shared resource 203 is a resource accessed from the first core 201 and the second core 202, and is, for example, one of an area of the RAM 205, a register of a CPU provided in the ECU 200, an actuator, a sensor, and a communication bus (not shown). It is. The test item input unit 206 is an input / output port for electronic data, and receives a test item generated by the test item generation device 100.

(Functional configuration of ECU)
FIG. 4 is a diagram showing a functional configuration of the ECU 200. Each function illustrated in FIG. 4 is realized by the first core 201 or the second core 202 executing a program stored in the ROM 204. The ECU 200 includes a normal mode unit 211, an operation verification mode unit 212, a mode switching unit 213, and a test execution data storage area 215 as its functions. The ECU 200 receives the test item input from the interface 104 of the test item generation device 100 at the test item input unit 206. ECU 200 stores the received test item in test execution data storage area 215. The ECU 200 also stores the check logic for checking the execution result of the test item in the test execution data storage area 215. This check logic may be created by the operator or the test item generation device 100.

The ECU 200 has two operation modes: a normal mode and an operation verification mode. The ECU 200 activates one of the normal mode and the operation verification mode according to an operation command of the mode switching unit 213 operated by the user 3. When the normal mode is valid, the normal mode unit 211 controls the operation of the ECU 200, and when the operation verification mode is valid, the operation verification mode unit 212 controls the operation of the ECU 200.
The normal mode unit 211 performs various arithmetic processes based on an input from a sensor (not shown) provided in the ECU 200 or a communication interface (not shown). The operation verification mode unit 212 sequentially executes each of the plurality of task execution permutations constituting the test item stored in the test execution data storage area 215, and compares the execution result with the check logic. The operation verification mode unit 212 may be configured to store the collation result in a storage unit (not shown) and access the collation result from outside. In addition, the operation verification mode unit 212 may notify the collation result using a notification unit included in the ECU 200 or a device to which the ECU 200 is connected, for example, a speaker or a light.

(Overview of test item generation)
FIG. 5 is a diagram illustrating an outline of test item generation by the test item generation device 100.
Source code 4001 is a source code of a program executed in ECU 200. As shown by reference numerals 4002 to 4007, the source code 4001 includes detailed information on the tasks f1 to f6 constituting the program, for example, whether or not each task accesses the shared resource 203. The source code 4001 includes information on the CPU cores on which each task is executed, and information on the order in which each task is executed on each CPU core. Note that the execution order of tasks executed by different CPU cores may be changed each time the execution is performed, and the source code 4001 describes only the execution order of tasks executed by the same CPU core. .

When the source code 4001 is input to the test item generation device 100 as the input information 6, the correspondence information unit 111 analyzes the source code 4001 and specifies a CPU core on which each task is executed as indicated by reference numeral 4009. That is, among the tasks f1 to f6 included in the test items, it is specified that the tasks of f1, f3, and f5 are executed by the first core 201, and the tasks of f2, f4, and f6 are executed by the second core 202.
The specific information unit 112 analyzes the source code 4001 and, as indicated by the reference numeral 4008, finds that among the tasks f1 to f6 included in the test items, the tasks that access the shared resource 203 of the ECU 200 are f3 and f4. Identify.

The order information unit 113 analyzes the source code 4001 and specifies, as indicated by reference numeral 4010, order information indicating the execution order of tasks executed by the same CPU core. Although FIG. 5 shows the execution order of tasks for each CPU core, the execution order may be shown in a state where tasks executed by a plurality of CPU cores are mixed. For example, the execution order of the tasks “f1, f2, f3, f4, f5, f6” may be specified as the order information.
The test item generation unit 114 generates a task execution permutation based on the information generated by the correspondence information unit 111, the specific information unit 112, and the order information unit 113, that is, information indicated by reference numerals 4008, 4009, and 4010. The test item generation unit 114 adapts the execution order of the plurality of tasks in the specified CPU core, and interchanges the execution order of the tasks f3 and f4 accessing the shared resources 203 respectively executed by different CPU cores. A plurality of task execution permutations, here two, are generated and stored as test items in the test item storage area 124 as indicated by reference numeral 4012. As a result, in the test item generation device 100, test items including the tasks f1 to f6 are created.

(Operation example of test item generation unit)
In the example shown in FIG. 5, since there are only two tasks for accessing the shared resource 203, the operation of the test item generation unit 114 will be described using a slightly more complicated example. Here, when the tasks f2, f3, f5, and f7 are executed by the first core 201, the tasks f4 and f6 are executed by the second core 202, and the f2 to f6 access the shared resource 203, the test item generation unit The test items generated by 114 will be described. Here, it is assumed that a task with a smaller number is executed in the same CPU core. In the following, the order in which a task and an execution sequence to be described later are executed is expressed using a right arrow “→”. For example, the execution of the task f3 after the task f2 is represented as “f2 → f3”.

  First, the test item generation unit 114 specifies the order in which the tasks that access the shared resource 203 are executed for each CPU core, and generates an execution sequence. The execution sequence is a task executed in the same CPU core, and is a task in which a plurality of tasks accessing the shared resource 203 are arranged in the execution order of the task indicated by the order information stored in the order information storage area 123. It is. Here, the generated execution sequences are referred to as α and β. The same number of execution sequences as the number of CPU cores are generated. The fact that the execution sequence α is composed of f2, f3, and f5 is hereinafter referred to as α0 (f2, f3, f5). Similarly, the execution sequence β is β0 (f4, f6).

Hereinafter, the procedure in which the test item generation unit 114 generates the task execution sequence will be continued with reference to FIG.
Next, the test item generation unit 114 creates a permutation using all the generated execution sequences, that is, all the orders that can be rearranged using all the generated execution sequences. In this example, as shown in the undeveloped column of FIG. 6, two items of α → β and β → α are created. Hereinafter, each of the created permutations is referred to as a “permutation element”.

  Then, the test item generation unit 114 expands α and β for each of the generated permutation elements, and increases the permutation elements that are variations of the execution order. For example, the development of α means that the head task among tasks constituting α is separated, and the number of separated tasks is added to the name of α. That is, α0 (f2, f3, f5) is expanded to f2 → α1 (f3, f5). Since the elements constituting the permutation elements are increased by this expansion, further rearrangement becomes possible. Note that, here, the expansion of the permutation element is also referred to as a “permutation element”, but may be referred to as an “expansion sequence”. Also, here, an example is shown in which the first task forming the execution sequence is separated, but the last task forming the execution sequence may be separated.

  Therefore, as one of the permutation elements, α → β, as shown in the column of “α expansion first time” in FIG. 6 by expanding α once, f2 → α1 (f3, f5) → β, f2 → β → α1 (f3, f5). When α is further expanded, the permutation elements α → β are expanded into a total of three as shown in the “α second expansion” column in FIG. 6. At this time, α2 (f5) obtained by expanding α0 (f2, f3, f5) twice is f5 itself, and cannot be expanded any further. Therefore, the next step is to expand β.

The permutation elements α → β are further expanded to β to develop a total of five as shown in the column of “first β expansion” in FIG. At this time, β1 (f6) obtained by expanding β0 (f4, f6) once is f6 itself, and cannot be further developed. Thus, the expansion processing of the permutation element of α → β is completed.
The test item generation unit 114 expands the permutation element β → α in the same manner as the expansion of the permutation element α → β described above. Since this processing is the same as the expansion of the permutation element α → β, the description and the illustration in FIG. 6 are omitted.

  The execution order of the task f7 that does not access the shared resource 203 is added to the permutation element generated in this manner, and is set as a task execution permutation. The execution order of the tasks that do not access the shared resource 203 is any one in accordance with the execution order in the same CPU core. For example, if the execution order excluding f7 is f2 → f3 → f5 → f4 → f6, since the execution order of f7 is after f5 executed by the same CPU core, insert f5 immediately after f5, f4, and f6. be able to. That is, in this case, it is possible to generate three execution orders depending on the insertion place of f7, but only one of the three is adopted to be a task execution sequence, that is, one of the test items. This is because a change in the execution order of tasks that do not access the shared resource 203 does not affect the test.

(Flowchart of test item generation unit)
FIG. 7 is a flowchart illustrating the operation of the test item generation unit 114. The subject of execution of each step of the flowchart described below is the CPU 101 of the test item generation device 100.
In step S301, a task that accesses the shared resource 203 is specified for each CPU core with reference to the outputs of the correspondence information unit 111 and the specific information unit 112. In the subsequent step S302, the execution order of the task accessing the shared resource 203 is specified for each CPU core with reference to the output of the order information unit 113.

  In a succeeding step S303, an execution sequence is generated. As described above, the execution sequence is a task that is executed by the same CPU core, and a plurality of tasks that access the shared resource 203 are stored in the execution order of the tasks indicated by the order information stored in the order information storage area 123. They are arranged. That is, in step S303, the same number of execution sequences as the number of CPU cores are generated. In a succeeding step S304, a permutation of the execution sequence, that is, a plurality of permutation elements is created. The number of permutation elements created here is a factorial of the number of execution sequences generated in step S303. This is because there is no restriction on the order of execution of tasks executed by different CPU cores. In the example of FIG. 6, this corresponds to creation of α → β and β → α.

  In a succeeding step S305, a first execution sequence, for example, α is set as a development target. In a succeeding step S306, the first task is developed from the execution sequence to be developed. In the example of FIG. 6, this corresponds to developing α0 (f2, f3, f5) into f2 → α1 (f3, f5). In a succeeding step S307, a permutation element including the order permutation accompanying the expansion in the step S306 is generated. In a succeeding step S308, it is determined whether or not the execution sequence to be expanded can be further expanded. If it is determined that further expansion is possible, the process returns to step S306. If it is determined that further expansion is not possible, the process proceeds to step S309. In the example of FIG. 6, after the second α-expansion or the first β-expansion, the process proceeds to step S309.

  In step S309, it is determined whether or not there is an unexpanded execution sequence. If it is determined that there is an unexpanded execution sequence, the process proceeds to step S310. If it is determined that there is no unexpanded execution sequence, the process proceeds to step S311. In step S310, one of the undeployed execution sequences is set as a development target, and the process returns to step S306. In step S311, a task that has not accessed the shared resource 203 is added to the permutation element, and is set as a task execution permutation. As a result, task execution sequences can be generated for all combinations of the execution orders of the tasks f2, f4, and f6 and the tasks f3 and f5 that are executed by different CPU cores and that access the shared resource 203. In a succeeding step S312, the generated task execution sequence is stored in the test item storage area 124, and the flowchart of FIG. 7 ends.

According to the first embodiment, the following operation and effect can be obtained.
(1) An arithmetic device including a plurality of CPU cores for executing a plurality of tasks and a shared resource 203 accessed by the plurality of CPU cores, that is, a test item generation method for generating test items in the ECU 200 includes the following test items: The process is executed by the generation device 100. This test item generation method includes the following four items. The first is to specify a task that accesses the shared resource 203 among a plurality of tasks executed by the specifying information unit 112. Second, a plurality of tasks executed by the correspondence information unit 111 are classified for each CPU core to be executed. Third, the order of execution of a plurality of classified tasks in the CPU core, which is executed by the order information unit 113, is specified. Fourth, two or more tasks that match the execution order of a plurality of tasks in the specified CPU core and are executed by the test item generation unit 114 and that access the shared resources 203 that are respectively executed by different CPU cores Is to generate a test item by generating a plurality of task execution permutations in which the execution order of the task is replaced with each other.
Therefore, since the test items in which the execution order of the task for accessing the shared resource 203 is replaced are created, an appropriate test item corresponding to the multi-core can be created.

(2) In the generation of test items of the test item generation device 100, task execution sequences are generated for all combinations of execution orders of tasks that are executed by different CPU cores and that access the shared resources 203, respectively.
Therefore, even if the number of tasks is large and the number of combinations is enormous, test items without omission can be created.

(3) The test item generation by the test item generation unit 114 includes the following five items. The first is to generate an execution sequence in which tasks executed in the same CPU core are arranged in the execution order in the specified CPU core (step S303 in FIG. 7). The second is to generate a permutation of a plurality of execution sequences (step S304 in FIG. 7). Third, for each of the permutations, the execution sequence is expanded by separating the first or last task constituting the execution sequence from the execution sequence, and the expanded execution sequence and the execution order of the separated tasks are maintained. This is to generate one or a plurality of expanded sequences that are generated by changing the order of all other execution sequences and other tasks (steps S306 and S307 in FIG. 7). Fourth, generation of an expanded sequence is repeated until the execution sequence cannot be expanded for each of the expanded sequences (repeated until a negative determination is made in step S308 in FIG. 7). Fifth, each of a plurality of expanded sequences generated by repetition, in which the execution sequence cannot be expanded, is set as the task execution sequence (step S312 in FIG. 7).
Therefore, even if the number of tasks is large and the number of combinations is enormous, it is possible to create test items without omission by repeatedly generating the permutation of the execution sequence and generating the expansion sequence.

(4) The arithmetic unit, that is, the ECU 200, includes a storage unit that stores the test items generated by the above-described test item generation method and check logic for confirming the test items, that is, a test execution data storage area 215.
Therefore, the ECU 200 can execute the test items in the actual ECU 200 and check the test result using the check logic. This test item is generated by the test item generation device 100, and is a test item in which the access order of each task to the shared resource 203 is not confirmed in the same order.

(5) The arithmetic device, that is, the ECU 200, includes an operation verification mode unit 212 that sequentially executes each of a plurality of task execution permutations constituting a test item, and a mode switching unit 213 that operates the operation verification mode unit 212. Therefore, ECU 200 can execute the test by switching the operation mode.

(Modification 1)
The correspondence information unit 111, the specific information unit 112, and the order information unit 113 store the input information 6 that has been input previously, and when the newly input information 6 matches the input information 6 that has been input previously. The analysis results stored in the respective storage areas may be output to the test item generation unit 114. According to the first modification, when there is no change in the input information 6, the analysis can be omitted. The effect of this modification is that the information input to the correspondence information section 111, the specific information section 112, and the order information section 113 are different from each other, and when only some of them are changed, This is remarkable when only the order is changed.

(Modification 2)
FIG. 8 is a diagram illustrating a functional configuration of the test item generation device 100 according to the second modification. The test item generation device 100 may further include a correspondence information change point analysis unit 131, a specific information change point analysis unit 132, an order information change point analysis unit 133, and a change point test item generation unit 134.
The correspondence information change point analysis unit 131 analyzes a change point of the input information 6, refers to the correspondence information stored in the correspondence information storage area 121, and converts the correspondence information relating to the changed part of the input information 6 to a change point test item. Output to the generation unit 134. The specific information change point analysis unit 132 analyzes the change of the input information 6, refers to the specific information stored in the specific information storage area 122, and converts the specific information related to the changed part of the input information 6 into a change test item. Output to the generation unit 134. The sequence information change point analysis unit 133 analyzes the change point of the input information 6, refers to the sequence information stored in the sequence information storage area 123, and changes the sequence information relating to the changed part of the input information 6 to a change point test item. Output to the generation unit 134.

The change point test item generation unit 134 outputs the output of the correspondence information change point analysis unit 131, the specific information change point analysis unit 132, and the order information change point analysis unit 133, and the test items stored in the test item storage area 124. To generate only those test items that need to be modified. Then, the changed point test item generation unit 134 updates the test items stored in the test item storage area 124.
According to the second modification, when the input information 6 is slightly changed, the processing of the test item generation device 100 can be reduced.

Although the program executed by the test item generation device 100 is stored in the ROM (not shown), the program may be stored in the RAM 103 or a flash memory (not shown). Further, the test item generating apparatus 100 may use the interface 104 to read a program from another apparatus via a medium that can be used by the interface 104 when necessary. Here, the medium refers to, for example, a storage medium detachable from an input / output interface, or a communication medium, that is, a network such as a wired, wireless, or optical network, or a carrier or a digital signal that propagates through the network. In addition, some or all of the functions realized by the program may be realized by a hardware circuit or an FPGA.
The above-described embodiments and modifications may be combined with each other.
Although various embodiments and modified examples have been described above, the present invention is not limited to these contents. Other embodiments that can be considered within the technical idea of the present invention are also included in the scope of the present invention.

100: test item generation device 111: correspondence information section 112: specific information section 113: order information section 114: test item generation section 124: test item storage area 201: first core 202: second core 203: shared resource 212: operation Verification mode unit 213 ... mode switching unit 215 ... test execution data storage area

Claims (5)

A test item generation method for generating a test item in an arithmetic device including a plurality of CPU cores executing a plurality of tasks and a shared resource accessed by the plurality of CPU cores,
A computer identifying, among the plurality of tasks, a task that accesses the shared resource;
A computer classifying the plurality of tasks for each CPU core to be executed;
A computer specifying an execution order in the CPU core of the classified tasks;
A task in which the computer conforms to the execution order of the plurality of tasks in the specified CPU core, and the execution order of two or more tasks each accessing the shared resource executed by a different CPU core is switched. Generating a test item by generating a plurality of execution permutations. The test item generation method according to claim 1,
In the test item generation method, a test item generation method for generating a task execution sequence for all combinations of execution orders of tasks that are executed by different CPU cores and that access the shared resources. The test item generation method according to claim 1,
The generation of the test item includes:
Generating a plurality of execution sequences in which the tasks executed in the same CPU core are arranged in the execution order based on all of the plurality of tasks; and generating a permutation of the plurality of execution sequences.
For each of the permutations, expand the execution sequence by separating the first or last task constituting the execution sequence from the execution sequence, and change the execution order of the expanded execution sequence and the separated tasks. Generating one or more expanded sequences, which are generated by changing the order of all other execution sequences and other tasks while maintaining them,
For each of the expansion sequences, repeating generation of the expansion sequence until the execution series can not be expanded,
Setting each of the plurality of expanded sequences generated by the repetition, in which the execution sequence cannot be expanded, as the task execution sequence.   An arithmetic unit including a storage unit that stores a test item generated by the test item generation method according to claim 1 and check logic for confirming the test item. The arithmetic unit according to claim 4,
An operation verification mode unit for sequentially executing each of the plurality of task execution permutations constituting the test item,
An arithmetic unit further comprising: a mode switching unit that operates the operation verification mode unit.

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