JP6664105B2 - Method, system, and computer program for accessing data in memory - Google Patents

Description

  The present invention relates generally to accessing memory by a processor, and more particularly, to accessing blocks of data in memory atomically, or block concurrently, by a processor.

  Scalar code expects the central processing unit (CPU) executing the code to access all bytes of the software variable as a whole. In a typical architecture for a CPU, such expectations for scalar code are met only if the access is performed to a memory boundary that is an integer multiple of the size of the data being accessed. When scalar code is vectorized by a compiler, load and store instructions are often translated into vector load and store instructions. However, vector load and vector store instructions often have no guarantee of consistency, i.e., if the vector load or store instruction is on a boundary that is the size of a vector register in the CPU. Only consistency is guaranteed. For non-atomic or block-simultaneous accesses, if one CPU writes data and another reads data at the same time, the CPU that is reading the data will access the memory location containing the variables of the latter CPU. It is possible to see partial updates. It is not consistent with the semantics of most programming languages or with programming techniques such as lock-free data structures.

z / Architecture Principles of Operation, SA22-7832-09 (10th ed. Sept. 2012) Power ISA (Version 2.06 RevisionB, Jul. 2010)

  Methods, systems, and computer programs for accessing data in a memory are provided.

  Embodiments include methods, systems, and computer program products for accessing data in a memory. According to one embodiment of the invention, there is provided a method for accessing data in a memory coupled to a processor. The method receives a memory reference instruction for accessing data of a first size at an address in memory. The method determines the alignment size of the address. This method accesses data of the first size in units of 11 or more groups of data by accessing each group of data simultaneously in blocks. The group of data has a size that is a multiple of the alignment size.

  According to another embodiment of the present invention, there is provided a system for accessing data. The system includes a memory and a processor configured to perform a method. The method receives a memory reference instruction for accessing data of a first size at an address in memory. The method determines the alignment size of the address. The method accesses data of a first size in units of one or more groups of data by accessing each group of data simultaneously in blocks. The group of data has a size that is a multiple of the alignment size.

  According to a further embodiment of the present invention, there is provided a computer program product for accessing data in a memory. The computer program product comprises a computer-readable storage medium having embodied machine instructions. The machine instructions, which are readable by the processor, cause the processor to perform a method. The method receives a memory reference instruction for accessing data of a first size at an address in memory. The method determines the alignment size of the address. The method accesses data of a first size in units of one or more groups of data by accessing each group of data simultaneously in blocks. The group of data has a size that is a multiple of the alignment size.

  According to a further embodiment of the present invention, there is provided a system for accessing data. The system includes a memory and a processor configured to perform a method. The method receives a memory reference instruction for accessing data of a first size at an address in memory. This memory reference instruction specifies a first size. The method determines the alignment size of the address. The method determines a greatest common divisor of the first size and the determined alignment size. The method accesses data of the first size in units of one or more groups of data. The group of data has a size that is a multiple of the size of the greatest common divisor.

  According to a further embodiment of the present invention, there is provided a computer program product for accessing data in a memory. The computer program product comprises a computer-readable storage medium having embodied machine instructions. The machine instructions, which are readable by the processor, cause the processor to perform a method. The method receives a memory reference instruction for accessing data of a first size at an address in memory. This memory reference instruction specifies the first size. The method determines the alignment size of the address. The method determines a greatest common divisor of the first size and the determined alignment size. The method accesses data of the first size in units of one or more groups of data. The group of data has a size that is a multiple of the size of the greatest common divisor.

  The subject matter that is regarded as an embodiment is particularly pointed out and distinctly claimed in the claims at the conclusion of this specification. These and other features and advantages of the embodiments will be apparent from the following detailed description, which should be read in conjunction with the accompanying drawings.

4 is an illustration of a portion of a memory having naturally aligned blocks according to some embodiments of the present invention. FIG. 4 is a diagram of a portion of a memory accessed in accordance with some embodiments of the present invention. FIG. 4 is a process flow diagram for accessing a memory according to some embodiments of the present invention. FIG. 4 is a process flow diagram for accessing a memory according to some embodiments of the present invention. 1 is an illustration of a system for accessing data in a memory according to some embodiments of the invention.

  Some programming language conventions state that every byte of a block of data in memory (eg, a variable of a native type, such as an integer, float, long, double, etc.) is stored by a processor (eg, a central processing unit (CPU)). Require that they be accessed at the same time. Accessing bytes of a block at the same time means that either the original value or the updated value is accessed and the mixture of the two values is not accessed. For example, when a block of data has the value "1234" and this value is being updated to "5678", only one of these two values is the correct value to fetch. Any partially updated value (e.g., "1278" or "5634") that may result from accessing a block of data asynchronously is not the correct value to fetch. This simultaneous access request is referred to as "block concurrency" in the present disclosure. Accessing a memory “block-simultaneously” or accessing a memory “block-simultaneously” means that the mode in which data in the memory is accessed satisfies the block concurrency. In conventional programming languages and processors, simultaneous block access to a block of data only occurs when the block is "naturally aligned", i.e., the address of the block is a multiple of the block's data type size. Guaranteed only when responding.

  2, 4, 8, 16 and 32 byte fields are given special names. A halfword is a group of two consecutive bytes. A word is a group of four consecutive bytes. A doubleword is a group of consecutive 8 bytes. A quadword is a continuous 16-byte group. An octoword is a continuous 32-byte group. When a memory address specifies "naturally aligned" halfwords, words, doublewords, quadwords, and octowords, the binary representation of that address is 1, 2, 3, 4, and 5 right-most zeros Include each bit. Halfwords, words, doublewords, or quadwords are referred to as blocks in the present disclosure.

  For some instructions that refer to data in memory, all the words in halfwords, words, doublewords, or quadwords will appear to be seen by other processors and the channel program as being block-simultaneous. Access to the byte is specified. When a fetch-type reference is specified to make it appear to be concurrent within a block, another processor or channel program can use the bytes contained in that block while one processor is fetching it. No store access to the block by is allowed. When a store type reference is specified to make it appear concurrent within a block, while a byte inside that block is being stored by one processor, it may be stored by another processor or channel program. Access to the block, either fetch type or store type, is not allowed. According to the traditional instruction set architecture, a single operand reference (eg, a single value is loaded into a single register, or a single operand is used by one instruction) If the specified address is on an integral boundary, it has a block concurrency corresponding to its operand size (ie, the size of the data being accessed). If the address specified in the operand is not on an integer boundary, the operand is block-simultaneous, corresponding to a size of only one byte.

  In conventional processors, all eight bits of a byte are always referred to as a whole, which is referred to as byte concurrency. Thus, block concurrency represents different levels of byte concurrency. For example, block concurrency for a 4-byte data block may be referred to as 4-byte concurrency. Further, when the memory is accessed with 4-byte concurrency, all four bytes of the 4-byte data block are accessed simultaneously as one unit, so that two 2-byte data blocks and four 1-byte data A block is a 2-byte simultaneous and a 1-byte simultaneous, respectively.

  Block-simultaneous memory operations are also called atomic operations related to memory references. A memory reference is considered block-simultaneous when all bytes within an integer block are accessed as a unit, as seen by other processors. An integer block is a block of data whose address is an integer multiple of the block length. An integer block is on an integer boundary, and the address of the first byte of the block is on an integer boundary.

  FIG. 1 illustrates a portion of memory having addresses that specify "naturally aligned" blocks. In particular, the figure shows bars 102-112 representing "naturally aligned" halfwords, words, doublewords, quadwords, and octowords, respectively. As illustrated, the memory is viewed as a long horizontal string of bits. The string of bits is further divided into units of bytes (ie, 8 bits). Each byte position in memory is identified by a unique non-negative integer, which is the address of that byte position.

  Bar 102 represents a memory having a block of one byte data. Each rectangle in bar 102 represents a block of one-byte data. The number included in each rectangle is the offset of the byte block from the base address (corresponding to the address of the first element labeled offset 0). Each byte can be accessed (ie, fetched from or stored in memory) using the address and an offset therefrom. In some embodiments, the memory is accessed block-concurrently (ie, byte-concurrent), at least at the byte level. Further, if the address of the first byte of data being accessed is an integer boundary for a larger block size, then access to the larger block will also be block synchronous with respect to that block size. Can be

  Bar 104 represents a memory having a naturally aligned block of 2-byte data. Each of the two-byte blocks is addressed using a multiple of two, all of the two-byte data blocks are integer blocks, and are accessed concurrently using a two-byte block size. obtain. Similarly, the 4-byte data block at bar 106, the 8-byte data block at bar 108, the 16-byte data block at bar 110, and the 32-byte data block at bar 112 are all integer blocks. , Access to these data blocks can be performed block-simultaneously for 4-byte, 8-byte, 16-byte, and 32-byte blocks.

In this disclosure, the address alignment size of a memory address is the size of the largest integer block addressable by that address, ie, the largest divisor of that address that is a power of two. For example, the address alignment size of address 96 is 32 (ie, 2 ⁵ ), and the address alignment size of address 64 is 64 (ie, 2 ⁶ ). In some embodiments, the address alignment size for an address is obtained by counting the trailing zeros of the address in the binary representation, and then creating a trailing zero power of 2 in the binary representation. That is, alignment_size (address) = 2 ^{trailing_zeros (address)} , where alignment_size () is a function that outputs an address alignment size of an input address when an address is input, and trailing_zeros () is When an address is input, this function outputs the number of trailing zeros at that address in binary representation. For example, the address 96 is 1100000 _2, which has five postfix zero. Therefore, the address alignment size of address 96 is ^25, or 32. Address 64 is 1000000 _2, which has six postfix zero. Therefore, the address alignment size of address 64 is ^26, or 64.

  For conventional memory reference instructions, block concurrency is based on whether the address of the first byte of the block of data being referenced is integer with respect to the memory reference size (ie, the first byte Whether the address is a multiple of the memory reference size, or whether the address alignment size is greater than or equal to the memory reference size). That is, block concurrency for conventional memory reference instructions depends on whether the block of data referenced by the instruction has the same address alignment size as the memory reference size. For example, if a conventional memory reference instruction references eight bytes of data on an eight-byte integer boundary (eg, addresses 0,8, shown in the portion of memory represented by bar 108). 16, 24, etc.), which are 8 bytes simultaneous. However, if a conventional memory reference instruction references 8 bytes of data on a 4 byte integer boundary (eg, addresses 4, 12,..., Shown in the portion of memory represented by bar 106). 20), 8 byte concurrency is not guaranteed. The reason for this is that when a conventional memory reference instruction refers to an 8-byte block of data in a memory that is aligned on a 4-byte boundary, two bytes are read while a processor refers to the 8-byte data block. This is because there is no guarantee that a 4-byte block or four 2-byte blocks will not be updated by another processor.

  If the address of the block of data being referenced is not integral with respect to the memory reference size of the instruction referencing that block, the conventional instruction set architecture loads into a single register or a single register. For example, in order to provide one operand from the memory to an instruction that expects a memory operand in the case of storing from a memory, a synchronization of only one byte is guaranteed. Thus, software can only rely on conventional memory references that provide block concurrency of memory reference size or just one byte of concurrency. Intermediate levels of block concurrency are not guaranteed with memory reference instructions using conventional instruction set architecture. That is, for example, if the memory reference size is 8 bytes and the block of data being referenced is aligned on a 4-byte or 2-byte boundary, then 1-byte concurrency (ie, 1-byte block Only block concurrency with size) is provided, because 8-byte concurrency is relative to an 8-byte (doubleword) reference at an integral 8-byte memory address (ie, Since the address is only provided when it is a multiple of the data size of 8 bytes), otherwise 1 byte concurrency is guaranteed.

  In modern processors, access for wide data references (eg, doublewords, quadwords, or octowords) can generally be performed at the same speed as references to smaller data sizes. Thus, when a larger memory area is accessed, processed, or copied, using memory instructions adapted to access, process or copy the memory using the larger memory reference size, or a combination thereof. It is desired to access, process, or copy large areas. Thus, for example, when two consecutive words are copied, a two-word load and a two-word store can be replaced by a single double-word load and a single double-word store. This doubles the speed of the copy operation. If an array of 32 2-byte variables is copied on a 2-byte boundary, then 32 halfword loads and 32 halfword stores are required to complete the copy. obtain. In processors that implement double word accesses, groups of four halfword accesses can each be replaced by a single doubleword access.

Embodiments of the present invention provide data sizes (e.g., 8 bytes) that are larger than the size of each individual data element (e.g., a word size that is 4 bytes) at its respective integer boundary. When copying such data using a memory reference to a (doubleword size), and the first individual data element at its respective integer boundary (eg, address 100 ₂ ) is When unaligned at an integer boundary of a larger data size (eg, address 1000 ₂ ) corresponding to the access size used to copy the series of data elements aligned at the integer boundary, a series of a in their integer address (e.g., address 100 ₂₎ Data in (e.g., word), and provides a mechanism for copying with a block simultaneity in each separate data element.

Embodiments of the present invention provide systems and methods that provide different levels of block concurrency, even when the address of the block of data being referenced is not integral to the memory reference size. In some embodiments, the operands of the instruction are made up of multiple simultaneous block accesses, each block corresponding to a block at its corresponding integer boundary. For example, some memory reference instructions embodiments, when referring to 8 bytes of data on the 4-byte boundaries (e.g., 100 ₂ or addresses listed in the part of the memory represented by a bar 106 1100 ₂ ) guarantees 4-byte concurrency for each 4-byte block aligned on an integer 4-byte boundary. Furthermore, two-byte concurrency is also guaranteed, because two-byte concurrency is implied by the guaranteed four-byte concurrency (ie, 4 is a multiple of two). Thus, any block that is aligned on an integer 4 byte boundary is also aligned on an integer 2 byte boundary). Similarly, if a memory reference instruction has a memory reference size of 16 bytes at an address of a memory having an 8-byte boundary (eg, an address 1000 ₂ or 11000 ₂ indicated in the portion of the memory represented by bar 106) ) Includes 8 byte block concurrency, 4 byte block concurrency, 2 byte block concurrency and 1 byte block concurrency, those integral 8 bytes with 16 byte blocks, 4 byte Guaranteed for 8-byte, 4-byte, 2-byte and 1-byte blocks aligned at the boundaries of a 2-byte and 1-byte block. That is, an 8-byte, 4-byte, 2-byte, or 1-byte block at that integer boundary with a reference size of 16 bytes accessed is guaranteed not to include a partially updated value.

  The address alignment size of the block of data being referenced is simply the minimum level of byte concurrency provided by the processor executing the memory reference instruction of some embodiments of the present invention. That is, in some embodiments, a single block concurrent access may be implemented as multiple accesses, with logic ensuring that multiple such accesses exhibit block concurrent behavior. In some embodiments, the concurrent block access is implemented as a single access providing at least block concurrent behavior for each block of the plurality of accesses aligned at some integer boundary. Is done.

  FIG. 2 illustrates a portion of a memory 200 accessed by a processor according to some embodiments of the present invention. In particular, this figure illustrates a portion of a memory having 32 to 55 addresses. Memory 200 has an 8-byte boundary (eg, cache interface size). That is, addresses 32, 40, and 48 have boundaries.

By way of example, a memory reference instruction according to some embodiments of the present invention has a memory reference size of 16 bytes (ie, the size of a quadword), and this 16 byte block has 34 addresses. (Ie, the first byte of this block is at address 34 of memory 200). These 16 bytes are shown in FIG. 2 as gray boxes. The processor executing this memory reference instruction can access 16 bytes of data while guaranteeing 2 bytes of concurrency. This is because address 34 in binary form (ie, 100010 ₂ ) has one trailing zero, so that the address has an alignment size of 2 bytes.

  In some embodiments, the processor accesses 16 bytes of data in groups of any size that is a multiple of the alignment size, as long as none of those groups extend across memory boundaries. I can do it. For example, the processor executing the instruction may have four bytes with addresses 34-37, two bytes with addresses 38 and 39, four bytes with addresses 40-43, four bytes with addresses 44-47, and address 48. And 2 bytes with the address 49 can be accessed. However, because access to each group is time consuming and impacts performance, the processor executing the instruction requires only a minimum number of accesses while avoiding cache line crossings. It will access byte data. In particular, the processor determines the first six bytes with addresses 34-39 up to cache line address 40, the next eight bytes with addresses 40-47 up to the next cache line address 48, address 48 and The next two bytes with 49 can be accessed. These three accesses (ie, a 6-byte access, an 8-byte access, and a 2-byte access) may be performed in any order to access all 16 bytes.

  In contrast to processors that execute memory reference instructions according to embodiments of the present invention, conventional memory reference instructions that reference 16 bytes of data at address 34 of memory 200 use up to 16 1-byte accesses. Thus, this 16-byte data is accessed. The reason is that in the case of a conventional memory reference instruction, the address of 16-byte data is not integral with respect to the memory reference size (ie, 16 bytes), and therefore only byte concurrency is guaranteed. Because. In some cases, a processor executing a conventional memory reference instruction may require byte addresses 32, 33, and 50 to access 16 bytes having addresses 34-49 without causing an alignment fault. ~ 55 may have to be padded with meaningless bytes. These extra steps can affect performance.

  The following code examples are specified based on exemplary instructions according to the IBM ™ z / architecture, unless otherwise stated. However, one of ordinary skill in the art will understand how to adapt the examples herein to other architectures, such as a power ISA architecture. The instruction set of the z server family of IBM systems, known as the z / architecture instruction set, is described in the IBM publication z / Architecture Principles of Operation, SA22-7832-09 (10th ed. Sept. 2012). Has been given. The power server instruction set, known as the Power ISA (Instruction Set Architecture), is provided in the Power ISA (Version 2.06 Revision B, Jul. 2010).

In the following exemplary z / architecture instruction (Example 1), a 16 halfword load and store copy loop is shown.
LHI R1, 16
XGR R3, R3
LOOP: LLH R2,0 (R3, R4)
STH R2,0 (R3, R5)
AGHI R3,2
BCT R1, LOOP
Here, LHI is a load halfword immediate (LOAD HALFWORD IMMEDIATE) instruction, XGR is an exclusive OR (EXCLUSIVE OR) instruction, LLH is a load logical halfword (LOAD LOGICAL HALFWORD) instruction, and STH is Is a store halfword (STORE HALFWORD) instruction, AGHI is an add halfword immediate (ADD HALFWORD IMMEDIATE) instruction, BCT is a branch on count (BRANCH ON COUNT) instruction, and R1 to R5 are registers. It is. A more detailed description of these instructions can be found in the z / Architecture Principles of Operation.

The 16 halfword loads and stores shown in Example 1 can be replaced by four doubleword loads and four stores, and such replacements are shown in Example 2 below. Thus, the execution time is reduced from the time corresponding to the execution of 66 instructions to the time corresponding to the execution of 18 instructions.
LHI R1, 4
XGR R3, R3
LOOP: LG R2,0 (R3, R4)
STG R2,0 (R3, R5)
AGHI R3,8
BCT R1, LOOP

  However, Example 1, based on copying 16 halfwords, has two byte block concurrencies where the addresses held in registers R4 and R5 correspond to at least two address alignment sizes, and one byte. (Ie, block concurrency corresponding to a block size of 1 byte). On the other hand, the instructions shown in Example 2 generally provide for quadword block concurrency if registers R4 and R5 have at least a quadword address alignment size, and byte concurrency otherwise. Can guarantee. Thus, the programmer or compiler translating the instructions from Example 1 to Example 2 would guarantee the block concurrency of Example 1 because of the block concurrency of halfwords, because the address concurrency less than quadword but at least halfword size. For addresses with an alignment size, it can be reduced to just byte concurrency. Thus, the programmer or compiler may cause a violation of the programming language or programming conventions with this otherwise beneficial change.

  As another example, if an array of 32 2-byte variables on a 2-byte boundary is copied, a load of 32 halfwords and 32 A halfword store may be required. If a single instruction multiple data (SIMD) load is used, which loads 16 bytes at a time according to some embodiments of the present invention, only two loads and two stores are required. This significantly reduces the copy execution time. When the SIMD load is implemented on az / architecture processor, the code in Example 3 below, as shown in Example 4 below, contains two vector load (VECTOR LOAD) instructions followed by 2 VECTOR STORE instructions.

Example 3 shows a 16 halfword load and store copy loop.
LHI R1, 16
XGR R3, R3
LOOP: LLH R2,0 (R3, R4)
STH R2,0 (R3, R5)
AGHI R3,2
BCT R1, LOOP
This copy loop can be replaced by only two loads and two stores of vector registers, and from the time corresponding to executing 66 instructions, as shown in Example 4 below. In addition, the execution time is reduced to a time corresponding to executing the four instructions.
VL V1, 0 (R4)
VST V1, 0 (R5)
VL V1, 16 (R4)
VST V1, 16 (R5)
Here, VL is a vector load (VECTOR LOAD) instruction, VST is a vector store (VECTOR STORE) instruction, and V1 is a vector data type.

  However, according to the conventional instruction architecture, Example 3, based on copying 16 halfwords, requires 2 addresses when the addresses held in registers R4 and R5 correspond to at least an address alignment size of 2. It gives byte block concurrency and one byte concurrency. On the other hand, Example 4 may generally guarantee quadword block concurrency if registers R4 and R5 have at least a quadword address alignment size, and byte concurrency otherwise. In this manner, the programmer or compiler translating the instructions from Example 3 to Example 4 may use the block concurrency guarantee of Example 3 because of the halfword block concurrency, the address of less than a quadword but at least halfword size. For addresses with an alignment size, it can be reduced to just byte concurrency. Thus, the programmer or compiler may cause a violation of the programming language or programming conventions with this otherwise beneficial change.

A similar conversion can be performed when the values of an array are incremented by a constant. In particular, Example 5 below shows a 16 halfword addition loop.
LHI R1, 16
LH R7, R6
XGR R3, R3
LOOP: LLH R2,0 (R3, R4)
AH R2, R6
STH R2,0 (R3, R5)
AGHI R3,2
BCT R1, LOOP
Here, LH is a load halfword (LOAD HALFWORD) instruction, AH is an addition halfword (ADD HALFWORD) instruction, and R6 and R7 are registers. This addition loop of 16 halfwords can be replaced by just two vector additions, in which case it corresponds to executing 83 instructions, as shown in Example 6 below. Execution time is reduced from time to the time corresponding to executing the seven instructions.
VLREPH V3, 0 (R6)
VL V1, 0 (R4)
VAH V1, V1, V3
VST V1, 0 (R5)
VL V1, 16 (R4)
VAH V1, V1, V3
VST V2, 16 (R5)
Here, VLREPH is a vector load and replica (VECTOR LOAD AND REPLICATE) instruction, VAH is a vector addition halfword (VECTOR ADD HALFWORD) instruction, and V1 to V3 are vectors.

  Example 5 provides block concurrency for each halfword so incremented if addresses R4 and R5 have an address alignment size of at least 2, while Example 6 provides , If addresses R4 and R5 have an address alignment size of at least 16, provide block concurrency for the group of eight halfwords so incremented, otherwise, Gives one byte of concurrency. Thus, the conversion from Example 5 to Example 6 does not preserve the block concurrency behavior of Example 5.

  It should be noted that the vector instructions shown in Examples 4 and 6 are new instructions, not conventional memory reference instructions. However, these new vector instructions do not have the block concurrency behavior according to some embodiments of the invention described herein.

  Embodiments of the present invention provide for a new definition of a memory reference instruction based on an address alignment size for a specified memory address, such instructions being aligned at that address alignment size. Block synchronism is provided for sub-blocks of a block size corresponding to the address alignment size. Thus, the three code conversions described above (Examples 1 to 2, Example 3 to 4, and Example 5 to 6) can be performed based on the new and changed instruction definition for the load and store instructions. This change corresponds to the block concurrency behavior described herein, while the behavior of other aspects of instruction execution remains unchanged. For clarity, the following exemplary modified instruction opcodes are denoted by an "m" prefix to the opcode in the instruction examples described below.

A halfword copy loop with halfword block concurrency may be performed using a modified doubleword access instruction, as shown in Example 7 below.
LHI R1, 4
XGR R3, R3
LOOP: mLG R2,0 (R3, R4)
mSTG R2,0 (R3, R5)
AGHI R3,8
BCT R1, LOOP
In some embodiments, this code of Example 7 provides two-byte block concurrency and one-byte concurrency when the addresses held in registers R4 and R5 correspond to at least two address alignment sizes. Give sex and. Further, in some embodiments, this code provides 4 bytes of block concurrency if the addresses held in registers R4 and R5 correspond to an address alignment size of at least 4. Further, in some embodiments, this code provides 8 bytes of block concurrency if the addresses held in registers R4 and R5 correspond to an address alignment size of at least 8.

Similarly, the instruction of Example 7 may be represented using a power ISA based on the modified power ISA instruction definition for load and store instructions. The changes correspond to the block concurrency behavior described herein, while the behavior of other aspects of instruction execution, as specified by the Power ISA definition, is left unmodified. You. Again, for clarity, in Example 7 described below, the opcodes of these modified instructions are denoted with an "m" at the beginning of the opcode.
LI R1, 4
MTCTR R1
XOR R3, R3, R3
LOOP: mLDX R2, R3, R4
mSTDX R2, R3, R5
ADDI R3, R3, 8
BDNZ LOOP
Here, LI is a Load Immediate instruction, MTCTR is a Move To Count Register instruction, XOR is an Exclusive OR instruction, and LDX is an exclusive OR (Exclusive OR) instruction. Is a load double word (Load Double Word) instruction, STDX is a store double word indexed instruction, ADDI is an Add Immediate instruction, and BDNZ is a branch ( (Branch) instruction, and R1 to R5 are registers.

Further, the optimized instructions of Example 4 can be converted to the instructions of Example 8 below. The optimized code may be executed with modified instructions as described below.
mVL V1, 0 (R4)
mVST V1, 0 (R5)
mVL V1, 16 (R4)
mVST V1, 16 (R5)

  In some embodiments, this code of Example 8 provides two-byte block concurrency and one-byte concurrency when the addresses held in registers R4 and R5 correspond to at least two address alignment sizes. (Ie, block concurrency with a block size corresponding to one byte). Further, in some embodiments, this code provides 4 bytes of block concurrency if the addresses held in registers R4 and R5 correspond to an address alignment size of at least 4. Further, in some embodiments, this code provides 8 bytes of block concurrency if the addresses held in registers R4 and R5 correspond to an address alignment size of at least 8. Further, in some embodiments, this code indicates that the addresses held in registers R4 and R5 correspond to an address alignment size of at least 16, and that the maximum block concurrency size for mVL and mVST is at least 16 If defined as bytes, it provides 16 byte block concurrency. In some embodiments, the code is such that the addresses held in registers R4 and R5 correspond to an address alignment size of at least 16 and the maximum block concurrency size for mVL and mVST is at least 8 bytes. If defined, gives 8 byte block concurrency.

Similarly, the code of Example 7 can be expressed using a modified power ISA definition, as in Example 8 below.
LI R1, 16
mLXVX V1, R0, R4
mSTXVX V1, R0, R5
mLXVX V1, R1, R4
mSTXVX V1, R1, R5

Similarly, the code of Example 6 can be represented as in Example 9 below.
VLREPH V3, 0 (R6)
mVL V1, 0 (R4)
VAH V1, V1, V3
mVST V1, 0 (R5)
mVL V1, 16 (R4)
VAH V1, V1, V3
mVST V2, 16 (R5)

  In some embodiments, the code of Example 9 has two byte block concurrency and one byte concurrency where the addresses held in registers R4 and R5 correspond to at least two address alignment sizes. (Ie, block concurrency using a block size corresponding to one byte). Further, in some embodiments, this code provides 4 bytes of block concurrency if the addresses held in registers R4 and R5 correspond to an address alignment size of at least 4. Further, in some embodiments, this code provides 8 bytes of block concurrency if the addresses held in registers R4 and R5 correspond to an address alignment size of at least 8. Further, in some embodiments, this code is used when the addresses held in registers R4 and R5 correspond to an address alignment size of at least 16 and the maximum block concurrency size for mVL and mVST. Is defined as at least 16 bytes, which provides 16 bytes of block concurrency. Further, in some embodiments, this code is used when the addresses held in registers R4 and R5 correspond to an address alignment size of at least 16 and the maximum block concurrency size for mVL and mVST. Is defined as at least 8 bytes, giving 8 bytes of block concurrency.

  In some embodiments, existing instructions and opcodes are modified, and no new mnemonics are introduced for the instructions. In other embodiments, new instructions and opcodes are introduced using the teachings on block concurrency based on address alignment sizes described herein.

  FIG. 3 illustrates a process flow for accessing memory according to some embodiments of the present invention. In some embodiments, a processor (eg, a CPU) performs the process flow illustrated in FIG. At box 305, the processor receives a memory reference instruction that references a block of data at an address in memory. The memory reference instruction includes any instruction that refers to a certain block of data in the memory (for example, an instruction that includes a certain address in the memory as an operand). Such instructions include load and store instructions, as well as arithmetic operations (eg, add, subtract, compare, etc.).

  At decision box 310, the memory at which the processor optionally references data from it is the maximum block concurrent memory reference size (or maximum block concurrent memory size) supported by the memory reference instruction received at box 305. It is determined whether or not a memory address boundary (ie, the address alignment size of the address specified by the memory reference instruction) is equal to or larger than the memory address boundary. The maximum memory reference size for an instruction is defined for all instructions in the instruction set architecture. The maximum block concurrent memory reference size may be the size of the memory reference of the instruction, or may correspond to the maximum block concurrent reference size defined for all instructions in the instruction set architecture. In some embodiments, the maximum block concurrent memory reference size can be the size of the memory reference of the instruction, or the maximum block concurrent memory reference size defined independently for each instruction in the instruction set architecture May correspond to

  If it is determined in decision box 310 that the memory address boundary is less than the maximum block concurrent memory reference size, the processor proceeds to decision box 320, which will be further described below. If it is determined in decision box 310 that the memory address boundary is greater than or equal to the maximum block concurrent memory reference size, the processor proceeds to box 315 and simultaneously accesses the memory by blocks of the maximum block concurrent memory reference size. For example, if the memory reference size is 32 bytes and the memory address boundary is 16 bytes, but the maximum block simultaneous memory reference size is 8 bytes, the processor accesses the memory 8 bytes at a time.

At decision box 320, the processor determines whether the alignment size of the requested memory address is 2 N (ie, 2 ^N ), where N is 2 ^N. The largest non-negative integer that is less than or equal to the memory reference size. For example, when the memory reference size is 36 bytes, the processor determines at decision box 320 whether the requested memory address has an alignment size of 32 bytes ( ²⁵ bytes). Upon determining that the requested memory address alignment size is 2 N, the processor proceeds to box 325 and simultaneously accesses the memory 2 ^N bytes. For example, if the memory address alignment size is 32 bytes and the memory reference size is 32 bytes, the processor may access the 32 bytes at a time to access all 32 bytes at a time. To access. Upon determining that the requested memory address alignment size is not 2 N, the processor proceeds to box 330. As described above, the maximum block concurrent memory reference size may be set for one or more instructions. In some embodiments, N is set to the largest non-negative integer such that 2 ^N is less than or equal to the maximum block concurrent memory reference size, independent of the memory reference size. For example, an instruction may provide a maximum block concurrent memory reference size of 8 bytes. At that time, even if the memory reference size is larger than 2 ^3, N is set to 3.

At decision box 330, the processor determines whether the requested memory address alignment size is 2 to the power of (N-1) (i.e., 2 ^(N-1) ). For example, when the memory reference size is 32 bytes (2 ⁵ bytes), the processor, in box 330, the requested memory address alignment size to determine whether 16 bytes (2 ⁴ bytes). If the processor determines that the requested memory address alignment size is 2 to the power of (N-1), the processor proceeds to box 335 and simultaneously accesses the memory by 2 ^(N-1) bytes. For example, if the memory reference size is 32 bytes (2 ⁵ bytes), the processor, in order to access all 32 bytes, 16 bytes each (2 ⁴ bytes) at a time, to simultaneously access block.

If the requested memory address alignment size is 2 (N-1) squared is determined not to be the processor, the requested memory address alignment size first power of 2 (i.e., 2 ^byte) Similarly, the process proceeds to the determination box 340 until the determination is made in the determination box 340. Upon determining that the requested memory address alignment size is two, the processor proceeds to box 345 and accesses the memory two bytes at a time. For example, if the memory reference size is 32 bytes, the processor accesses blocks simultaneously, 2 bytes at a time, to access all 32 bytes. If, in decision box 340, the processor determines that the requested memory address alignment size is not two, the processor proceeds to box 350 and accesses the memory one byte at a time. That is, the processor accesses one byte at a time to access all bytes specified by the memory reference instruction.

  In boxes 320 through 350, the processor enters the memory with block concurrency at the requested memory address alignment size when the requested memory address alignment size is smaller than the memory reference size of the memory reference instruction. Access should be recognized. That is, in some embodiments, the processor executing the memory reference instruction has block-concurrent access to any boundary where the address of the requested block of data is aligned (ie, the access is It works as if the block is simultaneous to any alignment size).

  In some embodiments, the memory reference size of a memory reference instruction is indicated, for example, by the opcode (operation code) of the instruction. The reason for this is that the instruction opcode indicates not only the operation to be performed, but also the data type of the data being referenced. Alternatively, or in conjunction with the above (Alternatively or conjunctively), in some embodiments, a memory reference instruction may be defined, for example, to explicitly specify a memory reference size in an operand of the instruction. For example, the operand of the instruction specifies the highest indexed byte to fetch or store. This allows the programmer to specify the memory reference size. In some cases, the specified memory reference size may not be a power of two (eg, 10 bytes) or may not match the memory reference size suggested by the opcode.

  Embodiments of the present invention provide systems and methods that provide block concurrency when the specified memory reference size and the requested memory address boundary are not the same. In some embodiments, when the memory reference size is specified in a memory reference instruction, the processor executing the instruction may use the greatest common denominator between the address boundary of the address of the requested memory and the specified memory reference size. The number is used as the block concurrent data access size. For example, if the operand address of an instruction is on a 4-byte boundary and the specified memory reference size is 10 bytes, then the greatest common divisor between 10 and 4 is 2, so data access is: At least two bytes appear to be concurrent with other processors. This allows data parallel code that behaves like scalar code and does not violate any programming language semantics or conventions.

  In some embodiments, the block size of block concurrency (ie, the level of block concurrency, eg, 2 byte concurrency, 4 byte concurrency, 16 byte concurrency, 32 byte concurrency, etc.) Is directly derived from the address alignment size. In another embodiment, the block concurrency size of the block simultaneous access is based on both the address alignment size and the memory reference size of the instruction. In some such embodiments, the block size for block concurrent access is the minimum block size of block concurrency directly derived from the address alignment and the size of the memory reference. In yet another embodiment, the block size for simultaneous block access is the two block sizes common between the address alignment size and the memory reference size, as further shown in FIG. Determined by the largest power.

  FIG. 4 illustrates a process flow for accessing memory when the block size for simultaneous block access is based on both the address alignment size and the memory reference size of the memory reference instruction. In some embodiments, the maximum block size for concurrent block access may be imposed on all instructions by the instruction set architecture, or on a particular instruction having the maximum block concurrency size. Some memory reference instructions explicitly specify a memory reference size, which may not be a power of two. However, in some implementations, only a power-of-2 block concurrent size may be allowed. In some such embodiments, a processor (eg, a CPU) executes the process flows illustrated in FIG.

  At box 405, the processor receives a memory reference instruction that references a block of data at an address in memory. The memory reference instruction also specifies the size of the data to be referenced, for example, in the operand of the instruction.

  At decision box 410, the memory that the processor optionally refers to, but that the processor references data from, has a memory address alignment size greater than or equal to the maximum block concurrent memory reference size of the memory reference instruction received at box 405. Is determined. If it is determined that the memory address alignment size is less than the maximum block concurrent memory reference size, the processor proceeds to decision box 420, which is described further below. If it is determined that the memory address alignment size is greater than or equal to the specified memory reference size, the processor proceeds to box 415 and simultaneously accesses the memory by blocks of the maximum block concurrent memory reference size. For example, if the specified memory reference size is 8 bytes and the memory address alignment size is 8 bytes, but the maximum block simultaneous access size is 4 bytes, then the processor will allocate 4 bytes of memory at a time. To access.

At decision box 420, the processor determines whether the requested memory address alignment size is 2 N (ie, 2 ^N ), where N is 2 ^N. The largest non-negative integer that is less than or equal to the specified memory reference size. For example, when the memory reference size specified is 10 bytes, the processor in box 420, the requested memory address to determine whether it is aligned to 8 bytes ⁽²³ bytes). If, at decision box 420, the processor determines that the requested memory address alignment size is not a power of 2 N, the processor proceeds to decision box 435, which is described further below.

If, at decision box 420, the processor determines that the requested memory address alignment size is 2 N, the processor proceeds to decision box 425 and the identified memory reference size is a multiple of 2 N. Determine whether or not. For example, when the specified memory reference size is 10 bytes, the processor determines at decision box 425 whether the specified memory reference size of 10 bytes is a multiple of 8 bytes. If the specified memory reference size is not a multiple of 2 N, the processor proceeds to decision box 440, which is described further below. If the specified memory reference size is a multiple of 2 N, the processor proceeds to box 430 and simultaneously accesses the memory 2 ^N bytes.

At decision box 435, the processor determines whether the requested memory address alignment size is 2 to the power of (N-1) (i.e., 2 ^(N-1) ). For example, when the memory reference size is 10 bytes, the processor, at decision box 435, the requested memory address alignment size to determine whether the 4 bytes (2 ² bytes). If the processor determines that the requested memory address alignment size is not a power of two (N-1), the processor proceeds to decision box 450, which is described further below.

If, at decision box 435, the processor determines that the requested memory address alignment size is a power of two (N-1), the processor proceeds to decision box 440 and determines that the specified memory reference size is two (N). -1) It is determined whether or not it is a multiple of the power. For example, when the memory reference size specified is 10 bytes, the processor, at decision box 440, the 10 bytes is a memory reference size specified to determine whether a multiple of 4 bytes (2 ² bytes) . If the specified memory reference size is not a multiple of 2 (N-1), the processor proceeds to decision box 455, which is described further below. If the determined memory reference size is a multiple of 2 ^(N-1) , the processor proceeds to box 445 and simultaneously accesses the memory 2 ^(N-1) bytes.

If at decision box 435, the processor determines that the requested memory address alignment size is not a multiple of 2 (N-1), the processor determines that the requested memory address alignment size is 2 to the power of 2 ( until it judged by 2 ¹⁾ decision box 450 to be likewise advanced to decision box 450. If, at decision box 450, the requested memory address alignment size is not two, the processor accesses the memory, one byte at a time, at box 465. That is, the processor accesses one byte at a time to access all bytes specified by the memory reference instruction.

  If, at decision box 450, the processor determines that the requested memory address alignment size is two, the processor proceeds to decision box 455 and determines whether the specified memory reference size is a multiple of two bytes. . If the specified memory reference size is not a multiple of two, the processor proceeds to box 465 and accesses the memory one byte at a time. If the specified memory reference size is a multiple of two, the processor proceeds to box 460 and accesses the memory two bytes at a time. For example, if the memory reference size is 10 bytes, the processor accesses the memory 2 bytes at a time to access all 10 bytes.

  In boxes 420 through 465, the processor identifies the greatest common divisor of the requested memory address alignment size and the specified memory reference size as a number of bytes, and with the greatest common divisor block concurrency, Should be recognized. For example, if the specified memory reference size is 10 bytes and the requested memory address alignment size is 4 bytes, the processor identifies the greatest common divisor, 2 bytes, and simultaneously allocates 2 bytes of memory at a time. (Ie, accessing all 10 bytes by accessing the block 2 bytes at a time at the same time).

In some embodiments, the maximum block concurrency size may be set for one or more instructions. For example, an instruction may provide a maximum block concurrency size of 8 bytes. At that time, even if the memory reference size specified is greater than 2 ^3, at decision box 420, N is set to 3. In some embodiments, the maximum block concurrency size applies to all instructions. In other embodiments, each instruction may have a distinct maximum block concurrency size.

  FIG. 5 illustrates a system 500 for accessing data in a memory, according to some embodiments of the present invention. In particular, this diagram illustrates that system 500 includes memory 505 and multiple processors 510 and 515, although other components are not shown for simplicity of illustration and description. The memory 505 and the processors 510 and 515 are interconnected via one or more buses 520. Processors 510 and 515 are shown as having registers 525 and 530, respectively, but other components internal to the processor (eg, arithmetic logic units, controllers, clocks, internal buses, etc.) are illustrated and described. Not shown for simplicity.

  In some embodiments, system 500 represents various parallel processing environments. For example, one of processors 510 and 515 may be a vector processor that executes vectorized instructions. One of the other processors may be a scalar processor executing scalar instructions. The vector processor and the scalar processor may share the memory 505. As another example, system 500 may represent a multi-core processor, where processors 510 and 515 are different cores sharing memory 505. As yet another example, system 500 may represent a mainframe computer system having processors 510 and 515 performing parallel processing.

  As is known in the art, processors or processor families (such as the 8086 and x86 families, or the IBM System z Server family) have their own set of machine instructions. For example, the instruction set of the IBM System z server family, known as the z / architecture instruction set, is defined by the z / Architecture Principles of Operation incorporated above, and the power server instruction set is , Known as the Power ISA (Instruction Set Architecture), defined by the Power ISA incorporated above. Machine instructions are patterns of bits designed to respond to different commands to the machine. In most cases, instruction sets are specific to a class of processors using the same architecture. Most instructions have one or more opcodes that identify the basic instruction type (arithmetic, memory reference, branch, etc.) and the actual operation (load, store, add, or compare, etc.), the type of operand, Addressing mode, addressing offset or index, or other fields that can provide the actual value itself. That is, each machine instruction is for performing a very specific task, such as a load, branch, or arithmetic and logic unit (ALU) operation, on a data unit in a register or memory. Some of these machine instructions are memory reference instructions, which reference data at a particular address in memory 505 and fetch that data from memory 505 to a register, or The data is stored in the memory 505 from the register.

  Processors 510 and 515 execute memory reference instructions that provide block concurrency even when the address of a block of data within memory 505 is not integral with the memory reference size for that memory reference instruction. , Can be configured. That is, in some embodiments, the memory reference instructions to the processors 510 and 515 function as if the instructions were block-concurrent on any boundary where the block of data being referenced is aligned. I do. In some embodiments, there is a maximum of 8 bytes of concurrency. In some embodiments, the processor identifies the greatest common divisor of the memory address alignment size and the specified memory reference size as a number of bytes and accesses memory 505 with block concurrency at the greatest common divisor. I do. In this manner, the functionality of a computer including processors 510 and 515 may be improved.

  In different embodiments, processors 510 and 515 are configured differently. For example, in some embodiments, processors 510 and 515 may add new definitions to existing conventional memory reference instructions to access memory 505 in accordance with various embodiments of the present invention when executing instructions. By providing Alternatively, or in conjunction with the above, processors 510 and 515 may be configured by defining a new memory reference instruction that accesses memory 505 in accordance with various embodiments of the present invention.

  For example, memory reference instructions include a vector load instruction, which often has a 16 byte alignment requirement. That is, a vector load instruction having a 16-byte alignment requirement is expected to load all 16 of the 16-byte blocks of data from memory as one unit. If the multi-threaded code is vectorized by a compiler, for example, to allow data parallel execution, certain variables are updated by a first CPU and read by a second CPU. Is assumed to look at the overall change to that variable, not the mixed result. With the definition of a conventional vector load instruction, it is impossible to guarantee block concurrency. Therefore, it is often difficult to use a higher degree of data parallelism when using thread parallelism. This limits the performance of potential software and creates a condition where hardware is underutilized.

  By configuring the processor to access memory in accordance with various embodiments of the present invention, the processor can use thread parallelism to require a lesser degree of external serialization (e.g., locks). High data parallelism can be used. Processors configured in accordance with embodiments of the present invention also improve software performance and facilitate hardware utilization. Embodiments of the present invention allow smaller data types to be packed into vectors, and other processors operate with the same semantics as if scalar instructions were used. looks like. Further, the block concurrency avoids extra alignment restrictions and allows the compiler to more easily automate the code because it avoids the need for extra code to handle portions of the data that cannot be aligned. Parallelization becomes possible.

In some embodiments of the present invention, a method is provided for accessing data in a memory coupled to a processor. The method receives a memory reference instruction for accessing data of a first size at an address in memory. The method determines the alignment size of the address. The method accesses data of a first size in units of one or more groups of data by accessing each group of data simultaneously in blocks. The group of data has a size that is a multiple of the alignment size. This method determines the alignment size by counting the number of trailing zeros in the address in binary representation. Each group of data is no larger in bytes than a predefined maximum block concurrency size. In some embodiments, the first size is larger than the determined alignment size. In some embodiments, the first size and the determined alignment size is the size of a number of bytes, the first size is 2 ^A, determined alignment size is 2 ^B, A is an integer greater than B, which is a non-negative integer. In some embodiments, the method determines the first size based on an opcode of the memory reference instruction. In some embodiments, the processor includes a vector processor and the memory reference instructions include vector instructions.

  In some embodiments of the present invention, a method is provided for accessing data in a memory coupled to a processor. The method receives a memory reference instruction for accessing data of a first size at an address in memory. A memory reference instruction specifies a first size. The method determines the alignment size of the address. The method determines a greatest common divisor of the first size and the determined alignment size. The method accesses data of the first size in units of one or more groups of data. The group of data has a size that is a multiple of the size of the greatest common divisor. In some embodiments, the first size is larger than the determined alignment size. In some embodiments, the first size and the determined alignment size are sizes in bytes, and the first size is not a power of two size and the determined alignment size is two. The size of the power. In some embodiments, the method determines the first size based on an operand of the memory reference instruction. In some embodiments, the processor comprises a vector processor and the memory reference instructions comprise vector instructions.

  The invention can be a system, method, or computer program product or a combination thereof. The computer program product may include computer readable storage medium (s) having computer readable program instructions for causing a processor to perform aspects of the present invention.

  A computer-readable storage medium may be any tangible device capable of holding and storing instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable one of the foregoing. Can be any combination. A non-exhaustive list of more specific examples of computer readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), Programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk A mechanically encoded device such as a (DVD), a memory stick, a floppy disk, a punched card or a raised structure having grooves in which instructions are recorded, and any of the above. Including appropriate combinations. As used herein, a computer readable storage medium is a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (eg, fiber optic cable It should not be interpreted as a transient signal itself, such as an optical pulse passing through a wire) or an electrical signal transmitted through a wire.

  The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing / processing device, or may be stored on an external computer or storage medium, such as the Internet, a local area. Can be downloaded over a network such as a network, wide area network, or wireless network or a combination thereof. The network may comprise copper transmission cable, optical transmission fiber, wireless transmission, router, firewall, switch, gateway computer, or edge server or a combination thereof. A network adapter card or network interface at each computing / processing device receives the computer readable program instructions from the network and stores the computer readable program instructions on a computer readable storage medium at each computing / processing device. To transfer.

  The computer readable program instructions for performing the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or one or more of the following. It can be either source code or object code written in any combination of programming languages, where programming language is an object-oriented programming language such as Smalltalk®, C ++, or “C Includes conventional procedural programming languages, such as programming languages or similar programming languages. The computer readable program instructions may be entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer, and partially on a remote computer. On or entirely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or A connection may be made to an external computer (e.g., through an Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) implements aspects of the present invention. The computer readable program instructions may be executed by customizing the electronic circuit with the status information of the computer readable program instructions to do so.

  Aspects of the invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart or block diagram or both, and combinations of blocks in the flowchart or block diagram or both, can be implemented by computer readable program instructions.

  These computer readable program instructions may include instructions for executing instructions via a processor of a computer or other programmable data processing device in one or more blocks of a flowchart or block diagram or both. It may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing device to create a machine so as to provide a means for implementing the action. The computer-readable program instructions also implement aspects of the functions / acts in which the computer-readable storage medium on which the instructions are stored is specified in one or more blocks in a flowchart and / or block diagrams. Instruct a computer, a programmable data processing device, or other device, or a combination thereof, stored in a computer readable storage medium to function in a particular manner, to constitute a product containing the instructions. There may be.

  Computer-readable program instructions also refer to functions / acts in which instructions that execute on a computer, other programmable device or other device, are specified in one or more blocks in a flowchart or block diagram, or both. As implemented, loaded on a computer, other programmable data processing device, or other device to cause a computer-implemented process to be executed on the computer, other programmable device, or other device. A series of operation steps may be executed.

  The flow diagrams and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the invention. In this regard, each block in the flowcharts or block diagrams represents a module, segment, or instruction with one or more executable instructions for implementing the identified logical function (s). Part. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown as being consecutive may, in fact, be executed substantially simultaneously, depending on the functions involved, or they may be performed in the reverse order. It could be performed. Each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, performs the specified function or action, or performs a combination of dedicated hardware and computer instructions. It may be implemented by a dedicated hardware-based system.

  While descriptions of various embodiments of the invention have been presented for purposes of illustration, the description is intended to be exhaustive and limited to the disclosed embodiments. Not something. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is to best describe the principles of embodiments, practical applications, or technical improvements to the technology found in the marketplace, or the implementations disclosed herein. The form has been chosen to enable others skilled in the art to understand the form.

Claims (26)

A method for accessing data in a memory coupled to a processor, the method comprising:
Receiving a memory reference instruction of a first size specified by the memory reference instruction for accessing data of a first size at an address in the memory;
Determining, by the processor, an alignment size of the address based on the address;
Accessing the data of the first size in units of one or more groups of data, wherein the groups of data have any size that is a multiple of the alignment size. Method. The method of claim 1, wherein the determined alignment size is smaller than the first size .   2. The method of claim 1, wherein determining the alignment size comprises determining the number of trailing zeros in the address in binary representation as N and the alignment size as 2 to the Nth power. .   2. The method of claim 1, wherein each group of data is no larger than a predefined maximum block concurrency size.   The method of claim 1, further comprising determining the first size based on an opcode of the memory reference instruction. A system for accessing data,
Memory and
And a processor, wherein the processor comprises:
Receiving a memory reference instruction of a first size specified by the memory reference instruction for accessing data of a first size at an address in the memory;
Determining an alignment size of the address based on the address;
Accessing the data of the first size in units of one or more groups of data, wherein the groups of data have any size that is a multiple of the alignment size;
A system configured to perform the method comprising: Wherein the first size and the determined alignment size is the size of a number of bytes, the first size is 2 ^A, alignment and size the determined is 2 ^B, B is 7. The system of claim 6 , wherein the non-negative integer is less than the integer A.   7. The system of claim 6, wherein determining the alignment size comprises determining the number of trailing zeros in the address in binary representation as N and the alignment size as 2 to the Nth power. .   7. The system of claim 6, wherein each group of data is no larger than a predefined maximum block concurrency size.   The system of claim 6, wherein the processor comprises a vector processor and the memory reference instructions comprise vector instructions. A computer program for accessing data,
To the processor,
Receiving a memory reference instruction of a first size specified by the memory reference instruction for accessing data of a first size at an address in memory;
Determining an alignment size of the address based on the address;
Accessing the data of the first size in units of one or more groups of data, wherein the groups of data have any size that is a multiple of the alignment size;
A computer program for performing a method comprising: The computer program according to claim 11, wherein the determined alignment size is smaller than the first size .   12. The computer of claim 11, wherein determining the alignment size comprises determining the number of trailing zeros in the address in binary representation as N and the alignment size as 2 to the Nth power. ·program.   The computer program of claim 11, wherein each group of data is not greater than a predefined maximum block concurrency size.   The computer program of claim 11, wherein the method further comprises determining the first size based on an opcode of the memory reference instruction. A method for accessing data in a memory coupled to a processor, the method comprising:
Receiving a memory reference instruction for accessing data of a first size at an address in the memory, wherein the memory reference instruction specifies the first size;
Determining, by the processor, an alignment size of the address based on the address;
Determining the greatest common divisor of the first size and the determined alignment size;
Accessing the data of the first size in units of one or more groups of data, wherein the groups of data have any size that is a multiple of the size of the greatest common divisor;
A method that includes 17. The method of claim 16, wherein the determined alignment size is smaller than the first size .   The first size and the determined alignment size are sizes in terms of number of bytes, and the first size is not a power of two size, but the determined alignment size is a power of two size. 17. The method of claim 16, wherein   17. The method of claim 16, further comprising determining the first size based on an operand of the memory reference instruction.   17. The method of claim 16, wherein the step of accessing the data of the first size is performed when the greatest common divisor is not greater than a predefined maximum block concurrency size. A system for accessing data,
Memory and
And a processor, wherein the processor comprises:
Receiving a memory reference instruction for accessing a data space having a first size at an address in the memory, wherein the memory reference instruction specifies the first size;
Determining an alignment size of the address based on the address;
Determining the greatest common divisor of the first size and the determined alignment size;
Accessing the data of the first size in units of one or more groups of data, wherein the groups of data have any size that is a multiple of the size of the greatest common divisor;
A system configured to perform the method comprising: 22. The system of claim 21, wherein the determined alignment size is smaller than the first size .   The first size and the determined alignment size are sizes in terms of number of bytes, and the first size is not a power of two size, but the determined alignment size is a power of two size. 22. The system of claim 21, wherein   22. The system of claim 21, wherein the method further comprises determining the first size based on an operand of the memory reference instruction.   22. The system of claim 21, wherein said processor comprises a vector processor and said memory reference instructions comprise vector instructions. A computer program for accessing data,
To the processor,
Receiving a memory reference instruction for accessing a data space having a first size at an address in a memory, wherein the memory reference instruction specifies the first size;
Determining an alignment size of the address based on the address;
Determining the greatest common divisor of the first size and the determined alignment size;
Accessing the data of the first size in units of one or more groups of data, wherein the groups of data have any size that is a multiple of the size of the greatest common divisor;
A computer program for performing a method comprising:

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