JP6683418B2 - Drive circuit for display device and display device - Google Patents

Description

  The present invention relates to a drive circuit of a liquid crystal display device or an organic EL display device, and more particularly to a partial drive circuit technology of a gate line capable of stable operation.

  In recent years, TVs and mobile phones / smartphones that use oxide semiconductors for backplane TFTs have been commercialized. The oxide semiconductor has favorable off-leakage characteristics and can reduce power consumption by lowering the refresh rate. There are the following two low refresh rate (LRR) technologies.

(1) Full screen LRR
This is a method in which the case where the video data of the previous screen and the screen to be displayed next time are the same is detected and the video data writing rate (refresh rate) is lowered. This technique is effective in the case of displaying a still image, and usually reduces 60 Hz operation to a rate of 10 Hz or less. In this case, the panel driving algorithm needs to be changed, but the circuit inside the panel need not be changed.

(2) Partial LRR
This is a method of detecting the difference from the previous screen data for each gate line and writing the video data only when the difference is detected. Mostly still images, but useful for images that need to be partially refreshed. In this case, it is necessary to change the panel driving algorithm and the circuit inside the panel (gate line driving circuit). The products equipped with the partial LRR circuit have not been put on the market yet, and it is considered that each company is currently developing reliable circuit technology.

  Further, by using the LRR drive, touch detection can be performed during the time when video data is not written. As a result, it becomes possible to detect smaller points (such as recognition of Pen destinations) and those that have not been able to obtain an S / N ratio up to now, and a more comfortable user interface function can be provided.

However, the conventional techniques have the following problems.
TFTs made of amorphous silicon or oxide have different degrees of deterioration depending on the operation frequency. As the deterioration factor, voltage stress (voltage application stress), heat stress, light stress, etc. can be considered. Among these, making the voltage stress uniform is effective for ensuring the reliability of circuit operation.

  When partial driving is performed to partially drive the gate line, the frequency of use of the GIP (Gate driver In Panel) circuit is different, so that the voltage stress state becomes non-uniform, and it becomes difficult to secure reliability. .

  That is, in the conventional normal drive, a uniform voltage load was applied to all the GIPs, so that the voltage stress was not a problem. However, partial driving causes a GIP circuit that is not activated or a GIP circuit that is always activated to appear, and there is a circuit whose degree of deterioration differs depending on the frequency of activation. As a result, a GIP circuit that does not operate appears, leading to a decrease in reliability.

  As described above, the non-uniformity of the voltage stress due to the presence of the circuits that are not driven is a problem that occurs with the realization of partial driving. Then, as a conventional technique, it has been considered to overcome this problem as a manufacturing method by guaranteeing TFT characteristics that are resistant to voltage stress in terms of process or device.

  However, the root cause of the above-mentioned problem is that the voltage stress is different, and it is necessary to equalize this voltage stress in order to solve it drivingly.

  The present invention has been made to solve the above problems, and a display device that realizes a gate line partial drive circuit technology capable of stable operation by equalizing voltage application stress during partial drive. The purpose is to obtain a driving circuit and a display device.

A drive circuit for a display device according to the present invention includes a shift register circuit including a plurality of stages of shift registers which operate in synchronization with any of a plurality of clocks having the same cycle and different phases, and a shift register circuit including a plurality of clocks. A driving circuit for a display device , which drives each of a plurality of gate lines in synchronization, and includes a plurality of stages of gate driver units each including a first to an eighth TFT, and is capable of partially driving a plurality of gate lines. In addition, a plurality of stages of Q node driver units provided corresponding to the plurality of stages of shift registers and the plurality of stages of gate driver units are further provided, and each of the plurality of stages of Q node driver units is applicable. in stage, the output of the shift register is "H" state, and QD nodes connected between the first 1TFT and the 6TFT gate driver part is "L" Because it is state, when the gate driver unit is determined not to be activated in the partial driving, using the clock to activate in a period that does not affect the display of the relevant stage or Vdd,, it has been activated The gate driver unit which is determined not to be activated is activated in a period in which the corresponding gate line is in the “L” state and inactive and does not affect the display.

  According to the present invention, the gate driver unit that has not been activated during partial driving is detected, and the gate driver unit that has not been activated is activated during a period that does not affect the display. It is possible to obtain a drive circuit and a display device for a display device which can realize uniform applied stress and realize a partial drive circuit technology of a gate line capable of stable operation.

It is the figure which showed the whole view of a display device, and the position of the GIP circuit. It is the figure which showed the GIP circuit structure of partial drive. FIG. 3 is a diagram showing a specific circuit configuration of a gate driver unit shown in FIG. 2. FIG. 3 is a diagram showing drive waveforms of respective parts of the partial GIP circuit shown in FIG. 2. FIG. 3 is a diagram showing a partial drive GIP circuit configuration in the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a Q node driver unit according to the first embodiment of the present invention. FIG. 7 is a diagram showing drive waveforms of respective parts of the partial GIP circuit shown in FIGS. 5 and 6 described above in the first embodiment of the present invention. 3 is a block diagram of a Q node driver unit in Embodiment 1. FIG. 7 is a block diagram of a Q node driver unit in Embodiment 2. FIG. FIG. 9 is a block diagram of a Q node driver unit in the third embodiment. It is explanatory drawing which put together the effect of the equalization of the voltage stress in Embodiment 1 of this invention.

  Preferred embodiments of a drive circuit for a display device and a display device of the present invention will be described below with reference to the drawings. In the following, first, a situation in which the voltage stress becomes non-uniform will be described with reference to FIGS. 1 to 4, and thereafter, the technical features of the present invention for equalizing the voltage stress will be described with reference to FIGS. This will be described with reference to FIG.

  FIG. 1 is an overall view of the display device and a view showing the position of the GIP circuit. FIG. 1 shows an example in which the Gate line is driven from both sides of the display surface. Further, FIG. 2 is a diagram showing a partial drive GIP circuit configuration, and specifically, shows the left side GIP circuit configuration in FIG. In addition, in FIG. 2, not all wirings are shown accurately.

  The partial GIP circuit shown in FIG. 2 includes a shift register section 10, an AND circuit 20, and a gate driver section 30, and particularly shows a circuit section related to the gate lines GL1, GL3, GL5, GL7, and GL9. ing. Here, the AND circuit 20 controls whether or not to raise the gate line by generating a DE (Driver Enable) signal.

  One-sided four-phase CLK signals CLK1, CLK3, CLK5, CLK7 are input to both the shift register unit 10 and the gate driver unit 30. Further, an AND logic output of an OE (Output Enable) signal and an output signal from the shift register unit 10 is input to the gate driver unit 30 as a DE signal.

  Here, the OE signal is a basic signal that controls whether or not to drive the gate line and realizes partial driving.

  FIG. 3 is a diagram showing a specific circuit configuration of the gate driver unit 30 shown in FIG. The gate driver unit 30 includes eight TFTs (T1 to T8). The shift register unit 10 is also composed of the same TFT.

  FIG. 4 is a diagram showing drive waveforms of respective parts of the partial GIP circuit shown in FIG. In FIG. 4, a waveform is shown when OE is always "H". Further, Qi indicates the Q node of the shift register unit 10.

  The operation of the gate line GL5 will be described below as an example using the circuit configurations of FIGS. 2 and 3 and the drive waveforms of FIG. At the timing when CLK1 switches to “H”, the Q5 node of the shift register unit 10 (5) becomes “H”. Here, since OE is always "H", the Q5 node becomes "H", and at the same time, the Q node of the gate driver unit 30 (5) also becomes "H", CLK5 is activated, and at the same time, the gate line GL5 becomes It is output as "H". The Q5 node drops to VSS at the timing when VSR9 becomes "H".

  When performing the partial drive, the shift register unit 10 always operates according to CLK. On the other hand, the gate driver unit 30 operates only when the DEi signal is “H”.

  When DEi is "H", T1 is turned ON, the Q node is turned "H", and T6 is turned ON. When DEi is "L" due to the partial drive, neither T1 nor T6 is turned on.

  Therefore, the partial drive causes a difference in the voltage application stress between the activated TFT and the non-activated TFT. This difference depends on the crystallinity of the semiconductor material, driving conditions (bias and temperature), etc., and making these conditions uniform is an effective means for ensuring product reliability. Amorphous silicon TFTs and oxide TFTs (that is, when a semiconductor in which amorphous occupies most of them are used for TFTs (thin film transistors)) have different deterioration rates depending on their BTS (Bias-Temperature Stress) conditions. is necessary.

Based on the above background, details of the technical features of the present invention for equalizing the voltage stress will be described below.
FIG. 5 is a diagram showing a partial drive GIP circuit configuration according to the first embodiment of the present invention. The GIP circuit according to the first embodiment shown in FIG. 5 is newly provided with a Q node driver section 40 instead of the AND circuit 20 as compared with the conventional GIP circuit shown in FIG. At the same time, the OE signal is directly input to each gate driver unit 30.

  In the newly added Q node driver unit 40, the gate driver unit 30 is not activated based on the signal (Vsr) from the shift register unit 10 and the QB node signal (QDB) of the gate driver unit 30. It is a circuit that sets the Q node (QD) of the gate driver unit 30 to “H” when this is detected.

  Further, the gate driver unit 30 operates so as not to raise the gate signal GLi when the OE signal is “L”.

  FIG. 6 is a circuit configuration diagram of Q node driver unit 40 in accordance with the first exemplary embodiment of the present invention. The Q-node driver unit 40 according to the first embodiment includes a detection circuit 41, a reset circuit 42, and a TFT 43 (Tdq) having a gate to which an output (Q-Act_n) from the detection circuit 41 is input. .

  Here, when the detection circuit 41 detects the gate driver unit 30 which has not been activated (that is, the QD node has not become “H”) due to partial driving, the detection circuit 41 sets the Q-Act signal to “H”. It is a circuit to do.

  The reset circuit 42 is a circuit that sets the detection circuit 41 and the QD node to VSS by using the outputs (Vsr_n + 4, Vsr_n + 8) from the shift register unit 10 of the next stage and subsequent stages.

  FIG. 7 is a diagram showing drive waveforms of respective parts of the partial GIP circuit shown in FIGS. 5 and 6 in the first embodiment of the present invention, and specifically shows the operation of the gate signal GL5. is there. When the Q node driver unit 40 (5) detects the QD5 that has not been activated (QDB5 “H” × Vsr5 “H”), it sets Q-Act5 to “H”.

  As a result, the Q node driver unit 40 (5) turns CLK1 that becomes “H” into Tdq during the period in which the internal Tdq is turned on and the GL5 is immutable (that is, the period when CLK5 is “L”). By inputting, QD5 is set to "H". Since Q-Act5 is "H" until CLK1 changes from "H" to "L", QD5 can be toggled from "H" to "L".

  Next, a specific configuration of the Q node driver unit 40 in the partial GIP circuit of the present invention will be specifically described as Examples 1 to 3 with reference to the drawings.

[Example 1]
FIG. 8 is a block diagram of the Q node driver unit 40 according to the first embodiment.
In the first embodiment, the detection circuit 41 that detects a GIP circuit that has not been activated is composed of vertically stacked Tsr and Tqb. Further, the reset circuit 42 resets the voltage of each node (Q-Act, N2, QD).

  The two transistors Tse3 and Tse4 have a role of setting the node N2 to “H” and the node Q-Act to “L” when the power is turned on.

[Example 2]
FIG. 9 is a block diagram of the Q node driver unit 40 according to the second embodiment.
The second embodiment shows an example in which CLK is introduced into the drain terminal of Tdq.

[Example 3]
FIG. 10 is a block diagram of the Q node driver unit 40 in the third embodiment.
In the third embodiment, CLK is introduced to the drain terminal of Tdq, and QDB is connected to the drain terminal of Tqb in the detection circuit 41, so that Tsr in the detection circuit 41 is unnecessary.

  FIG. 11 is an explanatory diagram summarizing the effects of equalizing the voltage stress according to the first embodiment of the present invention. More specifically, the states of the gate-source voltage (Vgs) applied to the transistors T1 and T6 in the gate driver unit 30 shown in FIG. 3 are schematically shown for various driving states. It is a figure.

  FIG. 11A shows a stress state in the case of normal driving, and FIG. 11B shows a stress state in the conventional circuit configuration (that is, the circuit configuration of FIG. 2) in the partial driving. 11 (c) shows a stress state in the circuit configuration of the first embodiment (that is, the circuit configuration of FIG. 5 including the Q node driver section 40) when the partial drive is performed.

  Further, in FIG. 11, PBTS represents that a + (plus) voltage is applied to the gate, and NBTS represents that a- (minus) voltage is applied to the gate. By adopting the circuit configuration of the first embodiment, the stress state of FIG. 11C is obtained, and the stress state closer to the normal drive of FIG. 11A is obtained as compared with the conventional configuration of FIG. 11B. You can see that.

As described above, according to the first embodiment, the following technical problems are solved in order to equalize the voltage application stress due to the partial drive.
(Technical problem 1) To detect a GIP circuit that is not activated in partial driving.
(Technical problem 2) To activate a GIP circuit that has not been activated and to apply a voltage stress during a period that does not affect the display.

In order to solve these technical problems 1 and 2, in the first embodiment, a Q node driver unit is provided and the following functions are realized.
(Function 1) For the technical problem 1, when the output of the shift register unit is "H", it is detected that the Q node of the gate driver unit is "L" and the Qb node is "H". Then, the GIP circuit which has not been activated is detected.
(Function 2) With respect to the technical problem 2, a GIP circuit which is not activated by pairing clocks with one of them active while the other is inactive and adopting the paired clock It is activated during the period that does not affect the display.

  By providing the Q node driver unit that realizes the functions 1 and 2 as described above, the number of times of voltage stress on the TFTs (T1 and T6) that are easily deteriorated in the GIP circuit can be made equal to that at the time of normal driving. As a result, it is possible to equalize the voltage application stress at the time of partial driving, and it is possible to obtain a drive circuit and a display device for a display device that realizes a gate line partial drive circuit technology that can be stably operated.

  10 shift register part, 20 AND circuit, 30 gate driver part, 40 Q node driver part, 41 detection circuit, 42 reset circuit, 43 transistor.

Claims (4)

A drive circuit for a display device capable of partially driving a plurality of gate lines,
A shift register circuit including a plurality of stages of shift registers that operate in synchronization with any of a plurality of clocks having the same cycle and different phases,
Wherein the plurality of synchronization with the one clock to drive each of the plurality of gate lines, each comprise a gate driver of the plurality of stages including a first to 8TFT, a,
The gate terminal, drain terminal, and source terminal of the first TFT are connected to the data enable signal DE, power supply voltage Vdd, and QD node , respectively, and the gate terminal, drain terminal, and source terminal of the sixth TFT are the QD node, clock, and output terminal. They are respectively connected to,
When the data enable signal DE has an "H" state, the first TFT is turned on and the QD node has an "H" state,
When the QD node has an “H” state, the sixth TFT is turned on and the “H” state of the clock is output through the output terminal,
Further comprising a plurality of stages of Q-node driver units provided corresponding to the plurality of stages of shift registers and the plurality of stages of gate driver units, respectively.
Each of the Q node drivers of the plurality of stages, in the appropriate stage, the output of the shift register is "H" state, and between the gate terminal of the source terminal of the first 1TFT gate driver unit first 6TFT since the QD nodes connected is "L" state, when the gate driver unit is determined not to be activated in the partial driving, activated in a period that does not affect the display of the relevant stage The gate line is inactive in the “L” state with respect to the QD node of the gate driver unit that is determined to be inactive by using the clock or the power supply voltage Vdd that does not affect the display. A drive circuit for a display device which applies the "H" state in a period. Each of the plurality of stages of Q node driver units is
Based on the output of the shift register and the output of the QD node of the gate driver unit in the corresponding stage, it is determined whether or not the gate driver unit of the corresponding stage is activated in the partial drive, and activation is performed. A detection circuit that outputs a signal in the "H" state when it is determined that the signal has not been converted,
A reset circuit that resets the output of the detection circuit and the QD node in accordance with the output of the shift register unit at a stage subsequent to the corresponding stage;
The output of the detection circuit is connected to the gate terminal, and the clock that is activated during a period that does not affect the display of the corresponding stage is connected to the drain terminal and is determined not to be activated. The drive circuit for a display device according to claim 1, further comprising a transistor that outputs a signal that applies an “H” state to the node during a period that does not affect the display. The drive circuit for a display device according to claim 1, which is applied to a display device including a TFT using an amorphous semiconductor. A display device comprising the drive circuit for the display device according to claim 1.

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