JP6686282B2 - Circuit device, physical quantity detection device, electronic device and moving body - Google Patents

Description

  The present invention relates to a circuit device, a physical quantity detection device, an electronic device, a moving body, and the like.

  Conventionally, there is known a circuit device that detects a physical quantity based on a detection signal from a physical quantity transducer. Taking a gyro sensor as an example, the circuit device detects an angular velocity or the like as a physical quantity. The gyro sensor is incorporated in an electronic device such as a digital camera or a smartphone or a moving body such as a car or an airplane, and shake correction, attitude control, GPS autonomous navigation, etc. are performed by using detected physical quantities such as angular velocity. .

  As a conventional technique of such a gyro sensor circuit device, there is a technique disclosed in Patent Document 1, for example.

JP, 2008-122122, A

  In this conventional technique, a differential signal processing circuit such as a differential amplifier circuit is provided at a stage subsequent to the first and second Q / V conversion circuits (charge / voltage conversion circuits) of the detection circuit. The differential signal processing circuit amplifies the differential components of the first and second signals from the first and second Q / V conversion circuits and outputs the amplified differential components to the subsequent circuit.

  However, until now, such failure detection of the differential signal processing circuit could not be performed. For example, the failure of the entire detection circuit could be detected, but the failure of the differential signal processing circuit could not be detected individually. For example, in the case where the differential signal processing circuit actually fails, but the differential component seems to be normally differentially amplified, in the failure detection of the detection circuit as a whole, Proper failure detection of the signal processing circuit cannot be realized. Therefore, when a failure occurs in the differential signal processing circuit over time while the circuit device is actually operating, it cannot be appropriately dealt with, and problems such as deterioration of reliability occur.

  According to some aspects of the present invention, it is possible to provide a circuit device, a physical quantity detection device, an electronic device, a moving body, and the like that can appropriately detect a failure of a differential signal processing circuit.

  The present invention has been made to solve at least a part of the problems described above, and can be realized as the following modes or modes.

  According to one aspect of the present invention, the first signal of the first and second signals forming a differential signal is input to an inverting input terminal and the second signal is input to a non-inverting input terminal. A first amplifier of differential input single-ended output, and a second amplifier of differential input single-ended output in which the first signal is input to a non-inverting input terminal and the second signal is input to an inverting input terminal. The present invention relates to a circuit device including an amplifier and a failure detection circuit that detects a failure based on the output signal of the first amplifier and the output signal of the second amplifier.

  According to one embodiment of the present invention, the first and second signals forming the differential signal are input to the inverting input terminal and the non-inverting input terminal, respectively. ) Of the differential input single-ended output (differential input & single-ended output) to which the first amplifier and the first and second signals are input to the non-inverting input terminal and the inverting input terminal, respectively. Two amplifiers are provided. By providing such first and second amplifiers, the output signals of the first and second amplifiers become differential output signals, and a differential signal processing circuit for differential input / differential output is realized. it can. In one aspect of the present invention, failure detection is performed based on the output signal of the first amplifier and the output signal of the second amplifier of the differential signal processing circuit configured as described above. By doing so, it becomes possible to detect even a fault that may be overlooked when the differential signal processing circuit is configured with one fully differential amplifier with differential input and differential output. It is possible to provide a circuit device that can appropriately detect a failure of the signal processing circuit.

  Further, according to one aspect of the present invention, the first and second amplifiers may be amplifiers that perform single-ended output based on the same analog common voltage.

  With this configuration, for example, when the first amplifier outputs a positive polarity signal based on the analog common voltage, the second amplifier outputs a negative polarity signal based on the analog common voltage, When the first amplifier outputs a negative signal with the analog common voltage as a reference, the second amplifier can output a positive signal with the analog common voltage as a reference. A processing circuit can be realized.

  Further, in one aspect of the present invention, in the failure detection circuit, a monitoring voltage based on a voltage of the output signal of the first amplifier and a voltage of the output signal of the second amplifier is based on the analog common voltage. The failure may be detected by detecting whether or not it is within the judgment voltage range.

  With this configuration, for example, when the monitoring voltage based on the voltage of the output signals of the first and second amplifiers is within the determination voltage range, it is determined that the normal state is established, and the monitoring voltage is determined as If it is out of the voltage range, it can be determined that a failure may have occurred.

  Further, in one aspect of the present invention, the failure detection circuit is based on a monitor voltage obtained by voltage-dividing the voltage of the output signal of the first amplifier and the voltage of the output signal of the second amplifier. Therefore, failure detection may be performed.

  With this configuration, the voltage of the output signals of the first and second amplifiers can be simply voltage-divided, and the monitoring voltage generated by the voltage division can be used to appropriately detect the failure. Fault detection is possible in the configuration.

  Further, in one aspect of the present invention, the failure detection circuit detects whether the monitoring voltage is within a determination voltage range between a high-potential-side threshold voltage and a low-potential-side threshold voltage. , Failure detection may be performed.

  With this configuration, for example, when the monitoring voltage is within the determination voltage range defined by the threshold voltage on the high potential side and the threshold voltage on the low potential side, it is determined to be in the normal state, and the monitoring voltage is If it is outside the judgment voltage range, it can be judged that a failure may have occurred.

  Further, in one aspect of the present invention, the first amplifier is provided between a first operational amplifier, the inverting input terminal of the first amplifier, and an inverting input terminal of the first operational amplifier. A first resistive element, a second resistive element provided between the inverting input terminal of the first operational amplifier, and an output terminal of the first operational amplifier, and the non-inverting element of the first amplifier. Between a third resistance element provided between an inverting input terminal and a non-inverting input terminal of the first operational amplifier, the non-inverting input terminal of the first operational amplifier, and an analog common voltage node And a fourth resistance element provided in the second operational amplifier, the second amplifier having a second operational amplifier, the inverting input terminal of the second amplifier, and the inverting input terminal of the second operational amplifier. A fifth resistance element provided between the A sixth resistance element provided between the inverting input terminal of the width device and the output terminal of the second operational amplifier; the non-inverting input terminal of the second amplifier; and the second operational amplifier. A seventh resistance element provided between the non-inverting input terminal and the non-inverting input terminal of the second operational amplifier, and an eighth resistance element provided between the non-inverting input terminal of the second operational amplifier and the analog common voltage node. May be included.

  With this configuration, the first and second signals that form the differential signal are input to the inverting input terminal and the non-inverting input terminal of the first amplifier of the differential input single-ended output, respectively. Can be realized by the operational amplifier and the first to fourth resistance elements. The first and second signals are respectively input to the non-inverting input terminal and the inverting input terminal of the differential input single-ended output second amplifier, the second operational amplifier and the fifth to fifth It can be realized with the resistance element of 8.

  Further, according to one embodiment of the present invention, a drive circuit that drives the physical quantity transducer, and a detection circuit to which first and second detection signals from the physical quantity transducer are input are provided, and the detection circuit includes the first and second detection signals. A differential amplifier circuit configured by a second amplifier and including the first and second signals corresponding to the first and second detection signals may be included.

  With this configuration, the differential amplifier circuit of the detection circuit that performs the detection operation based on the first and second detection signals from the physical quantity transducer driven by the drive circuit is It can be realized by the second amplifier. Then, in the detection circuit having such a configuration, it becomes possible to individually detect the failure of the differential amplifier circuit including the first and second amplifiers, and the reliability can be improved.

  Further, in one aspect of the present invention, the detection circuit is provided in a front stage side of the differential amplifier circuit, receives the first detection signal, and outputs the first signal. A circuit, and a second charge / voltage conversion circuit which is provided on the front side of the differential amplifier circuit and which receives the second detection signal and outputs the second signal may be included.

  With this configuration, the first and second detection signals that are charge signals are converted into the first and second signals that are voltage signals by the first and second charge / voltage conversion circuits, and these The differential components of the first and second signals can be differentially amplified by the differential amplifier circuit composed of the first and second amplifiers. Then, in the detection circuit having such a configuration, it is possible to individually detect a failure of the differential amplifier circuit, and it is possible to improve reliability and the like.

  Further, according to one aspect of the present invention, a gain adjustment amplifier may be included that is provided on a subsequent stage side of the differential amplifier circuit and that adjusts a gain of an output signal of the differential amplifier circuit.

  With this configuration, the gain of the output signal of the differential amplifier circuit can be variably adjusted by using the gain adjustment amplifier provided on the subsequent stage side of the differential amplifier circuit.

  Further, according to one aspect of the present invention, a synchronous detection circuit may be included which is provided on a subsequent stage side of the gain adjustment amplifier and performs synchronous detection based on a synchronous signal from the drive circuit.

  With this configuration, in the detection circuit configured to extract the desired signal included in the first and second detection signals by synchronous detection, individual failure detection of the differential amplifier circuit becomes possible, and reliability can be improved. It is possible to improve.

  Another aspect of the present invention relates to a physical quantity detection device including the circuit device described above and the physical quantity transducer.

  Further, another aspect of the present invention relates to an electronic device including the circuit device described above.

  Further, another aspect of the present invention relates to a mobile body including the circuit device described above.

1 is a basic configuration example of a circuit device according to this embodiment. Detailed configuration example of the circuit device. 3A and 3B are signal waveform diagrams for explaining the operation of the circuit device. Overall system configuration example of the circuit device. Configuration example of the detection circuit. The structural example of the circuit device, electronic device, and gyro sensor (physical quantity detection device) of this embodiment. Detailed configuration example of the drive circuit and the detection circuit. A more detailed configuration example of the detection circuit. Configuration example of analog common voltage generation circuit. The signal waveform diagram explaining the self-diagnosis by a diagnostic circuit. FIG. 6 is an operation sequence diagram illustrating the operation of the circuit device. 12A to 12D are examples of a moving body and an electronic device in which the circuit device of this embodiment is incorporated.

  Hereinafter, preferred embodiments of the present invention will be described in detail. Note that the present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Circuit Device FIG. 1 shows a basic configuration example of the circuit device of this embodiment. The circuit device of this embodiment includes a first amplifier AMC1 and a second amplifier AMC2. The first and second amplifiers AMC1 and AMC2 constitute a differential amplifier circuit 70 (a differential signal processing circuit in a broad sense). Furthermore, the circuit device of this embodiment includes a failure detection circuit 160.

  The first amplifier AMC1 is a differential input / single-ended output (differential input & single-ended output) amplifier. Specifically, the first amplifier AMC1 receives the first signal QB1 of the first and second signals QB1 and QB2 forming the differential signal at the inverting input terminal TM1 (−), The second signal QB2 is input to the non-inverting input terminal TP1 (+). Then, the single-ended signal QC1 is output to the output node NC1.

  The second amplifier AMC2 is also a differential input / single-ended output (differential input & single-ended output) amplifier. Specifically, to the second amplifier AMC2, the first signal QB1 of the first and second signals QB1 and QB2 forming the differential signal is input to the non-inverting input terminal TP2 (+). , And the second signal QB2 is input to the inverting input terminal TM2 (−). Then, the single-ended signal QC2 is output to the output node NC2.

  These first and second AMC1 and AMC2 are amplifiers that perform single-ended output based on the same analog common voltage. The output signals QC1 and QC2 of the amplifiers AMC1 and AMC2 form the differential output signal of the differential amplifier circuit 70. For example, when the first amplifier AMC1 outputs the signal QC1 having a positive voltage with reference to the analog common voltage (analog ground), the second amplifier AMC2 has the negative voltage with reference to the analog common voltage. The signal QC2 of is output. While the first amplifier AMC1 outputs the negative voltage signal QC1 with reference to the analog common voltage, the second amplifier AMC2 outputs the positive voltage signal QC2 with reference to the analog common voltage. To do. Therefore, these signals QC1 and QC2 are differential output signals.

  Then, the failure detection circuit 160 performs failure detection based on the output signal QC1 of the first amplifier AMC1 and the output signal QC2 of the second amplifier AMC2. For example, failure detection is performed based on the voltage of the output signal QC1 of the first amplifier AMC1 and the voltage of the output signal QC2 of the second amplifier AMC2. Specifically, in the failure detection circuit 160, the monitoring voltage based on the voltage of the output signal QC1 of the first amplifier AMC1 and the voltage of the output signal QC2 of the second amplifier AMC2 uses the analog common voltage as a reference (center). Failure detection is performed by detecting whether or not it is within the judgment voltage range.

  For example, the failure detection circuit 160 detects a failure based on a monitoring voltage (divided voltage) obtained by voltage-dividing the voltage of the output signal QC1 of the first amplifier AMC1 and the voltage of the output signal of the second amplifier AMC2. I do. That is, failure detection is performed by detecting whether or not the monitoring voltage is within the determination voltage range between the high-potential-side threshold voltage and the low-potential-side threshold voltage. Then, the monitoring result signal DGC (diagnosis signal, failure detection signal) is output.

  As described above, in the present embodiment, the differential amplifier circuit 70 is configured by the two differential input / single-ended output amplifiers AMC1 and AMC2.

  That is, normally, the differential amplifier circuit 70 is generally realized by using one differential input / differential output fully differential amplifier.

  Contrary to this, in the present embodiment, the differential amplifier circuit 70 is realized by using two differential input / single-ended output amplifiers AMC1 and AMC2. When the two amplifiers AMC1 and AMC2 are used in this way, the circuit scale may increase, but in the present embodiment, priority is given to properly detecting a failure of the differential amplifier circuit 70 and improving reliability. is doing.

  As described above, the differential amplifier circuit 70 is configured by the two differential input / single-ended output amplifiers AMC1 and AMC2, and the failure detection circuit is formed by using the output signals QC1 and QC2 of the single-ended output amplifiers AMC1 and AMC2. Since the fault detection is performed by 160, proper fault detection of the differential amplifier circuit 70 can be realized. For example, in a normal full differential amplifier with differential input and differential output, there are cases where even if there is a circuit failure, it seems that the differential components are properly amplified. In such cases Therefore, there is a possibility that proper failure detection of the differential amplifier circuit 70 cannot be realized.

In this respect, in the present embodiment, since the differential amplifier circuit 70 is configured by the two differential input / single-ended output amplifiers AMC1 and AMC2, the failure detection circuit 160 detects the failure based on the output signals QC1 and QC2. By performing the above, it becomes possible to properly detect the failure in the above case. That is, the output signal QC1 amplifier AMC1 is generated based on both the signal QB1, QB2, the output signal QC 2 amps AMC 2 is also generated based on both the signal QB1, QB2. Therefore, even when a failure occurs in the path of the signal QB1 or a failure occurs in the path of the signal QB2, the influence of the failure affects the output signals QC1 and QC2 of the amplifiers AMC1 and AMC2. Therefore, by monitoring the output signals QC1 and QC2 by the failure detection circuit 160, it becomes possible to properly detect the occurrence of failures in both cases, and it is possible to realize appropriate failure detection of the differential amplifier circuit.

  FIG. 2 shows a detailed configuration example of the circuit device of this embodiment. In FIG. 2, the differential amplifier circuit 70 includes an amplifier AMC1 and an amplifier AMC2, and the amplifier AMC1 has a first operational amplifier OPC1 and first to fourth resistance elements RC1 to RC4.

  The first resistance element RC1 is provided between the inverting input terminal TM1 (node NB1) of the amplifier AMC1 and the inverting input terminal (node NC3) of the first operational amplifier OPC1. The second resistance element RC2 is provided between the inverting input terminal of the first operational amplifier OPC1 and the output terminal of the first operational amplifier OPC1 (the output terminal of the amplifier AMC1. Node NC1). That is, the first and second resistance elements RC1 and RC2 are connected in series between the inverting input terminal TM1 of the amplifier AMC1 and the output terminal (NC1) of the first operational amplifier OPC1. The signal QB1 from the previous circuit is input to the inverting input terminal TM1 (−) of the amplifier AMC1.

  The third resistance element R3 is provided between the non-inverting input terminal TP1 (node NB2) of the amplifier AMC1 and the non-inverting input terminal (node NC4) of the first operational amplifier OPC1. The fourth resistance element RC4 is provided between the non-inverting input terminal (NC4) of the first operational amplifier OPC1 and the node NC7 of the analog common voltage VCM. That is, the third and fourth resistance elements RC3 and RC4 are connected in series between the non-inverting input terminal TP1 of the amplifier AMC1 and the node NC7. The signal QB2 from the previous circuit is input to the non-inverting input terminal TP1 (+) of the amplifier AMC1.

  Note that, in FIG. 2, the node NC7 is set to the analog common voltage VCM (analog common voltage), and this analog common voltage VCM is generated by the analog common voltage generation circuit described later. For example, by connecting the output terminal of the analog common voltage generation circuit to the node NC7, the node NC7 is set to the analog common voltage VCM.

  The amplifier AMC2 has a second operational amplifier OPC2 and fifth to eighth resistance elements RC5 to RC8.

  The fifth resistance element RC5 is provided between the inverting input terminal TM2 (node NB2) of the amplifier AMC2 and the inverting input terminal (node NC5) of the second operational amplifier OPC2. The sixth resistance element RC6 is provided between the inverting input terminal (NC5) of the second operational amplifier OPC2 and the output terminal of the second operational amplifier OPC2 (output terminal of the amplifier AMC2. Node NC2). That is, the fifth and sixth resistance elements RC5 and RC6 are connected in series between the inverting input terminal TM2 of the amplifier AMC2 and the output terminal (NC2) of the second operational amplifier OPC2. The signal QB2 from the previous circuit is input to the inverting input terminal TM2 (−) of the amplifier AMC2.

  The seventh resistance element R7 is provided between the non-inverting input terminal TP2 (node NB1) of the amplifier AMC2 and the non-inverting input terminal (node NC6) of the second operational amplifier OPC2. The eighth resistance element RC8 is provided between the non-inverting input terminal (NC6) of the second operational amplifier OPC2 and the node NC7 of the analog common voltage VCM. That is, the seventh and eighth resistance elements RC7 and RC8 are connected in series between the non-inverting input terminal TP2 of the amplifier AMC2 and the node NC7. The signal QB1 from the previous circuit is input to the non-inverting input terminal TP2 of the amplifier AMC2. The resistance elements RC1 to RC8 can be realized by poly resistors (polysilicon resistors) or the like.

  Thus, the differential amplifier circuit 70 is composed of two differential input / single-ended output amplifiers AMCC1 and AMC2. That is, in the differential amplifier circuit 70, the signal QB1 of the signals QB1 and QB2 forming the differential signal is input to the inverting input terminal TM1 (−), and the signal QB2 is input to the non-inverting input terminal TP1 (+). It is composed of an amplifier AMC1 and an amplifier AMC2 in which the signal QB1 is input to the non-inverting input terminal TP2 (+) and the signal QB2 is input to the inverting input terminal TM2 (−).

  With such a configuration, the differential amplifier circuit 70 outputs differential signals QC1 and QC2 whose voltage changes to the positive side or the negative side with reference to the analog common voltage VCM (analog ground). become. For example, when the signal QC1 is a positive voltage with respect to the analog common voltage VCM, the signal QC2 is a negative voltage with respect to VCM. When the signal QC1 has a negative voltage with respect to VCM, the signal QC2 has a positive voltage with respect to VCM.

  Resistance elements RC9 and RC10 are provided between the output node NC1 of the output signal QC1 of the amplifier AMC1 and the output node NC2 of the output signal QC2 of the amplifier AMC2. These resistance elements RC9 and RC10 form a voltage dividing circuit. Then, a monitoring voltage VB obtained by voltage-dividing the voltage of the output signal QC1 of the amplifier AMC1 and the voltage of the output signal QC2 of the amplifier AMC2 is generated at the connection node NC8 of the resistance element RC9 and the resistance element RC10. For example, when the resistance values of the resistance elements RC9 and RC10 are equal, the monitoring voltage VB becomes the midpoint voltage of the voltage of the signal QC1 and the voltage of the signal QC2. Therefore, if the voltage of the signal QC1 is VQC1 and the voltage of the signal QC2 is VQC2, the monitoring voltage can be expressed as VB = (VQC1 + VQC2) / 2. The resistance values of the resistance elements RC9 and RC10 are arbitrary.

  Then, the failure detection circuit 160 detects the failure of the differential amplifier circuit 70 based on the monitoring voltage VB. That is, the failure detection circuit 160 detects whether or not the monitoring voltage VB obtained by voltage division of the signals QC1 and QC2 is within the determination voltage range with the analog common voltage VCM as a reference (center). Detect. For example, failure detection is performed by detecting whether or not the monitor voltage VB is within the determination voltage range between the high-potential-side threshold voltage VTH and the low-potential-side threshold voltage VTL.

  Specifically, the failure detection circuit 160 has comparators CPC1 and CPC2 and an OR circuit ORC1. The threshold voltage VTH on the high potential side is input to the inverting input terminal of the comparator CPC1, and the monitoring voltage VB that is a divided voltage (midpoint voltage) by the resistance elements RC9 and RC10 is input to the non-inverting input terminal. . The monitor voltage VB is input to the inverting input terminal of the comparator CPC2, and the low-potential-side threshold voltage VTL is input to the non-inverting input terminal. The OR circuit ORC1 receives the output signals of the comparators CPC1 and CPC2 and outputs a monitoring result signal DGC (diagnosis signal, failure detection signal).

  For example, when the monitoring voltage VB is within the judgment voltage range between the threshold voltage VTH and the threshold voltage VTL, the monitoring result signal DGC becomes L level, and the failure is not detected. On the other hand, when the monitoring voltage VB is out of the judgment voltage range, the monitoring result signal DGC goes to H level, which tells that a failure is detected.

  In FIG. 2, for example, the resistance values of the resistance elements RC1, RC3, RC5, and RC7 are R1, the resistance values of the resistance elements RC2, RC4, RC6, and RC8 are R2, and the differential amplification gain of the differential amplification circuit 70 is GC. Then, the relationship of GC / 2 = R2 / R1 is established.

  Then, the voltage of the node NC3 of the inverting input terminal of the operational amplifier OPC1 and the voltage of the node NC4 of the non-inverting input terminal are equalized by the virtual ground (virtual short) by the operational amplifier OPC1, and therefore the following expression (1) is established.

QB1 + {R1 / (R1 + R2)} (QC1-QB1)
= QB2 + {R1 / (R1 + R2)} (VCM-QB2) (1)
Here, when A = R1 / (R1 + R2), the following equation (2) is derived from the above equation (1).

QC1 = VCM-{(1-A) / A} × (QB1-QB2) (2)
Further, since the voltage of the node NC5 of the inverting input terminal of the operational amplifier OPC2 and the voltage of the node NC6 of the non-inverting input terminal become equal due to virtual grounding by the operational amplifier OPC2, the following expression (3) is established.

QB2 + {R1 / (R1 + R2)} (QC2-QB2)
= QB1 + {R1 / (R1 + R2)} (VCM-QB1) (3)
The following equation (4) is derived from the above equation (3).

QC2 = VCM + {(1-A) / A} × (QB1-QB2) (4)
Here, since A = R1 / (R1 + R2), (1−A) / A = R2 / R1 = GC / 2. Therefore, the above equations (2) and (4) can be expressed as the following equations (5) and (6).

QC1 = VCM- (GC / 2) × (QB1-QB2) (5)
QC2 = VCM + (GC / 2) × (QB1-QB2) (6)
Further, the following expression (7) is derived from the above expressions (5) and (6).

QC1-QC2 = -GCx (QB1-QB2) (7)
In this way, the differential amplifier circuit 70 receives QC1 = VCM- (GC / 2) * (QB1-QB2) and QC2 = VCM + (GC / 2) * when the differential signals QB1 and QB2 are input. The signal of (QB1-QB2) is output. That is, the differential amplifier circuit 70 outputs differential signals QC1 and QC2 in which the differential components (QB1-QB2) of the signals QB1 and QB2 are multiplied by the gain GC and the polarities are inverted with respect to the analog common voltage VCM. To do.

  3A and 3B are signal waveform diagrams for explaining the operation of the circuit device of this embodiment. FIG. 3A is a signal waveform when a failure has not occurred, and FIG. 3B is a signal waveform when a failure has occurred.

  As described above, the amplifiers AMC1 and AMC2 are amplifiers that perform single-ended output based on the same analog common voltage VCM. Therefore, as shown in FIG. 3A, the output signal QC1 of the amplifier AMC1 and the output signal QC2 of the amplifier AMC2 have symmetrical signal waveforms with the analog common voltage VCM as the center (reference). That is, when the signal QC1 has a positive voltage with respect to VCM, the signal QC2 has a negative voltage with respect to VCM, and when the signal QC1 has a negative voltage with respect to VCM, QC2 has a positive voltage with respect to VCM. That is, in the above equations (5) and (6), QC1 = VCM- (GC / 2) * (QB1-QB2), QC2 = VCM + (GC / 2) * (QB1-QB2) , The signals QC1 and QC2 change in voltage level according to the signals QB1 and QB2. Then, the relation of (QC1 + QC2) / 2 = VCM is established.

  The resistance values of the resistance elements RC9 and RC10 in FIG. 2 are equal, and the monitoring voltage VB, which is a divided voltage by the resistance elements RC9 and RC10, is the midpoint voltage of the signals QC1 and QC2. Therefore, VB = (QC1 + QC2) / 2 = VCM, and the monitor voltage VB matches the analog common voltage VCM.

  As shown in FIG. 3A, the determination voltage range of the failure detection circuit 160 is a voltage range defined by the threshold voltages VTH and VTL, for example, (VTH + VTL) / 2 = VCM. That is, the analog common voltage VCM is the midpoint voltage between the threshold voltages VTH and VTL.

  When no failure has occurred, the monitor voltage VB is within the determination voltage range defined by the threshold voltages VTH and VTL, as shown in FIG. As a result, the failure detection circuit 160 outputs the L-level monitoring result signal DGC.

  FIG. 3B is a signal waveform when a failure occurs, for example, when the output signal QC2 of the amplifier AMC2 is short-circuited to the analog common voltage VCM. In this case, since the signal QC1 and the signal QC2 do not have symmetrical signal waveforms centering on the analog common voltage VCM, the voltage level of the monitoring voltage VB varies.

  That is, the voltage level of the signal QC1 changes according to the signals QB1 and QB2, as represented by QC1 = VCM- (GC / 2) * (QB1-QB2). However, the signal QC2 is short-circuited to the analog common voltage VCM, and the relationship of QC2 = VCM + (GC / 2) × (QB1−QB2) does not hold and QC2 = VCM. Therefore, in FIG. 3A, VB = (QC1 + QC2) / 2 = VCM holds, but it does not hold in FIG. 3B. That is, the voltage level of the monitor voltage VB varies as represented by VB = (QC1 + QC2) / 2 = (QC1 + VCM) / 2 = VCM− (GC / 4) × (QB1−QB2).

  In the period T1 of FIG. 3B, the monitoring voltage VB exceeds the threshold voltage VTH and is outside the determination voltage range, so that the monitoring result signal DGC is at the H level. In the period T2, the monitoring voltage VB becomes lower than the threshold voltage VTL and is out of the judgment voltage range, so that the monitoring result signal DGC is at the H level. The same applies to the periods T3, T4, T5, and T6. A failure can be detected from these judgment results.

  Specifically, for example, it is determined that a failure (abnormality) has occurred when the monitoring voltage VB is out of the determination range for a specified time or longer. For example, the monitoring result signal DGC, which is the monitoring result, may be periodically monitored, and if the number of times the monitoring result signal DGC has become the H level is equal to or greater than the specified number, it may be determined that a failure has occurred. . Alternatively, it may be determined that a failure has occurred when the duty ratio of the monitoring result signal DGC (the ratio occupied by the H level period) is equal to or higher than the specified duty ratio.

  As described above, in the present embodiment, whether the monitoring voltage VB based on the voltage of the output signal QC1 of the amplifier AMC1 and the voltage of the output signal QC2 of the amplifier AMC2 is within the determination voltage range based on the analog common voltage VCM. Failure detection is performed by detecting that. That is, the failure detection is performed based on the monitoring voltage VB obtained by dividing the voltage of the output signal QC1 of the amplifier AMC1 and the voltage of the output signal QC2 of the amplifier AMC2. By doing so, it becomes possible to properly realize individual failure detection of the differential amplifier circuit 70 with a simple circuit configuration.

  FIG. 4 is an example of the overall system configuration of the circuit device of this embodiment. The circuit device of FIG. 4 includes a drive circuit 30, a detection circuit 60, a control unit 140, a register unit 142, and a failure detection circuit 160.

  The drive circuit 30 drives the physical quantity transducer 18. For example, the physical quantity transducer 18 is driven by receiving the feedback signal DI from the physical quantity transducer 18 and outputting the drive signal DQ corresponding to the feedback signal DI. For example, the first and second detection signals IQ1 and IQ2 from the physical quantity transducer 18 are input to the detection circuit 60 of the circuit device via the terminals PD1 and PD2 (pads). The feedback signal DI from the physical quantity transducer 18 is input to the drive circuit 30 of the circuit device via the terminal PD3 (pad), and the drive circuit 30 outputs the drive signal DQ to the physical quantity transducer 18 via the terminal PD4 (pad). Output.

  The detection circuit 60 includes an amplifier circuit 61, an A / D conversion circuit 100, and a DSP section 110 (digital signal processing section). The amplifier circuit 61 has the differential amplifier circuit 70 described with reference to FIGS. 1 and 2. As described above, the circuit device of the present embodiment includes the drive circuit 30 that drives the physical quantity transducer 18, and the detection circuit 60 to which the first and second detection signals IQ1 and IQ2 from the physical quantity transducer 18 are input. The detection circuit 60 is composed of first and second amplifiers AMC1 and AMC2 as shown in FIGS. 1 and 2, and has first and second signals corresponding to the first and second detection signals IQ1 and IQ2. It includes a differential amplifier circuit 70 to which QB1 and QB2 are input. Details of the amplifier circuit 61, the A / D conversion circuit 100, and the DSP unit 110 will be described later.

  The detection circuit 60 is not limited to the configuration shown in FIG. 4, and various modifications can be made such as omitting some of the constituent elements and adding other constituent elements. For example, the detection circuit 60 may be a type that outputs an analog detection result without providing the A / D conversion circuit 100 and the DSP unit 110.

  The control unit 140 performs various control processes. For example, the control unit 140 performs control processing of the drive circuit 30 and control processing of the detection circuit 60. Further, the control unit 140 receives the monitoring result signal DGC from the failure detection circuit 160 and performs failure determination processing. That is, various failure determination processes as described with reference to FIGS. 3A and 3B are performed. The control unit 140 can be realized by, for example, a logic circuit generated by an automatic placement and routing method such as a gate array, or a processor that operates based on firmware or the like.

  The register unit 142 has a register in which various information is set. The register unit 142 can be realized by, for example, a memory such as SRAM or a flip-flop circuit. For example, the failure determination result information in the control unit 140 is stored in this register unit 142. Then, an external controller or the like can read the failure determination result information by accessing the register unit 142.

  FIG. 5 shows a configuration example of the detection circuit 60. The detection circuit 60 is not limited to the configuration shown in FIG. 5, and various modifications can be made such as omitting some of the constituent elements and adding other constituent elements.

  The detection circuit 60 includes Q / V conversion circuits 62 and 64 (first and second charge / voltage conversion circuits). The Q / V conversion circuit 62 is provided in the front stage side of the differential amplifier circuit 70, receives the first detection signal IQ1 and outputs the first signal QB1. The Q / V conversion circuit 64 is provided on the front side of the differential amplifier circuit 70, receives the second detection signal IQ2, and outputs the second signal QB2. The first signal QB1 is input to the inverting input terminal TM1 of the amplifier AMC1 and the non-inverting input terminal TP2 of the amplifier AMC2 of the differential amplifier circuit 70. The second signal QB2 is input to the non-inverting input terminal TP1 of the amplifier AMC1 of the differential amplifier circuit 70 and the inverting input terminal TM2 of the amplifier AMC2.

  The Q / V conversion circuits 62 and 64 (charge amplifiers) are circuits that convert a charge signal (minute charge signal, minute current signal) from the physical quantity transducer 18 into a voltage signal, and are considered as a type of I / V conversion circuit. You can also For example, the Q / V conversion circuit 62 converts the first detection signal IQ1 which is a minute charge signal into a first signal QB1 which is a voltage signal, and the Q / V conversion circuit 64 includes a second signal which is a minute charge signal. Detection signal IQ2 is converted into a second signal QB2 which is a voltage signal. The converted first and second signals QB1 and QB2 are also differential signals having opposite phases. These Q / V conversion circuits 62 and 64 include, for example, operational amplifiers and feedback capacitors. Further, the Q / V conversion circuits 62 and 64 may include feedback resistance elements.

  Further, the detection circuit 60 includes a gain adjustment amplifier 76 which is provided on the subsequent stage side of the differential amplification circuit 70 and which adjusts the gains of the output signals QC1 and QC2 of the differential amplification circuit 70. Specifically, the gain adjustment amplifier 76 receives the differential signals QC1 and QC2, amplifies these signals with an adjustable gain, and outputs the differential signals QD1 and QD2.

  Further, the detection circuit 60 includes a synchronous detection circuit 81 that is provided on the subsequent stage side of the gain adjustment amplifier 76 and performs synchronous detection based on the synchronous signal SYC from the drive circuit 30. The synchronous detection circuit 81 performs synchronous detection on the output signals QD1 and QD2 from the gain adjusting amplifier 76 based on the synchronous signal SYC, and performs synchronous detection to extract a desired signal while removing unnecessary signals.

  As described above, according to the circuit device of the present embodiment, by configuring the differential amplifier circuit 70 with the two amplifiers AMC1 and AMC2 for differential input / single-ended output, amplification of differential input / differential output is performed. By realizing the circuit and monitoring the output signals QC1 and QC2 of the amplifiers AMC1 and AMC2, individual failure detection of the differential amplifier circuit 70 is realized.

  For example, as a method of the comparative example of the present embodiment, a method of configuring the differential amplifier circuit 70 with one fully differential amplifier of differential input / differential output can be considered.

  However, the fully differential amplifier only amplifies the differential component of the first and second input signals, and the deviation of the midpoint voltage levels of the differential first and second output signals is allowed. . That is, although the differential components of the first and second output signals are properly amplified, the situation where the midpoint voltage level of the first and second output signals fluctuates is generally acceptable. It Therefore, for example, there is some failure in the differential amplifier circuit, and it seems that the differential component is properly amplified, but the voltage levels of the first and second output signals are abnormal voltage levels. Such cases may be overlooked. For example, such a case may be overlooked only by the method of detecting the failure of the detection circuit 60 as a whole, and the reliability may be lowered.

  In this respect, in the present embodiment, the differential amplifier circuit 70 is composed of two amplifiers AMC1 and AMC2 having a differential input and a single end output, and failure detection is performed based on the output signals QC1 and QC2. Therefore, although the circuit scale is slightly redundant, the above case can be detected by individual failure diagnosis of the differential amplifier circuit 70.

  For example, as described with reference to FIG. 3A, in the present embodiment, the amplifiers AMC1 and AMC2 are the amplifiers that perform single-ended output with the same analog common voltage VCM as a reference, so that in the normal state, , And signals QC1 and QC2 having symmetrical signal waveforms having positive or negative voltages with reference to the analog common voltage VCM. That is, not only the differential components of the signals QB1 and QB2 are amplified, but also the voltage levels of the signals QC1 and QC2 are maintained at the voltage level based on the analog common voltage VCM.

  Then, as described with reference to FIG. 3B, when a failure occurs in the differential amplifier circuit 70, the symmetry of the signal waveforms of the signals QC1 and QC2 is destroyed, so that the failure is detected by monitoring the signals QC1 and QC2. Can be detected. Further, the determination voltage range for the failure detection need only be set to a voltage range based on the analog common voltage VCM, so that the failure detection operation can be simplified. Therefore, the reliability and the like can be significantly improved as compared with the method of the comparative example in which the differential amplifier circuit 70 is configured by one all-differential amplifier.

  Further, in the detection circuit 60 as shown in FIG. 5, the method of only performing the entire failure diagnosis may miss the individual failure of the differential amplifier circuit 70.

  In this regard, in the present embodiment, the failure detection circuit 160 monitors the states of the output signals QC1 and QC2 of the differential amplifier circuit 70 configured by the two amplifiers AMC1 and AMC2 having the differential input and the single end output, Since the failure detection is performed, it is possible to individually detect the failure of the differential amplifier circuit 70. Therefore, even when a failure occurs in the differential amplifier circuit 70 over time, this can be appropriately dealt with, and the reliability against failure over time can be significantly improved.

2. Detailed Configuration of Electronic Device, Gyro Sensor, and Circuit Device FIG. 6 shows the circuit device 20 of the present embodiment, a gyro sensor 510 (a physical quantity detection device in a broad sense) including the circuit device 20, and an electronic device including the gyro sensor 510. The detailed structural example of 500 is shown.

  The circuit device 20, the electronic device 500, and the gyro sensor 510 are not limited to the configuration shown in FIG. 6, and various modifications such as omission of some of the components and addition of other components are possible. . Further, as the electronic device 500 of the present embodiment, various types of devices such as a digital camera, a video camera, a smartphone, a mobile phone, a car navigation system, a robot, a biological information detection device, a game machine, a clock, a health appliance, or a portable information terminal can be used. Equipment can be assumed. In the following, the case where the physical quantity transducer is a piezoelectric vibrating piece (vibration gyro) and the sensor is a gyro sensor will be described as an example, but the present invention is not limited to this. For example, the present invention is applicable to a vibration gyro of a capacitance detection method formed of a silicon substrate or the like, a physical quantity transducer that detects a physical quantity equivalent to angular velocity information or a physical quantity other than angular velocity information.

  The electronic device 500 includes a gyro sensor 510 and a processing unit 520. Further, the memory 530, the operation unit 540, and the display unit 550 can be included. A processing unit 520 (controller) realized by a CPU, MPU, etc. controls the gyro sensor 510 etc. and controls the electronic device 500 as a whole. The processing unit 520 also performs processing based on the angular velocity information (physical quantity in a broad sense) detected by the gyro sensor 510. For example, processing for camera shake correction, attitude control, GPS autonomous navigation, etc. is performed based on the angular velocity information. The memory 530 (ROM, RAM, etc.) stores control programs and various data, and functions as a work area and a data storage area. The operation unit 540 is for the user to operate the electronic device 500, and the display unit 550 displays various information to the user.

  The gyro sensor 510 (physical quantity detection device) includes the resonator element 10 and the circuit device 20. The resonator element 10 (a physical quantity transducer in a broad sense) is a piezoelectric resonator element formed of a thin plate of a piezoelectric material such as quartz. Specifically, the resonator element 10 is a double T-shaped resonator element formed of a Z-cut crystal substrate.

  The circuit device 20 includes a drive circuit 30, a detection circuit 60, a control unit 140, a register unit 142, a diagnostic circuit 150, and a failure detection circuit 160. Various modifications such as omitting some of these constituent elements and adding other constituent elements are possible.

  The drive circuit 30 outputs the drive signal DQ to drive the resonator element 10. For example, the vibrator element 10 is excited by receiving the feedback signal DI from the vibrator element 10 and outputting the drive signal DQ corresponding thereto. The detection circuit 60 receives the detection signals IQ1 and IQ2 (detection current, electric charge) from the vibrating piece 10 driven by the drive signal DQ, and from the detection signals IQ1 and IQ2, a desired signal corresponding to the physical quantity applied to the vibrating piece 10. (Coriolis force signal) is detected (extracted).

  The diagnostic circuit 150 is a circuit for diagnosing (self-diagnosing) the detection circuit 60 (circuit device) in the diagnostic mode (diagnostic period). For example, the diagnostic circuit 150 performs an operation of generating a pseudo desired signal (pseudo angular velocity signal or the like) for diagnosing the detection circuit 60 and supplying the pseudo desired signal to the detection circuit 60. Then, based on the detection result of the pseudo desired signal, a diagnosis is made to determine whether the detection circuit 60 or the like is operating normally. The details of the diagnostic circuit 150 will be described later.

  The vibrating piece 10 includes a base portion 1, connecting arms 2 and 3, driving arms 4, 5, 6, and 7 and detecting arms 8 and 9. The detection arms 8 and 9 extend in the + Y axis direction and the −Y axis direction with respect to the rectangular base 1. Further, the connecting arms 2 and 3 extend in the −X axis direction and the + X axis direction with respect to the base portion 1. The drive arms 4 and 5 extend in the + Y axis direction and the −Y axis direction with respect to the connecting arm 2, and the drive arms 6 and 7 extend in the + Y axis direction and the −Y axis direction with respect to the connecting arm 3. ing. The X axis, the Y axis, and the Z axis indicate the axes of the crystal, and are also called the electric axis, the mechanical axis, and the optical axis, respectively.

  The drive signal DQ from the drive circuit 30 is input to the drive electrodes provided on the upper surfaces of the drive arms 4 and 5 and the drive electrodes provided on the side surfaces of the drive arms 6 and 7. Further, signals from the drive electrodes provided on the side surfaces of the drive arms 4 and 5 and the drive electrodes provided on the upper surfaces of the drive arms 6 and 7 are input to the drive circuit 30 as a feedback signal DI. Further, signals from detection electrodes provided on the upper surfaces of the detection arms 8 and 9 are input to the detection circuit 60 as detection signals IQ1 and IQ2. The common electrodes provided on the side surfaces of the detection arms 8 and 9 are grounded, for example.

  When the alternating drive signal DQ is applied by the drive circuit 30, the drive arms 4, 5, 6, 7 perform bending vibration (excitation vibration) as shown by arrow A due to the inverse piezoelectric effect. That is, the tips of the drive arms 4 and 6 repeat approaching and separating from each other, and the tips of the drive arms 5 and 7 also perform bending vibrations repeating approaching and separating from each other. At this time, since the drive arms 4 and 5 and the drive arms 6 and 7 are vibrating in line symmetry with respect to the Y axis passing through the center of gravity of the base 1, the base 1, the connecting arms 2 and 3, and the detecting arm 8 are provided. , 9 hardly vibrates.

In this state, when an angular velocity about the Z axis as a rotation axis is applied to the vibrating piece 10 (when the vibrating piece 10 rotates around the Z axis), the drive arms 4, 5, 6, 7 are moved to the arrow B by the Coriolis force. Vibrate as shown. That is, the Coriolis force in the direction of the arrow B, which is orthogonal to the direction of the arrow A and the direction of the Z axis, acts on the drive arms 4, 5, 6, 7 to generate a vibration component in the direction of the arrow B. The vibration in the direction of arrow B is transmitted to the base 1 via the connecting arms 2 and 3, and the detection arms 8 and 9 perform bending vibration in the direction of arrow C. The charge signals generated by the piezoelectric effect due to the bending vibration of the detection arms 8 and 9 are input to the detection circuit 60 as detection signals IQ1 and IQ2. Here, the vibration of the drive arms 4, 5, 6, 7 in the direction of arrow B is the vibration in the circumferential direction with respect to the center of gravity of the base 1, and the vibration of the detection arms 8, 9 is in the direction of the arrow B. The vibration is in the direction of the opposite arrow C. Therefore, the detection signals IQ1 and IQ2 are signals whose phases are shifted by 90 degrees with respect to the drive signal DQ.

  For example, when the angular velocity of the vibrating element 10 (gyro sensor) around the Z axis is ω, the mass is m, and the vibration velocity is v, the Coriolis force is expressed as Fc = 2m · v · ω. Therefore, the detection circuit 60 can obtain the angular velocity ω by detecting the desired signal which is a signal corresponding to the Coriolis force. Then, by using the obtained angular velocity ω, the processing unit 520 can perform various processes for camera shake correction, attitude control, GPS autonomous navigation, and the like.

  Although FIG. 6 shows an example in which the resonator element 10 has a double T shape, the resonator element 10 of the present embodiment is not limited to such a structure. For example, a tuning fork type or an H type may be used. Further, the piezoelectric material of the vibrating piece 10 may be a material other than quartz such as ceramics or silicon.

  FIG. 7 shows a detailed configuration example of the drive circuit 30 and the detection circuit 60 of the circuit device.

  The drive circuit 30 includes an amplifier circuit 32 to which the feedback signal DI from the resonator element 10 is input, a gain control circuit 40 that performs automatic gain control, and a drive signal output circuit 50 that outputs a drive signal DQ to the resonator element 10. . It also includes a sync signal output circuit 52 that outputs the sync signal SYC to the detection circuit 60. Note that the configuration of the drive circuit 30 is not limited to that shown in FIG. 7, and various modifications can be made such as omitting some of these components and adding other components.

  The amplifier circuit 32 (I / V conversion circuit) amplifies the feedback signal DI from the resonator element 10. For example, the current signal DI from the vibrating element 10 is converted into a voltage signal DV and output. The amplifier circuit 32 can be realized by an operational amplifier, a feedback resistance element, a feedback capacitor and the like.

  The drive signal output circuit 50 outputs the drive signal DQ based on the signal DV amplified by the amplifier circuit 32. For example, when the drive signal output circuit 50 outputs a rectangular wave (or sine wave) drive signal, the drive signal output circuit 50 can be realized by a comparator or the like.

  The gain control circuit 40 (AGC) outputs the control voltage DS to the drive signal output circuit 50 to control the amplitude of the drive signal DQ. Specifically, the gain control circuit 40 monitors the signal DV and controls the gain of the oscillation loop. For example, in the drive circuit 30, in order to keep the sensitivity of the gyro sensor constant, it is necessary to keep the amplitude of the drive voltage supplied to the vibrating piece 10 (driving vibrating piece) constant. Therefore, a gain control circuit 40 for automatically adjusting the gain is provided in the oscillation loop of the drive vibration system. The gain control circuit 40 variably and automatically adjusts the gain so that the amplitude of the feedback signal DI from the resonator element 10 (vibration speed v of the resonator element) becomes constant. The gain control circuit 40 can be realized by a full-wave rectifier that full-wave rectifies the output signal DV of the amplifier circuit 32, an integrator that performs integration processing of the output signal of the full-wave rectifier, or the like.

  The synchronization signal output circuit 52 receives the signal DV after being amplified by the amplification circuit 32, and outputs the synchronization signal SYC (reference signal) to the detection circuit 60. The synchronization signal output circuit 52 includes a comparator for binarizing the sine wave (AC) signal DV to generate a rectangular wave synchronization signal SYC, and a phase adjustment circuit (transferring the phase of the synchronization signal SYC). It can be realized with a phaser).

  Further, the synchronization signal output circuit 52 outputs the signal DSFD to the diagnostic circuit 150. The signal DSFD is a signal having the same phase as the synchronization signal SYC, and is generated by, for example, a comparator that binarizes the sinusoidal signal DV. The synchronization signal SYC itself may be output to the diagnostic circuit 150 as the signal DSFD.

  The detection circuit 60 includes an amplification circuit 61, a synchronous detection circuit 81, a filter section 90, an A / D conversion circuit 100, and a DSP section 110. The amplifier circuit 61 receives the first and second detection signals IQ1 and IQ2 from the resonator element 10 and performs charge-voltage conversion, differential signal amplification, gain adjustment, and the like. The synchronous detection circuit 81 performs synchronous detection based on the synchronization signal SYC from the drive circuit 30. The filter unit 90 (low-pass filter) functions as a front-end filter of the A / D conversion circuit 100. The filter unit 90 also functions as a circuit that attenuates unnecessary signals that cannot be completely removed by synchronous detection. The A / D conversion circuit 100 performs A / D conversion of the signal after synchronous detection. The DSP unit 110 performs digital signal processing such as digital filter processing and digital correction processing on the digital signal from the A / D conversion circuit 100.

  The detection signals IQ1 and IQ2, which are charge signals (current signals) from the vibrating piece 10, are delayed by 90 degrees in phase from the drive signal DQ that is a voltage signal. Further, the phase is delayed by 90 degrees in the Q / V conversion circuit or the like of the amplifier circuit 61. Therefore, the phase of the output signal of the amplifier circuit 61 is delayed by 180 degrees with respect to the drive signal DQ. Therefore, for example, by performing synchronous detection using the synchronization signal SYC having the same phase as the drive signal DQ (DV), it becomes possible to remove an unnecessary signal whose phase is delayed by 90 degrees with respect to the drive signal DQ.

  The control unit 140 performs control processing of the circuit device 20. The control unit 140 can be realized by a logic circuit (gate array or the like), a processor, or the like. The control unit 140 controls various switches and sets modes in the circuit device 20.

  Note that FIG. 7 shows a configuration example of the circuit device of the digital gyro that outputs the detected angular velocity as digital data, but the present embodiment is not limited to this, and the detected angular velocity is output as an analog voltage (DC voltage). The configuration of the analog gyro circuit device may be used.

3. Detailed Circuit Configuration Example of Detection Circuit FIG. 8 shows a more detailed configuration example of the detection circuit 60. It should be noted that the detection circuit 60 is not limited to the configuration of FIG. 8, and various modifications can be made such as omitting some of the constituent elements and adding other constituent elements.

  The diagnostic circuit 150 has first and second capacitors C1 and C2. The first capacitor C1 is provided between the input node NA1 of the Q / V conversion circuit 62 to which the detection signal IQ1 is input and the first node N1. The second capacitor C2 is provided between the input node NA2 of the Q / V conversion circuit 64 to which the detection signal IQ2 is input and the first node N1. The input nodes NA1 and NA2 are nodes on one end side of the first and second capacitors C1 and C2, and the first node N1 is a node on the other end side of the first and second capacitors C1 and C2. .

  The capacitance value of the second capacitor C2 is different from the capacitance value of the first capacitor C1. For example, when the capacitance value of the first capacitor C1 is C, the capacitance value of the second capacitor C2 is C + ΔC. Here, ΔC may be a positive capacitance value or a negative capacitance value. The ratio of ΔC (absolute value of ΔC) to the capacitance value C can be set to, for example, about 5% to 30%.

  In the diagnosis mode (diagnosis period), the diagnosis signal SFD is input to the first node N1. For example, after the power is turned on and before the normal operation period, the diagnostic signal SFD is supplied to the first node N1, and the diagnostic processing (self-diagnosis) of the detection circuit 60 (circuit device) is executed. The diagnostic signal SFD is not a signal supplied from the outside of the circuit device but a signal generated inside the circuit device, for example. For example, as shown in FIG. 7, the diagnostic signal SFD is a signal generated based on the signal DSFD from the drive circuit 30. Specifically, it is a signal having the same phase (including substantially the same) as the synchronization signal SYC (reference signal) output from the drive circuit 30.

  In this way, in the diagnostic mode, the diagnostic signal SFD is input to the first node N1, so that the Q / V conversion circuit 62 becomes the first capacitor C1 and the feedback capacitor of the Q / V conversion circuit 62. The signal QB1 having the first voltage amplitude corresponding to the capacitance ratio of 1 is output. Further, the Q / V conversion circuit 64 outputs the signal QB2 having the second voltage amplitude corresponding to the second capacitance ratio between the second capacitor C2 and the feedback capacitor of the Q / V conversion circuit 64. Since the first and second capacitors C1 and C2 have different capacitance values, the first and second capacitance ratios also have different capacitance ratios. Therefore, the first voltage amplitude of the signal QB1 output by the Q / V conversion circuit 62 and the second voltage amplitude of the signal QB2 output by the Q / V conversion circuit 64 are different voltages. Therefore, the differential amplifier circuit 70 or the like in the subsequent stage differentially amplifies the voltage difference between the first and second voltage amplitudes to detect a desired diagnostic signal, which is a pseudo desired signal, in the diagnostic mode. It becomes possible to supply the circuit 60. Then, based on the detection result of the detection circuit 60 for the desired diagnostic signal, it is possible to diagnose whether the detection circuit 60 is operating normally.

  The diagnostic circuit 150 also includes first, second, third, and fourth switch elements SW4. Further, it has a fifth switch element SW5 for inputting the diagnostic signal SFD to the first node N1. The first switch element SW1 is provided between one end of the first capacitor C1 and the input node NA1. The second switch element SW2 is provided between one end of the second capacitor C2 and the input node NA2.

  The third switch element SW3 is provided between the terminal PD1 (FIG. 4) of the circuit device and the input node NA1. The fourth switch element SW4 is provided between the terminal PD2 and the input node NA2.

In the diagnosis mode (diagnosis period), the first and second switch elements SW1 and SW2 are turned on, and the third and fourth switch elements SW3 and SW4 are turned off. As a result, the electrical connection to the first and second terminals PD1 and PD2 side is cut off by the turned off third and fourth switch elements SW3 and SW4, and the turned on first and first terminals A desired signal for diagnosis (pseudo desired signal) using the diagnostic signal SFD can be supplied to the detection circuit 60 via the two switch elements SW1 and SW2.

  In the normal operation period, the first and second switch elements SW1 and SW2 are turned off, and the third and fourth switch elements SW3 and SW4 are turned on. Here, the normal operation period is a period in which the detection circuit 60 performs a detection operation. That is, it is a period in which the detection circuit 60 performs the detection process of the desired signal using the detection signals IQ1 and IQ2. By doing so, during the normal operation period, the electrical connection with the first and second capacitors C1 and C2 side is cut off by the first and second switch elements SW1 and SW2 that are turned off. However, it is possible to realize the detection processing using the first and second detection signals IQ1 and IQ2 input via the turned-on third and fourth switch elements SW3 and SW4.

  The Q / V conversion circuit 62 includes an operational amplifier OPB1, a feedback capacitor CB1, and a feedback resistance element RB1. The non-inverting input terminal of the operational amplifier OPB1 is set to the analog common voltage VCM. The feedback capacitor CB1 is provided between the output terminal and the inverting input terminal of the operational amplifier OPB1. The feedback resistance element RB1 is also provided between the output terminal and the inverting input terminal of the operational amplifier OPB1. The feedback resistance element RB1 is for setting the DC bias point of the output signal of the operational amplifier OPB1, and the feedback resistance element RB1 may be omitted.

  The Q / V conversion circuit 64 includes an operational amplifier OPB2, a feedback capacitor CB2, and a feedback resistance element RB2. The non-inverting input terminal of the operational amplifier OPB2 is set to the analog common voltage VCM. The feedback capacitor CB2 is provided between the output terminal and the inverting input terminal of the operational amplifier OPB2. The feedback resistance element RB2 is also provided between the output terminal and the inverting input terminal of the operational amplifier OPB2. The feedback resistance element RB2 is for setting the DC bias point of the output signal of the operational amplifier OPB2, and the feedback resistance element RB2 may be omitted.

  The Q / V conversion circuits 62 and 64 convert the charge signals into voltage signals by accumulating the charges of the charge signals, which are the detection signals IQ1 and IQ2 from the resonator element 10, in the feedback capacitors CB1 and CB2. The Q / V conversion circuits 62 and 64 have low-pass filter characteristics, and for example, the feedback capacitors CB1 and CB2 so that the cutoff frequency thereof is sufficiently lower than the drive frequency (resonance frequency) of the physical quantity transducer 18. Is set.

  A differential amplifier circuit 70 is provided after the Q / V conversion circuits 62 and 64. The configuration of the differential amplifier circuit 70 is the same as that described with reference to FIG.

  A high-pass filter unit 74 is provided at the subsequent stage of the differential amplifier circuit 70. The high pass filter unit 74 has capacitors CK1 and CK2 and resistance elements RK1 and RK2. One end of the capacitor CK1 is connected to the output node NC1 of the differential amplifier circuit 70. The other end of the capacitor CK1 is connected to one end of the resistance element RK1. One end of the capacitor CK2 is connected to the output node NC2 of the differential amplifier circuit 70. The other end of the capacitor CK2 is connected to one end of the resistance element RK2. The other end of the resistance element RK1 and the other end of the resistance element RK2 are connected to a node NK1, and the node NK1 is set to the analog common voltage VCM.

  By providing the high-pass filter unit 74 at the subsequent stage of the differential amplifier circuit 70, it is possible to remove the DC bias component of the signals QC1 and QC2. Further, since the node NK1 is set to the analog common voltage VCM, the signals QC1 and QC2 from the differential amplifier circuit 70 are symmetrical with respect to the analog common voltage VCM even after passing through the high pass filter unit 74. become.

  The gain adjustment amplifier 76 includes first and second operational amplifiers OPD1 and OPD2 and first to fourth resistance elements RD1 to RD4.

  In the first operational amplifier OPD1, the signal QC1 of the signals QC1 and QC2 (first and second signals) forming the differential signal is input to the non-inverting input terminal (first input terminal). In the second operational amplifier OPD2, the signal QC2 of the signals QC1 and QC2 is input to the non-inverting input terminal (first input terminal).

  The first resistance element RD1 is provided between the first node ND5 and the inverting input terminal (second input terminal, node ND3) of the first operational amplifier OPD1. The second resistance element RD2 is provided between the inverting input terminal (ND3) of the first operational amplifier OPD1 and the output terminal (node ND1) of the first operational amplifier OPD1.

  The first and second resistance elements RD1 and RD2 voltage-divide the voltage (VA) of the first node ND5 and the voltage of the output terminal of the first operational amplifier OPD1 (voltage of the output signal QD1), It functions as a first voltage division circuit that sets the inverting input terminal of the first operational amplifier OPD1 to the voltage VD1 obtained by the voltage division.

  The third resistance element RD3 is provided between the first node ND5 and the inverting input terminal (second input terminal, node ND4) of the second operational amplifier OPD2. The fourth resistance element RD4 is provided between the inverting input terminal (ND4) of the second operational amplifier OPD2 and the output terminal (node ND2) of the second operational amplifier OPD2.

  These third and fourth resistance elements RD3 and RD4 voltage-divide the voltage (VA) of the first node ND5 and the voltage of the output terminal of the second operational amplifier OPD2 (voltage of the output signal QD2), It functions as a second voltage division circuit that sets the inverting input terminal of the second operational amplifier OPD2 to the voltage VD2 obtained by the voltage division.

  As described above, the gain adjustment amplifier 76 includes the first operational amplifier OPD1, the first amplifier AMD1 having the first and second resistance elements RD1 and RD2, the second operational amplifier OPD2, and the third and fourth operational amplifiers OPD2. It is composed of a second amplifier AMD2 having resistance elements RD3 and RD4. Then, one end of the resistance element RD1 of the first amplifier AMD1 and one end of the resistance element RD3 of the second amplifier AMD2 are commonly connected to the node ND5. In this way, the first amplifier AMD1 and the second amplifier AMD2 constitute an instrumentation amplifier.

  The gain adjustment amplifier 76 receives the differential signals QC1 and QC2 and outputs the differential signals QD1 and QD2 to the nodes ND1 and ND2.

Further, RD1 to RD4 are resistance elements having variable resistance values, and the gain GD in the gain adjustment amplifier 76 is adjusted by adjusting the resistance values of these resistance elements. For example, the resistance values of the resistance elements RD1 and RD3 are R1, the resistance values of the resistance elements RD2 and RD4 are R2, and the reference resistance value is R. Then, the resistance values R1 and R2 for setting the gain GD can be expressed as R1 = R / GD and R2 = R × (1-1 / GD). When the signals QC1 and QC2 are input, the gain adjustment amplifier 76 outputs the signals QD1 and QD2 as shown in the following formula: QD1 = VA + (GD / 2) × (QC1-QC2)
QD2 = VA- (GD / 2) * (QC1-QC2)
QD1-QD2 = GD × (QC1-QC2)
Here, VA is the voltage of the node ND5. VA is a voltage obtained by dividing the voltage of the signals QD1 and QD2 by the resistance elements RD1 and RD2 and the resistance elements RD3 and RD4, and becomes the midpoint voltage of the signals QD1 and QD2. Therefore, the relationship of VA = (QD1 + QD2) / 2 holds. When the signals QC1 and QC2 are differential signals with the analog common voltage VCM as a reference (center voltage), and the relationship of VCM = (QC1 + QC2) / 2 holds, the relationship of VA = VCM holds.

  The configuration of the gain adjusting amplifier 76 may be omitted by providing the differential amplifier circuit 70 with a gain adjusting function.

  The monitoring voltage VA, which is the voltage of the node ND5, is input to the failure detection circuit 160. Specifically, the failure detection circuit 160 has comparators CPD1 and CPD2 and an OR circuit ORD1 in addition to the configuration described in FIG. The threshold voltage VTH on the high potential side is input to the inverting input terminal of the comparator CPD1, and the monitoring voltage VA is input to the non-inverting input terminal. The monitor voltage VA is input to the inverting input terminal of the comparator CPD2, and the low-potential-side threshold voltage VTL is input to the non-inverting input terminal. The OR circuit ORD1 receives the output signals of the comparators CPD1 and CPD2 and outputs the monitoring result signal DGD.

  For example, when the monitoring voltage VA is within the determination voltage range between the threshold voltage VTH and the threshold voltage VTL, the monitoring result signal DGD becomes L level, and the control unit 140 and the like are notified that the failure is not detected. Reportedly. On the other hand, when the monitoring voltage VA is out of the judgment voltage range, the monitoring result signal DGD becomes H level, and the control unit 140 and the like are notified that a failure is detected.

  By doing so, in FIG. 8, individual failure detection of the gain adjustment amplifier 76 is also realized. That is, the output signals QD1 and QD2 of the gain adjustment amplifier 76 also have a symmetrical signal waveform centered on the analog common voltage VCM as shown in FIG. 3A in the normal state, and the middle point of QD1 and QD2. The monitoring voltage VA, which is a voltage, matches the analog common voltage VCM. On the other hand, when a failure occurs, this symmetry is broken, the signal waveform becomes as shown in FIG. 3B, and the voltage level of the monitoring voltage VA fluctuates. The fluctuation of the monitoring voltage VA is detected by the failure detection circuit 160 (CPD1, CPD2, ORD1). That is, failure detection is performed by detecting whether the monitoring voltage VA is within the determination voltage range. By doing so, individual failure detection of the gain adjustment amplifier 76 can be realized.

  Moreover, in FIG. 8, the monitoring voltage VA is generated by voltage division in which the resistance elements RD1 and RD2 included in the amplifier AMD1 and the resistance elements RD3 and RD4 included in the amplifier AMD2 are effectively used.

  That is, in the differential amplifier circuit 70, the resistance elements RC9 and RC10 are newly provided for generating the monitoring voltage VB. On the other hand, the gain adjustment amplifier 76 effectively utilizes the resistance elements RD1 and RD2 and the resistance elements RD3 and RD4 used for gain adjustment to generate the monitoring voltage VA. Therefore, it becomes possible to realize the fault detection based on the monitoring voltage VA without increasing the circuit scale so much.

  The determination voltage range when detecting the failure of the differential amplifier circuit 70 may be different from the determination voltage range when performing the failure detection of the gain adjustment amplifier 76. That is, the high potential side threshold voltage VTH and the low potential side threshold voltage VTL defining the determination voltage range may be set to different voltages.

  The synchronous detection circuit 81 includes a switching mixer 82 and a switching mixer 84. The switching mixer 82 is a mixer for extracting a desired signal (angular velocity) (for normal operation). That is, the switching mixer 82 performs differential synchronous detection based on the synchronous signal SYC from the drive circuit 30 to detect the desired signal. The switching mixer 84 is a mixer for extracting (diagnosing) unnecessary signals.

  For example, a vibration leakage signal is arbitrarily generated in the vibrating element 10, and the switching mixer 84 detects the vibration leakage signal, so that the failure diagnosis of the detection circuit 60 is performed.

  For example, in FIG. 6, if the vibration energies of the driving arms 4 and 5 and the driving arms 6 and 7 when bending vibrations are balanced, detection is performed in a state where the angular velocity is not applied to the vibrating piece 10. The arms 8 and 9 do not perform bending vibration. On the other hand, when the balance of the vibration energy of both is unbalanced, the bending vibration of the detection arms 8 and 9 occurs even when the angular velocity is not applied to the vibrating piece 10. This bending vibration is called leaking vibration, and is bending vibration in the direction of arrow C, like the vibration based on Coriolis force. The vibrations (detection signals IQ1 and IQ2) based on the Coriolis force are signals whose phases are shifted by 90 degrees with respect to the drive signal DQ, but the leakage vibration is the same phase as the drive signal DQ. Since the phases of the Q / V conversion circuits 62 and 64 are deviated by 90 degrees, the signal based on the leakage vibration becomes a signal whose phase is deviated by 90 degrees from the synchronization signal SYC at the stage of synchronous detection.

  Then, in the present embodiment, the balance of the vibrational energy between the drive arms 4 and 5 and the drive arms 6 and 7 is slightly disturbed to positively generate the vibration leakage component of a desired level. For example, the weight of the drive arms 4 and 5 is different from the weight of the drive arms 6 and 7 by laser processing so that the weights of the drive arms 6 and 7 are different from each other in weight. Cause a leak. Since the level of this vibration leakage is a known value, the failure of the detection circuit 60 can be diagnosed by detecting the signal of this vibration leakage by the switching mixer 84.

  In the switching mixer 82, the signal QD1 from the gain adjustment amplifier 76 in the previous stage is input to the first input node ND1 and the signal QD2 is input to the second input node ND2. Then, differential synchronous detection is performed by the synchronous signal SYC (CK0) from the drive circuit 30, and differential signals QF1 and QF2 are output to the first and second output nodes NF1 and NF2.

  The switching mixer 82 has switch elements SF1, SF2, SF3, SF4. The switch element SF1 is provided between the first input node ND1 of the switching mixer 82 and the first output node NF1. The switch element SF2 is provided between the second input node ND2 of the switching mixer 82 and the second output node NF2. The switch element SF3 is provided between the second input node ND2 and the first output node NF1. The switch element SF4 is provided between the first input node ND1 and the second output node NF2. These switch elements SF1 to SF4 can be constituted by, for example, MOS transistors (for example, NMOS type transistors or transfer gates).

  The switch elements SF1 and SF2 are turned on / off by the clock signal CK0, and the switch elements SF3 and SF4 are turned on / off by the clock signal XCK0. The clock signal CK0 corresponds to the above-mentioned synchronization signal SYC, and the clock signal XCK0 is an inverted signal of the clock signal CK0 (a signal having a phase difference of 180 degrees). Therefore, the switch elements SF1 and SF3 are exclusively turned on / off, and the switch elements SF2 and SF4 are exclusively turned on / off. For example, when the clock signal CK0 (SYC) is at the H level (in a broad sense, the first voltage level), the switch elements SF1 and SF2 are turned on and the switch elements SF3 and SF4 are turned off. When the clock signal CK0 is at the L level (second voltage level in a broad sense), the switch elements SF1 and SF2 are turned off and the switch elements SF3 and SF4 are turned on.

  As a result, the differential signals QD1 and QD2 from the gain adjustment amplifier 76 are synchronously detected in the differential signal state, and the signals after synchronous detection are output as the differential signals QF1 and QF2. The switching mixer 82 frequency-converts unnecessary signals such as noise (1 / f noise) generated by the circuits (Q / V conversion circuit, differential amplification circuit, gain adjustment amplifier) in the preceding stage into a high frequency band. Also, the desired signal, which is a signal corresponding to the Coriolis force, is dropped into the DC signal. Then, an unnecessary signal such as 1 / f noise whose frequency is converted into a high frequency band by the switching mixer 82 is removed by the filter unit 90 (FIG. 7) provided in the subsequent stage. The filter unit 90 is, for example, a passive filter including a passive element. That is, as the filter unit 90, a passive filter including a passive element such as a resistance element or a capacitor can be adopted without using an operational amplifier.

  In the switching mixer 84, the signal QD1 from the gain adjustment amplifier 76 at the previous stage is input to the first input node ND1 and the signal QD2 is input to the second input node ND2. Then, the differential signals QG1 and QG2 are output to the first and second output nodes NG1 and NG2.

  The switching mixer 84 has switch elements SG1, SG2, SG3, SG4. The switch element SG1 is provided between the first input node ND1 and the first output node NG1. The switch element SG2 is provided between the second input node ND2 and the second output node NG2. The switch element SG3 is provided between the second input node ND2 and the first output node NG1. The switch element SG4 is provided between the first input node ND1 and the second output node NG2. These switch elements SG1 to SG4 can be configured by, for example, MOS transistors (for example, NMOS type transistors or transfer gates).

  The switch elements SG1 and SG2 are turned on / off by the clock signal CK90, and the switch elements SG3 and SG4 are turned on / off by the clock signal XCK90. The clock signal CK90 is a signal whose phase differs from that of the clock signal CK0 (synchronization signal SYC) by 90 degrees. The clock signal XCK90 is an inverted signal of the clock signal CK90 (a signal having a phase difference of 180 degrees). Therefore, the switch elements SG1 and SG3 are exclusively turned on / off, and the switch elements SG2 and SG4 are exclusively turned on / off. For example, when the clock signal CK90 is at the H level, the switch elements SG1 and SG2 are turned on and the switch elements SG3 and SG4 are turned off. When the clock signal CK90 is at the L level, the switch elements SG1 and SG2 are turned off and the switch elements SG3 and SG4 are turned on.

  The vibration leakage signal (unnecessary signal in a broad sense) arbitrarily generated in the vibrating piece 10 has a phase difference of 90 degrees from the synchronization signal SYC (desired signal). Therefore, the switching mixer 84 synchronously detects the signals QD1 and QD2 on the basis of the clock signal CK90 which is 90 ° out of phase with the clock signal CK0 which is the synchronization signal SYC, thereby extracting a vibration leakage signal arbitrarily mixed. . Since the level of the vibration leakage signal in this case is already known, the expected vibration leakage signal is mixed in QD1 and QD2 by A / D converting the detection result by the switching mixer 84 and comparing it with the expected value. Can be detected. When the expected vibration leakage signal is detected, the detection circuit 60 can be determined to be operating normally. The diagnosis process using the switch mixer 84 is executed during the constant diagnosis period shown in FIG. 11 described later.

  FIG. 9 is a configuration example of an analog common voltage generation circuit that generates a VCM. This analog common voltage generation circuit has an operational amplifier OPH, resistance elements RH1, RH2, RH3, and capacitors CH1, CH2. The resistance elements RH1 and RH2 are connected in series between the power supplies VDD and VSS and generate a divided voltage at the node NH3. The division voltage is, for example, a midpoint voltage between VDD and VSS. This divided voltage is supplied to the node NH2 of the non-inverting input terminal of the operational amplifier OPH via the noise reduction low-pass filter including the resistance element RH3 and the capacitor CH2. The operational amplifier OPH is so-called voltage follower connection, and outputs a voltage corresponding to the divided voltage to the node NH1 as the analog common voltage VCM. The capacitor CH1 is a capacitor for stabilizing the potential.

  FIG. 10 is a signal waveform diagram for explaining self-diagnosis by the diagnostic circuit 150. In FIG. 10, the diagnostic signal SFD whose voltage amplitude is VB is input to the first node N1 in FIG. Then, the Q / V conversion circuit 62 outputs the signal QB1 whose voltage amplitude is VB1, and the Q / V conversion circuit 64 outputs the signal QB2 whose voltage amplitude is VB2. Although the diagnostic signal SFD is a rectangular wave in FIG. 10, it may be a periodic signal such as a sine wave.

  For example, the capacitance values of the feedback capacitors CB1 and CB2 are equal, and the capacitance value of the capacitor C2 is larger than the capacitance value of the capacitor C1. The capacitance values of the capacitors CB1 and CB2 are, for example, about 0.5 pF to 1.5 pF, and the capacitance value C of the capacitor C1 is, for example, about 250 fF to 750 fF. The difference ΔC between the capacitance values of the capacitors C1 and C2 is, for example, about 50 fF to 150 fF. Note that C1, C2, CB1, and CB2 can be realized by, for example, a capacitor made of polysilicon (poly two-layer capacitor) or a capacitor made of MIM (Metal-Insulator-Metal).

  Thus, when the capacitance value of the capacitor C2 is larger than that of the capacitor C1, as shown in FIG. 10, the Q / V conversion circuits 62 and 64 have the signals QB1 and VB1 <VB2. Output QB2. Specifically, the Q / V conversion circuits 62 and 64 are inverting amplifiers. Therefore, as shown in FIG. 10, when the diagnostic signal SFD has a positive polarity, the Q / V conversion circuits 62 and 64 have a negative polarity with the analog common voltage VCM as a reference (center) and the voltage amplitude. The signals QB1 and QB2 that satisfy the relationship of VB1 <VB2 are output.

  That is, the potentials of the input nodes NA1 and NA2 are both set to the analog common voltage VCM by the virtual ground (virtual short) by the operational amplifiers OPB1 and OPB2 of the Q / V conversion circuits 62 and 64. Since the capacitance value of the capacitor C2 is larger than that of the capacitor C1, when the diagnostic signal SFD having a voltage amplitude of VB is applied to the other ends of the capacitors C1 and C2, the accumulated charge amount of the capacitor C1 is increased. The stored charge amount of the capacitor C2 is larger than that. Since the capacitance values of the feedback capacitors CB1 and CB2 of the Q / V conversion circuits 62 and 64 are equal, the relationship of VB1 <VB2 holds for the voltage amplitude of the signals QB1 and QB2. That is, the voltage amplitude VB1 of the signal QB1 is set to an amplitude corresponding to the capacitance ratio (C1 / CB1) of the capacitor C1 and the feedback capacitor CB1, and the voltage amplitude VB2 of the signal QB2 is set to the capacitance ratio of the capacitor C2 and the feedback capacitor CB2 ( The amplitude is set according to C2 / CB2). Since the capacitance value of C2 is larger than that of C1, the relationship of VB1 <VB2 is established.

  The differential amplifier circuit 70 amplifies the differential components of the signals QB1 and QB2. Therefore, as shown in FIG. 10, a signal obtained by multiplying and inverting the difference between the signals QB1 and QB2 is output as differential signals QC1 and QC2. For example, when the differential amplification gain of the differential amplifier circuit 70 is GC, the differential voltage between the signal QC1 and the signal QC2 can be expressed as VDF = GC × (VB2-VB1).

  As described above, by inputting the diagnostic signal SFD to the node N1 on the other end side of the capacitor C1, the desired signal for diagnosis (pseudo desired signal) as shown by the signals QC1 and QC2 can be supplied to the detection circuit 60. Then, the detection circuit 60 performs a detection operation of the desired signal for diagnosis, and monitors the detection result, so that it is possible to make a diagnosis (self-diagnosis, failure diagnosis) as to whether the detection circuit 60 is operating normally. Become. Specifically, the detection circuit 60 can be diagnosed by detecting the differential voltage VDF between the signals QC1 and QC2 in FIG.

  For example, since the capacitance values of the capacitors C1, C2, CB1 and CB2 and the voltage amplitude of the diagnostic signal SFD are known, the differential voltage VDF of the signals QC1 and QC2 is also known. Therefore, if the detection result of the detection circuit 60 corresponding to the differential voltage VDF is within the expected value range, it can be diagnosed that the detection circuit 60 is operating normally. Specifically, for example, the synchronous detection of the synchronous detection circuit 81 removes an unnecessary signal whose phase is different from that of the synchronous signal SYC (for example, an unnecessary signal whose phase is shifted by 90 degrees), while diagnosing the same phase as the synchronous signal SYC. The desired signal for use will be extracted. That is, the component of the desired signal for diagnosis appears in the frequency band such as DC in the frequency spectrum. Therefore, if the value of the DC component of the desired signal for diagnosis (DC voltage value or A / D conversion value of DC voltage) is within the expected range, it can be diagnosed that the detection circuit 60 is operating normally. .

  FIG. 11 is an operation sequence diagram for explaining the operation of the circuit device of this embodiment. As shown in FIG. 11, after the circuit device is powered on and turned on, the circuit device is set to the diagnostic mode and the initial diagnosis is performed. That is, diagnosis is performed to verify whether the detection circuit 60 is operating normally. During this initial diagnosis (diagnosis mode), the switch elements SW1 and SW2 of the diagnosis circuit 150 are turned on, while the switch elements SW3 and SW4 are turned off. As a result, the input of the detection signals IQ1 and IQ2 from the vibrating piece 10 is electrically cut off, and the signal obtained by converting the signal from the drive circuit 30 into a voltage level is used as a diagnostic signal SFD and is a node at the other end of the capacitors C1 and C2. It will be input to N1. As a result, as described with reference to FIG. 10, it is possible to supply a pseudo desired signal for diagnosis to the detection circuit 60 and diagnose whether or not each circuit of the detection circuit 60 is operating normally.

  On the other hand, when such an initial diagnosis is completed and a normal operation period for detecting a desired signal comes, the switch elements SW3 and SW4 are turned on, while the switch elements SW1 and SW2 are turned off. As a result, the detection signals IQ1 and IQ2 from the vibrating element 10 are input to the detection circuit 60, and the desired signal detection processing is performed. At this time, by turning off the switch elements SW1 and SW2, it is possible to suppress a situation in which, for example, noise or the like based on a signal from the drive circuit 30 is transmitted to the input nodes NA1 and NA2 of the detection circuit 60.

  As described above, in FIG. 11, the diagnostic mode is set after the power is turned on and before the normal operation period. The setting of the diagnostic mode is realized by, for example, a controller or the like outside the circuit device issuing a command for starting the diagnostic mode (initial diagnosis), and the command being accepted via the interface of the circuit device. Alternatively, the operation mode of the circuit device may be automatically set to the diagnostic mode after the power is turned on. In addition, after starting the normal operation, the normal operation may be temporarily stopped and the circuit device diagnostic process may be performed based on, for example, issuance of a command from a controller external to the circuit device.

  Further, as shown in FIG. 11, during the normal operation period, a constant diagnosis is performed to constantly confirm whether or not the detection circuit 60 is operating normally.

  In this constant diagnosis, the failure detection circuit 160 detects a failure of the differential amplifier circuit 70 and the gain adjustment amplifier 76. That is, the failure detection circuit 160 detects whether the monitoring voltages VB and VA are within the determination voltage range. Then, the control unit 140 performs failure diagnosis of the differential amplifier circuit 70 and the gain adjustment amplifier 76 based on the monitoring result signals DGC and DGD from the failure detection circuit 160.

  Further, in this constant diagnosis, the switching mixer 84 performs the synchronous detection for extracting the vibration leakage signal arbitrarily generated. Then, the control unit 140 performs failure diagnosis of the entire detection circuit 60 by detecting whether or not the extracted component of the vibration leakage signal is within the range of the expected value. At this time, the switching mixer 82 performs normal synchronous detection for extracting a desired signal. Therefore, it becomes possible to simultaneously perform the failure diagnosis by extracting the vibration leakage signal and the extraction processing of the desired signal by the synchronous detection, and the continuous diagnosis is realized.

  As described above, in the present embodiment, while the desired signal is being extracted by the synchronous detection, in parallel with this, the failure detection circuit 160 performs failure diagnosis of the differential amplifier circuit 70 and the gain adjustment amplifier 76, and the switching mixer 84. The failure diagnosis of the entire detection circuit 60 can be executed by the above, and the continuous diagnosis during the actual operation of the circuit device can be realized. Therefore, it is possible to greatly improve the reliability against failure and performance deterioration due to aging.

4. Moving Object, Electronic Device FIG. 12A shows an example of a moving object including the circuit device 20 of this embodiment. The circuit device 20 of the present embodiment can be incorporated in various moving bodies such as a car, an airplane, a motorcycle, a bicycle, or a ship. The moving body is a device / device that includes a drive mechanism such as an engine and a motor, a steering mechanism such as a steering wheel and a rudder, and various electronic devices, and moves on the ground, in the air, or on the sea. FIG. 12A schematically shows an automobile 206 as a specific example of a moving body. A gyro sensor 510 (sensor) having the resonator element 10 and the circuit device 20 is incorporated in the automobile 206. The gyro sensor 510 can detect the attitude of the vehicle body 207. The detection signal of the gyro sensor 510 is supplied to the vehicle body attitude control device 208. The vehicle body attitude control device 208 can control the hardness of the suspension and the braking of each wheel 209 according to the attitude of the vehicle body 207, for example. In addition, such attitude control can be used in various moving bodies such as a bipedal robot, an aircraft, and a helicopter. The gyro sensor 510 may be incorporated to realize the attitude control.

  As shown in FIGS. 12 (B) and 12 (C), the circuit device of the present embodiment is a digital still camera or a biological information detection device (wearable health device, such as a pulse meter, a pedometer, an activity meter, etc.). It can be applied to various electronic devices. For example, in a digital still camera, camera shake correction using a gyro sensor or an acceleration sensor can be performed. Further, in the biometric information detection device, a gyro sensor or an acceleration sensor can be used to detect a user's body movement or a motion state. Further, as shown in FIG. 12D, the circuit device of this embodiment can be applied to a movable part (arm, joint) or a main body part of a robot. The robot can be a moving body (running / walking robot) or an electronic device (non-running / non-walking robot). In the case of a traveling / walking robot, the circuit device of this embodiment can be used for autonomous traveling, for example.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the scope of the present invention. For example, in the specification or the drawings, a term (gyro sensor, vibrating piece, etc.) described together with a broader or synonymous different term (physical quantity detection device, physical quantity transducer, etc.) is used at least once in any part of the specification or the drawing. Even in, it can be replaced with the different term. Further, the configurations of the circuit device, the physical quantity detection device, the electronic device, the moving body, the structure of the resonator element, and the like are not limited to those described in the present embodiment, and various modifications can be made.

AMC1, AMC2 first and second amplifiers, TM1, TM2 inverting input terminals,
TP1, TP2 non-inverting input terminal, OPC1, OPC2, first and second operational amplifier,
RC1 to RC8 first to eighth resistance elements, RC9, RC10 resistance elements,
CPC1, CPC2 comparator, ORC1 OR circuit, VB monitoring voltage,
AMD1, AMD2 first and second amplifiers, RD1 to RD4 first to fourth resistance elements,
OPD1, OPD2 first and second operational amplifiers,
CPD1, CPD2 comparator, ORD1 OR circuit, VA monitoring voltage,
C1, C2 first and second capacitors, SW1 to SW4 first to fourth switch elements, PD1 to PD4 terminals, SFD diagnostic signal,
1 base, 2, 3 connecting arms, 4, 5, 6, 7 drive arms, 8, 9 detection arms,
10 vibrating bars, 18 physical quantity transducers,
20 circuit device, 30, drive circuit, 32 amplifier circuit (I / V conversion circuit),
40 gain control circuit, 50 drive signal output circuit, 52 sync signal output circuit,
60 detection circuit, 61 amplification circuit, 62, 64 Q / V conversion circuit,
70 differential amplifier circuit, 74 high-pass filter section, 76 gain adjustment amplifier,
81 synchronous detection circuit, 82, 83 switching mixer,
90 filter section, 100 A / D conversion circuit, 110 DSP section,
140 control unit, 142 register unit, 150 diagnostic circuit, 160 failure detection circuit,
206 moving body (automobile), 207 vehicle body, 208 vehicle body attitude control device, 209 wheels,
500 electronic equipment, 510 gyro sensor, 520 processing unit, 530 memory,
540 operation unit, 550 display unit

Claims (12)

Of the differential input single-ended output, the first signal of the first and second signals forming the differential signal is input to the inverting input terminal and the second signal is input to the non-inverting input terminal. The first amplifier,
A second amplifier having a differential input single-ended output in which the first signal is input to a non-inverting input terminal and the second signal is input to an inverting input terminal;
A failure detection circuit that performs failure detection based on the output signal of the first amplifier and the output signal of the second amplifier;
A plurality of resistance elements provided between the output node of the output signal of the first amplifier and the output node of the output signal of the second amplifier, and A voltage dividing circuit that divides the voltage of the output signal and the voltage of the output signal of the second amplifier to generate a monitoring voltage;
Including,
The first and second amplifiers are amplifiers that perform single-ended output based on the same analog common voltage,
The failure detection circuit,
Before Ki監 vision voltage, wherein by detecting whether the analog common voltage in determination voltage range based circuit device which is characterized in that the fault detection. Of the differential input single-ended output, the first signal of the first and second signals forming the differential signal is input to the inverting input terminal and the second signal is input to the non-inverting input terminal. The first amplifier,
A second amplifier having a differential input single-ended output in which the first signal is input to a non-inverting input terminal and the second signal is input to an inverting input terminal;
A failure detection circuit that performs failure detection based on the output signal of the first amplifier and the output signal of the second amplifier;
A plurality of resistance elements provided between the output node of the output signal of the first amplifier and the output node of the output signal of the second amplifier, and A voltage dividing circuit that divides the voltage of the output signal and the voltage of the output signal of the second amplifier to generate a monitoring voltage;
Including,
The failure detection circuit,
Based on prior Ki監 vision voltage circuit device which is characterized in that the fault detection. The circuit device according to claim 1 or 2 ,
The failure detection circuit,
A circuit device, wherein the failure detection is performed by detecting whether or not the monitoring voltage is within a determination voltage range between a high-potential-side threshold voltage and a low-potential-side threshold voltage. The circuit device according to any one of claims 1 to 3 ,
The first amplifier is
A first operational amplifier,
A first resistance element provided between the inverting input terminal of the first amplifier and the inverting input terminal of the first operational amplifier;
A second resistance element provided between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier;
A third resistance element provided between the non-inverting input terminal of the first amplifier and the non-inverting input terminal of the first operational amplifier;
A fourth resistance element provided between the non-inverting input terminal of the first operational amplifier and an analog common voltage node;
Including,
The second amplifier is
A second operational amplifier,
A fifth resistance element provided between the inverting input terminal of the second amplifier and the inverting input terminal of the second operational amplifier;
A sixth resistance element provided between the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier;
A seventh resistance element provided between the non-inverting input terminal of the second amplifier and the non-inverting input terminal of the second operational amplifier;
An eighth resistance element provided between the non-inverting input terminal of the second operational amplifier and the analog common voltage node,
A circuit device comprising: Of the differential input single-ended output, the first signal of the first and second signals forming the differential signal is input to the inverting input terminal and the second signal is input to the non-inverting input terminal. The first amplifier,
A second amplifier having a differential input single-ended output in which the first signal is input to a non-inverting input terminal and the second signal is input to an inverting input terminal;
A failure detection circuit that performs failure detection based on the output signal of the first amplifier and the output signal of the second amplifier;
Including,
The first amplifier is
A first operational amplifier,
A first resistance element provided between the inverting input terminal of the first amplifier and the inverting input terminal of the first operational amplifier;
A second resistance element provided between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier;
A third resistance element provided between the non-inverting input terminal of the first amplifier and the non-inverting input terminal of the first operational amplifier;
A fourth resistance element provided between the non-inverting input terminal of the first operational amplifier and an analog common voltage node;
Including,
The second amplifier is
A second operational amplifier,
A fifth resistance element provided between the inverting input terminal of the second amplifier and the inverting input terminal of the second operational amplifier;
A sixth resistance element provided between the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier;
A seventh resistance element provided between the non-inverting input terminal of the second amplifier and the non-inverting input terminal of the second operational amplifier;
An eighth resistance element provided between the non-inverting input terminal of the second operational amplifier and the analog common voltage node,
A circuit device comprising: The circuit device according to any one of claims 1 to 5 ,
A drive circuit for driving the physical quantity transducer,
A detection circuit to which the first and second detection signals from the physical quantity transducer are input,
The detection circuit is
A circuit device comprising a differential amplifier circuit configured by the first and second amplifiers, to which the first and second signals corresponding to the first and second detection signals are input. The circuit device according to claim 6 ,
The detection circuit is
A first charge / voltage conversion circuit which is provided on the front side of the differential amplifier circuit and which receives the first detection signal and outputs the first signal;
A second charge / voltage conversion circuit which is provided on the front side of the differential amplifier circuit and which receives the second detection signal and outputs the second signal;
A circuit device comprising: The circuit device according to claim 6 or 7 ,
A circuit device comprising a gain adjustment amplifier which is provided on a subsequent stage side of the differential amplifier circuit and which adjusts a gain of an output signal of the differential amplifier circuit. The circuit device according to claim 8 ,
A circuit device comprising a synchronous detection circuit which is provided at a subsequent stage of the gain adjustment amplifier and performs synchronous detection based on a synchronous signal from the drive circuit. A circuit device according to any one of claims 6 to 9 ,
The physical quantity transducer;
A physical quantity detection device comprising: An electronic apparatus comprising a circuit arrangement as claimed in any one of claims 1 to 9. Mobile, characterized in that it comprises a circuit device according to any one of claims 1 to 9.

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