JP6686571B2 - Counter circuit, time measuring circuit and temperature sensor circuit - Google Patents

Description

  The technology disclosed in this specification relates to a counter circuit, a time measuring circuit, and a temperature sensor circuit.

  There is known a time measuring circuit that measures time using a clock signal. Such a time measuring circuit is required in various situations. For example, Patent Document 1 discloses a temperature sensor circuit including this type of time measuring circuit. In the temperature sensor circuit of Patent Document 1, the time measuring circuit is used to measure the delay time of the delay signal having the temperature dependent characteristic.

  In this type of time measuring circuit, it is desired to improve the time resolution. Patent Document 2 discloses a time measuring circuit that uses a low-speed clock signal having a relatively low frequency and a high-speed clock signal having a relatively high frequency. The time measuring circuit is configured to switch from the low speed clock signal to the high speed clock signal when the time from the start of measuring the measurement target time reaches a set value. As a result, this time measurement circuit can perform measurement by using the high-speed clock signal in a period close to the end timing of the measurement target time, so that the measurement target time can be measured with high resolution.

JP, 2013-185985, A JP-A-5-34474

  In time measurement using a clock signal, a counter circuit having a plurality of stages of flip-flops is used to measure the number of clocks. As such a counter circuit, a synchronous counter circuit and an asynchronous counter circuit are known. The synchronous counter circuit excels at accurate measurement using a low-speed clock signal. However, the synchronous counter circuit has a problem that the delay between each bit is large and it is difficult to measure accurately when a high-speed clock signal is used. On the other hand, since the asynchronous counter circuit has a small delay between bits, it is good at measurement using a high-speed clock signal. However, the asynchronous counter circuit has a problem that accurate measurement is difficult especially in the flip-flop in the subsequent stage because the delay between each bit is accumulated.

  Therefore, to realize highly accurate time measurement using low-speed clock signals and high-speed clock signals, prepare a synchronous counter circuit for low-speed clock signals and an asynchronous counter circuit for high-speed clock signals. There is a need to. However, if the synchronous counter circuit and the asynchronous counter circuit are separately prepared, many circuit resources are required.

  In the above, the time measurement circuit using the low speed clock signal and the high speed clock signal is illustrated, and the scene where both the synchronous counter circuit and the asynchronous counter circuit are necessary has been described. However, not only the time measuring circuit but also various circuits need both the synchronous counter circuit and the asynchronous counter circuit. The present specification provides a technique for integrating a synchronous counter circuit and an asynchronous counter circuit while suppressing an increase in circuit resources.

  One embodiment of the counter circuit disclosed in the present specification includes a plurality of stages of flip-flops, a plurality of first switches, and a plurality of second switches. The type of flip-flop is not particularly limited, and may be, for example, a JK-type flip-flop, a T-type flip-flop, or a D-type flip-flop. Each of the plurality of first switches is provided corresponding to each clock terminal of the flip-flops of the second and subsequent stages, and is configured to switch the signal input to the clock terminal. Each of the plurality of second switches is provided corresponding to each input terminal of the flip-flops of the second and subsequent stages, and is configured to switch the signal input to the input terminal. The plurality of first switches and the plurality of second switches constitute a wiring pattern such that the flip-flops of the multiple stages become a synchronous counter circuit in the synchronous mode, and the flip-flops of the multiple stages in the asynchronous mode are asynchronous counters. The wiring pattern is configured so that The counter circuit of this embodiment can switch the signal input to the clock terminal and the input terminal by switching the first switch and the second switch. As a result, the counter circuit of this embodiment can be switched to the synchronous counter circuit and the asynchronous counter circuit, and the synchronous counter circuit and the asynchronous counter circuit can be integrated. When the flip-flop is a JK-type flip-flop or a T-type flip-flop, the first switch is configured so that the clock signal is input to the clock terminal in the synchronous mode, and the output of the preceding flip-flop is input to the clock terminal in the asynchronous mode. Is configured to enter. The second switch is configured so that a carry signal is input to the input terminal in the synchronous mode and a high signal is input to the input terminal in the asynchronous mode. The carry signal is a signal indicating whether or not all the outputs of the flip-flops of the lower bits are Hi, when all are Hi, it is Hi, and the others are Lo. The counter circuit of this embodiment can be switched to a synchronous counter circuit and an asynchronous counter circuit by switching the first switch and the second switch. The counter circuit of this embodiment can integrate a synchronous counter circuit and an asynchronous counter circuit using JK type flip-flops or T type flip-flops while suppressing an increase in circuit resources.

  One embodiment of the time measurement circuit disclosed in the present specification includes an oscillation circuit and a counter circuit. The oscillator circuit generates a low speed clock signal having a relatively low frequency and a high speed clock signal having a relatively high frequency. The counter circuit measures the target time based on the low speed clock signal or the high speed clock signal output from the oscillation circuit. For example, the counter circuit may measure the time corresponding to the edges of the pulse signal. The counter circuit may switch the low-speed clock signal and the high-speed clock signal during measurement of the target time to measure the target time. Typically, the counter circuit may start measuring the target time using the low-speed clock signal, and may switch from the low-speed clock signal to the high-speed clock signal during the measurement to measure the remaining target time. The counter circuit includes a plurality of flip-flops, a plurality of first switches, and a plurality of second switches. The type of flip-flop is not particularly limited, and may be, for example, a JK-type flip-flop, a T-type flip-flop, or a D-type flip-flop. Each of the plurality of first switches is provided corresponding to each clock terminal of the flip-flops of the second and subsequent stages, and is configured to switch the signal input to the clock terminal. Each of the plurality of second switches is provided corresponding to each input terminal of the flip-flops of the second and subsequent stages, and is configured to switch the signal input to the input terminal. The plurality of first switches and the plurality of second switches constitute a wiring pattern such that the flip-flops of the multiple stages become a synchronous counter circuit in the synchronous mode, and the flip-flops of the multiple stages in the asynchronous mode are asynchronous counters. The wiring pattern is configured so that Since the time measuring circuit of this embodiment can be switched to the synchronous counter circuit and the asynchronous counter circuit by switching the first switch and the second switch, the time can be accurately controlled while suppressing an increase in circuit resources. It can be measured. When the flip-flop is a JK-type flip-flop or a T-type flip-flop, the first-stage flip-flop is configured so that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the high-speed clock signal is input to the clock terminal in the asynchronous mode. Is configured to enter. The first switch is configured such that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the output of the preceding flip-flop is input to the clock terminal in the asynchronous mode. The second switch is configured so that a carry signal is input to the input terminal in the synchronous mode and a high signal is input to the input terminal in the asynchronous mode. The carry signal is a signal indicating whether or not all the outputs of the flip-flops of the lower bits are Hi, when all are Hi, it is Hi, and the others are Lo. The counter circuit of the time measuring circuit of this embodiment can be switched between a synchronous counter circuit and a non-synchronous counter circuit using a JK flip flop or a T flip flop by switching the first switch and the second switch. it can. The counter circuit of the time measuring circuit of this embodiment can integrate a synchronous counter circuit and an asynchronous counter circuit using JK type flip-flops or T type flip-flops while suppressing an increase in circuit resources. Therefore, the time measuring circuit of this embodiment can measure time with high accuracy while suppressing an increase in circuit resources.

  One embodiment of the temperature sensor circuit disclosed in this specification includes an oscillation circuit, a delay circuit, and a counter circuit. The oscillator circuit generates a low speed clock signal having a relatively low frequency and a high speed clock signal having a relatively high frequency. The delay circuit generates a delay signal whose delay time has a temperature dependent characteristic. The counter circuit measures the delay time of the delay signal based on the low speed clock signal or the high speed clock signal output from the oscillation circuit. For example, the counter circuit may switch the low-speed clock signal and the high-speed clock signal while measuring the delay time to measure the delay time. Typically, the counter circuit may start measuring the delay time by using the low-speed clock signal, and switch the low-speed clock signal to the high-speed clock signal during the measurement to measure the remaining delay time. The counter circuit includes a plurality of flip-flops, a plurality of first switches, and a plurality of second switches. The type of flip-flop is not particularly limited, and may be, for example, a JK-type flip-flop, a T-type flip-flop, or a D-type flip-flop. Each of the plurality of first switches is provided corresponding to each clock terminal of the flip-flops of the second and subsequent stages, and is configured to switch the signal input to the clock terminal. Each of the plurality of second switches is provided corresponding to each input terminal of the flip-flops of the second and subsequent stages, and is configured to switch the signal input to the input terminal. The plurality of first switches and the plurality of second switches constitute a wiring pattern such that the flip-flops of the multiple stages become a synchronous counter circuit in the synchronous mode, and the flip-flops of the multiple stages in the asynchronous mode are asynchronous counters. The wiring pattern is configured so that Since the temperature sensor circuit of this embodiment can be switched between the synchronous counter circuit and the asynchronous counter circuit by switching the first switch and the second switch, the temperature can be accurately controlled while suppressing an increase in circuit resources. Can be measured. When the flip-flop is a JK-type flip-flop or a T-type flip-flop, the first-stage flip-flop is configured so that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the high-speed clock signal is input to the clock terminal in the asynchronous mode. Is configured to enter. The first switch is configured such that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the output of the preceding flip-flop is input to the clock terminal in the asynchronous mode. The second switch is configured so that a carry signal is input to the input terminal in the synchronous mode and a high signal is input to the input terminal in the asynchronous mode. The carry signal is a signal indicating whether or not all the outputs of the flip-flops of the lower bits are Hi, when all are Hi, it is Hi, and the others are Lo. The counter circuit of the temperature sensor circuit of this embodiment can be switched between a synchronous counter circuit and a non-synchronous counter circuit using a JK-type flip-flop or a T-type flip-flop by switching the first switch and the second switch. it can. The counter circuit of the temperature sensor circuit of this embodiment can integrate the synchronous counter circuit and the asynchronous counter circuit using the JK type flip-flop or the T type flip-flop while suppressing the consumption of circuit increase. Therefore, the temperature sensor circuit of this embodiment can measure temperature with high accuracy while suppressing an increase in circuit resources.

It is a block diagram which shows the outline of a temperature sensor circuit. It is a block diagram which shows the outline of an oscillation circuit. It is a circuit diagram which shows the outline of the ring oscillator contained in an oscillation circuit. It is a circuit diagram which shows the outline of the inverter chain contained in a delay circuit. It is a circuit diagram of a CMOS inverter that constitutes a ring oscillator and an inverter chain. It is a circuit diagram showing an outline of a counter circuit, and a mode that a 1st switch and a 2nd switch change in synchronous mode (A) and asynchronous mode (B) is shown. 6 is a timing chart showing how the temperature sensor circuit operates. It is a figure which shows the outline of a switching signal generation circuit. FIG. 3 is a circuit diagram of a bootstrap type CMOS inverter that constitutes a ring oscillator. It is a circuit diagram which shows the outline of the counter circuit of a modification, and a mode that a 1st switch and a 2nd switch are switched by a synchronous mode (A) and an asynchronous mode (B). It is a circuit diagram which shows the outline of the counter circuit of a modification, and a mode that a 1st switch and a 2nd switch are switched by a synchronous mode (A) and an asynchronous mode (B).

  As shown in FIG. 1, the temperature sensor circuit 1 is an integrated circuit that is made into one chip, and includes an oscillation circuit 2, a pulse generation circuit 4, a delay circuit 6, a counter circuit 8 and a switching signal generation circuit 10.

  The oscillator circuit 2 is configured to generate a low speed clock signal CLK1 having a relatively low frequency and a high speed clock signal CLK2 having a relatively high frequency. These clock signals CLK1 and CLK2 are rectangular waves having a duty ratio of 50%, for example. The pulse generation circuit 4 is configured to generate the pulse signal V1. The pulse generation circuit 4 may be configured to generate the pulse signal V1 by using the clock signals CLK1 and CLK2 generated by the oscillation circuit 2. For example, the pulse generating circuit 4 may be configured to generate a pulse signal V1 by lowering the frequency of the low speed clock signal CLK1 by using a frequency dividing circuit. The delay circuit 6 is configured to generate a delayed pulse signal V2 by delaying the pulse signal V1. The counter circuit 8 is configured to measure the time difference between the pulse signal V1 and the delayed pulse signal V2 (corresponding to the delay time of the delayed pulse signal V2) based on the number of clocks of the low speed clock signal CLK1 and the high speed clock signal CLK2. There is. As will be described later, the counter circuit 8 uses the clock signal selected from the low-speed clock signal CLK1 and the high-speed clock signal CLK2 to determine the time difference between the pulse signal V1 and the delay pulse signal V2 (the delay time of the delay pulse signal V2). Equivalent). The counter circuit 8 is also configured to output the measured clock number as digital temperature information Dout. The switching signal generation circuit 10 is configured to generate the switching signal S1 based on the number of clocks measured by the counter circuit 8.

  As shown in FIG. 2, the oscillation circuit 2 has a low speed clock signal generation circuit 2A and a high speed clock signal generation circuit 2B. The low speed clock signal generation circuit 2A is configured to generate the low speed clock signal CLK1. The high speed clock signal generation circuit 2B is configured to generate the high speed clock signal CLK2. The oscillator circuit 2 selects one of the low-speed clock signal generation circuit 2A and the high-speed clock signal generation circuit 2B based on the switching signal S1 from the switching signal generation circuit 10 and outputs the clock signals CLK1 and CLK2. It is configured.

  As shown in FIG. 3, each of the low-speed clock signal generation circuit 2A and the high-speed clock signal generation circuit 2B of the oscillation circuit 2 is composed of a ring oscillator in which a plurality of first inverters INV1 are connected in a ring shape. . The number of stages of the first inverter INV1 of each of the low-speed clock signal generation circuit 2A and the high-speed clock signal generation circuit 2B is different, so that the frequencies of the oscillated clock signals CLK1 and CLK2 are different. In this example, the number of stages of the low-speed clock signal generation circuit 2A is larger than that of the high-speed clock signal generation circuit 2B. For example, the low-speed clock signal generation circuit 2A has 15 stages of the first inverter INV1. The high-speed clock signal generation circuit 2B has three stages of first inverters INV1.

  As shown in FIG. 4, the delay circuit 6 is composed of an inverter chain in which a plurality of second inverters INV2 are connected in series. For example, the inverter chain has 50 stages of second inverters INV2.

  As shown in FIG. 5, the first inverter INV1 of the ring oscillator and the second inverter INV2 of the inverter chain are both connected in series between the positive power supply line (Vdd line) and the negative power supply line (Vss). A CMOS having one transistor Tr1 and a second transistor Tr2 is provided. The first transistor Tr1 is a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the source is connected to the Vdd line, and the drain is connected to the drain of the second transistor Tr2. The second transistor Tr2 is an n-type MOSFET, the drain is connected to the drain of the first transistor Tr1, and the source is connected to the negative power supply line Vss. The connection point between the first transistor Tr1 and the second transistor Tr2 is connected to the gate of the transistor that forms the CMOS inverter of the next stage.

  In the temperature sensor circuit 1, the channel length modulation effect by the transistors Tr1 and Tr2 forming the first inverter INV1 of the ring oscillator and the channel length modulation effect by the transistors Tr1 and Tr2 forming the second inverter INV2 of the inverter chain are different from each other. It is characterized by being. Specifically, when the gate width is constant, the gate lengths of the transistors Tr1 and Tr2 forming the first inverter INV1 of the ring oscillator are equal to the gate lengths of the transistors Tr1 and Tr2 forming the second inverter INV2 of the inverter chain. Configured to be shorter than. In this example, the gate length of the first transistor Tr1 of the first inverter INV1 is shorter than the gate length of the first transistor Tr1 of the second inverter INV2, and the gate length of the second transistor Tr2 of the first inverter INV1 is It is shorter than the gate length of the second transistor Tr2 of the second inverter INV2. Instead of this example, only one of the first transistor Tr1 and the second transistor Tr2 of the first inverter INV1 may have a short gate length.

  Normally, the operating current of the transistors Tr1 and Tr2 becomes smaller at a higher temperature than at a low temperature, and the operating speed decreases. Therefore, in the first inverter INV1 of the ring oscillator, the operating speed decreases at a temperature higher than the low temperature, so that the cycle of the oscillating clock signals CLK1 and CLK2 increases (frequency decreases). That is, the cycles of the clock signals CLK1 and CLK2 have a positive temperature-dependent characteristic that increases with a substantially linear function with respect to temperature. Further, also in the second inverter INV2 of the inverter chain, the operation speed decreases at a temperature higher than the low temperature, so that the delay time of the delay pulse signal V2 increases. That is, the delay time of the delayed pulse signal V2 also has a positive temperature-dependent characteristic that increases with a substantially linear function with respect to temperature. Here, the channel length modulation effect refers to the amount of current increase in the saturation region of the IV characteristic. Therefore, that the channel length modulation effect is different means that the amount of current increase in the saturation region of the IV characteristic is different. In this embodiment, since the gate lengths of the transistors Tr1 and Tr2 that form the first inverter INV1 of the ring oscillator are shorter than the gate lengths of the transistors Tr1 and Tr2 that form the second inverter INV2 of the inverter chain, the saturation region of the IV characteristic is obtained. With respect to the amount of increase in current, the transistors Tr1 and Tr2 forming the first inverter INV1 of the ring oscillator are larger than the transistors Tr1 and Tr2 forming the second inverter INV2 of the inverter chain. Therefore, when the temperature changes from a low temperature to a high temperature, the amount of change in current in the transistors Tr1 and Tr2 of the ring oscillator is relatively small, and the amount of change in current in the transistors Tr1 and Tr2 of the inverter chain is relatively large. As a result, when the temperature changes from low temperature to high temperature, the decrease amount of the operating speed of the ring oscillator is relatively small, and the decrease amount of the operating speed of the inverter chain is relatively large.

  In the temperature sensor circuit 1, the channel length modulation effect of the transistors Tr1 and Tr2 forming the first inverter INV1 of the ring oscillator is different from the channel length modulation effect of the transistors Tr1 and Tr2 forming the second inverter INV2 of the inverter chain. Therefore, in the present embodiment, when the temperature changes from low temperature to high temperature, the decrease amount of the operating speed of the ring oscillator and the decrease amount of the operating speed of the inverter chain are different, and the clock signals CLK1 and CLK2 generated by the ring oscillator are different. And the temperature dependence of the delayed pulse signal V2 generated by the inverter chain are different. As described above, the cycles of the clock signals CLK1 and CLK2 have a positive temperature-dependent characteristic that increases with a substantially linear function with respect to temperature. The delay time of the delayed pulse signal V2 also has a positive temperature dependence characteristic that increases with a substantially linear function with respect to temperature. Furthermore, the rate of change of the delay time of the delay pulse signal V2 with respect to temperature (the ratio of the delay time at an arbitrary temperature when the delay time of the reference temperature is "1") is the rate of change of the cycle of the clock signals CLK1 and CLK2 with respect to temperature ( The ratio is larger than the ratio of the cycle at an arbitrary temperature when the cycle of the reference temperature is “1”), and both temperature dependence characteristics are different.

  Thus, if the temperature dependence characteristics of the clock signals CLK1 and CLK2 generated by the ring oscillator and the temperature dependence characteristics of the delayed pulse signal V2 generated by the inverter chain are different, the number of clocks measured by the counter circuit 8 Fluctuates with temperature. In the temperature sensor circuit 1, the temperature information Dout can be obtained by utilizing the difference between the temperature dependence characteristics of the clock signals CLK1 and CLK2 and the temperature dependence characteristics of the delayed pulse signal V2.

  FIG. 6 shows a circuit diagram of the counter circuit 8. Although the 4-bit counter circuit 8 is illustrated in FIG. 6, the number of bits is not limited to this example. The counter circuit 8 is configured to be capable of dynamically switching between the synchronous mode shown in (A) and the asynchronous mode shown in (B). The counter circuit 8 includes a plurality of JK flip-flops FF, a plurality of first switches SW1, a plurality of second switches SW2, and a plurality of AND circuits 9. A combination of the first switch SW1 and the second switch SW2 is provided corresponding to each of the second and subsequent JK flip-flops FF. The AND circuit 9 is provided corresponding to each of the JK type flip-flops FF in the third and subsequent stages.

  In the first-stage JK flip-flop FF, clock signals CLK1 and CLK2 are input to its clock terminal (CLK), Hi is input to its input terminals (both J input and K input), and its output terminal (Q) is input. The first switch SW1 and the second switch SW2 of the JK flip-flop FF in the next stage are configured to be connected. Further, the first-stage JK flip-flop FF is configured such that the low-speed clock signal CLK1 is input to the clock terminal (CLK) in the synchronous mode (A), and the high-speed clock signal (CLK) is input to the clock terminal (CLK) in the asynchronous mode (B). The clock signal CLK2 is input. In the JK flip-flop FF of the second and subsequent stages, the first switch SW1 is connected to its clock terminal (CLK), the second switch SW2 is connected to its input terminals (both J input and K input), and its output The first switch SW1 of the next stage is connected to the terminal (Q). The AND circuit 9 is configured to generate a carry signal S2 whose output becomes Hi when the outputs of the output terminals (Q) of the lower bits are all Hi, and which otherwise becomes Lo.

  The first switch SW1 and the second switch SW2 are configured to switch connection destinations in synchronization with the switching signal S1 from the switching signal generation circuit 10 in correspondence with the synchronous mode (A) and the asynchronous mode (B). Has been done. The first switch SW1 is configured so that the low-speed clock signal CLK1 is input to the clock terminal (CLK) of the JK flip-flop FF in the synchronous mode (A), and the low speed clock signal CLK1 is input in the asynchronous mode (B). The output of the output terminal (Q) of the preceding JK type flip-flop FF is input to the clock terminal (CLK). In the synchronous mode (A), the second switch SW2 is connected to the input terminal of the JK type flip-flop FF and the output terminal of the AND circuit 9 (however, regarding the second stage JK type flip-flop FF, the preceding stage JK type flip-flop FF is used. Output terminal (Q)) is connected, and Hi is input to the input terminal of the JK flip-flop FF in the asynchronous mode (B). In this way, the counter circuit 8 operates as a synchronous counter circuit in the synchronous mode (A) by switching between the first switch SW1 and the second switch SW2, and an asynchronous counter in the asynchronous mode (B). It can operate as a circuit.

  FIG. 7 shows how the temperature sensor circuit 1 measures the delay time. In this example, the time from timing T1 to timing T2 corresponds to the delay time. The timing T1 corresponds to the rising edge of the pulse signal V1 and the timing T2 corresponds to the rising edge of the delayed pulse signal V2 (see FIGS. 1 and 4).

  The temperature sensor circuit 1 is characterized by executing temporary measurement and actual measurement. The temporary measurement is characterized in that the delay time is measured using only the low-speed clock signal CLK1. The actual measurement is characterized in that the delay time is measured using the low speed clock signal CLK1 and the high speed clock signal CLK2. In the actual measurement, the timing at which the low-speed clock signal CLK1 is switched to the high-speed clock signal CLK2 is when the time after the measurement of the delay time has reached the set value. Specifically, the timing at which the low-speed clock signal CLK1 is switched to the high-speed clock signal CLK2 is when the number of clocks of the low-speed clock signal CLK1 reaches the set number after the measurement of the delay time is started. This set number is calculated by subtracting a predetermined number of clocks from the number of clocks of the low speed clock signal CLK1 measured by the provisional measurement.

  The timing of switching the low speed clock signal CLK1 from the high speed clock signal CLK2 is controlled by the switching signal generating circuit 10 (see FIG. 1). As shown in FIG. 8, the switching signal generation circuit 10 includes a subtraction circuit 11, a register 13, a comparison circuit 15, a measurement count recording circuit 17, and an AND circuit 19.

  Dc1 is a digital count value output from the counter circuit 8 and corresponds to the number of clocks of the low-speed clock signal CLK1 measured by provisional measurement. K is a predetermined digital predetermined value. The predetermined value K may be a fixed value or a value that can be changed as appropriate. The subtraction circuit 11 calculates a value (Dc1-K) obtained by subtracting the predetermined value K from the counter value Dc1. The value (Dc1-K) is a set number that determines the timing of switching from the low speed clock signal CLK1 to the high speed clock signal CLK2 in actual measurement. The register 13 stores the set number (Dc1-K).

  Dc2 is a digital count value output from the counter circuit 8 and corresponds to the number of clocks of the low-speed clock signal CLK1 measured by actual measurement. The comparator circuit 15 switches the output from low to high when the counter value Dc2 exceeds the set number (Dc1-K). The measurement number recording circuit 17 is a 1-bit memory, and outputs low at the time of temporary measurement and outputs high at the time of actual measurement. The AND circuit 19 performs the actual measurement, and when the counter value Dc2 exceeds the set number (Dc1-K), that is, the number of clocks of the low-speed clock signal CLK1 after starting the delay time measurement in the actual measurement is the set number. When it reaches (Dc1-K), the switching signal S1 is output.

  As shown in FIGS. 1 and 2, when the switching signal S1 is input, the oscillation circuit 2 changes the connection destination of the switch from the low speed clock signal generation circuit 2A to the high speed clock signal generation circuit 2B, and the counter circuit 8 The clock signal provided to the high speed clock signal CLK1 is switched from the low speed clock signal CLK1 to the high speed clock signal CLK2. In this way, the switching signal generation circuit 10 can control the timing of switching from the low-speed clock signal CLK1 to the high-speed clock signal CLK2 in actual measurement.

  As shown in FIG. 1 and FIG. 6, when the switching signal S1 is input, the counter circuit 8 switches the connection destination of the first switch SW1 and the second switch SW2, thereby changing from the synchronous mode (A) to the asynchronous mode. It is possible to switch to the expression mode (B). Further, the counter circuit 8 resets the counter value when the switching signal S1 is input. As described above, the counter circuit 8 can operate in the synchronous mode (A) in the temporary measurement and in the synchronous mode (A) and the asynchronous mode (B) in the actual measurement. The counter circuit 8 can integrate a synchronous counter circuit and an asynchronous counter circuit while suppressing an increase in circuit resources. For example, the number of gates of the counter circuit 8 is reduced by about 43% as compared with the case where the 4-bit synchronous counter circuit and the asynchronous counter circuit are separately integrated.

  Generally, the synchronous counter circuit can read the counter value from each bit in real time because the delay between each bit is constant with respect to the clock signal. Therefore, the synchronous counter circuit can accurately measure the number of clocks. On the other hand, the synchronous counter circuit is not suitable for increasing the speed of the clock signal because the delay between bits is relatively large. Therefore, it is desirable to use a low-speed clock signal for the synchronous counter circuit.

  In general, an asynchronous counter circuit has a relatively small delay between bits because it has no logic gate other than a flip-flop. Therefore, the asynchronous counter circuit can handle a high-speed clock signal. On the other hand, the asynchronous counter circuit is not suitable for reading the counter value from each bit in real time because the delay between the bits accumulates. Therefore, it is desirable to use a high speed clock signal for the asynchronous counter circuit.

  As described above, the counter circuit 8 can operate to measure the low speed clock signal CLK1 in the synchronous mode (A) and can operate to measure the high speed clock signal CLK2 in the asynchronous mode (B). . Therefore, the counter circuit 8 can accurately measure the counter value Dc1 in the temporary measurement by executing the synchronous mode (A), and further, the counter value Dc1 to the set number (Dc1-K) in the actual measurement. The time to reach can be measured accurately. In addition, the counter circuit 8 executes the asynchronous mode (B) so that the period from the time when the set number (Dc1-K) in the actual measurement is reached to the timing T2 when the delay time ends (see FIG. 7). Can be measured accurately. In this way, the counter circuit 8 can accurately measure the delay time of the delayed pulse signal V2. As a result, the temperature sensor circuit 1 can accurately measure the temperature.

  The counter circuit 8 of the temperature sensor circuit 1 provides the set value (Dc1-K) and the counter value based on the high-speed clock signal CLK2 as the temperature information Dout. The counter value based on the high-speed clock signal CLK2 is obtained by resetting the counter value of the counter circuit 8 in synchronization with the switching signal S1 of the switching signal generation circuit 10 in actual measurement. In this way, the temperature sensor circuit 1 can output the count number measured using the low speed clock signal CLK1 and the counter number measured using the high speed clock signal CLK2 as the temperature information Dout in actual measurement.

  The oscillation circuit 2 of the temperature sensor circuit 1 described above changes the connection destination of the switch from the low-speed clock signal generation circuit 2A to the high-speed clock signal generation circuit 2B so that the clock signal provided to the counter circuit 8 is changed from the low-speed clock signal CLK1. Switch to the high-speed clock signal CLK2. Instead of this, as shown in FIG. 9, the ring oscillator of the oscillation circuit 2 may be configured by a bootstrap type CMOS inverter.

  As shown in FIG. 9, the first inverter INV1 which is a bootstrap type CMOS inverter has a plurality of switch circuits SW11, SW12, SW13, SW14 and a plurality of capacitors C1, C2, as compared with the example of FIG. . The switch circuits SW11 and SW12 are configured to switch between a state in which the capacitor C1 is connected to the gate of the first transistor Tr1 and a state in which the capacitor C1 is not connected. The switch circuits SW13 and SW14 are configured to switch between a state where the capacitor C2 is connected to the gate of the second transistor Tr2 and a state where the capacitor C2 is not connected.

  In the bootstrap type first inverter INV1, the bootstrap becomes effective when the switching signal S1 of the switching signal generating circuit 10 is input, and the switch circuits SW11 and SW12 connect the capacitor C1 to the gate of the first transistor Tr1 and switch the switch circuit. SW13 and SW14 connect the capacitor C2 to the gate of the second transistor Tr2. The capacitor C1 is precharged with electric charges so that the gate side of the first transistor Tr1 becomes negative, whereby the first transistor Tr1 can operate at high speed. The capacitor C2 is pre-charged so that the gate side of the second transistor Tr2 is positive, which allows the second transistor Tr2 to operate at high speed.

  In this way, when the bootstrap type first inverter INV1 is adopted as the ring oscillator of the oscillation circuit 2 of the temperature sensor circuit 1, the low speed clock signal generation circuit 2A and the high speed clock signal generation circuit 2B are provided as in the example of FIG. It is not necessary to prepare them individually, and it is possible to suppress an increase in circuit resources. Moreover, since the high-speed clock signal CLK2 can be generated only when necessary, power consumption can be suppressed low.

  The counter circuit 8 is composed of a plurality of JK flip-flops FF. Instead of this, the counter circuit 8 may be composed of a plurality of stages of T-type flip-flops FF as shown in FIG. The wiring pattern of the counter circuit 8 including a plurality of stages of T-type flip-flops FF is the same as that of the case including a plurality of stages of JK-type flip-flops FF. Further, the counter circuit 8 may be composed of a plurality of stages of D-type flip-flops FF as shown in FIG. In this example, the second switch SW2 switches the signal input to the XOR circuit between the synchronous mode and the asynchronous mode. As a result, the second switch SW2 is configured so that the exclusive OR of the carry signal S2 and the output Q is input to the input terminal of the D-type flip-flop FF in the synchronous mode (A), and the asynchronous mode (B ), The exclusive OR of the Hi signal and the output Q is input to the input terminal of the D-type flip-flop FF. Each of the counter circuits 8 of FIG. 10 and FIG. 11 integrates a conventionally known synchronous counter circuit and asynchronous counter circuit only by mounting a plurality of first switches SW1 and a plurality of second switches SW2. can do.

  Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Further, the technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings can simultaneously achieve a plurality of objects, and achieving the one object among them has technical utility.

1: Temperature sensor circuit 2: Oscillation circuit 3: Frequency divider circuit 4: Delay circuit 5: Delay time measurement circuit 6: Switching signal generation circuit CLK1: Low speed clock signal CLK2: High speed clock signal

Claims (8)

A counter circuit,
Multiple stages of flip-flops,
A plurality of first switches, each of the plurality of first switches is provided corresponding to each clock terminal of each of the flip-flops of the second and subsequent stages, and a signal input to the clock terminal. A plurality of first switches configured to switch
A plurality of second switches, wherein each of the plurality of second switches is provided corresponding to each input terminal of the second and subsequent stages of the flip-flops, and a signal input to the input terminal And a plurality of second switches configured to switch between,
The plurality of first switches and the plurality of second switches configure a wiring pattern so that the plurality of stages of flip-flops become a synchronous counter circuit in the synchronous mode, and the plurality of stages of flip-flops in the asynchronous mode. The wiring pattern is configured so that is an asynchronous counter .
The first switch is configured such that a clock signal is input to the clock terminal in the synchronous mode, and an output of the previous flip-flop is input to the clock terminal in the asynchronous mode,
The counter circuit is configured such that a carry signal is input to the input terminal in the synchronous mode and a high signal is input to the input terminal in the asynchronous mode . The counter circuit according to claim 1 , wherein the flip-flop is a JK type flip-flop. A time measuring circuit,
An oscillation circuit that generates a low-speed clock signal having a relatively low frequency and a high-speed clock signal having a relatively high frequency,
A counter circuit that measures a target time based on the low-speed clock signal or the high-speed clock signal output from the oscillator circuit,
The counter circuit is
Multiple stages of flip-flops,
A plurality of first switches, each of the plurality of first switches is provided corresponding to each clock terminal of each of the flip-flops of the second and subsequent stages, and a signal input to the clock terminal. A plurality of first switches configured to switch
A plurality of second switches, wherein each of the plurality of second switches is provided corresponding to each input terminal of the second and subsequent stages of the flip-flops, and a signal input to the input terminal And a plurality of second switches configured to switch between,
The plurality of first switches and the plurality of second switches configure a wiring pattern so that the plurality of stages of flip-flops become a synchronous counter circuit in the synchronous mode, and the plurality of stages of flip-flops in the asynchronous mode. A time measurement circuit that configures the wiring pattern so that it becomes an asynchronous counter. The first-stage flip-flop is configured such that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the high-speed clock signal is input to the clock terminal in the asynchronous mode.
The first switch is configured such that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the output of the preceding flip-flop is input to the clock terminal in the asynchronous mode. Cage,
The second switch, the is configured to carry signals to the input terminals in the synchronous mode is entered, a high signal to the input terminal in the asynchronous mode is configured to input, claim 3 Time measurement circuit described in. The time measuring circuit according to claim 4 , wherein the flip-flop is a JK type flip-flop. A temperature sensor circuit,
An oscillation circuit that generates a low-speed clock signal having a relatively low frequency and a high-speed clock signal having a relatively high frequency,
A delay circuit for generating a delay signal having a delay time having a temperature dependent characteristic;
A counter circuit for measuring the delay time of the delay signal based on the low-speed clock signal or the high-speed clock signal output from the oscillation circuit,
The counter circuit is
Multiple stages of flip-flops,
A plurality of first switches, each of the plurality of first switches is provided corresponding to each clock terminal of each of the flip-flops of the second and subsequent stages, and a signal input to the clock terminal. A plurality of first switches configured to switch
A plurality of second switches, wherein each of the plurality of second switches is provided corresponding to each input terminal of the second and subsequent stages of the flip-flops, and a signal input to the input terminal And a plurality of second switches configured to switch between,
The plurality of first switches and the plurality of second switches configure a wiring pattern so that the plurality of stages of flip-flops become a synchronous counter circuit in the synchronous mode, and the plurality of stages of flip-flops in the asynchronous mode. A temperature sensor circuit in which the wiring pattern is configured so that is an asynchronous counter. The first-stage flip-flop is configured such that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the high-speed clock signal is input to the clock terminal in the asynchronous mode.
The first switch is configured such that the low-speed clock signal is input to the clock terminal in the synchronous mode, and the output of the preceding flip-flop is input to the clock terminal in the asynchronous mode. And
The second switch, the carry signal to the input terminal In synchronous mode is configured to input a high signal to the input terminal in the asynchronous mode is configured to input, claim 6 The temperature sensor circuit according to. The temperature sensor circuit according to claim 7 , wherein the flip-flop is a JK type flip-flop.

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