JP6686599B2 - Image processing apparatus, load balancing method, and load balancing program - Google Patents

Description

  The present invention relates to an image processing apparatus, a load distribution method, and a load distribution program, and more particularly to an image processing apparatus including a multi-core processor having a plurality of cores, a load distribution method and a load distribution program executed by the image processing apparatus.

  In recent years, a multi-core processor having a plurality of cores is known, and it is conceivable to mount the multi-core processor on an MFP (Multi Function Peripheral) typified by an image processing apparatus that processes an image. In a multi-core processor, threads are assigned to a plurality of cores to execute different processes in parallel. However, depending on the thread allocation state, the load on one core may be greater than that on another core. Therefore, there is known a technique for distributing the load among a plurality of cores.

  For example, Japanese Unexamined Patent Application Publication No. 2008-191949 discloses a multi-core system having a plurality of multi-core processors having a plurality of core processors and a shared resource that shares the resources of each multi-core processor, and the load information of each multi-core processor. And load information collecting means for acquiring load information at the time of accessing the shared resource, load information of each of the multi-core processors acquired by the load information collecting means, and load information at the time of access based on conditions In a multi-core system having a load balancing determining unit that determines whether to perform load balancing, and a load balancing unit that balances the load when the load balancing determining unit determines to perform load balancing. A multi-core system is described, characterized in that In the multi-core system described in Japanese Unexamined Patent Application Publication No. 2008-191949, the threads assigned to the multi-core processor with the increased load are moved to the multi-core processor with the lighter load, so that the load can be distributed among the multi-core processors. it can.

However, in the multi-core processor after moving the thread, it takes time to write the data in the cache memory, and the cache hit rate for accessing the cache memory when executing the thread to be moved is higher than that before moving. It is not always high. Therefore, there is a problem in that the processing speed at which the moved multi-core processor executes the thread to be moved may be slower than that before the movement.
JP, 2008-191949, A

  The present invention has been made to solve the above-described problems, and one of the objects of the present invention is to reduce the processing time after the movement of a thread to be moved and to distribute the load of a plurality of processor cores. It is to provide an image processing apparatus capable of performing the above.

  Another object of the present invention is to provide a load distribution method capable of distributing the loads of a plurality of processor cores while shortening the processing time after the migration target thread is migrated.

  Still another object of the present invention is to provide a load distribution program capable of distributing the loads of a plurality of processor cores while shortening the processing time after the migration of threads to be migrated.

  According to an aspect of the present invention in order to achieve the above-mentioned object, an image processing apparatus includes a plurality of processor cores, a plurality of cache memories respectively corresponding to the plurality of processor cores, and a target core of the plurality of processor cores. Target thread determining means for determining one of the one or more threads allocated to the target thread as a target thread, a hit rate acquiring means for acquiring a cache hit rate of each of a plurality of processor cores, and a target rate acquiring means for acquiring the target core. Based on the cache hit rate, the first predicting unit that predicts the first processing speed at which the target core executes the target thread, and the candidate core different from the target core among the plurality of processor cores determines the cache hit rate. Second predicting means for predicting a second processing speed when the target thread is executed as zero, and a first processing speed And a second processing speed are compared to determine the allocation of the target thread from the target core to the candidate core, and the allocation of the target thread based on the result of the determination by the determination means. Allocation changing means for changing the target core to the candidate core.

  According to this aspect, the first processing speed at which the target core executes the target thread is predicted based on the cache hit rate acquired for the target core, and the candidate core executes the target thread with the cache hit rate set to zero. In this case, the second processing speed is predicted, and by comparing the first processing speed and the second processing speed, it is determined whether the allocation of the target thread is changed from the target core to the candidate core. Based on this, the allocation of the target thread is changed from the target core to the candidate core. Therefore, since the first processing speed before moving the target thread and the second processing speed after moving the target thread are compared, it is predicted that the processing speed for processing the target thread will be high. The target thread is moved to. As a result, it is possible to provide an image processing apparatus capable of distributing the loads of a plurality of processor cores while shortening the processing time after the movement of the thread to be moved.

Preferably, a occupancy ratio acquisition unit for acquiring an occupancy ratio, which is a ratio of the entire thread processing time, to each of the one or more threads executed by each of the plurality of processor cores is further provided, and the first prediction unit includes the occupancy ratio. The first processing speed is predicted based on the occupancy ratio of the target thread acquired by the acquisition unit and the cache hit ratio of the target core acquired by the hit ratio acquisition unit, and the second prediction unit is the occupancy ratio acquisition unit. The second processing speed is predicted based on the spare capacity of the candidate core calculated from the occupancy of each of the one or more threads executed by the candidate core acquired by.

  According to this aspect, the first processing speed is predicted based on the occupancy rate of the target thread and the cache hit rate of the target core, and the candidate is calculated from the occupancy rates of the one or more threads executed by the candidate core. The second processing speed is predicted based on the remaining capacity of the core. Therefore, the processing speed before and after moving the target thread can be accurately predicted.

Preferably, the system further comprises capacity information acquisition means for acquiring the processing capacities of the plurality of processor cores, and the first prediction means predicts the first processing speed further based on the processing capacity of the target core , and the second prediction means. Estimates the second processing speed further based on the processing capabilities of the candidate cores.

  According to this aspect, it is possible to adapt to the case where the processing performance of the processor core before moving the target thread is different from that of the processor core after moving.

  Preferably, the determination means determines whether to change the allocation of the target thread from the target core to the candidate core at predetermined time intervals.

  According to this aspect, it is determined whether or not the allocation of the target thread is changed at a predetermined time interval, so that it is possible to distribute the load on the plurality of processor cores at the predetermined time interval.

  Preferably, when the target thread divides the image data to be processed by the target thread into a plurality of processing unit parts to process, the target thread assigns the allocation of the target thread determined to be changed by the determining means. The value is changed according to the completion of processing of any of the plurality of processing unit parts.

  According to this aspect, the thread assignment is not changed until the processing of any one of the plurality of processing unit parts of the image data is completed, so that the same processing is prevented from being executed before and after the movement. can do.

  Preferably, the target thread determining means further comprises a variable thread determining means for determining a thread for executing a program in which any one of the plurality of processor cores defines a process for converting image data, as a variable thread. One of the one or more variable threads determined by is determined as the target thread.

  According to this aspect, since the thread that executes the program that defines the processing for converting the image data is the target of movement, it is possible to accurately predict the first processing speed and the second processing speed.

  Preferably, the target thread determining means determines the target thread in the descending order of priority among the plurality of variable threads determined by the variable thread determining means.

  According to this aspect, it is determined whether or not the plurality of variable threads are moved in descending order of priority, so that the processing of the variable threads with high priority can be terminated early.

  According to another aspect of the present invention, a load balancing method is a load balancing method executed by an image processing apparatus, wherein the image processing apparatus includes a plurality of processor cores and a plurality of processor cores respectively corresponding to the plurality of processor cores. A target thread determining step of determining one of the one or more threads allocated to the target core among the plurality of processor cores as a target thread, and a cache hit ratio of each of the plurality of processor cores. A hit rate acquisition step, a first prediction step of predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step, and a plurality of processor cores A candidate core other than the target core executes the target thread with a cache hit rate of zero. The second prediction step of predicting the second processing speed in the case of performing the first processing speed and the second processing speed are compared to determine whether the allocation of the target thread is changed from the target core to the candidate core. The determination step includes a determination step of determining, and an assignment changing step of changing the assignment of the target thread from the target core to the candidate core based on the determination result in the determination step.

  According to this aspect, it is possible to provide a load balancing method capable of balancing the loads of a plurality of processor cores while shortening the processing time after the migration of the thread to be migrated.

  According to still another aspect of the present invention, the load distribution program is a load distribution program executed by a multi-core processor that controls the image processing apparatus, and the multi-core processor includes a plurality of processor cores and a plurality of processor cores. A target thread determining step of determining one of the one or more threads allocated to the target core among the plurality of processor cores as a target thread, and a cache of each of the plurality of processor cores. A hit rate acquisition step of acquiring a hit rate, and a first prediction step of predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step, Different from the target core among multiple processor cores The core allocates the target thread by comparing the first processing speed and the second processing speed with the second prediction step of predicting the second processing speed when the target thread is executed with the cache hit rate set to zero. A multi-core processor, a determination step of determining whether to change from the target core to the candidate core, and an assignment change step of changing the assignment of the target thread from the target core to the candidate core based on the determination result in the determination step. To run.

  According to this aspect, it is possible to provide a load distribution program capable of distributing the loads of a plurality of processor cores while shortening the processing time after the thread to be moved is moved.

FIG. 3 is a perspective view showing the external appearance of the MFP according to the present embodiment. 3 is a block diagram showing an outline of a hardware configuration of the MFP according to the present embodiment. FIG. It is a figure which shows an example of a structure of the multi-core processor with which the MFP in this Embodiment is equipped. FIG. 3 is a diagram showing an example of functions of a multicore processor included in the MFP according to the present embodiment. It is a figure which shows an example of capability definition data. It is a 1st figure for demonstrating movement of the thread for processing. It is a 2nd figure for demonstrating movement of the thread for processing. It is a flow chart which shows an example of the flow of load distribution processing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are designated by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

  FIG. 1 is a perspective view showing the appearance of the MFP according to the present embodiment. FIG. 2 is a block diagram showing an outline of the hardware configuration of the MFP according to this embodiment. 1 and 2, MFP 100 functioning as an image processing apparatus includes a main circuit 110, a document reading unit 130 for reading a document, and an automatic document feeding device for feeding a document to document reading unit 130. 120, an image forming section 140 for forming an image on a sheet based on image data output by the original reading section 130 reading an original, and a paper feeding section 150 for supplying a sheet to the image forming section 140. , And an operation panel 160 as a user interface.

  The main circuit 110 includes a multi-core processor 111, a communication interface (I / F) unit 112, a ROM 113, a RAM 114, a hard disk drive (HDD) 115 as a mass storage device, a facsimile unit 116, and a CD-ROM ( An external storage device 117 to which a Compact Disk ROM) 118 is attached. The multi-core processor 111 is connected to the automatic document feeder 120, the document reading unit 130, the image forming unit 140, the paper feeding unit 150, and the operation panel 160, and controls the entire MFP 100.

  The ROM 113 stores a program executed by the multi-core processor 111, or data necessary for executing the program. The RAM 114 is used as a work area when the multi-core processor 111 executes a program.

  Communication I / F unit 112 is an interface for connecting MFP 100 to a network. The multi-core processor 111 communicates with a computer connected to the network and transmits / receives data via the communication I / F unit 112. Moreover, the communication I / F unit 112 can communicate with a computer connected to the Internet via a network.

  Facsimile unit 116 is connected to the public switched telephone network (PSTN) and transmits facsimile data to PSTN or receives facsimile data from PSTN. The facsimile unit 116 stores the received facsimile data in the HDD 115 or outputs it to the image forming unit 140. The image forming unit 140 prints the facsimile data received by the facsimile unit 116 on paper. Facsimile unit 116 also converts the data stored in HDD 115 into facsimile data and transmits the facsimile data to a facsimile device connected to PSTN.

  A CD-ROM 118 is attached to the external storage device 117. The multi-core processor 111 can access the CD-ROM 118 via the external storage device 117. The multi-core processor 111 loads the program recorded in the CD-ROM 118 mounted on the external storage device 117 into the RAM 114 and executes the program. The medium for storing the program executed by the multi-core processor 111 is not limited to the CD-ROM 118, and may be an optical disc (MO (Magnetic Optical disc) / MD (Mini Disc) / DVD (Digital Versatile Disc)), an IC card, an optical disc. It may be a semiconductor memory such as a card, a mask ROM, an EPROM (Erasable Programmable ROM), or an EEPROM (Electrically EPROM).

  Further, the program executed by the multi-core processor 111 is not limited to the program recorded in the CD-ROM 118, and the program stored in the HDD 115 may be loaded into the RAM 114 and executed. In this case, another computer connected to the network may rewrite the program stored in HDD 115 of MFP 100, or may additionally write a new program. Further, MFP 100 may download the program from another computer connected to the network and store the program in HDD 115. The program referred to here includes not only a program directly executable by the multi-core processor 111, but also a source program, a compressed program, an encrypted program, and the like.

  The operation panel 160 includes a display unit 161 and an operation unit 163. The display unit 161 is, for example, a liquid crystal display device (LCD), and displays an instruction menu for the user, information regarding acquired image data, and the like. The operation unit 163 includes a touch panel 165 and a hard key unit 167. The touch panel 165 is of a capacitance type. Note that the touch panel 165 is not limited to the electrostatic capacitance method, and other methods such as a resistance film method, a surface acoustic wave method, an infrared method, and an electromagnetic induction method can be used. The hard key unit 167 includes a plurality of hard keys. The hard key is, for example, a contact switch.

  FIG. 3 is a diagram showing an example of a configuration of a multi-core processor included in the MFP according to the present embodiment. With reference to FIG. 3, the multi-core processor 111 includes a first processor core 51, a first cache memory 53 dedicated to the first processor core 51, a second processor core 55, and a second processor core 55 dedicated to the second processor core 55. 2 cache memory 57. The first cache memory 53 and the second cache memory 57 are connected to the RAM 114, and the first processor core 51 and the second processor core 55 share the RAM 114.

  In the multi-core processor 111, each of the first processor core 51 and the second processor core 55 can execute a program, so that the program can be executed in parallel. An operating system (hereinafter referred to as “OS”) executed by the multi-core processor 111 allocates a thread to either the first processor core 51 or the second processor core 55. A thread is a process defined by a part of a program. The OS executed by the multi-core processor 111 generally assigns each of a plurality of threads for processes that do not depend on each other to either the first processor core 51 or the second processor core 55. When one or more threads are assigned to the first processor core 51 and one or more threads are assigned to the second processor core 55, a plurality of threads are executed in parallel.

  The load of each of the first processor core 51 and the second processor core 55 depends on the processing executed by one or more threads assigned to the first processor core 51 and the second processor core 55. Therefore, the respective loads of the first processor core 51 and the second processor core 55 are different due to the difference between the thread assigned to the first processor core 51 and the thread assigned to the second processor core 55. Further, the frequency and cache hit rate of threads assigned to the first processor core 51 accessing the first cache memory 53, and the frequency and cache of threads assigned to the second processor core 55 accessing the second cache memory 57. The hit rate is often different. Therefore, the OS executed by the multi-core processor 111 changes the thread allocation in order to level the load of the first processor core 51 and the load of the second processor core 55.

  FIG. 4 is a diagram showing an example of functions of the multicore processor included in the MFP according to the present embodiment. The function shown in FIG. 4 is realized by one of the first processor core 51 and the second processor core 55 included in the multi-core processor 111 executing the load balancing program stored in the ROM 113, the HDD 115 or the CD-ROM 118. This is a function realized by 111. Referring to FIG. 4, the multi-core processor 111 includes a variable thread determination unit 11, a processing target thread determination unit 13, a first prediction unit 15, a candidate core determination unit 17, a second prediction unit 19, and a determination unit. 21, an allocation changing unit 23, and an acquisition unit 25 are included.

  The variable thread determination unit 11 determines a variable thread from the threads assigned to the first processor core 51 and the second processor core 55, respectively. The variable thread is a thread that executes a program that defines a process for converting image data, among threads executed by either the first processor core 51 or the second processor core 55. The process of converting the image data includes a process of repeating a predetermined process a plurality of times. Processing other than variable threads is called fixed threads. The variable thread determination unit 11 outputs the thread identification information for identifying the determined variable thread to the processing target thread determination unit 13. When determining a plurality of variable threads, the variable thread determining unit 11 outputs a plurality of thread identification information for identifying each of the plurality of variable threads to the processing target thread determining unit 13.

  The processing target thread determining unit 13 determines a processing target variable thread from among the one or more variable threads corresponding to the one or more thread identification information input from the variable thread determining unit 11. The variable threads have priorities set in advance, and the processing target thread determination unit 13 determines the variable thread having the highest priority among the one or more variable threads as the processing target thread. After the processing target thread determination unit 13 determines the processing target thread, the determination result is input from the determination unit 21 described later. When the determination result indicating that the allocation is not changed is input from the determination unit 21, the processing target thread determination unit 13 includes one or more variables corresponding to the one or more thread identification information input from the variable thread determination unit 11. Among the threads, the variable thread having the second highest priority next to the priority of the variable thread previously determined as the processing target thread is determined as the processing target thread. The processing target thread determination unit 13 outputs the thread identification information of the variable thread determined as the processing target thread to the first prediction unit 15 and the candidate core determination unit 17 in response to the determination of the processing target thread.

  The acquisition unit 25 acquires the states of the first processor core 51 and the second processor core 55, respectively. When acquiring the states of the first processor core 51 and the second processor core 55, the acquisition unit 25 outputs the acquired states to the first prediction unit 15 and the second prediction unit 19. The acquisition unit 25 includes a capability information acquisition unit 31, a hit ratio acquisition unit 33, and an occupancy ratio acquisition unit 35.

  The capability information acquisition unit 31 acquires capability information of each of the first processor core 51 and the second processor core 55. The capability information of each of the first processor core 51 and the second processor core 55 is information indicating the calculation speed. The information indicating the calculation speed is, for example, the clock frequency.

  The hit rate acquisition unit 33 acquires the cache hit rate of each of the first processor core 51 and the second processor core 55. The cache hit rate is the rate at which the data to be read is stored in the cache memory. The hit rate acquisition unit 33 acquires the first cache hit rate for the first processor core 51 and the second cache hit rate for the second processor core 55.

  The occupation rate acquisition unit 35 acquires the occupation rates of the first processor core 51 and the second processor core 55, respectively. The timing at which the occupancy rate acquisition unit 35 acquires the occupancy rate is the same as the timing at which the hit rate acquisition unit 33 acquires the cache hit rate. The occupancy rate is the ratio of the thread processing time to the entire processing time. The occupancy rate acquisition unit 35 acquires the occupancy rate for each of the one or more threads assigned to the first processor core 51 with respect to the first processor core 51, and assigns the occupancy rate to the first processor core 51 for the first processor core 51. The occupancy rate is acquired for each thread of 1 or more.

  In the first prediction unit 15, the thread identification information of the processing target thread is input from the processing target thread determination unit 13, and the states of the first processor core 51 and the second processor core 55 are input from the acquisition unit 25. The first prediction unit 15 identifies one of the first processor core 51 and the second processor core 55 to which the processing target thread is assigned.

  Here, a case where the processing target thread is assigned to the first processor core 51 will be described as an example. In this case, the first prediction unit 15 identifies the first processor core 51 that executes the processing target thread. The first prediction unit 15 predicts the first processing speed at which the first processor core 51 executes the processing target thread based on the cache hit rate of the first processor core 51 and the occupation rate of the processing target thread. Specifically, the first predicting unit 15 predicts the first processing speed by referring to predetermined capacity definition data for the capacity information of the first processor core 51. The capacity definition data defines an occupancy rate and a processing time for processing unit data for each of a plurality of cache hit rates.

  FIG. 5 is a diagram showing an example of the ability definition data. The capability definition data defines the relationship between the processing time for processing unit data and the occupancy rate for each of a plurality of cache hit rates. In FIG. 5, the horizontal axis represents the CPU occupancy rate, the vertical axis represents the processing time, and the unit data is 1 GByte data. The capacity definition data 201 corresponding to a cache hit rate of 0%, the capacity definition data 203 at a cache hit rate of 40%, and the capacity definition data 205 at a cache hit rate of 80% are shown. As shown in FIG. 5, the higher the cache hit rate, the shorter the processing time, and the higher the CPU occupancy rate, the shorter the processing time.

  Returning to FIG. 4, the first prediction unit 15 stores in advance capacity definition data corresponding to the capacity information of the first processor core 51, and based on the capacity definition data, a cache hit of the first processor core 51. The first processing speed is predicted based on the rate and the occupation rate of the processing target thread, and a pair of core identification information for identifying the first processor core 51 and the first processing speed is output to the determination unit 21. Specifically, the first predicting unit 15 refers to the capability definition data corresponding to the capability information of the first processor core 51, and in the capability definition data corresponding to the cache hit rate of the first processor core 51, the processing target A value obtained by dividing the data amount of the unit data by the processing time corresponding to the thread occupancy is the first processing speed. For example, if the cache hit rate is 80% and the occupancy rate of the processing target thread is 20%, the processing time for processing the unit data is 500 μs, so the first processing speed is determined to be 2 Mbyte / μs. If the cache hit rate is 40% and the occupancy rate of the processing target thread is 40%, the processing time for processing the unit data is 500 μs, so the first processing speed is determined to be 2 Mbyte / μs. If the cache hit rate is 0% and the processing target thread occupancy rate is 75%, the processing time for processing unit data is 500 μs, so the first processing speed is determined to be 2 Mbyte / μs.

  In response to the thread identification information of the processing target thread input from the processing target thread determination unit 13, the candidate core determination unit 17 determines a processor core different from the processor core to which the processing target thread is assigned as a candidate core. To do. Here, since the processing target thread is assigned to the first processor core 51, the candidate core determination unit 17 determines the second processor core as the candidate core. The candidate core determination unit 17 outputs the core identification information for identifying the second processor core determined as the candidate core and the thread identification information of the processing target thread to the second prediction unit 19. When the multi-core processor 111 has three or more processor cores, the candidate core determination unit 17 determines each of two or more processor cores different from the processor core to which the processing target thread is assigned among the three or more processor cores. Is determined as a candidate core. The candidate core determination unit 17 outputs to the second prediction unit 19 two or more pieces of core identification information for identifying each of the two or more processor cores determined as candidate cores and the thread identification information of the thread to be processed.

  The second prediction unit 19 receives the core identification information of the candidate core and the thread identification information of the processing target thread from the candidate core determination unit 17. The second predicting unit 19 predicts the second processing speed when the candidate core executes the processing target thread with the cache hit rate set to zero, and determines the set of the core identification information of the candidate core and the second processing speed. Output to. Here, the core identification information of the second processor core 55 is input. In this case, the second prediction unit 19 predicts the second processing speed when the second processor core 55 executes the target thread with the cache hit rate of 0%. Specifically, the second predicting unit 19 calculates the remaining capacity of the second processor core 55 based on the occupancy rates of all threads assigned to the second processor core 55. A value obtained by subtracting the sum of the occupancy rates of all the threads assigned to the second processor core 55 from 100% is the remaining capacity of the second processor core 55. The second predicting unit 19 refers to capacity definition data that is predetermined for the capacity information of the second processor core 55, and assumes that the processing target thread occupies all of the calculated remaining capacity of the second processor core 55. Then, the second processing speed is predicted. The capacity definition data defines an occupancy rate and a processing time for processing unit data for each of a plurality of cache hit rates. The second predicting unit 19 refers to the capability definition data corresponding to the cache hit rate of 0%, sets the available capacity as the occupancy rate, and divides the data amount of the unit data by the processing time corresponding to the occupancy rate. The second processing speed is determined. The second prediction unit 19 outputs the set of the core identification information of the second processor core and the second processing speed to the determination unit 21. When the plurality of core identification information is input from the candidate core determination unit 17, the second prediction unit 19 predicts the second processing speed for each of the plurality of processor cores identified by the plurality of core identification information, The processor core having the maximum second processing speed is specified, and the set of the core identification information of the specified processor core and the second processing speed is output to the determination unit 21.

  The determination unit 21 receives the set of the core identification information of the processor core to which the processing target thread is allocated and the first processing speed from the first prediction unit 15, and the second prediction unit 19 receives the core identification information of the candidate core and the first processing speed. A pair of two processing speeds is input. The determination unit 21 compares the first processing speed with the second processing speed, determines whether to change the allocation of the processing target thread, and outputs the determination result to the allocation changing unit 23. The determination unit 21 determines at predetermined time intervals whether to change the allocation of the processing target thread. The determination unit 21 determines to change the allocation of the processing target thread if the second processing speed is higher than the first processing speed. However, if the second processing time is less than or equal to the first processing time, the processing target thread is allocated. Judge not to change. The judgment result indicates whether or not to change the allocation. When determining to change the allocation, the determination unit 21 outputs the core identification information of the candidate core to the allocation changing unit 23 in addition to the determination result.

  Here, the determination unit 21 receives the set of the core identification information of the first processor core 51 to which the processing target thread is assigned and the first processing speed from the first prediction unit 15, and the second prediction unit 19 determines the candidate core. The set of the core identification information of the second processor core 55 and the second processing speed determined by the above is input. If the second processing speed is higher than the first processing speed, the judgment unit 21 judges that the allocation of the thread to be processed is changed, and the judgment result indicating that the allocation is changed and the core identification information of the second processor core 55 are displayed. It is output to the allocation changing unit 23. If the second processing speed is equal to or lower than the first processing speed, the determination unit 21 determines that the allocation of the processing target thread is not changed, and outputs a determination result indicating that the allocation is not changed to the processing target thread determination unit 13.

  When the determination result indicating that the allocation is to be changed is input from the determination unit 21, the allocation change unit 23 inputs the processing target thread input from the processing target thread determination unit 13 together with the determination result from the determination unit 21. It is assigned to the second processor core specified by the core identification information. As a result, the variable thread that is the processing target thread that has been executed by the first processor core 51 is executed by the second processor core 55.

  The allocation changing unit 23 includes a processing unit determining unit 27. The processing unit determination unit 27 determines a processing unit when the processing target thread divides the image data into a plurality of processing unit portions and processes the image data. The allocation changing unit 23 changes the allocation in response to the completion of any one of the processing unit portions. For example, when the image data includes a plurality of pages, the processing unit determination unit 27 determines the portion of each of the plurality of pages as the processing unit portion. In this case, the allocation changing unit 23 assigns the second processing target thread to the second processing target thread when the processing target thread allocated to the first processor core 51 completes processing of any one of the plurality of pages included in the image data. Assign to processor core.

  Further, when the image data includes a plurality of lines, the processing unit determination unit 27 determines the portions of each of the plurality of lines as the processing unit portion. In this case, the allocation changing unit 23 assigns the second processing target thread to the second processing target thread when the processing target thread allocated to the first processor core 51 completes processing of any one of the plurality of rows included in the image data. Assigned to the processor core.

  When the image data includes a plurality of attribute-based data having different attributes, the processing unit determination unit 27 determines the plurality of attribute-based data as the processing unit portion. For example, when the image data includes a character area in which characters are represented, a line drawing area in which graphics are represented, and a photo area in which photographs are represented, the image data includes attribute-based data consisting only of character areas and graphics. Attribute-based data consisting of and attribute-based data consisting of only photographs. When the image data is color, the image data includes attribute-based data that includes only red, attribute-based data that includes only green, and attribute-based data that includes only blue. In this case, the allocation changing unit 23 performs processing in response to the processing target thread allocated to the first processor core 51 completing processing of any one of the attribute-based data of the plurality of attribute-based data included in the image data. The target thread is assigned to the second processor core.

  In addition, when the target thread executes the encoding process of encoding the image data, the processing unit determination unit 27 determines the unit part to be encoded as the processing unit part. In this case, when the processing target thread assigned to the first processor core 51 performs the encoding process on the image data, the assignment changing unit 23 selects one of the plurality of unit parts to be encoded included in the image data. In response to the completion of the processing of the unit portion, the processing target thread is assigned to the second processor core.

<Specific example>
Next, a specific example will be described when the capabilities of the first processor core 51 and the second processor core 55 are the same.

  FIG. 6 is a first diagram for explaining the movement of the processing target thread. Referring to FIG. 6, when the cache hit rate of the first processor core 51 is 80% and the occupancy rate of the processing target thread is 10%, refer to the capacity definition data 205 with the cache hit rate of 80%. Then, since the processing time corresponding to the occupancy rate of 10% is 1000 μs, the first processing speed is estimated to be 1 Mbyte / μs. When the cache hit rate of the second processor core 55 is 0% and the capacity definition data 201 with a cache hit rate of 0% is referred to, the occupancy rate corresponding to the processing time of 1000 μs is 40%. Therefore, when the total occupation rate of all threads assigned to the second processor core 55 is smaller than 60%, the second processing speed is higher than 1 Mbyte / μs. In other words, if the reserve capacity of the second processor core 55 is greater than 40%, the second processing speed will be greater than 1 Mbyte / μs. Therefore, it is predicted that the thread to be processed is terminated earlier when the thread to be processed is executed by the second processor core 55 than when it is continuously executed by the first processor core 51.

  FIG. 7 is a second diagram for explaining the movement of the processing target thread. Referring to FIG. 7, when the cache hit rate of the first processor core 51 is 40% and the occupancy rate of the processing target thread is 20%, refer to the capacity definition data 203 having the cache hit rate of 40%. Then, since the processing time corresponding to the occupation rate of 20% is 1000 μs, the first processing speed is estimated to be 1 Mbyte / μs. When the cache hit rate of the second processor core 55 is 0% and the capacity definition data 201 with a cache hit rate of 0% is referred to, the occupancy rate corresponding to the processing time of 1000 μs is 40%. Therefore, when the total occupation rate of all threads assigned to the second processor core 55 is smaller than 60%, the second processing speed is higher than 1 Mbyte / μs. In other words, if the reserve capacity of the second processor core 55 is greater than 40%, the second processing speed will be greater than 1 Mbyte / μs. Therefore, it is predicted that the thread to be processed is terminated earlier when the thread to be processed is executed by the second processor core 55 than when it is continuously executed by the first processor core 51.

  FIG. 8 is a flowchart showing an example of the flow of load distribution processing. In the load distribution process, the first processor core 51 or the second processor core 55 included in the multicore processor 111 executes the load distribution program stored in the ROM 113, the HDD 115, or the CD-ROM 118, so that the multicore processor 111 executes the load distribution process. This is the process to be executed. With reference to FIG. 8, the multi-core processor 111 determines whether a predetermined time has passed (step S01). The predetermined time is an elapsed time after the processing of step S01 is executed, and is an elapsed time after the execution of the load balancing processing and an elapsed time after the end of the load balancing processing. The predetermined time can be set arbitrarily. The process waits until a predetermined time elapses (NO in step S01), and if the predetermined time elapses (YES in step S02), the process proceeds to step S02.

  In step S02, a variable thread is determined and the process proceeds to step S03. A variable thread is determined as one or more threads that are executing in the first processor core 51 and the second processor core 55, respectively, and that execute processing for converting image data. In step S03, the variable thread having the highest priority is set as the processing target thread from the one or more variable threads determined in step S02. When one variable thread is determined in step S02, the variable thread is set as the processing target thread. Here, a case where a variable thread assigned to the first processor core 51 is set as a processing target thread will be described as an example.

  In the next step S04, the processor core to which the processing target thread is assigned is determined as the target core, and the process proceeds to step S05. If the processing target thread is assigned to the first processor core 51, the first processor core 51 is determined as the target core, and if the processing target thread is assigned to the second processor core 55, the second processor core 55 is set as the target core. To decide. In step S05, the state information of each of the first processor core 51 and the second processor core 55 is acquired. Specifically, the capability information and cache hit rate of each of the first processor core 51 and the second processor core 55, the occupancy rate of each of the one or more threads assigned to the first processor core 51, and the second processor core 55 are assigned. The occupancy rate of each of the one or more threads thus obtained is acquired.

  In step S06, the first processing time is predicted. A first processing speed at which the processing target thread is executed by the first processor core 51 to which the processing target thread is assigned is predicted. Assuming that the occupancy rate acquired in step S05 for the thread to be processed continues in the first processor core 51, it corresponds to the cache rate acquired in step S05 among the capability definition data corresponding to the first processor core 51. The first processing time is set to a value obtained by dividing the data amount of the unit data by the processing time corresponding to the occupation rate of the processing target thread.

  In the next step S07, a processor core other than the target core is selected, and the process proceeds to step S08. Here, since only the second processor core 55 exists in addition to the first processor core 51 which is the target core, the second processor core 55 is selected. If there are three or more processor cores, one is selected from two or more processor cores other than the target core.

  In the next step S08, the second processing time is predicted, and the process proceeds to step S09. The second processor core 55 selected in step S07 sets the cache hit rate to 0% and predicts the second processing speed for executing the variable thread set as the processing target thread in step S03. Specifically, the spare capacity of the second processor core 55 is calculated based on the occupancy rates of all the threads allocated to the second processor core 55, which are acquired in step S05. A value obtained by subtracting the sum of the occupancy rates of all the threads assigned to the second processor core 55 from 100% is the remaining capacity of the second processor core 55. Then, of the capability definition data predetermined for the capability information of the second processor core 55, the capability definition data corresponding to the cache hit rate of 0% is referred to, and the processing target thread is the second processor core 55. Assuming that all of the spare capacity is occupied in the processing time of the second processor core 55, the spare capacity is taken as the occupancy rate, and the value obtained by dividing the data amount of the unit data by the processing time corresponding to the occupancy rate is determined as the second processing speed. To do.

  In the next step S09, it is determined whether or not there is a processor core not selected in step S07. If there is an unselected processor core, the process returns to step S07, but if not, the process proceeds to step S10. If the process proceeds to step S10 and the number of processor cores is three or more, the second processing time is determined for each of the two or more processor cores other than the target core.

  In step S10, the processor core having the maximum second processing speed is set as the candidate core, and the process proceeds to step S11. In step S11, the first processing speed predicted in step S06 is compared with the second processing speed predicted for the processor core set as the candidate core in step S10. If the second processing speed is higher than the first processing speed, the process proceeds to step S12. If not, the process proceeds to step S15. In step S15, it is determined whether or not there is an unselected variable tax. Among the variable threads determined in step S02, it is determined whether or not there is a variable thread that is not set as the processing target thread in step S03. If there is an unselected variable thread, the process returns to step S03, but if not, the process returns to step S01.

  In step S12, the processing unit is determined. The processing unit is determined based on the processing executed by the variable thread set as the processing target thread in step S03 or the image data to be processed by the variable thread. When the image data includes a plurality of pages, the portion of each of the plurality of pages is determined as the processing unit portion. In addition, when the image data includes a plurality of lines, each of the plurality of lines is determined as a processing unit part. When the image data includes a plurality of attribute-based data having different attributes, the plurality of attribute-based data are determined as the processing unit portion. When the process executed by the variable thread is a coding process for coding image data, the unit part to be coded is determined as the processing unit part.

  In step S13, it is determined whether or not the processing of the processing unit determined in step S12 is completed. In the processing target thread that is being executed in the first processor core 51, the processing target portion is placed in a standby state until the processing of the processing unit portion is completed, and when the processing of the processing unit portion is completed, the process proceeds to step S14.

  In step S14, the variable thread set as the processing target thread in step S03 is assigned to the processor core set as the candidate core in step S10, and the process returns to step S01. Here, the variable thread executed in the first processor core 51 is assigned to the second processor core 55. As a result, the variable thread that was being executed by the first processor core 51 is executed by the second processor core 55. Therefore, the load of the first processor core 51 can be distributed to the second processor core 55.

  As described above, the MFP 100 according to the present embodiment functions as an image processing apparatus, and the first processor core 51 operates based on the cache hit rate acquired for the first processor core 51 to which the processing target thread is assigned. The first processing speed for executing the processing target thread is predicted, and the second processing speed when the second processor core 55 determined as the candidate core executes the processing target thread with the cache hit rate set to zero, The first processing speed is compared with the second processing speed, and when the second processing speed is higher than the first processing speed, the allocation of the thread to be processed is changed from the first processor core 51 to the second processor core 55. Therefore, since the first processing speed before moving the target thread and the second processing speed after moving the target thread are compared, it is predicted that the processing speed for processing the target thread will be high. The target thread is moved to. As a result, the load on a plurality of processor cores can be distributed while shortening the processing time after the thread to be moved is moved.

  Further, one or more threads executed by the second processor core 55 are predicted by predicting the first processing speed based on the occupation rate of the processing target thread in the first processor core 51 and the cache hit rate of the first processor core 51. Since the second processing speed is predicted based on the remaining capacity of the second processor core 55 calculated from the respective occupancy rates, it is possible to accurately predict the processing speed before and after moving the processing target thread.

  Further, the first processing speed is predicted by referring to the capacity definition data corresponding to the processing capacity of the first processor core 51, and the second processing core is referred to by the capacity definition data corresponding to the processing capacity of the second processor core 55. Since the processing speed is predicted, even when the processing capacities of the first processor core 51 and the second processor core 55 are different, the processing time after the movement of the thread to be moved is shortened and the loads of the plurality of processor cores are distributed. be able to.

  Further, since it is determined at predetermined time intervals whether or not to change the allocation of the threads to be processed, it is possible to distribute the load on the plurality of processor cores at predetermined time intervals.

  In addition, when the image data to be processed by the processing target thread is divided into a plurality of processing unit parts for processing, the processing target threads are allocated until the processing of any one of the plurality of processing unit parts is completed. Since it is not changed, it is possible to prevent the same processing from being executed repeatedly before and after the movement.

  In addition, a thread that executes a program that defines a process for converting image data is determined as a variable thread, and one of one or more variable threads is determined as a target thread. Therefore, a thread that executes a process for repeatedly executing the same process. Can be determined as the target thread. Moreover, the first processing speed and the second processing speed before and after the movement can be accurately predicted.

  Further, when there are a plurality of variable threads, the target threads are determined in descending order of priority, so that the variable threads with high priority can be terminated early.

  In the above-described embodiment, the MFP 100 has been described as an example of the image processing apparatus. However, a load balancing method that causes the MFP 100 to execute the load balancing processing illustrated in FIG. The invention can be understood as a load balancing program to be executed by the multi-core processor 111 included in the MFP 100.

  The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

<Appendix>
(1) The image processing apparatus according to claim 5, wherein, when the image data includes a plurality of pages, the allocation changing unit determines a portion of each of the plurality of pages as a processing unit portion.
(2) The image processing device according to claim 5 or (1), wherein when the image data includes a plurality of lines, the allocation changing unit determines each of the plurality of lines as a processing unit part.
(3) When the image data includes a plurality of attribute-based data having different attributes, the allocation changing unit determines the plurality of attribute-based data as a processing unit portion. The image processing device according to any one of 1) to 5).
(4) The image according to claim 5, wherein when the target thread executes an encoding process for encoding image data, the allocation changing unit determines a unit part to be encoded as a processing unit part. Processing equipment.

  100 MFP, 110 main circuit, 111 multi-core processor, 112 communication I / F unit, 113 ROM, 114 RAM, 115 HDD, 116 facsimile unit, 117 external storage device, 118 CD-ROM, 120 automatic document feeder, 130 document reading Unit, 140 image forming unit, 150 paper feeding unit, 160 operation panel, 161 display unit, 163 operation unit, 165 touch panel, 167 hard key unit, 11 variable thread determination unit, 13 processing target thread determination unit, 15 first prediction unit , 17 candidate core determination unit, 19 second prediction unit, 21 determination unit, 23 allocation change unit, 25 acquisition unit, 27 processing unit determination unit, 31 capability information acquisition unit, 33 hit ratio acquisition unit, 35 occupancy ratio acquisition unit, 51 first processor core, 53 first cache memory, 55 2 processor cores, 57 second cache memory.

Claims (9)

Multiple processor cores,
A plurality of cache memories respectively corresponding to the plurality of processor cores,
A target thread determining unit that determines one of the one or more threads assigned to the target core among the plurality of processor cores as the target thread;
Hit ratio acquisition means for acquiring the cache hit ratio of each of the plurality of processor cores,
First prediction means for predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core by the hit rate acquisition means;
Second prediction means for predicting a second processing speed when a candidate core different from the target core among the plurality of processor cores executes the target thread with a cache hit rate of zero;
Determining means for determining whether or not to change the allocation of the target thread from the target core to the candidate core by comparing the first processing speed and the second processing speed;
An image processing apparatus comprising: an assignment changing unit that changes the assignment of the target thread from the target core to the candidate core based on the determination result by the determination unit. For each of one or more threads executed by each of the plurality of processor cores, an occupancy rate acquisition unit for acquiring an occupancy rate, which is a ratio of the entire thread processing time, is further provided.
The first predicting unit is configured to perform the first processing speed based on an occupancy ratio of the target thread acquired by the occupancy ratio acquiring unit and a cache hit ratio of the target core acquired by the hit ratio acquiring unit. Predict
The second prediction unit predicts the second processing speed based on the remaining capacity of the candidate core calculated from the occupancy of each of the one or more threads executed by the candidate core acquired by the occupancy acquisition unit. The image processing device according to claim 1. Further comprising capability information acquisition means for acquiring the processing capabilities of the plurality of processor cores,
The first predicting means predicts the first processing speed further based on the processing capacity of the target core ;
The image processing apparatus according to claim 2, wherein the second predicting unit predicts the second processing speed further based on the processing capacity of the candidate core.   The image processing apparatus according to claim 1, wherein the determination unit determines whether or not to change the allocation of the target thread from the target core to the candidate core at predetermined time intervals.   The allocation changing means, when dividing the image data to be processed by the target thread into a plurality of processing unit parts for processing, assigns the allocation of the target thread determined to be changed by the determining means to the target thread. The image processing apparatus according to claim 1, wherein the thread changes in response to completion of processing of any one of the plurality of processing unit parts. A variable thread determining means for determining a thread one of the plurality of processor cores to execute a program that defines the processing for converting image data into variable thread, further comprising,
The image processing apparatus according to claim 1, wherein the target thread determination unit determines one of the one or more variable threads determined by the variable thread determination unit as a target thread.   7. The image processing apparatus according to claim 6, wherein the target thread determining unit determines a target thread in descending order of priority from the plurality of variable threads determined by the variable thread determining unit. A load balancing method executed by an image processing device, comprising:
The image processing device includes a plurality of processor cores,
A plurality of cache memories respectively corresponding to the plurality of processor cores,
A target thread determination step of determining one of the one or more threads allocated to the target core among the plurality of processor cores as the target thread;
A hit ratio acquisition step of acquiring a cache hit ratio of each of the plurality of processor cores,
A first prediction step of predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step;
A second prediction step of predicting a second processing speed when a candidate core different from the target core among the plurality of processor cores executes the target thread with a cache hit rate of zero;
A determination step of determining whether or not to change the allocation of the target thread from the target core to the candidate core by comparing the first processing speed and the second processing speed;
A load balancing method comprising: an assignment changing step of changing the assignment of the target thread from the target core to the candidate core based on the determination result in the determination step. A load balancing program executed by a multi-core processor that controls an image processing apparatus,
The multi-core processor includes a plurality of processor cores,
A plurality of cache memories respectively corresponding to the plurality of processor cores,
A target thread determination step of determining one of the one or more threads allocated to the target core among the plurality of processor cores as the target thread;
A hit ratio acquisition step of acquiring a cache hit ratio of each of the plurality of processor cores,
A first prediction step of predicting a first processing speed at which the target core executes the target thread based on the cache hit rate acquired for the target core in the hit rate acquisition step;
A second prediction step of predicting a second processing speed when a candidate core different from the target core among the plurality of processor cores executes the target thread with a cache hit rate of zero;
A determination step of determining whether or not to change the allocation of the target thread from the target core to the candidate core by comparing the first processing speed and the second processing speed;
A load balancing program that causes the multi-core processor to execute an assignment changing step of changing the assignment of the target thread from the target core to the candidate core based on the determination result in the determination step.

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