JP6688038B2 - Solid-state imaging device and imaging device - Google Patents

Description

  The present invention relates to a solid-state image pickup device and an image pickup apparatus that obtain an image signal from an image pickup device such as an image sensor and remove noise from the obtained image signal.

  In order to reduce the size of the image pickup device, the drive unit of the image pickup device, such as an autofocus lens drive mechanism and a camera shake correction function for moving the position of the image sensor, should be placed near the image sensor for image signal acquisition. Is increasing. In this case, an electric noise source (external noise) generated when the drive unit operates is likely to be mixed as noise in the image signal acquired from the image sensor.

  Further, conventionally, a correlated double sampling circuit (CDS circuit) has been known as a method for removing noise generated in an image sensor. For example, Patent Document 1 discloses a technique of reducing quantization noise at the time of AD conversion that occurs in a random cycle by AD-converting a reset level and a signal level a plurality of times by a CDS circuit and averaging each. Proposed.

JP, 2009-296423, A

  When the image sensor and the driving unit in the image pickup apparatus are close to each other, it becomes difficult to electrically shield the signal line of the image signal output from the image sensor from noise. It is conceivable to remove the external noise by the CDS circuit as disclosed in the above-mentioned Patent Document 1.

  In an image sensor, when an external noise is removed by using a CDS circuit, for example, when the reset signal level and the pixel signal level are AD-converted twice, respectively, the CDS frequency (reset signal acquisition timing and pixel signal acquisition timing Is defined as a CDS frequency) (the number of combinations of sampling timing time differences becomes four in a series of CDS operations). Therefore, external noise radiated from the drive unit and electronic components around the image sensor cannot be canceled well. That is, it is difficult to cancel the external noise because the noise frequency region that can be suppressed by the CDS circuit does not necessarily match the frequency region of the external noise.

  Under such circumstances, by devising the read-out control means (or signal processing means) of the image signal acquired from the image sensor, the image signal noise peculiar to the conventional image sensor is removed (random noise removal by CDS processing. , And quantization noise removal by digital CDS processing), and an object of the invention is to provide means for removing the influence of external noise.

  The present invention has been made in view of such circumstances, and even when external noise is generated from a driving unit or electronic components arranged around the image sensor, the noise is mixed from the image signal from the image sensor. It is an object of the present invention to provide a solid-state imaging device and an imaging device capable of removing the external noise.

In order to achieve the above object, a solid-state imaging device according to the first invention has a reference signal generation unit that generates a reference signal based on a ramp signal that changes at a predetermined time change rate, a comparison unit, and a counter unit, An AD conversion unit that acquires digital data to be processed based on output data of the counter unit, and the comparison unit includes the reference signal supplied from the reference signal generation unit and the solid-state imaging device. output at pixel circuit is compared with the second processing target signal is a first processed signal and the analog signal at the time of the video signal acquisition is an analog signal at the time of reset, the counter unit, for AD conversion Of the first processing target signal, the solid-state imaging device further performs the counting operation based on the comparison result of the comparison unit. Definitive first AD conversion processing and the second processing the second predetermined number of times for the AD conversion processing in the target signal (N times: N ≧ 2) is carried out repeatedly a plurality of times, the first digital A drive control unit that controls the reference signal generation unit and the AD conversion unit so as to execute an integration process and a second digital integration process; and a first control unit obtained by executing the first digital integration process. and digital data, based on the second digital data obtained by executing the second digital integration process, comprising: a CDS processing unit which performs correlated double sampling operation, and the AD conversion unit, The time from the timing of starting the first AD conversion process performed for the first time to the timing of starting the second AD conversion process performed for the first time is set to Tcds1, and the number of times from the second time onward is set to N One A timing for starting the D conversion processing, the time until a timing for starting the second AD conversion processing performed in N th When TcdsN, TcdsN = Tcds1 × M ( M is an integer of 2 or more) in the composed relation time The first AD conversion processing and the second AD conversion processing are performed.

  A solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect of the present invention, further including noise frequency detection means for detecting a frequency of external noise mixed in the first processing target signal and the second processing target signal. The AD conversion section has a timing of starting the first AD conversion process performed for the first time and a second time of the first AD conversion process corresponding to the noise frequency detected by the noise frequency detection means. The time (Tcds1) until the timing of starting the AD conversion process is set.

A solid-state image sensor according to a third aspect of the present invention includes a reference signal generation unit that generates a reference signal based on a ramp signal that changes at a predetermined time rate of change, a comparison unit, and a counter unit. And an AD conversion unit that acquires digital data to be processed based on the above, and the comparison unit outputs the reference signal supplied from the reference signal generation unit and the pixel circuit in the solid-state imaging device. , Comparing the first processing target signal, which is an analog signal at the time of reset, and the second processing target signal, which is an analog signal at the time of acquiring a video signal, and the counter unit receives the supply of the count clock for AD conversion. performs a count operation based on the comparison result of the comparison unit, the solid-state imaging device, further, for the processed signal, the first AD converter in the first processing signal And a second digital conversion process for the second signal to be processed, the first digital process being performed a plurality of times, which is a predetermined number of times (N times: N ≧ 2) for at least one of them. A drive control unit that controls the reference signal generation unit and the AD conversion unit so as to execute an integration process and a second digital integration process; and a first control unit obtained by executing the first digital integration process. and digital data, based on the second digital data obtained by executing the second digital integration process, comprising: a CDS processing unit which performs correlated double sampling operation, and the AD conversion unit, The first AD conversion process is repeatedly performed N times (N is a plurality of times), and the second AD conversion process is performed once. When the first AD conversion process is started for the first time, Do the first time The timing time until the second AD conversion process is started is set to Tcds1 and the second and subsequent times are set to N, and the first AD conversion process is started at the Nth time and the second AD conversion process is performed at the first time. When the time until the timing to start is TcdsN, the first AD conversion processing and the second AD conversion processing are performed at a time of a relationship of TcdsN = Tcds1 / M (M is an integer of 2 or more ).

A solid-state image sensor according to a fourth aspect of the present invention includes a reference signal generation unit that generates a reference signal based on a ramp signal that changes at a predetermined time rate of change, a comparison unit, and a counter unit. And an AD conversion unit that acquires digital data to be processed based on the above, and the comparison unit outputs the reference signal supplied from the reference signal generation unit and the pixel circuit in the solid-state imaging device. , Comparing the first processing target signal, which is an analog signal at the time of reset, and the second processing target signal, which is an analog signal at the time of acquiring a video signal, and the counter unit receives the supply of the count clock for AD conversion. performs a count operation based on the comparison result of the comparison unit, the solid-state imaging device, further, for the processed signal, the first AD converter in the first processing signal And a second digital conversion process for the second signal to be processed, the first digital process being performed a plurality of times, which is a predetermined number of times (N times: N ≧ 2) for at least one of them. A drive control unit that controls the reference signal generation unit and the AD conversion unit so as to execute an integration process and a second digital integration process; and a first control unit obtained by executing the first digital integration process. and digital data, based on the second digital data obtained by executing the second digital integration process, comprising: a CDS processing unit which performs correlated double sampling operation, and the AD conversion unit, The first AD conversion process is performed once, and the second AD conversion process is repeated N times (N is a plurality of times), and the timing of starting the first AD conversion process for the first time and Do the first time The time until the timing of starting the second AD conversion processing is set to Tcds1, and the time for starting the second AD conversion processing performed for the second and subsequent N times and the time for starting the first AD conversion processing performed for the first time. When the time of TcdsN is TcdsN, the first AD conversion processing and the second AD conversion processing are performed in a time period in which TcdsN = Tcds1 × M (M is an integer of 2 or more ).

An image pickup apparatus according to a fifth aspect of the present invention is a solid-state image pickup element according to the first , third, or fourth aspect of the present invention, a drive unit for image pickup, and a driver for supplying a drive voltage to the drive unit. An image pickup apparatus comprising: a circuit; and a control unit that controls a drive voltage with respect to the driver circuit by a PWM-modulated modulation signal, wherein the control unit sets a carrier frequency Fe related to the PWM modulation to (1 / Tcds) × L = Fe (where L is an integer).

A solid-state imaging device according to a sixth aspect of the present invention is the solid-state imaging device according to the third or fourth aspect of the present invention, further comprising external noise mixed in the first processing target signal and the second processing target signal. The AD conversion unit has a noise frequency detection unit that detects a frequency, and the AD conversion unit starts the first AD conversion process performed for the first time in response to the noise frequency detected by the noise frequency detection unit. The time (Tcds1) until the timing of starting the second AD conversion process performed for the first time is set.
An image pickup apparatus according to a seventh aspect of the present invention is a solid-state image pickup element according to the second or sixth aspect of the present invention, a drive section for image pickup, a driver circuit for supplying a drive voltage to the drive section, and the driver. An image pickup apparatus comprising: a control unit that controls a drive voltage by a PWM-modulated modulation signal for a circuit, wherein the control unit operates a carrier frequency related to the PWM modulation by Fe, and the solid-state image pickup device. The noise frequency detection means provided in the above detects the carrier frequency Fe related to the PWM modulation as an external noise frequency, and the AD conversion unit executes the first AD conversion processing and the second AD conversion processing. The time interval is set so as to have a relationship of (1 / Tcds) × L = Fe (where L is an integer).

  According to the present invention, even when external noise is generated from the drive unit or electronic components arranged around the image sensor, the external noise mixed from the image signal from the image sensor can be removed. An image pickup device and an image pickup device can be provided.

FIG. 2 is a block diagram mainly showing an electrical configuration of the camera of the first embodiment of the present invention. It is a block diagram showing composition of an image sensor part concerning a 1st embodiment of the present invention. It is a figure which shows the operation | movement of AD conversion of the image pick-up element part which concerns on 1st Embodiment of this invention. It is a figure which shows the operation | movement of AD conversion when the external noise is mixed in the image pick-up element part which concerns on 1st Embodiment of this invention. It is a figure which shows the operation | movement of AD conversion of the image pick-up element part which concerns on 1st Embodiment of this invention. 6 is a graph showing a relationship between a frequency transfer characteristic by a CDS frequency and an external noise frequency in the image pickup device unit according to the first embodiment of the present invention. It is a figure which shows the operation | movement of AD conversion in the 1st modification of 1st Embodiment of this invention. It is a figure which shows operation | movement of AD conversion in the 2nd modification of 1st Embodiment of this invention. It is a block diagram showing mainly electric composition of a camera concerning a 2nd embodiment of the present invention. It is a figure which shows the external noise detection drive change in 2nd Embodiment of this invention. It is a figure which shows the external noise detection operation of the image sensor part which concerns on 2nd Embodiment of this invention. It is a figure which shows the read-out operation | movement of the pixel signal of the image pick-up element part which concerns on 2nd Embodiment of this invention.

  Hereinafter, preferred embodiments will be described with reference to the drawings using an image pickup apparatus to which the present invention is applied.

In the first embodiment, the image pickup device 1 in the image pickup apparatus 1 converts an analog image signal into a digital signal by a double correlation sampling circuit (CDS circuit). In this CDS circuit, when the first CDS frequency is f_cds1 when AD-converting the reset level and the signal level N times (N is an integer of 2 or more), the CDS frequencies f_cdsN up to the Nth time are
fcdsN = 1 / M x f_cds1 (M is an integer of 1 or more) (1)
The imaging device is operated at the timing.

Next, the frequency f_noise of external noise is
f_noise = L × f_cds1 (L is an integer of 1 or more) (2)
Set the frequency so that

  By setting the CDS frequency according to the external noise of the drive unit and electronic components arranged around the image sensor 1, not only random noise but also external noise of fixed frequency can be reduced.

  FIG. 1 is a block diagram mainly showing the electrical configuration of the image pickup apparatus 1 according to the first embodiment. The image pickup apparatus 1 is a digital camera capable of displaying an image acquired by the image pickup element unit 100 on the display unit 130 and recording the image in the external memory 145 according to a user's operation.

  In the image pickup unit 100 of the image pickup apparatus 1, an image pickup device unit 10, a lens 150, a diaphragm 160, a shutter 170, and a camera shake correction unit 180 are arranged. The lens 150 forms an optical image of a subject, and is moved in the optical axis direction by a lens driving mechanism (not shown) to perform focusing.

  The diaphragm 160 is arranged on the optical axis of the lens 150, and changes the diaphragm value (aperture diameter) to limit the light flux passing from the lens 150 and adjust the exposure amount. The shutter 170 is arranged on the optical axis of the lens 150, and controls exposure and blocking of the subject light flux to the image sensor unit 10 by passing or blocking the light flux from the lens 150. The exposure time can be adjusted by controlling the opening time (shutter speed) of the shutter 170.

  Pixels are two-dimensionally arranged in the image sensor unit 10, and these pixels are photoelectrically converted from the optical image from the lens 150. The photoelectrically converted analog image signals are sequentially read out by the reading operation. The read analog image signal is AD-converted, and is output to the data bus 190 as a digital image signal based on the AD-converted digital value. The detailed configuration of the image sensor unit 10 will be described later with reference to FIG.

  The camera shake correction unit 180 has a camera shake sensor and a camera shake correction mechanism, and prevents camera shake of an optical image of a subject due to camera shake during hand-held shooting. That is, the camera shake sensor detects a movement applied to the image pickup apparatus 1, and the camera shake correction mechanism moves the image pickup element unit 10 so as to cancel the deviation of the optical image based on this movement. In the present embodiment, the camera shake correction unit 180 is of a type that drives the image pickup device unit 10, but the present invention is not limited to this, and the lens 150 is moved in a plane perpendicular to the optical axis to form an optical image. The blurring of the image position may be canceled.

  The data bus 190 is a signal line or a clock line for transmitting / receiving a signal between the blocks in the image pickup apparatus 1 or transmitting / receiving a clock.

  The data bus 190 of the imaging device 1 is connected to the control unit 90, the image processing unit 110, the input interface (input IF) 120, the display unit 130, the internal memory 140, and the external memory 145, in addition to the above-described imaging device unit 10. ing.

  The internal memory 140 is composed of a non-volatile memory such as a flash memory or a volatile memory such as a DRAM (Dynamic Random Access Memory). The internal memory 140 temporarily stores various setting information necessary for camera operation and images in the middle of image processing.

  The image processing unit 110 generates image data from the image signal read from the image sensor unit 10, and performs exposure correction, noise processing, WB on the generated image data or the image data stored in the internal memory 140. Various image processes such as gain correction, edge enhancement, and false color correction are performed. Further, the image processing unit 110 also performs a process (developing process) of converting the image data subjected to the above-described image processing into a recording data format.

  Further, in the present embodiment, the image processing unit 110 is a dedicated image processing processor including an arithmetic circuit that performs image processing arithmetic. However, the present invention is not limited to this configuration, and the image processing operation may be expanded to a general-purpose signal processor such as a digital signal processor (DSP) based on an image processing program.

  The external memory 145 has a recording medium such as an SD card or a CF card, and records the image data developed by the image processing unit 110. The image data recorded in the external memory 145 can be moved to the outside of the imaging device 1.

  The display unit 130 has a rear display unit including a display panel such as a liquid crystal monitor and an organic EL monitor, and an electronic viewfinder (EVF). The display unit 130 displays an image based on the image data processed by the image processing unit 110 for image display and the recorded image data recorded in the external memory 145. Further, a menu image or the like is also displayed based on the data from the control unit 90.

  The input IF 120 includes operation members such as various operation buttons, a touch panel, and the like, and inputs various mode settings and instructions for shooting operations such as shutter release based on operations by the photographer.

  The control unit 90 has a CPU (Central Processing Unit) and its peripheral circuits, and controls the entire imaging device 1 according to a program stored in the internal memory 140. The control unit 90 controls the shutter speed of the shutter 170 and the opening amount of the diaphragm 160 to control the exposure amount of the image pickup device unit 10 at the time of shooting, and also as an image pickup control unit that controls the image pickup timing. Have a function. In addition, a master clock signal, which is a reference timing signal for operation timing, is transmitted to the image sensor unit 10.

  Further, when the image pickup unit 100 has a drive mechanism (focus drive mechanism) for adjusting the focus, the control unit 90 controls the focus drive mechanism to drive the focus position. Further, the control unit 90 controls the diaphragm driving mechanism so that the diaphragm 160 has a predetermined diaphragm opening amount. Further, the opening / closing control of the shutter 170 and the drive control of the camera shake correction unit 180 are performed.

  Next, the internal configuration of the image sensor unit 10 will be described with reference to FIG. In FIG. 2, a part of the connection line of the image pickup device section 10 is omitted, and each section such as the pixel array section 2 is configured by a hardware circuit.

  In the present embodiment, the image sensor unit 10 employs a CMOS image sensor. Although part of the image pickup device section 10 is omitted, the pixel array section 2 in which tens to thousands of unit pixels 20 are two-dimensionally arranged in each row and each column is provided. The unit pixel 20 includes a charge generation unit (for example, a photodiode) and an in-pixel amplifier including a semiconductor element for amplification (for example, a transistor).

  Further, the image pickup device unit 10 includes a column AD conversion unit 6, a reference signal generation unit 4, and a video data conversion unit 8. The column AD conversion unit 6 AD-converts the signal from the pixel array unit 2. The reference signal generation unit 4 supplies a reference signal for AD conversion to the column AD conversion unit 6. The video data converter 8 outputs the signal AD-converted by the column AD converter 6 to the subsequent circuit.

  The column AD conversion unit 6 includes an AD conversion unit 60 arranged for each vertical column. The AD conversion unit 60 includes a comparison unit 600, a counter unit 601, a switch unit 602, and a memory 603. The comparison unit 600 compares the reference signal generated by the reference signal generation unit 4 and the signal of the pixel array unit 2. In the operation of the comparison unit 600, the counter unit 601 counts the active period of the count enable signal line 6000, which has a constant relationship until the completion of the comparison process, with the count clock received from the count clock line 53. The memory unit 603 holds and stores the count result of the counter unit 601. The switch unit 602 switches whether or not to transfer the counter result to the memory unit 603.

  The video data conversion unit 8 has a digital calculation unit 80 and an interface (IF) unit 81. The digital calculation unit 80 performs various digital calculation processes on the signal output from the column AD conversion unit 6. The IF unit 81 has a function of interfacing with the outside. The output of the IF unit 81 is connected to the video output signal line 800, and the video data is output to the subsequent circuit by this output.

  The drive control unit 3 includes a horizontal scanning unit 7, a vertical scanning unit 9, and a system control unit 5. The horizontal scanning unit 7 includes a horizontal address setting unit and a horizontal driving unit that control column addresses and column scanning for each unit image 20 of the pixel array unit 2. Further, the vertical scanning unit 9 includes a vertical address setting unit and a vertical driving unit that control row addresses and row scanning for each unit image 20 of the pixel array unit 2.

  The system control unit 5 has a clock conversion function of inputting a master clock from the control unit 90 via the master clock line 55 and generating an internal clock. In addition, the system control unit 5 inputs data, which is supplied from the control unit 90, instructing an operation mode and the like via the system data signal line 56, and further controls data including information such as the operation mode of the image sensor unit 10. The unit 90 has a function block for outputting a data signal as a data signal via the system data signal line 56 and a function for controlling each unit.

  The unit pixel 20 is a column AD conversion unit in which a vertical scanning unit 9 is provided via a row control line 91 for row selection, and an AD conversion unit 60 is provided for each vertical column via a vertical signal line 21. 6 are connected respectively. Here, the row control line 91 indicates the entire wiring from the vertical scanning unit 9 to each unit pixel 20 included in the pixel array unit 2.

  In response to the control signals 52 and 57 output from the system control unit 5, the horizontal scanning unit 7 and the vertical scanning unit 9 shift the unit pixels 20 to be controlled in the horizontal direction and the vertical direction, respectively. (Scanning) is started. Therefore, for example, on the row control line 91, various pulse signals for driving the unit pixels 20 (for example, a pixel reset pulse that defines an initialization control potential, a transfer pulse that defines a transfer control potential, and a vertical selection pulse). ) Or the like is applied.

  The reference signal generation unit 4 has a DA conversion unit, and this DA conversion unit uses the count clock line 51 from the initial value indicated by the control data input from the system control unit 5 via the control data signal line 50. The ramp wave is generated in synchronization with the input count clock. Each AD converter 60 of the column AD converter 6 is supplied with the generated reference signal of the ramp wave from the reference signal line 40 as a reference voltage for AD conversion.

  The counter unit 601 of the AD conversion unit 60 is connected to the system control unit 5 by the count control signal line 54. In performing the reference signal comparison type AD conversion, the count operation effective period is determined based on the time from the conversion start (comparison processing start) to the conversion end (comparison processing end), and based on the count enable signal 6000. The analog signal to be processed is converted into digital data.

  Further, the counter unit 601 is connected to the switch unit 602 with an output enable signal 61 and a signal line for transmitting information on the count result by AD conversion. The output enable signal 61 is a signal for notifying the switch unit 602 that conversion of an analog processing target signal into digital data has been completed (that is, AD conversion has been completed). Here, when the output enable signal 61 is output in the enabled state, it is a state in which the counter unit 601 outputs the information of the count result by the AD conversion to the switch unit 602.

  A pixel signal voltage is applied to the vertical signal line 21, and the signal level of the pixel signal voltage appears as a time series after a reset level including noise of the pixel signal as a reference level. Here, the process for the reference level (effectively equivalent to the reset level) is referred to as the process of the precharge phase (hereinafter abbreviated as P phase) (or the process of the reset counter period). Further, the processing regarding the signal level is referred to as the processing of the data phase (hereinafter abbreviated as D phase) (or the processing of the data counter period). When the D phase processing is performed after the P phase processing, the D phase processing is processing for the signal level obtained by adding the signal component to the reset level.

  The system control unit 5 transmits the count pulse signal at the time of AD conversion to the counter unit 601 via the count clock line 53 as described above. Further, control information for the count operation performed by the counter unit 601 is instructed via the count control signal line 54. This control information includes, for example, setting of whether the P-phase / D-phase counting process operates in the down-count mode or the up-count mode, setting of an initial value in the P-phase counting process, and resetting process. , Instruct other control information.

  In the present embodiment, a configuration in which the memory unit 603 is provided in the AD conversion unit 60 is adopted. In this case, in order to transfer and store the count result (count value) output from the counter unit 601 to the memory unit 603 in synchronization with a predetermined timing, the counter unit 601 and the memory unit 603. The switch unit 602 is configured to be connected between and.

  When the output enable signal is output from the counter unit 601 in the enabled state, the AD conversion operation by the counter unit 601 is completed. This is a state in which the counter section 601 inputs the information of the count result by the AD conversion to the switch section 602 in the switch section 602.

  The switch unit 602 is supplied with a memory transfer instruction pulse as a control pulse via the SW instruction line 59 at a predetermined timing from the system control unit 5 in common with the switch units 602 in the other vertical columns. When the memory transfer instruction pulse is supplied, each switch of the switch unit 602 transfers the count value of the corresponding counter unit 601 to the memory unit 603. The memory unit 603 holds and stores the count value transferred from the counter unit 601.

  The configuration for holding the count value of the counter unit 601 in the memory unit 603 at a predetermined timing may be a configuration in which the switch unit 602 is not provided between the two. For example, the counter unit 601 and the memory unit 603 are directly connected, and the SW instruction line 59 is not connected to the system control unit 5 and the switch unit 602.

  Instead of the memory transfer instruction pulse output from the system control unit 5, the AD output from the counter unit 601 is based on the start timing of the output enable signal 61 output from the counter unit 601 at the end of AD conversion. Information of the count result by conversion can be held and controlled in the memory unit 603. That is, in this configuration, when the AD conversion operation by the counter unit 601 ends, the count result is immediately stored in the memory unit 603.

  A control pulse is input to the memory unit 603 from the horizontal scanning unit 7 via the control line 70. The memory unit 603 holds the count value fetched from the counter unit 601 until instructed by a control pulse via the control line 70. The output of the memory unit 603 is connected to the horizontal signal line 22. The horizontal signal line 22 has a signal line corresponding to the bit width of the AD conversion unit 60 or a double width thereof (for example, in the case of complementary output), and a video data conversion unit having a sense amplifier corresponding to each output line. 8 is connected.

  Further, the image pickup device section 10 can make the pixel array section 2 compatible with color image pickup by using a color separation (color separation) filter. That is, any color filter of a color separation filter including a combination of color filters of a plurality of colors for capturing a color image on the light-receiving surface on which light of each charge generation unit (photodiode or the like) in the pixel array unit 2 is incident. Is provided in an array such as a Bayer array, so as to support color image capturing. In addition, the image sensor unit 10 includes reference unit pixels (OB pixels: optical black pixels) that prevent light from entering due to light blocking even when a color separation (color separation) filter is used.

  Next, the AD conversion processing in the image sensor unit 10 will be described. First, in the comparison unit 600 arranged in each column of the AD conversion unit 60, the analog pixel signal voltage read from each unit pixel 20 to the vertical signal line 21 and the reference output from the reference signal generation unit 4 Compare the signals. The reference signal outputs a ramp wave whose voltage changes linearly with time.

  At this time, similarly to the comparison unit 600, the counter units 601 arranged in each column are operated by the count enable signal 6000, and the potential with the reference signal (reference voltage for AD conversion) and the counter unit 601 are in a one-to-one correspondence. Change while taking action. When the reference signal and the pixel signal voltage match, the enable signal from the comparison unit 600 is inverted, the counting operation in the counter unit 601 is stopped, and the count value in the counter unit 601 at this time corresponds to the pixel signal voltage. That is, the pixel signal voltage output to the vertical signal line 21 is converted into digital data.

  The AD conversion process will be described with reference to FIG. In FIG. 3, within one horizontal scanning period (the period from the fall of HD to the return to the H level and the fall again), first, in the P-phase processing period which is the AD conversion period at the reset level. , Resets the count value of each flip-flop of the counter unit 601 to the initial value “0”.

  Subsequently, the counter unit 601 is set to the down-count mode, and the P-phase level of the AD conversion reference voltage and the pixel signal voltage by the comparison unit 600 (in the P-phase, the pixel signal voltage is the reset voltage) is compared. In 600, a comparison process is performed, and in parallel with this comparison process, a counter unit 601 performs a count process to perform P-phase level AD conversion. When the AD conversion reference voltage and the pixel signal voltage match, the counter section 601 shows the count value indicating the digital value (reset data) DATArst corresponding to the magnitude of the reset level (indicating −DATArst if the sign is added). Retained.

Furthermore, in order to reduce random noise, the above-mentioned processing is performed N times in total (N is an integer of 2 or more), and when added, the digital values of all reset levels become
-DATArst × N (3)
Becomes

  In the example shown in FIG. 3, the count value DATArst = 5 in the first AD conversion, the count value DATArst = 5 in the second AD conversion, and the count value DATArst = 5 in the Nth AD conversion.

  During the subsequent processing of the second signal, that is, during the D-phase processing period that is the AD conversion period for the signal level, in addition to the reset level, the signal component corresponding to the incident light amount for each unit pixel 20 is read out, and P The same operation as the phase reading is performed.

  First, the counter unit 601 is set to the up-count mode that is the reverse of the P-phase processing, and the AD conversion reference voltage by the comparison unit 600 and the D-phase level of the pixel signal voltage (the pixel signal voltage is incident in the D-phase). The voltage corresponding to the light amount) is compared in the comparison unit 600, and in parallel with this comparison process, the counter unit 601 performs the counting process, and the D-phase level AD conversion is performed.

  At this time, the digital value (reset data) DATArst of the reset level of the pixel signal voltage acquired at the time of P-phase reading and AD conversion is used as a start point, and the counter is up-counted in the opposite manner to the P-phase. Since the signal level is the level obtained by adding the signal component to the reset level, the count value of the AD conversion result of the signal level is basically "DATArst + DATAsig".

Furthermore, in order to reduce random noise, the above-mentioned processing is performed N times in total (N is an integer of 2 or more), and when added, the digital values of all signal levels are
(DATArst + DATAsig) × N (4)
Becomes

  In the example shown in FIG. 3, the count value DATArst + DATAsig = 11 in the first AD conversion of the D phase, the count value DATArst + DATAsig = 11 in the second AD conversion, and the count value DATArst + DATAsig = 11 in the Nth AD conversion. ing.

As described above, in each of the P-phase and D-phase processing, data (added data) obtained by multiplying the AD conversion result of the same signal by N is obtained. By reversing the count mode for P phase and D phase,
-N x DATArst + N x (DATArst + DATAsig) = N x DATAsig (5)
The following calculation result is obtained.

  In the P phase and the D phase, when the AD conversion result of the same signal is multiplied by N, the addition data is substantially acquired, so it is understood that the counter unit 601 functions as a digital integrator. . In this calculation, the signal component after addition is N times, but the random noise is considered to be √N times, so that the noise characteristic of the image signal can be improved. The addition operation by the AD conversion described above can reduce random noise without the problem of the dynamic range such as the analog addition operation as in the conventional multi-sampling CDS circuit (for example, the above-mentioned Patent Document 1). it can.

Next, with reference to FIG. 4, an AD conversion process when external noise is generated will be described. As described above, the pixel signal is calculated from the P-phase and D-phase counter values,
-N x DATArst + N x (DATArst + DATAsig) = N x DATAsig (5)
Is output with.

  A voice coil motor (VCM motor) is often used as a drive motor in the camera shake correction unit 180, and this VCM motor is generally driven by a PWM (Pulse Width Modulation) driver circuit. In the PWM driver circuit, the carrier frequency during driving is determined, and when the image stabilization unit 180 is arranged near the image sensor unit 10, the PWM carrier frequency causes the analog pixel from the image sensor unit 10 as magnetic radiation noise. The signal voltage (here, it corresponds to the voltage signal output to the vertical signal line 21) is changed.

  Therefore, for example, when the number of AD conversions of the reset level and the signal level is set to “2” as shown in FIG. 4, the pixel signal level changes line by line, and the video data conversion unit 8 is left as it is. Horizontal stripe noise appears in the image output from.

  In FIG. 4, the upper stage (above the black downward arrow) shows the case where no external noise is mixed in the image signal, and the lower stage (below the black downward arrow) shows the case where the external noise is mixed into the image signal. .

  When no external noise is mixed, the signal of the first line has the reset voltage of "-5" for the first time, "-5" for the second time, "11" for the first time of the signal voltage, and "11" for the second time. is there. Therefore, the pixel signal level of the first line is −5−5 + 11 + 11 = 12. Similarly, the pixel signal level of the second line is -5-5 + 11 + 11 = 12.

  On the other hand, when external noise is mixed, the signals of the first line are “−4” at the first reset voltage, “−5” at the second reset voltage, “11” at the first reset voltage, and “10” at the second reset voltage. . Therefore, the pixel signal level of the second line is −5−4 + 11 + 101 = 11.

  In this way, when the external noise is not mixed, the pixel signal levels of the first line and the second line are the same as shown in the example of FIG. Does not occur. However, if external noise is mixed, since the pixel signal levels of the first line and the second line are different, a striped pattern is generated in the image due to the external noise, resulting in an unsightly image.

  Therefore, in the present embodiment, even when external noise is mixed, the influence of external noise is removed or reduced. A method for removing and reducing the influence of external noise will be described with reference to FIG.

In the present embodiment, as shown in FIG. 5, when the start timings of the first and second AD conversions of the reset level are Trst1 and Trst2 and the signal level start timings are Tsig1 and Tsig2, the reset level and the signal When the time difference of the AD conversion timing of Tcds1 (= Tsig1-Trst1) and Tcds2 (= Tsig2-Trst2) is set, the time difference is set so as to satisfy the relationship of the following expression (6).
Tcds2 = M × Tcds1 (6)
Note that M is an integer of 1 or more.

The frequency of the AD conversion timing (CDS frequency) at that time is given by the following equations (7) and (8).
fcds1 = 1 / Tcds1 (7)
fcds2 = 1 / Tcds2 = 1 / M × fcds1 (8)

Further, when the time of one cycle of the external noise is T_noise and the frequency is f_noise, it is set so as to satisfy the relationships of the following expressions (9) to (11).
T_noise = 1 / f_noise (9)
T_noise = 1 / L × T_cds1 (10)
f_noise = L × fcds1 (11)
Note that L is an integer of 1 or more.
In FIG. 5, N = 2, M = 2, and L = 5.

  As described above, in the present embodiment, the noise levels on the pixel signal levels of all lines are the same, and horizontal stripes do not occur. Comparing FIG. 4 and FIG. 5, although the change in the pixel signal level for each line is eliminated, there is a difference from the original pixel signal level. That is, it is "12" in the upper part of FIG. 4 and "13" in FIG. However, as shown in FIG. 1, when image processing or the like is performed in the subsequent stage of the image sensor unit 10, the unit pixel 20 uses the level of the OB pixel from the OB pixel as a reference, and thus the difference is resolved.

  FIG. 6 shows the action of removing external noise from the relationship between the frequency transfer characteristic by the CDS frequency and the external noise frequency. As shown in FIG. 6, the transfer characteristics are suppressed to near zero near the frequencies (fcds, fcds2, ...) Each of which is an integral multiple of the CDS frequency of each pair with the P-phase and D-phase signals. To do.

Similarly, when the reset level and the signal level are performed N times (N is an integer of 2 or more),
fcds2 = 1 / M1 x fcds1 (M1 is an integer of 1 or more)
fcds3 = 1 / M2 x fcds1 (M2 is an integer of 1 or more)
...
fcdsN = 1 / Mn × fcds1 (Mn is an integer of 1 or more)
age,
f_noise = L × fcds1 (L is an integer of 1 or more)
And

  In this embodiment, as can be seen from the time t of one horizontal period (the period between the horizontal synchronization signals HD) in FIGS. 4 and 5, the time Tcds1 or Tcds2 is taken, so the total AD conversion time is It will be longer than before, and the frame rate will decrease, which is disadvantageous when shooting moving images.

  However, when a mechanical shutter (referred to as a mechanical shutter) is used, such as when capturing a still image, the signal charge accumulation time is from the opening of the mechanical shutter to the closing of the shutter, and the shutter is closed. Pixel signals are read from the pixel array section 2 to the column AD conversion section 6 side for each line, and the AD conversion section 60 performs AD conversion processing. Since the pixel signal reading process and the AD conversion process may be performed at a low speed, the reduction in frame rate does not pose a problem.

  Next, a first modification of the first embodiment will be described with reference to FIG. In the first embodiment, the reset level and the signal level are AD-converted N times (N is an integer of 2 or more). In this modification, the reset level AD conversion is performed N times and the signal level AD conversion is performed once.

In this modified example, as shown in FIG. 7, when the first and second reset level AD conversion timings are Trst1 and Trst2 and the signal level timing is Tsig1, the reset level and the signal AD conversion timing are set. Let Tcds1 (= Tsig1 − Trst1) and Tcds2 (= Tsig1 − Trst2) be the time difference between Tcds2 and Tcds2 so as to satisfy the following equation (12).
Tcds2 = 1 / M × Tcds1 (12)
Note that M is an integer of 1 or more.

The frequency of the AD conversion timing (CDS frequency) at that time is given by the following equations (13) and (14).
fcds1 = 1 / Tcds1 (13)
fcds2 = 1 / Tcds2 = M × fcds1 (14)

Further, when the time of one cycle of the external noise is T_noise and the frequency is f_noise, it is set so as to satisfy the relationships of the following equations (15) to (17).
T_noise = 1 / f_noise (15)
T_noise = 1 / L × T_cds1 (16)
f_noise = L × fcds1 (17)
L is an integer of 1 or more.
In FIG. 7, N = 2, M = 1, and L = 5.

Similarly, when the reset level is performed N times (N is an integer of 2 or more),
fcds2 = M1 × fcds1 (M1 is an integer of 1 or more)
fcds3 = M2 × fcds1 (M2 is an integer of 1 or more)
...
fcdsN = Mn × fcds1 (Mn is an integer of 1 or more)
age,
f_noise = L × fcds1 (L is an integer of 1 or more)
And

  As described above, in the first modification, the AD conversion unit 60 repeatedly performs the first AD conversion process N times (N multiple times) and the second AD conversion process once. Then, the time from the timing of starting the first AD conversion processing in the first processing and the timing of starting the second AD conversion processing in the first processing is Tcds1, and the number of times of the second and subsequent times is N. Letting TcdsN be the time from the timing of starting the first AD conversion process performed for the Nth time to the timing of starting the second AD conversion process performed for the first time, TcdsN = Tcds1 / M (M is an integer) The first AD conversion process and the second conversion process are performed at the related time.

  Next, a second modification of the first embodiment will be described with reference to FIG. In the first embodiment, as described above, the reset level and the signal level are AD-converted N times (N is an integer of 2 or more). In this modification, the reset level AD conversion is performed once and the signal level AD conversion is performed N times.

In this modification, when the reset level first AD conversion timing is Trst1 and the signal level first and second timings are Tsig1 and Tsig2, as shown in FIG. 8, the reset level and the signal AD conversion are performed. If the time difference between the timings is Tcds1 (= Tsig1-Trst1) and Tcds2 (= Tsig2-Trst1), Tcds2 is set so as to satisfy the following expression (18).
Tcds2 = M × Tcds1 (18)
Note that M is an integer of 1 or more.

The frequency of the AD conversion timing (CDS frequency) at that time is given by the following equations (19) and (20).
fcds1 = 1 / Tcds1 (19)
fcds2 = 1 / Tcds2 = 1 / M × fcds1 (20)

Further, when the time of one cycle of the external noise is T_noise and the frequency is f_noise, it is set so as to satisfy the relationships of the following expressions (21) to (23).
T_noise = 1 / f_noise (21)
T_noise = 1 / L × T_cds1 (22)
f_noise = L × fcds1 (23)
L is an integer of 1 or more.
In FIG. 8, N = 2, M = 1, and L = 5.

  As described above, in the second modification, the AD conversion unit 60 processes the first AD conversion process once and repeatedly performs the second AD conversion process N times (N is a plurality). The time from the timing of starting the first AD conversion processing to the first time to the timing of starting the second AD conversion processing to be performed for the first time is set to Tcds1 (see FIG. 8), and the second and subsequent N-th operations are performed. When the time from the timing of starting the second AD conversion processing to the timing of starting the first AD conversion processing performed for the first time is TcdsN (see Tcds2 in FIG. 8), TcdsN = Tcds1 × M (M is an integer) The first AD conversion process and the second conversion process are performed at the time of the relation.

  As described above, in the first embodiment and the modified example of the present invention, the control unit 90 in the imaging device serves as a source of external noise in accordance with the information of the CDS frequency (f_cds) set in the imaging device unit 10. The PWM carrier frequency of the driver circuit of the camera shake correction unit 180, which can be specified, is set so that the relationship of the above mathematical formula is established. Therefore, even when external noise is generated from the drive unit and the electronic components arranged around the image sensor unit 10, the external noise mixed from the image signal from the image sensor unit 10 can be removed or reduced. it can. The first and second modifications can be applied not only to the first embodiment but also to a second embodiment described later.

  Next, a second embodiment of the present invention will be described with reference to FIGS. In the first embodiment of the present invention, after the CDS frequency (f_cds) for AD conversion in the image pickup device unit 10 is determined, the frequency f_noise (PWM of external noise generated in the drive unit and electronic components in the image pickup apparatus 1 is determined. The PWM carrier frequency of the driver circuit) was determined. As a result, not only random noise generated from individual pixels in the image sensor but also external noise of fixed frequency mixed into the image signal is reduced.

  On the other hand, in the second embodiment of the present invention, when the reset signal level read from the unit pixel 20 in the image sensor 10 is acquired, the external noise of a predetermined fixed frequency is measured, and the external noise is measured. The CDS frequency (f_cds) is set so that the influence of noise is reduced. The external noise is measured under the control of the system control unit 5 in the image pickup device unit 10.

  The overall configuration of this embodiment is the same as that of the block diagram shown in FIG. 1 according to the first embodiment, and detailed description thereof will be omitted. Further, the image pickup device section 10 in the image pickup apparatus 1 is substantially similar to the block diagram shown in FIG. 2, and different points will be mainly described.

  The image pickup device unit 10 according to the present embodiment shown in FIG. 9 is different from the image pickup device unit 10 according to the first embodiment shown in FIG. 2 in that a timing signal line connecting the system control unit 5 and the video data conversion unit 8 is connected. The difference is that 58 is provided. The timing signal line 58 calculates the signal data obtained from the external noise detection drive by the digital calculation unit 80, and sends the timing signal data to the system control unit 5. The system control unit 5 determines the AD conversion timing in the AD conversion unit 60 based on the timing signal data received from the digital calculation unit 80.

  Next, the external noise detection drive will be described with reference to FIG. FIG. 10 shows an example of external noise detection. In this example, when switching from the moving image mode to the still image mode, the period (exposure frame) during which an image is not captured is used to shift to external noise detection drive. The external noise detection drive can be performed when there is a period during which an image is not captured, other than when switching from the moving image mode to the still image mode.

  In the example shown in FIG. 10, times t1 to t2 are moving image modes such as live view display and moving image recording. At time t2, when the user operates the release button to instruct to shoot a still image, the mode shifts to the still image mode. In the still image mode, the shutter 170 is closed and then opened, and the subject image formed by the lens 150 is formed on the pixel array 2 of the image sensor 10. This exposure continues for an exposure time determined by the shutter speed of the shutter 170 (exposure frame: between times t2 and t3).

  External noise detection drive is performed during the exposure frame from time t2 to time t3. Here, the frequency of the external noise generated from the drive unit, the electronic component, and the like arranged inside the image pickup apparatus 1 and mixed in the image signal from the image pickup element unit 10 is detected. This external noise detection drive will be described later with reference to FIG.

  Times t3 to t4 are read frames, and the image signal is read from each pixel unit 20 in the pixel array 2 during the exposure frame. During this reading, AD conversion is performed and digital image data is output. At this time, the CDS frequency (f_cds) is set using the frequency of the external noise detected in the external noise detection drive, and AD conversion is performed.

  Next, the detection operation in the external noise detection drive will be described with reference to FIG. The external noise detection drive is performed only when reading the P phase (reset voltage detection). P-phase reading is performed N times (N is an even number), and the first, second, ..., Nth AD conversion timing within the first horizontal scanning period (the period between the horizontal synchronization signals HD) of the first line is performed. When Trst1, Trst2 ... TrstN are set, the time interval (Trst_H1) is made constant.

  The counter 601 down-counts the signal of the odd-numbered AD conversion timing, up-counts the signal of the even-numbered AD conversion timing, and outputs the count result to the digital arithmetic unit 80. In the digital operation unit 80, the count values from the AD conversion units 60 in each column are added to obtain DATArst_H1. Since the down count and the up count may be switched alternately, the odd count does not necessarily have to be the down count and may be the up count.

  In the external noise detection operation, the first, second, ... Nth AD conversion timing in the first horizontal scanning period of the second line (the period between the horizontal synchronizing signals HD) is set to Trst1, Trst2, ... TrstN. In this case, the same processing is performed by changing the time interval from the first line (Trst_H2) (DATArst_H2). Do the same for all lines from the third line onward (DATArst_HN). Among all the added values (DATArst_H1, DATArst_H2, ... DATArst_HN), the minimum value is output to the system control unit 5.

  The system control unit 5 reads the pixel signal in the frame next to the exposure frame based on the time interval in which the added value obtained by the video data conversion unit 8 during the external noise detection drive becomes the minimum, and performs AD conversion. Set the CDS frequency of P phase and D phase. For example, when DATArst_Hx is (x indicates a line number), Trst2−Trst1 = Trst_Hx, and as shown in FIG. 12, Tcds1 = α × Trst_Hx (α is an integer of 1 or more) of the read frame is automatically set.

  As described above, in the second embodiment, not only random noise but also external noise having a fixed frequency can be reduced in the pixel signal reading frame subsequent to the exposure frame. That is, in the first embodiment, the PWM carrier frequency of the external noise source (for example, the PWM driver circuit) is set according to the CDS frequency. On the other hand, in the second embodiment, the image pickup device unit 10 measures (detects) the frequency of the external noise generation source (PWM driver circuit), which is an arbitrary value that has been set in advance, and measures it. Each CDS frequency (f_cds) in the image pickup device unit 10 is set in accordance with the external noise frequency.

  For example, the drive motor (VCM coil or the like) of the camera shake correction unit 180 has a different optimum PWM carrier frequency with less pulsating current (ripple) of the drive current according to the electric characteristic of the motor (impedance characteristic of the coil). It has been known. Further, the supply of the drive voltage (including the PWM carrier frequency) to the drive motor (VCM coil, etc.) of the camera shake correction unit 180 is performed, for example, when the camera shake correction function is activated and when the same function is not activated (hold at a fixed position). It is known that the behavior is different). Even if the external noise frequency changes according to the optimum characteristics of the motor or the operating conditions as described above, in the present embodiment, the CDS signal can be appropriately set and a noise-free image signal can be obtained. You can

  Further, in the second embodiment of the present invention, the external noise mixed in the first processing target signal (for example, the reset voltage of FIG. 12) and the second processing target signal (for example, the signal voltage of FIG. 12) is mixed. It has a noise frequency detection unit (for example, see FIGS. 9 and 11) that detects a frequency. The AD conversion unit 60 corresponds to the noise frequency detected by the noise frequency detection unit until the timing of starting the first AD conversion process performed for the first time and the start of the second AD conversion process performed for the first time. The timing time (Tcds1) is set. Therefore, as described above, even when the external noise generated outside the imaging device unit 10 is unknown, it is possible to remove not only the noise of the image signal but also the external noise.

  As described above, in each of the embodiments and modifications of the present invention, when the reset level and the signal level are AD-converted twice, the timings of the first and second AD conversions of the reset level are Trst1, Trst2, and the signal. When the level timing is Tsig1 and Tsig2, the time difference between the reset level and the AD conversion timing of the signal is Tcds1 (= Tsig1-Trst1), and Tcds2 (= Tsig2-Trst2), Tcds2 is an integer (including 1) times Tcds1. The image sensor unit 10 is driven at an AD conversion timing that is equal to (see, for example, FIG. 5).

  When the reset level and the signal level are AD-converted N times (N is an integer of 2 or more), TcdsN (2 to N) is an integer (Tcds1) of the integer ( The image pickup device unit 10 is driven at an AD conversion timing that is equal to twice (including 1).

  Further, when the reset level is AD-converted twice and the signal level is AD-converted once, the timings of the first and second AD conversions of the reset level are Trst1 and Trst2, the signal level timing is Tsig1, and Tcds1 (= Tsig1 − Trst1) and Tcds2 (= Tsig1-Trst2), the image sensor is driven at the AD conversion timing at which Tcds2 becomes 1 / integer of Tcds1 (see, for example, FIG. 7).

  Further, when the reset level is AD N times (N is an integer of 2 or more) and the signal level is AD once, TcdsN (2 to 2 is used in the same way as in the case where the reset level is AD converted twice and the signal level is AD-converted once. The image sensor unit 10 is driven at the AD conversion timing such that (up to N) is 1 / integer (including 1) of Tcds1.

  Further, when the reset level is AD-converted once and the signal level is AD-converted twice, the first AD conversion timing of the reset level is Trst1, the first signal level timing is Tsig1, Tsig2, and Tcds1 (= Tsig1 − Trst1) and Tcds2 (= Tsig2-Trst1), the image sensor is driven at the AD conversion timing at which Tcds2 is an integer (including 1) times Tcds1 (for example, refer to FIG. 8).

  When AD conversion is performed for the reset level once, the signal level N times (N is an integer of 2 or more), TcdsN (2 to 2 is used in the same way as when the reset level is once and the signal level is AD converted twice. The image sensor is driven at the AD conversion timing at which (up to N) is an integer (including 1) times Tcds1.

  The drive frequency, which is a noise source of other components other than the image sensor constituting the image pickup apparatus such as a camera, is set to be an integral multiple of the plurality of CDS frequencies. Even in an image pickup apparatus in which an external noise cannot be removed only by the image sensor control circuit, that is, a PWM driver circuit (for example, for a camera shake correction function) serving as an external noise generation source is arranged, the influence of the external noise can be removed. it can.

  Further, the above-mentioned Tcds can be optimally changed in accordance with the driving frequency which becomes a noise source of other components inside the sensor. By enabling automatic change, even if an unknown external noise appears, the influence of the external noise can be removed.

  As described above, in each of the embodiments and the modified examples of the present invention, the reference signal generation unit that generates the reference signal based on the ramp signal that changes at the predetermined time change rate is provided, and the comparison unit 601 and The counter unit 603 is provided, and the AD conversion unit 6 that acquires the digital data to be processed based on the output data of the counter unit 603 is provided. The comparison unit 601 described above includes a reference signal supplied from the reference signal generation unit 4 and a first processing target signal (for example, FIG. 5) which is an analog signal at the time of reset, which is output in the pixel circuit in the solid-state imaging device. Reset voltage) and a signal to be processed (for example, the signal voltage in FIG. 5) including the second processed signal that is an analog signal when the video signal is acquired. The counter unit 603 is supplied with a count clock for AD conversion, performs a counting operation based on the comparison result of the comparison unit 601, and AD-converts the second processing target signal that is an analog signal.

  Further, in each of the embodiments and each modification of the present invention, regarding the processing target signal, the first AD conversion processing in the first processing target signal (for example, the reset voltage of FIG. 5) and the second processing target signal. (For example, in the second AD conversion process in the signal voltage of FIG. 5, at least one is a predetermined number of times (N times: N ≧ 2), and is repeatedly performed a plurality of times. Processing, the system control unit 5 that controls the reference signal generation unit 4 and the AD conversion unit so as to execute the second digital integration process, and the first digital data obtained by executing the first digital integration process. And a CDS processing unit for performing correlated double sampling calculation based on the second digital data obtained by executing the second digital integration processing. AD conversion by so-called correlated double sampling (CDS) processing is possible using the first processing target signal and the second processing signal.

  In addition, in each of the embodiments and the modified examples of the present invention, the AD conversion unit 60 performs the first AD conversion processing or the second AD conversion processing N times, when the AD conversion section 60 repeats the first AD conversion processing N times. Is set to Tcds1 (see, for example, FIG. 5), the time until the second AD conversion process performed for the first time is set to Tcds1 (see, for example, FIG. 5), and the number of times from the second time onward is set to N. Assuming that TcdsN (for example, Tcds2 in FIG. 5) is the time to start the first AD conversion processing and the time to start the second AD conversion processing performed for the Nth time, TcdsN = Tcds1 / M (M is an integer ), The first AD conversion process and the second AD conversion process are performed.

  Further, the image pickup apparatus 1 according to each of the embodiments and the modified examples of the present invention includes a drive unit (for example, a camera shake correction unit 180) relating to image pickup, a driver circuit that supplies a drive voltage to the drive unit, and a driver circuit. On the other hand, a control unit (for example, a control unit 90) that controls the drive voltage by a PWM-modulated modulation signal is provided, and the control unit 90 sets the carrier frequency Fe related to the PWM modulation to (1 / Tcds) × L = Fe (where L is an integer) is set (for example, the external noise frequency f_noise is set to be the carrier aberration number Fe according to the equation (11)).

  Further, the image pickup apparatus according to each of the embodiments and the modified examples of the present invention includes a drive unit (for example, a camera shake correction unit 180) relating to image pickup, a driver circuit that supplies a drive voltage to the drive unit, and a driver circuit. On the other hand, a control unit (for example, a control unit 90) that controls a drive voltage by a PWM-modulated modulation signal is provided, and the control unit causes the imaging element unit 10 to operate the carrier frequency related to the PWM modulation with Fe. The provided noise frequency detection unit (see, for example, FIGS. 9 and 11) detects the carrier frequency Fe associated with PWM modulation as an external noise frequency, and the AD conversion unit 60 performs the first AD conversion process and the second AD conversion process. The time interval for executing the conversion process is set so as to have a relationship of (1 / Tcds) × L = Fe (where L is an integer).

  In addition, in each embodiment and each modification of the present invention, AD conversion by correlated double sampling has been described. However, the present invention is not limited to this, and as long as it is an AD converter of a type that converts a reset voltage and a signal voltage into digital values and removes noise from both digital values, the sampling timing of each embodiment and each modification example. You can also use

  In addition, in each embodiment and each modification of the present invention, the image processing unit 110 and the like are configured separately from the control unit 90, but all or part of each unit is configured by software, and the control unit Of course, it does not matter even if it is executed by the CPU in 1. Similarly, the system control unit 5, the video data conversion unit 8 and the like may be configured in software by a CPU and a program in addition to the hardware circuit or the single component, or by using a DSP (Digital Signal Processor). You may comprise. Of course, these may be combined appropriately.

  Further, in the present embodiment, a digital camera is used as a device for shooting, but the camera may be a digital single-lens reflex camera or a compact digital camera, and a video camera, a movie camera such as a movie camera may be used. It may be a camera, or may be a camera built in a mobile phone, a smartphone, a personal digital assistant (PDA), a personal computer (PC), a tablet computer, a game machine, or the like. In any case, the present invention can be applied to any device having a solid-state image sensor.

  Further, among the techniques described in this specification, the control mainly described in the flowchart is often settable by a program and may be stored in a recording medium or a recording unit. The recording medium and the recording unit may be recorded at the time of product shipment, may be used as a distributed recording medium, or may be downloaded via the Internet.

  In addition, regarding the operation flow in the claims, the specification, and the drawings, even if the description is made using words that express the order of “first”, “next”, and the like for convenience, It does not mean that implementation in this order is essential.

  The present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements within a range not departing from the gist of the invention in an implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some of all the constituent elements shown in the embodiment may be deleted. Furthermore, the constituent elements of different embodiments may be combined appropriately.

DESCRIPTION OF SYMBOLS 1 ... Imaging device, 2 ... Pixel array, 3 ... Drive control part, 4 ... Reference signal generation part, 5 ... System control part, 6 ... Column AD conversion part, 7 ... ..Horizontal scanning unit, 8 ... video data conversion unit, 9 ... vertical scanning unit, 10 ... image sensor unit, 20 ... unit pixel, 21 ... vertical signal line, 22 ... Horizontal signal line, 40 ... Reference signal line, 50 ... Control data signal line, 51 ... Count clock line, 52 ... Control signal, 53 ... Count clock line, 54 ... Count control Signal line, 55 ... Master clock signal line, 56 ... System data signal line, 57 ... Control signal, 58 ... Timing signal line, 59 ... SW instruction line, 60 ... AD conversion Section, 61 ... Output enable signal, 70 ... Control line, 80 ... Digitizer Calculation unit, 81 ... I / F minutes, 90 ... Control unit, 91 ... Row control line, 100 ... Imaging unit, 110 ... Image processing unit, 120 ... Input IF, 130 ... Display unit, 140 ... Internal memory, 145 ... External memory, 150 ... Lens, 160 ... Aperture, 170 ... Shutter, 180 ... Image stabilization unit, 190 ... Data bus, 600 ... Comparison unit, 601 ... Counter unit, 602 ... Switch unit, 603 ... Memory unit, 800 ... Video output signal line, 6000 ... Count enable signal line

Claims (7)

A solid-state image sensor,
A reference signal generation unit that generates a reference signal based on a ramp signal that changes at a predetermined time rate of change;
An AD conversion unit having a comparison unit and a counter unit for acquiring digital data to be processed based on the output data of the counter unit;
Have
The comparison unit is configured to acquire the reference signal supplied from the reference signal generation unit and a first processing target signal and a video signal, which are analog signals at reset, which are output from the pixel circuit in the solid-state image sensor. of comparing the second processing object signal is an analog signal,
The counter section is supplied with a count clock for AD conversion, performs a counting operation based on the comparison result of the comparison section,
The solid-state image sensor further includes
For the processed signal, the first process the first AD conversion process in the target signal, and the second processing the second predetermined number of times for the AD conversion processing in the target signal (N times: N ≧ 2) And a drive control unit that controls the reference signal generation unit and the AD conversion unit so as to execute a first digital integration process and a second digital integration process that are repeatedly performed a plurality of times.
Correlated double sampling operation based on the first digital data obtained by executing the first digital integration processing and the second digital data obtained by executing the second digital integration processing. A CDS processing unit that performs
Equipped with,
The AD converter is
Let Tcds1 be the time from the timing of starting the first AD conversion processing performed for the first time to the timing of starting the second AD conversion processing performed for the first time.
Let TcdsN be the time from the timing of starting the first AD conversion processing performed at the Nth time to the timing of starting the second AD conversion processing performed at the Nth time, where N is the number of times from the second time onward.
TcdsN = Tcds1 × M (M is an integer of 2 or more )
A solid-state imaging device, wherein the first AD conversion process and the second AD conversion process are performed for a time period of a relationship such that Furthermore, it has a noise frequency detection means for detecting the frequency of the external noise mixed in the first processing target signal and the second processing target signal,
The AD conversion section starts the first AD conversion process at the first time and the second AD conversion process at the first time in response to the noise frequency detected by the noise frequency detection means. The solid-state imaging device according to claim 1, wherein a time (Tcds1) until timing is set. A solid-state image sensor,
A reference signal generation unit that generates a reference signal based on a ramp signal that changes at a predetermined time rate of change;
An AD conversion unit having a comparison unit and a counter unit for acquiring digital data to be processed based on the output data of the counter unit;
Have
The comparison unit is configured to acquire the reference signal supplied from the reference signal generation unit and a first processing target signal and a video signal, which are analog signals at reset, which are output from the pixel circuit in the solid-state image sensor. The second processed signal, which is an analog signal of
The counter section is supplied with a count clock for AD conversion, performs a counting operation based on the comparison result of the comparison section,
The solid-state image sensor further includes
For the processing target signal, at least one of the first AD conversion processing of the first processing target signal and the second AD conversion processing of the second processing target signal has a predetermined number of times (N Number of times: N ≧ 2), a drive control unit that controls the reference signal generation unit and the AD conversion unit to execute a first digital integration process and a second digital integration process that are repeatedly performed a plurality of times. When,
Correlated double sampling operation based on the first digital data obtained by executing the first digital integration processing and the second digital data obtained by executing the second digital integration processing. A CDS processing unit that performs
Equipped with,
The AD conversion unit repeatedly processes the first AD conversion process N times (N is a plurality) and processes the second AD conversion process once.
The timing of starting the first AD conversion process for the first time and the timing time until starting the second AD conversion process for the first time are set to Tcds1,
Letting the number of times from the second time onward be N, the time from the timing of starting the first AD conversion processing performed at the Nth time to the timing of starting the second AD conversion processing performed at the first time is TcdsN,
TcdsN = Tcds1 / M (M is an integer of 2 or more )
Become in time relation, the first AD conversion processing and the second solid-state image pickup element you and performs AD conversion. A solid-state image sensor,
A reference signal generation unit that generates a reference signal based on a ramp signal that changes at a predetermined time rate of change;
An AD conversion unit having a comparison unit and a counter unit for acquiring digital data to be processed based on the output data of the counter unit;
Have
The comparison unit is configured to acquire the reference signal supplied from the reference signal generation unit and a first processing target signal and a video signal, which are analog signals at reset, which are output from the pixel circuit in the solid-state image sensor. The second processed signal, which is an analog signal of
The counter section is supplied with a count clock for AD conversion, performs a counting operation based on the comparison result of the comparison section,
The solid-state image sensor further includes
For the processing target signal, at least one of the first AD conversion processing of the first processing target signal and the second AD conversion processing of the second processing target signal has a predetermined number of times (N Number of times: N ≧ 2), a drive control unit that controls the reference signal generation unit and the AD conversion unit to execute a first digital integration process and a second digital integration process that are repeatedly performed a plurality of times. When,
Correlated double sampling operation based on the first digital data obtained by executing the first digital integration processing and the second digital data obtained by executing the second digital integration processing. A CDS processing unit that performs
Equipped with,
The AD conversion unit processes the first AD conversion process once and repeatedly executes the second AD conversion process N times (N is a plurality).
Let Tcds1 be the time between the timing of starting the first AD conversion processing for the first time and the timing of starting the second AD conversion processing for the first time.
Let TcdsN be the time to start the second AD conversion process performed in the Nth time after the second time and the time to start the first AD conversion process performed in the first time.
TcdsN = Tcds1 × M (M is an integer of 2 or more )
Become in time relation, the first AD conversion processing and the second solid-state image pickup element you and performs AD conversion. A solid-state imaging device according to claim 1 , or 3 or 4 ,
A drive unit related to imaging,
A driver circuit that supplies a drive voltage to the drive unit,
A control unit for controlling a drive voltage by a PWM-modulated modulation signal for the driver circuit;
An imaging device having
The control unit sets the carrier frequency Fe related to the PWM modulation to (1 / Tcds) × L = Fe (where L is an integer)
An image pickup apparatus, which is set so as to satisfy the following relationship. Furthermore, it has a noise frequency detection means for detecting the frequency of the external noise mixed in the first processing target signal and the second processing target signal,
The AD conversion section starts the first AD conversion process at the first time and the second AD conversion process at the first time in response to the noise frequency detected by the noise frequency detection means. The solid-state image sensor according to claim 3 or 4, wherein a time (Tcds1) until timing is set. A solid-state image sensor according to claim 2 or 6 ,
A drive unit related to imaging,
A driver circuit that supplies a drive voltage to the drive unit,
A control unit for controlling a drive voltage by a PWM-modulated modulation signal for the driver circuit;
An imaging device having
The control unit operates the carrier frequency related to the PWM modulation with Fe,
The noise frequency detection means provided in the solid-state imaging device detects the carrier frequency Fe related to the PWM modulation as an external noise frequency,
The AD conversion unit sets a time interval for executing the first AD conversion processing and the second AD conversion processing as
(1 / Tcds) × L = Fe (where L is an integer)
An image pickup apparatus, which is set so as to satisfy the following relationship.

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