JP6696473B2 - Multilayer SOI wafer and method of manufacturing the same - Google Patents

Description

  The present invention relates to a multilayer SOI wafer and a method for manufacturing the same.

  An SOI (Silicon on Insulator) wafer has a structure in which an oxide film and an active layer (SOI layer) are stacked on a supporting substrate. Further, a multi-layered SOI wafer is advantageous as a highly integrated device. The multi-layered film SOI wafer has a structure in which at least a first oxide film, a first active layer, a second oxide film, and a second active layer are stacked on a support substrate. That is, the multilayer SOI wafer has a plurality of active layers.

  Patent Document 1 describes the following technique as a method for manufacturing a multilayer film SOI wafer. First, oxygen ions are implanted from the surface of the first active layer wafer to form an oxygen ion implanted layer inside the first active layer wafer, and then oxygen ions are implanted from the surface where the oxygen ions are implanted by thermal oxidation. The first oxide film is formed up to this point. Next, the supporting substrate wafer and the first active layer wafer are superposed on each other with the first oxide film interposed therebetween, and subjected to a bonding heat treatment to bond the supporting substrate wafer and the first active layer wafer. Next, the thickness of the first active layer wafer is reduced to obtain an SOI wafer having the first active layer. Next, oxygen ions are implanted from the surface of the second active layer wafer to form an oxygen ion implantation layer inside the second active layer wafer, and then oxygen ions are implanted from the surface where the oxygen ions are implanted by thermal oxidation. A second oxide film is formed up to the layer. Next, the second active layer wafer is superposed on the first active layer side of the SOI wafer through the second oxide film, and a bonding heat treatment is performed to bond the SOI wafer and the second active layer wafer. To match. Next, the thickness of the second active layer wafer is reduced to obtain a multi-layered SOI wafer having the desired thickness of the second active layer.

JP 2007-109961A

  In Patent Document 1, no attention is paid to the structure of the end face of the wafer in the process of manufacturing the multi-layered SOI wafer. However, in order to improve the manufacturing yield of semiconductor devices, the area of a device-formable region in the active layer (hereinafter, also referred to as “effective area”) is increased, and as the semiconductor devices are miniaturized, the active layer becomes flat. The structure of the end surface of the wafer is important in recent years when it is required to improve the property. From this viewpoint, focusing on the structure of the end face of the wafer, a multilayer film SOI wafer is obtained based on an SOI wafer obtained by bonding a supporting substrate wafer and a first active layer wafer through a first oxide film by a usual method. The present inventors have found that there are the following problems when they are manufactured.

  First, a procedure for manufacturing an SOI wafer obtained by bonding by a normal method will be described. Usually, a wafer used as the supporting substrate wafer 10 or the first active layer wafer 20 has a chamfered portion on its end face as shown in FIG. 5 (A). As shown in FIGS. 5A to 5D, when such wafers are bonded together via the first oxide film 12, the chamfered parts are not bonded to each other outside the outer periphery of the bonded surface. An unbonded area is generated (FIG. 5 (D)). If this unbonded area is left as it is, it may cause the wafer to be chipped or broken in a later step. Therefore, by chamfering or etching the outer peripheral region of the first active layer wafer 20, the unbonded region is removed. Specifically, as shown in FIG. 5D, after the supporting substrate wafer 10 and the first active layer wafer 20 are bonded to each other via the first oxide film 12, the first active layer wafer 20 is The peripheral area is reduced by chamfering. As a result, a silicon residue portion remains under the outer peripheral region of the first active layer wafer 20 (FIG. 5 (E)). Subsequently, this silicon residue portion is removed by etching treatment (FIG. 5 (F)). When the unbonded area is removed by such a procedure, the terrace portion 34 is formed above the outer peripheral area of the support substrate 10. That is, the terrace portion 34 means a region above the outer peripheral region of the support substrate 10 in which the outer peripheral region of the first active layer wafer 20 is removed so that the first active layer wafer 20 does not exist. Here, the “outer peripheral region of the supporting substrate” refers to a region of 1 to 3 mm radially inward from the outermost peripheral end of the supporting substrate, and the “outer peripheral region of the first active layer wafer” means the first active layer. A region of 1 to 3 mm radially inward from the outermost peripheral edge of the wafer. In this specification, the processing described with reference to FIGS. 5D to 5F is referred to as “terrace processing”. After that, the first active layer wafer is ground and polished to manufacture the SOI wafer 32 having the first active layer 22 having a desired thickness (FIG. 5G).

  Next, a procedure for producing a multi-layered SOI wafer based on the SOI wafer produced by the above procedure will be described. As shown in FIGS. 4A to 4D, the SOI wafer 32 and the second active layer wafer 40 are bonded together with the second oxide film 24 interposed therebetween. Then, the outer peripheral region of the second active layer wafer 40 is chamfered to reduce its thickness. As a result, a silicon residue portion remains below the outer peripheral region of the second active layer wafer 40 (FIG. 4 (E)). Subsequently, this silicon residue portion is removed by etching treatment (FIG. 4 (F)). After that, the second active layer wafer is ground and polished to fabricate a multilayer SOI wafer 300 having the second active layer 44 having a desired thickness (FIG. 4G).

  However, in the multi-layered SOI wafer 300 manufactured by the above procedure, the second active layer is further laminated on the first active layer whose effective area is reduced due to the formation of the terrace portion 34 with the second oxide film interposed therebetween. Therefore, there is a problem that the effective area of the second active layer is smaller than the effective area of the first active layer.

  When the first active layer wafer 20 shown in FIG. 5 (F) is ground to reduce its thickness, the end surface of the first active layer obtained by grinding has an angular shape. When the surface of the first active layer in such a state is polished, the polishing pad largely sinks at the outer peripheral edge of the first active layer, and a load is intensively applied. Therefore, at the outer peripheral edge of the first active layer 22 after polishing shown in FIG. 5G, polishing is promoted as compared with the central portion, and peripheral sag occurs, so that the flatness of the first active layer 22 is flattened. Will be low. Referring also to FIG. 4, the second active layer 44 grinds and polishes the second active layer wafer 40 laminated on the first active layer 22 having such low flatness via the second oxide film 24. Obtained. Therefore, it has been found that the flatness of the second active layer 44 is worse than the flatness of the first active layer 22, and as a result, the in-plane thickness variation of the second active layer 44 becomes large.

  Therefore, in view of the above problems, the present invention provides a multi-layered SOI wafer having a large area of a device-formable region in the second active layer and having a small in-plane thickness variation of the second active layer, and a method for manufacturing the same. The purpose is to

The gist of the present invention for solving the above problems is as follows.
(1) A multi-layer SOI wafer in which a first oxide film, a first active layer, a second oxide film, and a second active layer are laminated on a supporting substrate,
Of the end faces of the multilayer SOI wafer, the end face composed of the end face of the support substrate, the end face of the first oxide film, and the end face of the first active layer has a continuous round shape in a cross section in the wafer thickness direction. A multi-layer SOI wafer.

  (2) The multilayer SOI wafer according to (1) above, which has a terrace portion where the second active layer does not exist above the outer peripheral region of the first active layer.

  (3) The multilayer SOI wafer according to (1) or (2) above, wherein the in-plane thickness variation of the second active layer is 0.40 μm or less.

(4) A first oxide film and a first active layer are stacked on a support substrate, and the end face of the support substrate, the end face of the first oxide film, and the end face of the first active layer are formed. A first step of forming an SOI wafer having a rounded end face in the wafer thickness direction,
A second step of forming a second oxide film on the surface of the first active layer or the surface of the second active layer wafer, or on the surface of the first active layer and the surface of the second active layer wafer;
The SOI wafer and the second active layer wafer are overlapped with each other with the second oxide film interposed therebetween, and a bonding heat treatment is performed to bond the SOI wafer and the second active layer wafer to each other. A third step of forming a bonded wafer,
A fourth step of reducing the thickness of the bonded wafer from the second active layer wafer side to obtain a multilayer SOI wafer having a second active layer;
A method of manufacturing a multi-layered SOI wafer, comprising:

  (5) Prior to the thickness reduction in the fourth step, an unbonded region generated outside the outer periphery of the bonding surface between the SOI wafer and the second active layer wafer in the third step is removed. Further, a step of performing a chamfering process and an etching process on an outer peripheral region of the second active layer wafer to form a terrace portion where the second active layer wafer does not exist above the outer peripheral region of the first active layer. The method for manufacturing a multi-layered SOI wafer according to (4) above.

(6) The first step is
The surface or a part of the wafer for a supporting substrate to be the supporting substrate is the surface of the first active layer wafer to be the first active layer, or the surface of the supporting substrate wafer and the surface of the first active layer wafer. Step A of forming the first oxide film on
The support substrate wafer and the first active layer wafer are superposed on each other with the first oxide film interposed therebetween, and a bonding heat treatment is performed to bond the support substrate wafer and the first active layer wafer. Together, step B of forming a wafer composite,
A chamfering process is performed on the end face of the wafer composite, and the end face of the support substrate, the end face of the first oxide film, and the end face of the portion of the wafer for the first active layer to be the first active layer are removed. A step C of forming a part of the end face of the wafer composite into a continuous round shape in a cross section in the wafer thickness direction,
After the step C, a step D of reducing the thickness of the wafer composite from the first active layer wafer side to form the SOI wafer having the first active layer,
The method for producing a multilayer SOI wafer according to (4) or (5) above, which further comprises:

  (7) After the step C and before the step D, a part of the end surface of the wafer composite is subjected to an alkali etching treatment to remove a processing strain caused by the chamfering processing in the step C. The method for manufacturing a multilayer SOI wafer according to (6), further including a step of removing.

  (8) After the step of removing the processing strain, but before the step D, a chamfering tape having abrasive grains attached is pressed against a part of the end surface of the wafer composite to obtain the wafer. The method for producing a multi-layered SOI wafer according to (7), further including a step of performing a tape chamfering process for grinding a part of the end surface of the wafer composite by sliding along the end surface of the composite. Method.

  (9) The method further comprising a step of performing an additional alkali etching treatment on a part of the end surface of the wafer composite after the step of performing the tape chamfering process and before the step D. A method for manufacturing a multi-layered SOI wafer according to item 1.

  (10) The method according to (9), further including a step of polishing a part of the end face of the wafer composite after the step of performing the additional alkali etching treatment and before the step D. Method for manufacturing multi-layer SOI wafer.

  According to the present invention, it is possible to obtain a multi-layered SOI wafer in which the area of a device-formable region in the second active layer is large and the variation in the in-plane thickness of the second active layer is small.

FIG. 3 is a schematic cross-sectional view explaining the method for manufacturing the multilayer-film SOI wafer 100 according to the first embodiment of the present invention. It is a schematic cross section for explaining the manufacturing method of multilayered film SOI wafer 200 according to the second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a terrace-free SOI wafer 30 that can be used in the present invention. FIG. 11 is a schematic cross-sectional view illustrating a method for manufacturing a conventional multilayer SOI wafer 300. FIG. 6 is a schematic cross-sectional view explaining the method of manufacturing the SOI wafer 32 having the terrace portion 34.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In principle, the same constituent elements in each embodiment are designated by the same reference numerals, and the repetitive description will be omitted. Further, in FIGS. 1 to 5, for convenience of description, unlike the actual thickness ratio, the support substrate wafer 10, the first active layer wafer 20, the SOI wafer 30, and the second active layer wafer 40 are different from each other. , The thicknesses of the first oxide film 12 and the second oxide films 24 and 26 are exaggerated.

(Multilayer SOI wafer)
First, referring to FIGS. 1 and 2, a multilayer SOI wafer 100, 200 according to an embodiment of the present invention will be described. In the multi-layered SOI wafers 100 and 200, the first oxide film 12, the first active layer 22, the second oxide films 24 and 26, and the second active layer 44 are laminated on the support substrate 10. Further, among the end faces of the multi-layered SOI wafers 100 and 200, the end face formed of the end face of the support substrate 10, the end face of the first oxide film 12, and the end face of the first active layer 22 are continuous in the wafer thickness direction. It is characterized by a round shape. In addition, the multilayer SOI wafers 100 and 200 have the terrace portion 35 above the outer peripheral region of the first active layer 22 as shown in FIGS. Here, the terrace portion 35 means the second active layer 44 (for the second active layer) so that the second active layer 44 (for the second active layer wafer 40) does not exist above the outer peripheral region of the first active layer 22. The outer peripheral region of the wafer 40) is meant to be removed. The “outer peripheral region of the first active layer” in the present specification refers to a region of 1 to 3 mm radially inward from the outermost peripheral edge of the first active layer wafer, and refers to the “second active layer (second active layer)”. The "outer peripheral region of the layer wafer)" refers to a region of 1 to 3 mm radially inward from the outermost peripheral end of the second active layer wafer.

  According to the multi-layered SOI wafers 100 and 200, the area of the device-formable region in the second active layer 44 can be increased. For example, when a wafer having a diameter of 200 mm is used as the supporting substrate wafer, the first active layer wafer, and the second active layer wafer, the effective area of the first active layer is 194 mm and the effective area of the second active layer is 190 mm. Become. Further, the in-plane thickness variation of the second active layer 44 can be suppressed to 0.40 μm or less. The reasons for these will be described later.

  Here, the support substrate 10 has a thickness of 400 μm or more and 725 μm or less, the first oxide film 12 has a thickness of 0.1 μm or more and 3 μm or less, and the first active layer 22 has a thickness of 1 μm or more and 100 μm or less. The thickness of the second oxide films 24 and 26 is preferably 0.1 μm or more and 3 μm or less, and the thickness of the second active layer 44 is preferably 1 μm or more and 100 μm or less.

  In addition, the support substrate 10, the first active layer 22, and the second active layer 44 can be manufactured from a single crystal silicon wafer. Furthermore, an arbitrary impurity may be added to this wafer to make it n-type or p-type. Further, at least one of the support substrate 10, the first active layer 22, and the second active layer 44 may be manufactured from a polished wafer.

  The multilayer film SOI wafer of the present invention has been described above by taking the multilayer film SOI wafers 100 and 200 as an example. However, the multilayer film SOI wafer of the present invention is not limited to this, and appropriate changes are made within the scope of the claims. be able to.

(Method for manufacturing multi-layered SOI wafer)
Hereinafter, an example of a method of manufacturing the above-described multilayer SOI wafers 100 and 200 will be described with reference to FIGS.

(First embodiment)
First, with reference to FIG. 1, a method of manufacturing the multilayer SOI wafer 100 according to the first embodiment of the present invention will be described. In this embodiment, first, the SOI wafer 30 in which the first oxide film 12 and the first active layer 22 are stacked on the support substrate 10 is formed. At this time, the end surface composed of the end surface of the support substrate 10, the end surface of the first oxide film 12, and the end surface of the first active layer 22 is processed into a continuous round shape in a cross section in the wafer thickness direction (first step). ). Next, the second oxide film 24 is formed on the surface 22A of the SOI wafer 30 on the first active layer 22 side (second step). Next, the SOI wafer 30 and the second active layer wafer 40 are superposed on each other with the second oxide film 24 interposed therebetween. That is, the SOI wafer 30 and the second active layer wafer 40 are superposed so that the second oxide film 24 is located between the surface 22A of the first active layer and the surface 40A of the second active layer wafer. After that, a bonding heat treatment is performed to bond the SOI wafer 30 and the second active layer wafer 40 to form a bonded wafer 42 (third step). Next, in the third step, the non-bonded region generated outside the outer circumference of the bonding surface between the SOI wafer 30 and the second active layer wafer 40 is removed. That is, the peripheral area of the second active layer wafer 40 is reduced in thickness by chamfering. As a result, a silicon residue portion remains below the outer peripheral region of the second active layer wafer 40. Subsequently, this silicon residue portion is removed by etching. When the unbonded region is removed in this manner, the terrace portion 35 is formed in which the second active layer wafer 40 is removed so that the second active layer wafer 40 does not exist above the outer peripheral region of the first active layer 22. To be done. Next, the thickness of the bonded wafer 42 is reduced from the second active layer wafer 40 side to obtain the multi-layered SOI wafer 100 having the second active layer 44 (fourth step).

  In this multi-layered SOI wafer 100, a first oxide film 12, a first active layer 22, a second oxide film 24, and a second active layer 44 are laminated on a support substrate 10.

(Second embodiment)
Next, with reference to FIG. 2, a method of manufacturing the multilayer SOI wafer 200 according to the second embodiment of the present invention will be described. In this embodiment, first, the SOI wafer 30 in which the first oxide film 12 and the first active layer 22 are stacked on the support substrate 10 is formed. At this time, the end surface composed of the end surface of the support substrate 10, the end surface of the first oxide film 12, and the end surface of the first active layer 22 is processed into a continuous round shape in a cross section in the wafer thickness direction (first step). ). Next, the second oxide film 26 is formed on the surface 40A of the second active layer wafer 40 (second step). Next, the SOI wafer 30 and the second active layer wafer 40 are superposed on each other with the second oxide film 26 interposed therebetween. That is, the SOI wafer 30 and the second active layer wafer 40 are superposed so that the second oxide film 26 is located between the surface 22A of the first active layer and the surface 40A of the second active layer wafer. After that, a bonding heat treatment is performed to bond the SOI wafer 30 and the second active layer wafer 40 to form a bonded wafer 42 (third step). Next, in the third step, the non-bonded region that is formed outside the outer periphery of the bonding surface between the SOI wafer 30 and the second active layer wafer 40 is removed. That is, the peripheral area of the second active layer wafer 40 is reduced in thickness by chamfering. As a result, a silicon residue portion remains under the outer peripheral region of the second active layer wafer 40. Subsequently, this silicon residue portion is removed by etching. When the unbonded region is removed in this manner, the terrace portion 35 is formed in which the second active layer wafer 40 is removed so that the second active layer wafer 40 does not exist above the outer peripheral region of the first active layer 22. To be done. Next, the thickness of the bonded wafer 42 is reduced from the second active layer wafer 40 side to obtain the multilayer SOI wafer 200 having the second active layer 44 (fourth step).

  In this multi-layered film SOI wafer 200, a first oxide film 12, a first active layer 22, a second oxide film 26, and a second active layer 44 are laminated on a support substrate 10.

(First step: formation of SOI wafer)
In the first step, referring to FIGS. 1 and 2, an SOI wafer 30 in which a first oxide film 12 and a first active layer 22 are stacked on a support substrate 10 is formed. At this time, the end surface composed of the end surface of the support substrate 10, the end surface of the first oxide film 12, and the end surface of the first active layer 22 is processed into a continuous round shape in a cross section in the wafer thickness direction. Here, the wafer thickness direction cross section is a cross section that passes through the wafer center axis and does not pass through the notch portion of the wafer. In this specification, the SOI wafer 30 obtained in the first step is also referred to as a "terrace-free SOI wafer 30". Hereinafter, an example of a method of manufacturing the terrace-free SOI wafer 30 will be described with reference to FIG.

(Step A: formation of first oxide film)
In step A, the first oxide film 12 is formed on the surface of the supporting substrate wafer 10. The thickness of the first oxide film 12 is preferably 0.1 μm or more and 3 μm or less. Here, the method for forming the first oxide film 12 is not particularly limited, and for example, a known thermal oxidation method can be preferably used. In this case, the thermal oxidation conditions are preferably 900 ° C. or more and 1200 ° C. or less and 30 minutes or more and 2 hours or less in an oxygen atmosphere. The first oxide film 12 may be formed on the surface of the first active layer wafer 20, or may be formed on the surfaces of both the supporting substrate wafer 10 and the first active layer wafer 20. .. The diameter of the support substrate wafer 10 and the first active layer wafer 20 is preferably 200 mm.

(Process B: Formation of Wafer Complex)
In step B, the supporting substrate wafer 10 and the first active layer wafer 20 are superposed with the first oxide film 12 interposed therebetween. That is, the support substrate wafer 10 and the first active layer wafer 20 are stacked so that the first oxide film 12 is located between the surface of the support substrate wafer 10 and the surface of the first active layer wafer 20. To match. After that, a bonding heat treatment is performed to bond the support substrate wafer 10 and the first active layer wafer 20 to each other to form a wafer composite 36. Here, the bonding heat treatment is preferably performed in an oxidizing gas or inert gas atmosphere at a wafer temperature of 400 ° C. or more and 1200 ° C. or less for 10 minutes or more and 6 hours or less. By setting the wafer temperature to 400 ° C. or higher, sufficient bonding strength can be obtained, and by setting the wafer temperature to 1200 ° C. or lower, the occurrence of slip can be suppressed.

(Process C: Chamfering)
After step B, an unbonded region is formed outside the outer periphery of the bonding surface between the supporting substrate wafer 10 and the first active layer wafer 20, but this unbonded region is left as it is. Then, it may cause the wafer to be chipped or broken in the later process. Therefore, in step C, the non-bonded region is removed by performing the following processing. That is, the end surface of the wafer composite 36 is chamfered so that the end surface of the support substrate 10, the end surface of the first oxide film 12, and the portion of the first active layer wafer 20 to be the first active layer 22 later. A part of the end face of the wafer composite 36, which is composed of the end face, is formed into a continuous round shape in a cross section in the wafer thickness direction. As a result, the unbonded region can be removed without performing the terrace processing shown in FIGS. The action and effect obtained by removing the unbonded region by chamfering the round end face in this way will be described later.

  For the chamfering process in the step C, a known flat grindstone capable of grinding the end surface of the wafer composite 36, a grindstone capable of forming the above-mentioned end surface shape, or the like can be preferably used. Further, from the viewpoint of suppressing the warp of the wafer composite 36, it is preferable to leave the oxide film on the front and back surfaces of the wafer composite 36 as shown in FIG.

  Next, after step C but before step D, an alkali etching treatment, a tape chamfering treatment, an additional alkali etching treatment, and polishing described below are performed. Note that these processes are not essential.

(Alkaline etching treatment)
First, a part of the end face of the wafer composite 36 is subjected to alkali etching treatment. Here, due to the chamfering process in the process C, a processing strain is introduced into the end surface of the wafer composite body 36. This processing strain causes the chipping or cracking of the wafer in the subsequent steps. Therefore, this processing strain is removed by subjecting part of the end surface of the wafer composite 36 to alkali etching. Furthermore, according to the alkali etching treatment, unlike the case of the acid etching treatment, only silicon can be selectively etched. That is, even when the etching liquid contacts the oxide film left on the front and back surfaces of the wafer composite 36, the oxide film remains without being etched. Therefore, during this etching process, it is not necessary to protect the oxide film left on the front and back surfaces of the wafer composite body 36 so that the oxide film is not exposed to the etching solution. The processing strain can be easily removed by the above method.

  The etching allowance in the alkaline etching treatment may be such that the processing strain can be removed, and specifically, it is preferably 30 μm or less. The etching solution used for the alkaline etching treatment is not particularly limited as long as it is an alkaline etching solution having a large etching rate selectivity between silicon and an oxide film, and specifically, a KOH aqueous solution, a NaOH aqueous solution, tetramethyl hydroxide is used. An ammonium (TMAH) aqueous solution or the like can be preferably used.

(Tape chamfering)
The above processing strain can be removed by performing an alkali etching process. However, due to the anisotropy and selectivity of the alkali etching, the shape of the end face of the wafer composite 36 after the alkali etching treatment is slightly distorted and the flatness is poor. Therefore, from the viewpoint of improving the flatness of the end surface of the wafer composite 36 after the alkali etching treatment, it is preferable to perform a tape chamfering process on a part of the end surface of the wafer composite 36. Here, the tape chamfering process is performed by pressing a chamfering tape to which abrasive grains are attached onto a part of the end surface of the wafer composite 36 and sliding the tape along the end surface of the wafer composite 36. The grain size of the abrasive grains is preferably # 1000 to # 3000.

(Additional alkali etching treatment)
From the viewpoint of removing damage caused by tape chamfering, it is preferable to perform additional alkali etching treatment. The etching allowance is preferably about 3 μm.

(Polishing)
From the viewpoint of further improving the flatness of the end surface of the wafer composite 36, it is preferable to polish a part of the end surface of the wafer composite 36 after the additional etching treatment. For the polishing here, an arbitrary or known polishing method can be preferably used, and examples thereof include a mirror surface polishing method.

(Process D: Formation of First Active Layer)
Next, in step D, the thickness of the wafer composite 36 is reduced from the first active layer wafer 20 side to form the SOI wafer 30 having the first active layer 22. The thickness of the first active layer 22 is preferably 1 μm or more and 100 μm or less. For the thickness reduction, any known or known grinding method or polishing method can be preferably used, and examples thereof include a surface grinding method and a mirror surface polishing method. Also, other techniques such as the well-known Smart Cut method (registered trademark) may be used. Referring to FIG. 3, the SOI wafer 30 thus obtained has a structure in which the first oxide film 12 and the first active layer 22 are stacked on the support substrate 10. In addition, the end surface composed of the end surface of the support substrate 10, the end surface of the first oxide film 12, and the end surface of the first active layer has a continuous round shape in the wafer thickness direction cross section.

  Below, the effects obtained by manufacturing the terrace-free SOI wafer 30 through steps A to D will be described. With reference to FIG. 3, the end surface of the terrace-free SOI wafer 30 has a continuous round shape in a cross section in the wafer thickness direction. In particular, when the second active layer wafer 20 shown in step C is ground and reduced in thickness, the end surface of the first active layer obtained by grinding has an angular shape unlike the case of the SOI wafer 32 having the terrace portion 34. is not. Therefore, when the surface of the first active layer in such a state is polished, sinking of the polishing pad at the outer peripheral edge of the first active layer is suppressed, and the load applied to the outer peripheral edge of the first active layer is suppressed. To be done. Therefore, the outer peripheral sag in the first active layer 22 after polishing can be suppressed. In addition, in the terrace-free SOI wafer 30, the unbonded region is removed by chamfering the round end face in step C instead of forming the terrace portion. Therefore, the area of the effective area of the first active layer 22 can be increased as compared with the SOI wafer 32 having the terrace portion 34 shown in FIG.

  Although an example of a specific method for manufacturing the terrace-free SOI wafer 30 has been described above, the method for manufacturing the terrace-free SOI wafer according to the present invention is not limited to this, and can be appropriately modified within the scope of the claims. ..

(Second step: formation of second oxide film)
In the second step, as shown in FIG. 1, the second oxide film 24 is formed on the surface 22A of the SOI wafer 30 on the first active layer 22 side. Alternatively, as shown in FIG. 2, the second oxide film 26 is formed on the surface 40A of the second active layer wafer 40. The thickness of the second oxide films 24 and 26 is preferably 0.1 μm or more and 3 μm or less. Here, the method of forming the second oxide films 24 and 26 is not particularly limited, and for example, a known thermal oxidation method can be preferably used. In this case, the thermal oxidation conditions are preferably 900 ° C. or more and 1200 ° C. or less and 30 minutes or more and 2 hours or less in an oxygen atmosphere. As another embodiment of the present invention, the second oxide film may be formed on both the surface of the SOI wafer 30 and the surface of the second active layer wafer 40. The diameter of the second active layer wafer is preferably 200 mm.

(Third step: formation of bonded wafer)
In the third step, as shown in FIGS. 1 and 2, the SOI wafer 30 and the second active layer wafer 40 are superposed with the second oxide films 24 and 26 interposed therebetween. That is, the second oxide films 24 and 26 are located between the surface 22A of the first active layer and the surface 40A of the second active layer wafer 40. Thereafter, a bonding heat treatment is performed to bond the SOI wafer 30 and the second active layer wafer 40 to form a bonded wafer 42. The bonding heat treatment is preferably performed in an oxidizing gas or inert gas atmosphere at a wafer temperature of 400 ° C. to 1200 ° C. for 10 minutes to 6 hours. By setting the wafer temperature to 400 ° C. or higher, sufficient bonding strength can be obtained, and by setting the wafer temperature to 1200 ° C. or lower, the occurrence of slip can be suppressed.

(Chamfering and etching)
Here, as shown in FIGS. 1 and 2, an unbonded region is formed outside the outer periphery of the bonding surface of the bonded wafer 42 by the third step. This may cause the wafer to chip or break during the process. Therefore, the unbonded region is removed by the method described below before the thickness reduction in the fourth step. First, the peripheral area of the second active layer wafer 40 is chamfered to reduce its thickness. As a result, a silicon residue portion remains below the outer peripheral region of the second active layer wafer 40. The thickness of the silicon residue portion is preferably about 5 to 50 μm from the bonding surface of the SOI wafer 30 and the second active layer wafer 40 toward the second active layer wafer 40. Subsequently, this silicon residue portion is removed by etching. By removing the unbonded area in this manner, the terrace portion 35 is formed above the outer peripheral area of the first active layer 22. That is, the terrace portion 35 means a region in which the outer peripheral region of the second active layer wafer 40 is removed so that the second active layer wafer 40 does not exist above the outer peripheral region of the first active layer 22. .. A known chamfering apparatus can be preferably used for the chamfering process, and an arbitrary or known etching solution can be preferably used for the etching.

(Fourth step: formation of second active layer)
In the fourth step, as shown in FIGS. 1 and 2, the thickness of the bonded wafer 42 is reduced from the second active layer wafer 40 side, and the multilayer SOI wafer 100 having the second active layer 44 having a desired thickness is obtained. Form 200. The desired thickness of the second active layer 44 is preferably 1 μm or more and 100 μm or less. The multilayer film SOI wafers 100 and 200 obtained in this way have an end surface composed of the end surface of the support substrate 10, the end surface of the first oxide film 12, and the end surface of the first active layer 22 among the end surfaces. The wafer has a continuous round shape in the cross section in the thickness direction. For the thickness reduction, an arbitrary or known grinding method or polishing method can be preferably used, and examples thereof include a surface grinding method and a mirror surface polishing method. Also, other techniques such as the well-known Smart Cut method (registered trademark) may be used.

  Below, the operation effect obtained by this embodiment is explained. First, by using the terrace-free SOI wafer 30 obtained through the steps A to D as described above, compared with the case of using the SOI wafer 32 having the terrace portion 34 shown in FIG. The outer peripheral sag in the active layer 22 is suppressed. The area of the effective area in the first active layer 22 is also increasing. Therefore, the in-plane thickness variation of the second active layer 44 laminated on the first active layer 22 through the second oxide films 24 and 26 through the second to fourth steps is suppressed to 0.40 μm or less. can do. Further, the area of the effective area in the second active layer 44 can be increased as the area of the effective area in the first active layer 22 is increased. For example, when a wafer having a diameter of 200 mm is used as the supporting substrate wafer, the first active layer wafer, and the second active layer wafer, the effective area of the first active layer is 194 mm and the effective area of the second active layer is 190 mm. Become.

  In addition, the following additional effects can be obtained in this embodiment. First, in the multi-layered film SOI wafers 100 and 200, the unbonded regions that are generated during the manufacturing process are removed as described above. Therefore, according to this embodiment, the wafer is not chipped or cracked in the subsequent steps.

  Furthermore, in the technique described in Patent Document 1, oxygen ions are implanted into the first active layer wafer and the second active layer wafer when forming the first oxide film and the second oxide film. A crystal defect due to is formed in the first active layer and the second active layer. A region having such a crystal defect cannot be used as a device formation region. Therefore, in the technique described in Patent Document 1, the device formation region in the first active layer and the second active layer becomes narrow. There is. On the other hand, in the present embodiment, the ion implantation is not performed for forming the first oxide film and the second oxide film, and the crystal defect due to the ion implantation is not formed. Therefore, it is possible to secure a wider area for device formation in the first active layer and the second active layer than in the conventional case.

(Support substrate wafer, first active layer wafer, second active layer wafer)
As the support substrate wafer 10, the first active layer wafer 20 and the second active layer wafer 40 of the present invention, single crystal silicon wafers can be used. As the single crystal silicon wafer, a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) sliced with a wire saw or the like can be used. Furthermore, these wafers may be made into n-type or p-type by adding arbitrary impurities.

  At least one of the support substrate 10, the first active layer 22, and the second active layer 44 is preferably made of a polished wafer. Here, the polished wafer can be obtained by polishing the above-mentioned single crystal silicon wafer with abrasive grains and subjecting it to a surface treatment by a chemical method.

  The method for manufacturing the multilayer SOI wafer according to the present invention has been described above by taking the first and second embodiments as an example. However, the method for manufacturing the multilayer SOI wafer according to the present invention is not limited to the above-described embodiment. Modifications can be appropriately made within the scope of the claims.

  Specifically, the chamfering process and the etching process performed after the third step but before the fourth step can be replaced by other known or arbitrary methods, for example, the terrace polishing method. May be. When the terrace polishing method is used, the thickness of the second active layer wafer constituting the bonded wafer is reduced by a known surface grinding method, and then the second active layer is obliquely inclined with respect to the surface of the second active layer wafer. The outer peripheral region of the wafer for polishing is polished by a known polishing method. In this way, the unbonded area is removed.

(Invention Example 1)
According to the procedure shown in FIGS. 1 and 3, the multilayer film SOI wafer of Inventive Example 1 was produced.

  First, as the wafer for the supporting substrate, the wafer for the first active layer, and the wafer for the second active layer, polished wafers prepared from silicon wafers obtained from CZ single crystal silicon ingots were prepared. The diameter of these wafers was 200 mm and the thickness was 725 μm.

  Next, a first oxide film was formed on the surface of the supporting substrate wafer by a thermal oxidation method. The thickness of the first oxide film was 1 μm. Next, after the wafer for the supporting substrate and the wafer for the first active layer are superposed on each other with the first oxide film interposed therebetween, a bonding heat treatment is performed to bond the wafer for the supporting substrate and the wafer for the first active layer to each other. , Formed a wafer composite. The conditions of the bonding heat treatment were 1150 ° C. and 2 hours in an oxygen atmosphere. Next, the end surface of the wafer composite was chamfered as shown in step C of FIG. 3 to make a part of the end surface of the wafer composite into a round end surface.

  Next, an alkali etching treatment was applied to a part of the end surface of the wafer composite. The stock removal by alkali etching was 15 μm. Next, the tape chamfering process described above was applied to a part of the end face of the wafer composite. The grain size of the abrasive grains attached to the chamfering tape was # 3000. Next, an additional alkali etching treatment was applied to a part of the end surface of the wafer composite. The etching allowance in this additional alkali etching treatment was 3 μm. Next, a part of the end surface of the wafer composite was polished.

  Next, the wafer composite was ground and polished from the first active layer wafer side to form a terrace-free SOI wafer having a round end face as shown in FIG. The thickness of the first active layer was 5 μm.

  Next, a second oxide film was formed on the surface of the terrace-free SOI wafer on the side of the first active layer by the thermal oxidation method. The thickness of the second oxide film was 1 μm.

  Next, the terrace-free SOI wafer and the wafer for the second active layer are overlapped with each other with the second oxide film interposed therebetween, and a bonding heat treatment is performed to bond the terrace-free SOI wafer and the wafer for the second active layer. , A bonded wafer was formed. The conditions of the bonding heat treatment were 1150 ° C. and 2 hours in an oxygen atmosphere.

  Next, after removing the unbonded area generated outside the outer periphery of the bonded surface of the bonded wafer by the chamfering process and the etching treatment shown in FIG. 1, the bonded wafer is ground and polished from the second active layer wafer side. Then, a multi-layered SOI wafer having a second active layer with a thickness of 5 μm was formed.

(Invention Example 2)
A multilayer film SOI wafer was produced in the same manner as in Inventive Example 1, except that the thickness of the second active layer was 1 μm.

(Comparative Example 1)
Next, according to the procedure shown in FIGS. 4 and 5, a multilayer film SOI wafer 300 of a comparative example was manufactured.

  First, as the wafer for the supporting substrate, the wafer for the first active layer, and the wafer for the second active layer, the same wafers as the invention examples were prepared.

  Next, a first oxide film was formed on the surface of the supporting substrate wafer by the thermal oxidation method (FIGS. 5A and 5B). The thickness of the first oxide film was 1 μm. Next, after the wafer for the supporting substrate and the wafer for the first active layer are superposed on each other with the first oxide film interposed therebetween, a bonding heat treatment is performed to bond the wafer for the supporting substrate and the wafer for the first active layer to each other. , A wafer composite was formed (FIGS. 5C and 5D). The conditions of the bonding heat treatment were 1150 ° C. and 2 hours in an oxygen atmosphere. Next, terrace processing and grinding and polishing shown in FIGS. 5D to 5G were performed to obtain an SOI wafer having a terrace portion. Here, the radial width of the terrace portion was 1.5 mm inward in the radial direction from the outermost peripheral edge of the support substrate. The thickness of the first active layer was 5 μm.

  Next, a second oxide film was formed on the surface of the SOI wafer on the first active layer side (FIGS. 4A and 4B). The thickness of the second oxide film was 1 μm. Next, after the SOI wafer and the second active layer wafer are superposed on each other with the second oxide film interposed therebetween, a bonding heat treatment is performed to bond the SOI wafer and the second active layer wafer to each other to obtain a bonded wafer. Was formed (FIGS. 4C and 4D). The conditions of the bonding heat treatment were 1150 ° C. and 2 hours in an oxygen atmosphere. Next, chamfering etching, grinding, and polishing shown in FIGS. 4E to 4G were performed to obtain a multilayer film SOI wafer 300 having a second active layer with a thickness of 5 μm.

(Comparative example 2)
A multilayer SOI wafer was produced in the same manner as in Comparative Example 1 except that the thickness of the second active layer was 1 μm.

(Evaluation methods)
For each of Invention Examples 1 and 2 and Comparative Examples 1 and 2, the in-plane thickness variation of the first active layer and the second active layer was evaluated. Here, “in-plane thickness variation” means the above when the center point of the surface of the active layer and the radius of the surface of the active layer are R for each of the first active layer and the second active layer. Of the thickness of the active layer at 9 points, the maximum of the thickness of the active layer is 4 points that divides the circumference of the radius R / 2 centered on the center point into 4 equal parts It means the difference between the value and the minimum value. Here, the thickness of each active layer was measured using a film thickness measuring instrument to which Fourier Transform Infrared Spectroscopy (FTIR) was applied. The evaluation results are shown in Table 1. In addition, in each of Invention Examples 1 and 2 and Comparative Examples 1 and 2, the size of the device-formable region (effective area) in the first active layer and the second active layer was evaluated. The diameter of the effective area in the first active layer and the second active layer was used as the evaluation index. The evaluation results are shown in Table 1.

(Explanation of evaluation results)
In Invention Examples 1 and 2, the effective area of the first active layer was larger than that of Comparative Examples 1 and 2, and the effective area of the second active layer could be increased. Further, in Inventive Examples 1 and 2, in-plane thickness variation of the first active layer could be suppressed more than in Comparative Examples 1 and 2, so that in-plane thickness variation of the second active layer should be significantly suppressed. I was able to.

  According to the present invention, it is possible to obtain a multi-layered SOI wafer in which the area of a device-formable region in the second active layer is large and the variation in the in-plane thickness of the second active layer is small.

100,200 Multi-layer SOI wafer 10 Wafer for supporting substrate (supporting substrate)
12 First Oxide Film 20 Wafer for First Active Layer 22 First Active Layer 22A Surface of First Active Layer 24, 26 Second Oxide Film 30 Terrace Free SOI Wafer 35 Terrace Part 36 Wafer Complex 40 Wafer for Second Active Layer 40A Surface of second active layer wafer 42 Bonded wafer 44 Second active layer

Claims (9)

A multi-layered SOI wafer in which a first oxide film, a first active layer, a second oxide film, and a second active layer are stacked on a supporting substrate,
Of the end faces of the multilayer SOI wafer, the end face composed of the end face of the support substrate, the end face of the first oxide film, and the end face of the first active layer has a continuous round shape in a cross section in the wafer thickness direction. der is,
Multilayer film SOI wafer, comprising Rukoto to have a terrace portion of the second active layer is not present in the peripheral region above the first active layer. The multilayer SOI wafer according to claim 1, wherein the in-plane thickness variation of the second active layer is 0.40 μm or less. A first oxide film and a first active layer are laminated on a support substrate, and an end face composed of the end face of the support substrate, the end face of the first oxide film, and the end face of the first active layer is formed. A first step of forming a continuous round SOI wafer in a cross section in the wafer thickness direction,
A second step of forming a second oxide film on the surface of the first active layer or the surface of the second active layer wafer, or on the surface of the first active layer and the surface of the second active layer wafer;
The SOI wafer and the second active layer wafer are overlapped with each other with the second oxide film interposed therebetween, and a bonding heat treatment is performed to bond the SOI wafer and the second active layer wafer to each other. A third step of forming a bonded wafer,
A fourth step of reducing the thickness of the bonded wafer from the second active layer wafer side to obtain a multilayer SOI wafer having a second active layer;
A method of manufacturing a multi-layered SOI wafer, comprising: Before the thickness reduction in the fourth step, the non-bonded region generated outside the outer periphery of the bonding surface between the SOI wafer and the second active layer wafer in the third step is removed. The method further includes chamfering and etching the outer peripheral region of the second active layer wafer to form a terrace portion above the outer peripheral region of the first active layer where the second active layer wafer does not exist. Item 4. A method for manufacturing a multi-layered SOI wafer according to Item 3 . The first step is
The surface or a part of the wafer for a supporting substrate to be the supporting substrate is the surface of the first active layer wafer to be the first active layer, or the surface of the supporting substrate wafer and the surface of the first active layer wafer. Step A of forming the first oxide film on
The support substrate wafer and the first active layer wafer are superposed on each other with the first oxide film interposed therebetween, and a bonding heat treatment is performed to bond the support substrate wafer and the first active layer wafer. Together, step B of forming a wafer composite,
A chamfering process is performed on the end face of the wafer composite, and the end face of the support substrate, the end face of the first oxide film, and the end face of the portion of the wafer for the first active layer to be the first active layer are removed. A step C of forming a part of the end face of the wafer composite into a continuous round shape in a cross section in the wafer thickness direction,
After the step C, a step D of reducing the thickness of the wafer composite from the first active layer wafer side to form the SOI wafer having the first active layer,
The a method for producing a multilayer SOI wafer according to claim 3 or 4. After the step C but before the step D, a step of performing an alkali etching treatment on a part of the end surface of the wafer composite to remove a processing strain caused by the chamfering processing in the step C. The method for manufacturing a multi-layer SOI wafer according to claim 5 , further comprising: After the step of removing the processing strain and before the step D, a chamfering tape to which abrasive grains are attached is pressed against a part of the end face of the wafer composite to remove the wafer composite. The method for producing a multilayer SOI wafer according to claim 6 , further comprising a step of performing a tape chamfering process for grinding a part of the end surface of the wafer composite by sliding along the end surface. The multilayer according to claim 7 , further comprising a step of performing an additional alkali etching treatment on a part of the end surface of the wafer composite after the step of performing the tape chamfering process and before the step D. Method for manufacturing a film SOI wafer. The multilayer SOI wafer according to claim 8 , further comprising a step of polishing a part of the end surface of the wafer complex after the step of performing the additional alkali etching treatment and before the step D. Manufacturing method.

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