JP6699499B2 - filter - Google Patents

Description

  The present invention relates to a filter including an ESD protection element and a common mode choke coil.

  For example, in a high-speed serial interface, a "differential transmission system" that transmits signals whose phases are different by 180° on a balanced line is used. In the differential transmission method, radiation noise and external noise are canceled by the balanced line, so that they are less likely to be affected by these noises. However, depending on the usage environment, a common mode noise current is generated due to the asymmetry of the signal line and the like. A common mode filter is used to suppress such common mode noise.

  Further, in a high-speed serial interface, an ESD protection element is used to protect an electronic circuit from external ESD (Electro-Static Discharge).

  For example, Patent Document 1 discloses a common mode filter with an ESD protection circuit, which includes an ESD protection element and a common mode choke coil.

International Publication No. 2016/080108

  Since the common mode filter with an ESD protection circuit is a circuit in which the common mode filter and the ESD protection element are connected by some kind of wiring, it has an inductive component (parasitic inductance) generated in its wiring portion. Further, the ESD protection element has a capacitive component (parasitic capacitance) in its structure in a normal state where the operating voltage is not reached. Therefore, the common mode filter with the ESD protection circuit also includes the capacitance component of the ESD protection element.

  Since the inductive component and the capacitive component affect the original characteristics of the common mode filter, the filter characteristics in the actual use state are different from the characteristics of the common mode filter alone. Further, if the ESD protection element is downsized in order to reduce the parasitic capacitance of the ESD protection element in consideration of the filter characteristics of the common mode filter, the ESD protection characteristics deteriorate. If the inductance component of the path through which the ESD current flows is reduced in consideration of the ESD protection characteristic, the desired filter characteristic of the common mode filter cannot always be obtained.

  An object of the present invention is to provide a filter that secures predetermined filter characteristics of a common mode filter without degrading the ESD protection characteristics of the ESD protection element. Another object of the present invention is to provide a filter in which the filter characteristics of the common mode filter are improved by using the ESD protection element.

(1) The filter of the present invention is
A differential transmission line that includes a first signal line and a second signal line and that transmits a high-frequency signal;
A common mode choke coil including a first inductor inserted in the first signal line and a second inductor inserted in the second signal line and magnetically coupled to the first inductor;
And an ESD protection circuit,
The ESD protection circuit is
A series circuit of a first ESD protection element and a second ESD protection element connected between the first signal line and the second signal line, a connection point of the first ESD protection element and the second ESD protection element, and a ground. A third ESD protection element connected between the third ESD protection element and a third inductor connected in series to the third ESD protection element, the inductor being a parasitic element or an inductor element.
An inductor element or a fourth inductor based on a parasitic inductance component, which is connected in series to the third ESD protection element,
A first series resonance circuit is configured by the parasitic capacitance of the first ESD protection element, the parasitic capacitance of the third ESD protection element, and the third inductor, and the parasitic capacitance of the second ESD protection element, the parasitic capacitance of the third ESD protection element, and A second series resonance circuit is formed by the third inductor,
A third series resonance circuit is configured by the parasitic capacitance of the first ESD protection element, the parasitic capacitance of the third ESD protection element, and the fourth inductor, and the parasitic capacitance of the second ESD protection element, the parasitic capacitance of the third ESD protection element, and A fourth series resonant circuit is formed by the fourth inductor,
The inductance of the third inductor and the inductance of the fourth inductor are different.

  With the above configuration, the resonance frequencies of the first series resonance circuit and the second series resonance circuit are different from the resonance frequencies of the third series resonance circuit and the fourth series resonance circuit. You can set the characteristics. Further, the third inductor and the fourth inductor have different inductances, whereby the ESD protection characteristic can be set. Therefore, it is possible to obtain a filter having adaptability between the stop band characteristic of the common mode filter and the ESD protection characteristic.

(2) It is preferable that the third inductor and the fourth inductor are configured to be connected in series to the third ESD protection element in a selectable state. Thereby, the selective connection of the third inductor and the fourth inductor to the third ESD protection element facilitates the setting of the stop band characteristic and the ESD protection characteristic of the common mode filter.

(3) The third inductor and the fourth inductor are formed of, for example, a coil-shaped or linear conductor pattern having less than one turn. As a result, the inductances of the third inductor and the fourth inductor L4 do not become too large, and the resistance components of the third inductor and the fourth inductor L4 are suppressed, so that the deterioration of the ESD protection performance is suppressed.

(4) It is preferable that the differential transmission line, the common mode choke coil, and the ESD protection circuit are provided on a single base material. This constitutes a small filter. In addition, since the wiring of each part is shortened and the parasitic component is suppressed, the filter characteristics of the common mode filter and the ESD protection performance of the EDS protection element are improved.

(5) An input/output terminal formed on the base material and connected to the differential transmission line is provided, the ESD protection circuit and the common mode choke coil overlap each other in a plan view of the base material, and the ESD protection circuit is In comparison with the common mode choke coil, it is preferably arranged at a position closer to the input/output terminals of the base material. With this structure, the area occupied when the filter is mounted on a circuit board or the like is reduced. Further, since the path from the EDS protection element to the ground conductor formed on the circuit board or the like is shortened, the parasitic component in the path is small and the ESD protection performance is improved.

(6) It is preferable that the third inductor and the fourth inductor do not overlap with the first inductor and the second inductor in a plan view of the base material. With this structure, unnecessary coupling between the first inductor and the second inductor does not occur via the third inductor or the fourth inductor, and the first inductor when an ESD current flows in the third inductor or the fourth inductor and No unnecessary induction to the second inductor occurs.

(7) It is preferable that a matching inductor inserted in the differential transmission line is further provided at a front stage, a rear stage, or both of the ESD protection circuit. As a result, impedance matching of the ESD protection circuit with respect to the differential transmission line is performed.

  According to the present invention, a filter having a predetermined filter characteristic of a common mode filter can be obtained without degrading the ESD protection characteristic of the ESD protection element. Furthermore, a filter in which the filter characteristic of the common mode filter is improved by using the ESD protection element can be obtained.

FIG. 1 is a circuit diagram of a filter according to the first embodiment. FIG. 2A is an equivalent circuit diagram of the filter for a differential signal. FIG. 2(B) is an equivalent circuit diagram for common mode noise in a state where one end of the third inductor L3 of the filter is grounded, and FIG. 2(C) shows one end of the fourth inductor L4 of the filter. It is an equivalent circuit diagram with respect to the common mode noise in the state grounded. FIG. 3 is a circuit diagram of the filter 101 of the present embodiment, including the parasitic components. FIG. 4 is a diagram showing frequency characteristics of the filter 101 of the first embodiment. FIG. 5A is a waveform of a voltage applied from the electrostatic tester to the first signal line SL1 or the second signal line SL2 in a state where the filter 101 of the first embodiment is not connected to the differential transmission line. .. FIG. 5B shows a clamp voltage waveform when the filter 101 of this embodiment is connected. FIG. 6 is a circuit diagram of the filter 102 according to the second embodiment. FIG. 7A is an equivalent circuit diagram for the differential signal of the filter 102. FIG. 7B is an equivalent circuit diagram in which the first Zener diode ZD1 and the second Zener diode ZD2 are further represented by capacitors. 8A and 8B are circuit diagrams of the ESD protection circuit. 9A, 9B, and 9C are circuit diagrams of other ESD protection circuits according to the third embodiment. FIG. 10 is a cross-sectional view of the diode chip according to the fourth embodiment. FIG. 11 is a sectional view of another diode chip according to the fourth embodiment. FIG. 12 is a cross-sectional view of yet another diode chip according to the fourth embodiment. FIG. 13 is a plan view of each layer of the filter according to the fifth embodiment. FIG. 14 is a cross-sectional view of the filter 102 of the fifth embodiment in a mounted state on the circuit board 201. FIG. 15 is a diagram showing a circuit connected to each terminal of the filter 102. 16(A), 16(B), and 16(C) are examples of conductor patterns on a circuit board on which the filter shown in FIG. 15 is mounted. FIG. 17 is a plan view of each layer of the filter according to the sixth embodiment. FIG. 18 is a front view of the filter according to the seventh embodiment.

  Hereinafter, a plurality of modes for carrying out the present invention will be shown with some specific examples with reference to the drawings. In the drawings, the same parts are designated by the same reference numerals. Although the embodiments are shown separately for the sake of convenience of explanation or understanding of the main points, partial replacement or combination of the configurations shown in different embodiments is possible. In the second and subsequent embodiments, description of matters common to the first embodiment will be omitted, and only different points will be described. In particular, similar effects obtained by the same configuration will not be sequentially described for each embodiment.

<<First Embodiment>>
FIG. 1 is a circuit diagram of a filter according to the first embodiment.

  The filter 101 includes a differential transmission line DTL, a common mode choke coil CMCC, and an ESD protection circuit PC. The “filter” in the present invention is a filter that suppresses common mode noise and passes differential signals.

  The differential transmission line DTL includes a first signal line SL1 connected between the terminals P1 and P2 and a second signal line SL2 connected between the terminals P3 and P4, and for example, a high frequency signal in the UHF band or the SHF band. To transmit.

  The common mode choke coil CMCC includes a first inductor L1 inserted in the first signal line SL1 and a second inductor L2 inserted in the second signal line SL2 and magnetically coupled to the first inductor L1.

  The ESD protection circuit PC includes a series circuit of the first Zener diode ZD1 and the second Zener diode ZD2 connected between the first signal line SL1 and the second signal line SL2, and the first Zener diode ZD1 and the second Zener. The third zener diode ZD3 connected between the connection point NP of the diode ZD2 and the ground terminal P5, the third inductor L3, and the fourth inductor L4 are included. The third inductor L3 and the fourth inductor L4 are inserted between the third Zener diode ZD3 and the ground.

  The first series resonance circuit SR1 is configured by the parasitic capacitance of the first Zener diode ZD1, the parasitic capacitance of the third Zener diode ZD3, and the third inductor L3. Further, the parasitic capacitance of the second Zener diode ZD2, the parasitic capacitance of the third Zener diode ZD3, and the third inductor L3 form a second series resonance circuit SR2. The third series resonance circuit SR1 is configured by the parasitic capacitance of the first Zener diode ZD1, the parasitic capacitance of the third Zener diode ZD3, and the fourth inductor L4. Furthermore, the parasitic capacitance of the second Zener diode ZD2, the parasitic capacitance of the third Zener diode ZD3, and the fourth inductor L4 form a fourth series resonance circuit SR4.

  The first Zener diode ZD1 is an example of the "first ESD protection element" in the present invention, the second Zener diode ZD2 is an example of the "second ESD protection element" in the present invention, and the third Zener diode ZD3 is the present invention. It is an example of the "third ESD protection element" in the invention.

The inductance of the third inductor L3 and the inductance of the fourth inductor L4 are different. Here, when the inductance of the third inductor L3 is represented by L3 and the inductance of the fourth inductor L4 is represented by L4,
It is expressed by the relationship of L3>L4.

  For example, L3 = 0.5nH and L4 = 0.05nH.

Further, when the DC resistance component of the third inductor L3 is represented by R3 and the DC resistance component of the fourth inductor L4 is represented by R4,
It is expressed by the relationship of R3>R4.

  As will be described later, the third inductor L3 and the fourth inductor L4 are provided so that it is possible to select whether to ground one end of the third inductor L3 or ground one end of the fourth inductor L4. When grounded via the third inductor L3 having a large inductance, the common mode noise stop band is widened. Further, grounding via the fourth inductor L4 having a small inductance improves the ESD protection performance.

In the present embodiment, the parasitic capacitances of the first Zener diode ZD1 and the second Zener diode ZD2 are substantially equal, and the parasitic capacitance of the third Zener diode ZD3 is the same as the parasitic capacitance of the first Zener diode ZD1 and the second Zener diode ZD2. Greater than parasitic capacitance. Here, when the parasitic capacitance of the first Zener diode ZD1 is represented by Czd1, the parasitic capacitance of the second Zener diode ZD2 is represented by Czd2, and the parasitic capacitance of the third Zener diode ZD3 is represented by Czd3,
Czd1≈Czd2, Czd3>Czd1, and Czd3>Czd2.

  The parasitic capacitance of each of the first Zener diode ZD1, the second Zener diode ZD2, and the third Zener diode ZD3 is mainly the capacitance of the depletion layer generated when the reverse bias voltage is applied to each Zener diode.

  Here, the parasitic capacitance of each Zener diode is generally determined by the size of each Zener diode. With the above configuration, the size of the third Zener diode ZD3 is relatively larger than that of the first Zener diode ZD1 and the second Zener diode ZD2, so that the resistance value of the ESD protection circuit PC is small and the ESD protection performance is small. Will be higher.

  FIG. 2A is an equivalent circuit diagram of the filter for a differential signal. FIG. 2(B) is an equivalent circuit diagram for common mode noise in a state where one end of the third inductor L3 of the filter is grounded, and FIG. 2(C) shows one end of the fourth inductor L4 of the filter. It is an equivalent circuit diagram with respect to the common mode noise in the state grounded.

  As shown in FIG. 2B, when one end of the third inductor L3 is grounded, during the ESD protection operation, the first Zener diode ZD1 or the second Zener diode ZD2, the third Zener diode ZD3, and the third inductor An ESD current flows through L3. Further, as shown in FIG. 2C, when one end of the fourth inductor L4 is grounded, the first Zener diode ZD1 or the second Zener diode ZD2, the third Zener diode ZD3, and the The ESD current flows through the 4-inductor L4.

  Grounding via the fourth inductor L4 having a small inductance and DC resistance component improves the ESD protection performance. That is, when importance is attached to the ESD protection performance, one end of the fourth inductor L4 is grounded as shown in FIG. 2(C).

  In the filter 101 shown in FIG. 1, since the parasitic capacitance of the first Zener diode ZD1 of the ESD protection circuit PC and the parasitic capacitance of the second Zener diode ZD2 are substantially equal, the first Zener diode ZD1 and the second Zener diode ZD2 A connection point (hereinafter "neutral point") NP with is a neutral potential, that is, a ground potential. Therefore, a circuit from the neutral point NP to the ground terminals P5 and P6 (the third Zener diode ZD3, the third inductor L3, and the fourth inductor L4) does not exist equivalently for the differential signal.

  Therefore, the differential signal is not affected by the presence of the third Zener diode ZD3, the third inductor L3, and the fourth inductor L4 having relatively large parasitic capacitance.

  As shown in FIG. 2B, when one end of the third inductor L3 is grounded, the first series resonant circuit SR1 and the second series resonant circuit SR2 deal with common mode noise with respect to common mode noise. Acts as a trap filter. Similarly, as shown in FIG. 2C, in a state where one end of the fourth inductor L4 is grounded, the third series resonance circuit SR3 and the fourth series resonance circuit SR4 are connected to the common mode against common mode noise. Acts as a trap filter for mode noise.

  FIG. 3 is a circuit diagram of the filter 101 of the present embodiment, including the parasitic components. The first inductor L1 has a parasitic capacitance C1 and the second inductor L2 has a parasitic capacitance C2. The first inductor L1 and the parasitic capacitance C1 form an LC parallel resonance circuit, and the second inductor L2 and the parasitic capacitance C2 form an LC parallel resonance circuit. The two LC parallel resonance circuits act as band stop filters for common mode noise.

  FIG. 4 is a diagram showing frequency characteristics of the filter 101 of this embodiment. In FIG. 4, the curve SCC21(1) is the insertion loss of the common mode noise when one end of the third inductor L3 is grounded, and the curve SCC21(2) is the common mode noise when the one end of the fourth inductor L4 is grounded. Is the insertion loss of. Curve SDD21(1) is the insertion loss of the differential signal when one end of the third inductor L3 is grounded, curve SDD21(2) is the insertion loss of the differential signal when one end of the fourth inductor L4 is grounded, Is.

here,
L3 = 0.5nH
L4 = 0.05nH
Czd1 = Czd2 = 0.4pF
Czd3 = 3pF
Is.

  As shown in FIG. 4, the insertion loss SCC21(1) of the common mode noise has attenuation poles at the frequency f1 (near 3 GHz) and the frequency f21 (near 9.4 GHz). The attenuation pole of the frequency f1 is an attenuation pole generated by the two LC parallel resonance circuits configured by L1, L2, C1 and C2 shown in FIG. Since the first inductor L1 and the second inductor L2 of the common mode choke coil CMCC are rectified for differential signals, mutual inductance is added. As a result, the resonance frequencies of the two LC parallel resonance circuits with respect to the differential signals are outside the used frequency band.

  The attenuation pole of the frequency f21 shown in FIG. 4 is an attenuation pole generated by the first series resonance circuit SR1 and the second series resonance circuit SR2 shown in FIG. 2B. The resonance frequency of the first series resonance circuit SR1 is determined by the combined capacitance of the parasitic capacitance Czd1 of the first Zener diode ZD1 and the parasitic capacitance Czd3 of the third Zener diode ZD3 and the inductance of the third inductor L3. Similarly, the resonance frequency of the second series resonance circuit SR2 is determined by the combined capacitance of the parasitic capacitance Czd2 of the second Zener diode ZD2 and the parasitic capacitance Czd3 of the third Zener diode ZD3 and the inductance of the third inductor L3.

  The attenuation pole of the frequency f22 shown in FIG. 4 is the attenuation by the third series resonance circuit SR3 and the fourth series resonance circuit SR4 shown in FIG. 2(C). The resonance frequency of the third series resonance circuit SR3 is determined by the combined capacitance of the parasitic capacitance Czd1 of the first Zener diode ZD1 and the parasitic capacitance Czd3 of the third Zener diode ZD3 and the inductance of the fourth inductor L4. Similarly, the resonance frequency of the fourth series resonance circuit SR4 is determined by the combined capacitance of the parasitic capacitance Czd2 of the second Zener diode ZD2 and the parasitic capacitance Czd3 of the third Zener diode ZD3 and the inductance of the fourth inductor L4.

  Therefore, the attenuation pole frequency f21 for the common mode noise of the filter 101 of this embodiment is lower than f22.

  When the stop band of the common mode noise is defined as the frequency band in which the insertion loss is -10 dB or less, as shown in FIG. 4, when one end of the third inductor L3 is grounded, the stop band of the common mode noise is Is 1.5 GHz or more and 12 GHz or less, which is very wide. Therefore, when importance is attached to the wide band property of the stop band of the common mode noise, one end of the third inductor L3 is grounded as shown in FIG.

  FIG. 5A shows a waveform of a voltage applied from the static electricity tester to the first signal line SL1 or the second signal line SL2 in a state where the filter 101 of this embodiment is not connected to the differential transmission line. FIG. 5B shows a clamp voltage waveform when the filter 101 of this embodiment is connected.

  In FIG. 5B, the voltage waveform WF1 shows the characteristics when one end of the third inductor L3 is grounded, and the voltage waveform WF2 shows the characteristics when one end of the fourth inductor L4 is grounded. In this way, by grounding one end of the fourth inductor L4 having a small inductance and a small DC resistance component, the peak of the clamp voltage can be suppressed low and a better ESD protection performance can be obtained. Therefore, when importance is attached to the ESD protection performance, one end of the fourth inductor L4 is grounded as shown in FIG.

<<Second Embodiment>>
The second embodiment shows an example of a filter including a matching circuit.

  FIG. 6 is a circuit diagram of the filter 102 according to the second embodiment. In this example, a matching inductor LM11 is provided between the first inductor L1 and the first Zener diode ZD1, and a matching inductor LM12 is provided between the terminal P2 and the first Zener diode ZD1. Similarly, a matching inductor LM21 is provided between the second inductor L2 and the second Zener diode ZD2, and a matching inductor LM22 is provided between the terminal P4 and the second Zener diode ZD2.

  FIG. 7A is an equivalent circuit diagram for the differential signal of the filter 102. FIG. 7B is an equivalent circuit diagram in which the first Zener diode ZD1 and the second Zener diode ZD2 are further represented by capacitors.

  In this way, by providing the matching inductors LM11, LM12, LM21, LM22 inserted in the differential transmission line DTL at the front stage and the rear stage of the ESD protection circuit, the impedance matching of the ESD protection circuit PC with respect to the differential transmission line DTL is performed. Can be achieved.

  In the example shown in FIG. 6, the matching inductor is inserted in both the front stage and the rear stage of the ESD protection circuit PC, but the matching inductor may be inserted in the front stage or the rear stage of the ESD protection circuit.

<<Third Embodiment>>
In the third embodiment, some examples of ESD protection circuits are shown. 8A and 8B are circuit diagrams of the ESD protection circuit.

  In the ESD protection circuit shown in FIG. 8A, the first ESD protection element connected between the first signal line SL1 and the neutral point NP is the first Zener diode ZD1 and the first Zener diode ZD1. Therefore, with respect to the first diode D1 connected in series in the direction in which the forward bias current of the first Zener diode ZD1 is blocked and the series circuit of the first Zener diode ZD1 and the first diode D1, the first diode D1 is The second diode D2 is connected in parallel with the opposite polarity and is configured. The second ESD protection element connected between the second signal line SL2 and the neutral point NP is the second Zener diode ZD2 and the forward bias of the second Zener diode ZD2 with respect to the second Zener diode ZD2. A fourth diode connected in parallel to the third diode D3 connected in series in the direction of blocking the current and a series circuit of the second Zener diode ZD2 and the third diode D3 with a polarity opposite to that of the third diode D3. And D4.

  In the ESD protection circuit shown in FIG. 8B, the third ESD protection element connected between the neutral point NP and the ground is the third Zener diode ZD3 and the third Zener diode ZD3. A fifth diode D5 connected in series in a direction that blocks the forward bias current of the Zener diode ZD3 and a series circuit of the third Zener diode ZD3 and the fifth diode D5 are parallel to each other in the opposite polarity to the fifth diode D5. The sixth diode D6 connected thereto is included.

  According to the configurations shown in FIGS. 8A and 8B, the diode D1 is connected in series to the first Zener diode ZD1 and the diode D3 is connected in series to the second Zener diode ZD2. Therefore, the combined capacitance of the first ESD protection element and the second ESD protection element is small. Therefore, the influence of the first ESD protection element and the second ESD protection element on the differential signal is reduced, and the deterioration of the differential signal pass characteristic is suppressed. In addition, the size of the Zener diodes ZD1 and ZD2 can be increased as the combined capacitance is reduced, which can improve the ESD protection performance.

  Further, according to the configuration shown in FIG. 8B, since the combined capacitance of the third ESD protection element can be reduced, even if the third Zener diode ZD3 having a large size is used, the configuration shown in FIGS. Since the size of the third Zener diode ZD3 can be increased while setting the resonance frequencies of the first series resonance circuit SR1 and the second series resonance circuit SR2 to predetermined values, the ESD protection performance can be further improved.

  9A, 9B, and 9C are circuit diagrams of other ESD protection circuits according to the third embodiment. The ESD protection circuit shown in FIG. 9A is obtained by reversing the polarities of the respective elements of the ESD protection circuit PC shown in FIG. The ESD protection circuits shown in FIGS. 9B and 9C are obtained by reversing the polarities of the respective elements of the ESD protection circuit PC shown in FIGS. 8A and 8B. ..

  As described above, the same characteristics can be obtained by reversing the directions of the Zener diodes and the diodes.

<<Fourth Embodiment>>
The fourth embodiment shows a configuration example of a diode chip including a plurality of Zener diodes and the like.

  FIG. 10 is a cross-sectional view of a diode chip in which the first Zener diode ZD1, the second Zener diode ZD2, and the third Zener diode ZD3 shown in FIG. 1, for example, are configured in one chip. This diode chip includes a P substrate, an N type epitaxial layer formed on the P substrate, N type diffusion layers N1, N2 and N3 formed on the N type epitaxial layer, and element isolation trenches reaching the P type substrate from the surface. Equipped with T. The epitaxial layer is separated by a trench T, and epitaxial layers Ne1, Ne2 and Ne3 are formed. The junction layer between the P-type substrate and the epitaxial layer Ne1 constitutes the first Zener diode ZD1, the junction layer between the P-type substrate and the epitaxial layer Ne2 constitutes the second Zener diode ZD2, and the P-type substrate and the epitaxial layer Ne3. The third zener diode ZD3 is formed by the junction layer of.

  FIG. 11 shows the first Zener diode ZD1, the second Zener diode ZD2, the third Zener diode ZD3, the first diode D1, the second diode D2, the third diode D3, and the fourth diode shown in FIG. 8A. It is sectional drawing of the diode chip which comprised D4 in one chip. This diode chip includes a P substrate, an N-type epitaxial layer formed on the P substrate, an N-type diffusion layer and a P-type diffusion layer formed on the N-type epitaxial layer, and an element isolation trench reaching from the surface to the P-type substrate. Equipped with T. In FIG. 11, the first zener diode ZD1 is formed by the junction layer between the P-type substrate and the N-type diffusion layer Nz1, and the second Zener diode ZD2 is formed by the junction layer between the P-type substrate and the N-type diffusion layer Nz2. The junction layer between the P-type substrate and the N-type diffusion layer Nz3 constitutes the third Zener diode ZD3. The junction layer between the P-type substrate and the epitaxial layer Ne12 constitutes the second diode D2, and the junction layer between the P-type substrate and the epitaxial layer Ne22 constitutes the fourth diode D4. Further, the junction layer between the epitaxial layer Ne11 and the P-type diffusion layer Pd1 constitutes the first diode D1, and the junction layer between the epitaxial layer Ne21 and the P-type diffusion layer Pd3 constitutes the third diode D3.

  FIG. 12 shows the first Zener diode ZD1, the second Zener diode ZD2, the third Zener diode ZD3, the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 shown in FIG. 8B. FIG. 11 is a cross-sectional view of a diode chip in which a fifth diode D5 and a sixth diode D6 are formed in one chip. In FIG. 12, the junction layer between the P-type substrate and the N-type diffusion layer Nz3 constitutes the third Zener diode ZD3, and the junction layer between the epitaxial layer Ne31 and the P-type diffusion layer Pd5 constitutes the fifth diode D5. The junction layer between the P-type substrate and the epitaxial layer Ne32 constitutes the sixth diode D6. Other configurations are the same as those shown in FIG.

<<Fifth Embodiment>>
The fifth embodiment shows an example of a filter configured as a single element.

  FIG. 13 is a plan view of each layer when the filter of the present embodiment is formed of a laminated body. The circuit configuration of this filter is as shown in FIG.

  In FIG. 13, the first layer (1) is the bottom layer and the fifteenth layer (15) is the top layer. Both are layers of non-magnetic resin. External terminals P1 to P6 are formed on the first layer (1). Each conductor pattern is formed on each of the second layer (2) to the fourteenth layer (14). The diode chip ZDC is mounted on the fifth layer (5). An opening for forming a cavity for housing the diode chip ZDC is formed from the sixth layer (6) to the eighth layer (8). A third inductor L3 and a fourth inductor L4 are formed on the second layer (2) by a conductor pattern.

  In FIG. 13, conductor patterns W11, W13, W14, W21, W22, W23, and W24 are wiring patterns. In addition, the conductor patterns L1a, L1b, L1c, L1d, and L1e form the first inductor L1 when they are continuous via the via conductor. Similarly, the conductor patterns L2a, L2b, L2c, L2d, and L2e form the second inductor L2 when they are continuous via the via conductor. The reference numerals attached to the other conductor patterns correspond to the circuit elements shown in FIG. 6, respectively.

  FIG. 14 is a cross-sectional view of the filter 102 of the present embodiment in a mounted state on the circuit board 201. FIG. 15 is a diagram showing a circuit connected to each terminal of the filter 102.

  In the examples shown in FIGS. 13 and 14, the ESD protection circuit and the common mode choke coil overlap each other in a plan view of the base material, and the ESD protection circuit is closer to the input/output terminal of the base material than the common mode choke coil ( It is located at the bottom).

  In the examples shown in FIGS. 13 and 14, the third inductor L3 and the fourth inductor L4 hardly overlap the first inductor L1 and the second inductor L2 in a plan view of the base material.

  16(A), 16(B), and 16(C) are examples of conductor patterns on a circuit board on which the filter shown in FIG. 15 is mounted. The terminals P5 and P6 of the filter are connected to the conductor patterns GND1 and GND2 on the circuit board.

  In the example of FIG. 16A, the conductor pattern GND1 is connected to the ground conductor of the circuit board, and the conductor pattern GND2 is not connected to the ground conductor of the circuit board. In the example of FIG. 16B, the conductor pattern GND2 is connected to the ground conductor of the circuit board, and the conductor pattern GND1 is not connected to the ground conductor of the circuit board. In the example of FIG. 16C, both the conductor patterns GND1 and GND are connected to the ground conductor of the circuit board.

  When the filter is mounted on the circuit board having the conductor pattern shown in FIG. 16A, one end of the third inductor L3 is grounded, and the filter is mounted on the circuit board having the conductor pattern shown in FIG. 16B. Then, one end of the fourth inductor L4 is grounded. When the filter is mounted on the circuit board on which the conductor pattern shown in FIG. 16C is formed, both ends of the third inductor L3 and the fourth inductor L4 are grounded.

  In this way, the inductance of the inductor inserted in the path through which the ESD current flows can be selected from among three patterns depending on the conductor pattern of the circuit board on which the ESD current is mounted.

  According to the present embodiment, since the third inductor L3 and the fourth inductor L4 are configured with a coil-shaped or linear conductor pattern having less than one turn, the inductance of the third inductor L3 and the fourth inductor L4 becomes too large. In addition, since the resistance components of the third inductor L3 and the fourth inductor L4 are suppressed, deterioration of the ESD protection performance is suppressed.

  Further, according to this embodiment, it is preferable that the differential transmission line, the common mode choke coil CMCC, and the ESD protection circuit are provided on a single base material. This constitutes a small filter. In addition, since the wiring of each part is shortened and the parasitic component is suppressed, the filter characteristics of the common mode filter and the ESD protection performance of the EDS protection element are improved.

  Further, according to this embodiment, the ESD protection circuit and the common mode choke coil overlap each other in a plan view of the base material, and the ESD protection circuit is closer to the input/output terminal of the base material (maximum than the common mode choke coil). Since the filter is arranged at a position closer to the lower layer, the area occupied when the filter is mounted on a circuit board or the like is reduced. Further, since the path from the EDS protection element to the ground conductor formed on the circuit board or the like is short and the parasitic component in the path is small, high ESD protection performance can be obtained.

  Further, according to the present embodiment, the third inductor L3 and the fourth inductor L4 hardly overlap the first inductor L1 and the second inductor L2 in a plan view of the base material, and thus the third inductor L3 or the fourth inductor L3 is not included. Unnecessary coupling between the first inductor L1 and the second inductor L2 via L4 does not occur. Moreover, unnecessary induction to the first inductor L1 and the second inductor L2 when an ESD current flows through the third inductor L3 or the fourth inductor L4 does not occur.

<<Sixth Embodiment>>
The sixth embodiment shows an example in which the third inductor L3 and the fourth inductor L4 are selected by trimming the conductor pattern included in the filter configured as a single component.

  FIG. 17 is a plan view of each layer of the filter according to the sixth embodiment. The configuration of the first layer (1) and the second layer (2) is different from the example shown in FIG. 13 in the fifth embodiment. In the present embodiment, not only the external terminals P1 to P6 but also the third inductor L3 and the fourth inductor L4 are formed by the conductor pattern on the first layer (1). Therefore, the conductor pattern of the third inductor L3 and the fourth inductor L4 is not formed on the second layer (2). Other configurations are the same as those shown in the fifth embodiment.

  In the filter of the present embodiment, the common-mode noise stop band characteristic can be switched by appropriately trimming the conductor patterns of the third inductor L3 and the fourth inductor L4 exposed on the external terminal formation surface. Therefore, the characteristics of the filter can be set after the laminated body is formed.

<<Seventh Embodiment>>
The seventh embodiment shows a filter including two chip components and a circuit board.

  FIG. 18 is a front view of the filter according to the seventh embodiment. The common mode choke coil CMCC and the diode chip ZDC are surface-mounted on the circuit board 201. The common mode choke coil CMCC is the common mode choke coil CMCC shown in FIG. 1 configured as a single chip component. As shown in FIG. 12 and FIG. 8B, for example, the diode chip ZDC has a plurality of Zener diodes and a plurality of diodes configured as a single chip component. On the circuit board 201, the conductor pattern W(L3) forms a third inductor L3. Further, the conductor pattern W(L4) constitutes the fourth inductor L4. The first end of the third inductor L3 or the fourth inductor L4, or the first end of both the third inductor L3 and the fourth inductor L4 is connected to a third ESD protection element (zener diode ZD3, diode D5, diode D5, diode D5) in the diode chip ZDC. D6) and the ground.

  As in the present embodiment, the third inductor L3 and the fourth inductor L4 may be formed on the circuit board side.

<<Other Embodiments>>
In each of the embodiments described above, three types of inductances and three types of resistance values are selected by selectively grounding the third inductor L3 and the fourth inductor L4. However, three or more inductors are provided. Alternatively, four or more kinds of inductance and resistance values may be selected.

  In each of the embodiments described above, an example in which the Zener diode is configured as an ESD protection element or as a main part of the ESD protection element has been described. A resistance element can also be used. Further, it is also possible to use a discharge element in which the resistance value is reduced by discharging between the spark gaps when a high voltage is applied.

  Further, in each of the above-described embodiments, an example in which the third inductor L3 and the fourth inductor L4 are configured by the conductor pattern is shown. However, the inductor as the chip component may be used in the stack or in the stack forming the common mode choke coil. It may be provided on the body. Further, the inductor as the chip component may be mounted on the circuit board.

  In each of the above-described embodiments, the first inductor L1 and its parasitic capacitance C1 form an LC circuit, and the second inductor L2 and its parasitic capacitance C2 form an LC circuit. A capacitor may be connected to each of the first inductor L1 and the second inductor L2.

  Finally, the above description of the embodiments is illustrative in all respects and not restrictive. Modifications and changes can be appropriately made by those skilled in the art. The scope of the invention is indicated by the claims rather than the embodiments described above. Further, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.

C1, C2... Parasitic capacitance CMCC... Common mode choke coil
Czd1, Czd2, Czd3... Parasitic capacitance D1... First diode D2... Second diode D3... Third diode D4... Fourth diode D5... Fifth diode D6... Sixth diode DTL... Differential transmission line L1... First inductor L1a , L1b, L1c, L1d, L1e... Conductor pattern L2... Second inductor L2a, L2b, L2c, L2d, L2e... Conductor pattern L3... Third inductor L4... Fourth inductor LM11, LM12, LM21, LM22... Matching inductor N1 , N2, N3... N type diffusion layers Ne1, Ne2, Ne3... Epitaxial layers Ne11, Ne12... Epitaxial layers Ne21, Ne22... Epitaxial layers Ne31, Ne32... Epitaxial layer NP... Neutral points Nz1, Nz2, Nz3... N type diffusion layers P1 to P6... Terminal PC... ESD protection circuit Pd1, Pd3... P type diffusion layer SL1... First signal line SL2... Second signal line SR1... First series resonance circuit SR2... Second series resonance circuit T... Element isolation trench W11, W13, W14, W21, W22, W23, W24... Conductor pattern ZD1... First Zener diode (first ESD protection element)
ZD2... Second Zener diode (second ESD protection element)
ZD3... Third Zener diode (third ESD protection element)
ZDC... Diode chips 101, 102... Filter 201... Circuit board

Claims (7)

A differential transmission line that includes a first signal line and a second signal line and that transmits a high-frequency signal;
A common mode choke coil including a first inductor inserted in the first signal line and a second inductor inserted in the second signal line and magnetically coupled to the first inductor;
And an ESD protection circuit,
The ESD protection circuit is
A series circuit of a first ESD protection element and a second ESD protection element connected between the first signal line and the second signal line, a connection point of the first ESD protection element and the second ESD protection element, and a ground. A third ESD protection element connected between the third ESD protection element and a third inductor connected in series to the third ESD protection element, the inductor being a parasitic element or an inductor element.
An inductor element or a fourth inductor based on a parasitic inductance component, which is connected in series to the third ESD protection element,
A first series resonance circuit is configured by the parasitic capacitance of the first ESD protection element, the parasitic capacitance of the third ESD protection element, and the third inductor, and the parasitic capacitance of the second ESD protection element, the parasitic capacitance of the third ESD protection element, and A second series resonance circuit is formed by the third inductor,
A third series resonance circuit is configured by the parasitic capacitance of the first ESD protection element, the parasitic capacitance of the third ESD protection element, and the fourth inductor, and the parasitic capacitance of the second ESD protection element, the parasitic capacitance of the third ESD protection element, and A fourth series resonant circuit is formed by the fourth inductor,
The inductance of the third inductor and the inductance of the fourth inductor are different,
filter.   The filter according to claim 1, wherein the third inductor and the fourth inductor are configured to be connected in series to the third ESD protection element in a selectable state.   The filter according to claim 1 or 2, wherein the third inductor and the fourth inductor are constituted by a coil-shaped or linear conductor pattern having less than one turn.   The filter according to claim 1, wherein the differential transmission line, the common mode choke coil, and the ESD protection circuit are provided on a single base material. An input/output terminal formed on the base material and connected to the differential transmission line,
The ESD protection circuit and the common mode choke coil overlap each other in a plan view of the base material, and the ESD protection circuit is arranged at a position closer to the input/output terminal of the base material than the common mode choke coil. The filter according to claim 4, which comprises:   The filter according to claim 4, wherein the third inductor and the fourth inductor do not overlap with the first inductor and the second inductor in a plan view of the base material.   7. The filter according to claim 1, further comprising a matching inductor inserted in the differential transmission line in a front stage, a rear stage, or both of the ESD protection circuit.