JP6701414B2 - Amusement machine - Google Patents

Description

  The present invention relates to an electronic game machine with a built-in computer device, and is particularly preferably applied to a rotating body game machine.

  In a spinning machine such as a slot machine, when a player inserts a medal into a medal insertion slot and operates a start lever, the rotation of a rotary reel is started accordingly. Then, when the player presses the stop button to stop the rotary reels, when the symbols are aligned on an effective stop line (hereinafter, referred to as an effective line), a payout medal corresponding to the symbol is paid out.

  However, in reality, the winning/non-winning state of each game is predetermined by the internal lottery process in the main control unit before the player starts the stop operation, and the symbols internally won by the lottery process are selected by the player. The payout medals are paid out by arranging on the activated line.

  Among the winning symbols, a combination of big bonus (BB) symbols has a particularly high value. When the player internally wins this BB combination and the player aligns the BB symbols on the activated line, the big bonus game is started, and after that, the winning probability of the small symbol symbol is maintained to be significantly high, so that a large amount of The number of dividend medals can be expected.

JP, 2015-198715, A JP, 2016-063865, A

  By the way, a large number of gaming machines of this kind are densely arranged in the gaming hall, so if high-level high-frequency noise is radiated, not only is there a fear of malfunctioning of the gaming machine, but also surrounding gaming machines. Also has an adverse effect.

  Therefore, the applicant has proposed various noise countermeasures such as a configuration in which a power factor correction circuit is provided on the power supply substrate (Patent Document 1) and a configuration in which a ferrite core or a varistor is provided in the speaker wiring (Patent Document 2).

  However, if the commercial power source (100 VAC) is used as it is without stepping down with the power transformer, further measures are required. That is, radiation noise and propagation noise passing through the power supply line of the commercial power supply legally pose a problem, and it is necessary to completely clear the regulations of Chapter 5 of the Electrical Appliance and Material Safety Law.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine with improved noise countermeasures.

In order to achieve the above object, the present invention executes a lottery process based on a predetermined switch signal to generate a DC voltage used by a main control means for integrally controlling a game operation based on the lottery result. power supply means for the first choke coil for receiving an AC voltage (LL), and a first circuit for noise countermeasures configured in the downstream side of the capacitor bank (C1, C2), the AC output of the first circuit a second circuit for rectifying the (RECT), and the second circuit third circuit (24) for improving the power factor by receiving a rectified output voltage of (RECT), based on an output of said third circuit (24) a fourth circuit for generating a DC output voltage (25), is configured to have a third circuit (24) is rectified output voltage of said second circuit (RECT), and the fourth circuit (25 ) with reference to the DC output voltage of the PFC controller for outputting a PWM control signal, the second circuit (second choke coil (L1 for smoothing the output current of the RECT)), the second choke coil ( a semiconductor device located downstream of the L1), a first terminal and a second terminal and a third terminal, when turned oN by receiving a PWM control signal to the first terminal, the said second terminal and a switching element that short-circuit state between the third terminal, characterized in that it is configured to have a snubber circuit which is disposed between the third terminal and the second terminal of the switching element.

  In this case, the snubber circuit is preferably composed of a series circuit of a resistance and an absorption capacitor, and a fourth circuit in which a diode and an output capacitor are connected in series is connected in parallel to the snubber circuit. preferable.

  According to the present invention described above, it is possible to realize a gaming machine with improved measures against noise.

FIG. 8 is a front view of the slot machine related to the embodiment. FIG. 2 is a right side view (a) and a plan view (b) of the slot machine of FIG. 1. It is the figure which showed the front panel of the slot machine from the back. It is an internal front view of a main body case of the slot machine. FIG. 3 is a block diagram showing a circuit configuration of the slot machine of FIG. 1. It is a block diagram showing a circuit configuration of a main control board. It is a block diagram which shows the circuit structure of a power supply board. It is a circuit diagram which shows the circuit structure of a 1st power supply board. 3 is a diagram illustrating a PFC circuit of a first power supply board. It is a block diagram which shows the internal structure of the LLC current resonance control circuit of a 1st power supply board. 5 is a diagram illustrating an operation of an LLC current resonance control circuit. It is the block diagram which shows the circuit constitution of the production interface board. 3 is a diagram illustrating an internal configuration and operation of a voice ROM. It is drawing explaining the internal structure and operation|movement of a speech synthesis circuit. It is a block diagram which shows the internal structure of a speech synthesis circuit in more detail. It is drawing explaining the internal structure of a 1st digital amplifier, and wiring with an upper side speaker. It is drawing explaining the internal structure of a 2nd digital amplifier, and wiring with a lower side speaker. 6 is a diagram illustrating an operation of the digital amplifier.

  Hereinafter, the present invention will be described in more detail based on examples. 1 to 4 illustrate the slot machine SL according to the embodiment. In the slot machine SL, a rectangular box-shaped main body case 1 and a front panel 2 on which various game members are mounted are connected via a hinge 3, and the front panel 2 can be opened and closed with respect to the main body case 1. (Fig. 2). 1 is a front view of the front panel 2, FIG. 2 is a right side view (a) and a plan view (b) of the slot machine SL, FIG. 3 is a rear view of the front panel 2, and FIG. The front view is shown.

  As shown in FIG. 4, the symbol rotation unit 4 including the three rotation reels 4a to 4c is arranged substantially in the center of the main body case 1, and the medal payout device 5 is arranged below the symbol rotation unit 4. A BB symbol, an RB symbol, various fruit symbols, a replay symbol, etc. are drawn on each of the rotating reels 4a to 4c. The medal payout device 5 is provided with a medal hopper 5a for storing medals, a payout motor M, a medal payout control board ME, a payout relay board PAY, a payout sensor (not shown), and the like. Here, based on the rotation of the payout motor M, the medal is led out from the payout exit 5b toward the front of the drawing. The medals stored in excess of the limit amount are configured to drop into the auxiliary tank 6 through the overflow portion 5c.

  Power supply boards 62A and 62B are arranged adjacent to the above-mentioned medal payout device 5, and a main control board 50 is arranged above the symbol rotation unit 4, and a rotation body setting board SET is arranged adjacent to the main control board 50. It is arranged. Inside the symbol rotation unit 4, a rotation LED drive board DR1 and a rotation relay board IM2 are provided, and an external concentrated terminal board OUT is arranged adjacent to the symbol rotation unit 4.

  As shown in FIG. 1, a display device (LCD unit) 7 is arranged above the front panel 2. Then, by displaying various characters on the display device 7, the game operation is effectively excited. Further, three display windows 8a to 8c corresponding to the rotary reels 4a to 4c are arranged below the display device 7. Through the display windows 8a to 8c, about three symbols can be seen in the rotating direction of each of the rotary reels 4a to 4c, and three symbols in total are three in the horizontal direction and two in the diagonal direction. Is a virtual stop line.

  On the left side of such a display window 8a, an LED group 9 indicating a game state is provided, and below that, a payout display unit 10 for displaying the number of medals to be paid out as a game result, and the number of medals in a credit state. A storage number display unit 11 for displaying is provided.

  The payout display unit 10 is configured by arranging two 7-segment LEDs in series, and specifies the payout medal number and also functions as an error indicator for displaying the content of the abnormality when any abnormal situation occurs. ..

  A medal insertion slot 12 for inserting medals is provided in the center of the front panel 2 in the vertical direction, and a return button 13 for returning a clogged medal in the medal insertion slot 12 is provided adjacent to the medal insertion slot 12. Further, a credit settlement button 14 for paying out medals in a credit state, an insertion button 15 for artificially inserting one medal in a credit state instead of inserting a medal in the medal insertion slot 12, and a pseudo medal for a medal in a credit state. A max throw button 16 for throwing three sheets is provided.

  Below these game members, a start lever 17 for starting the rotation of the rotating reels 4a-4c and stop buttons 18a-18c for stopping the rotating reels 4a-4c are provided.

  In this embodiment, the internal lottery process is executed due to the operation of the start lever 17, and it is determined whether or not the internal winning state for the BB symbol or the small winning symbol is achieved. Then, normally, the three rotation reels 4a to 4c start normal rotation in the forward direction, but as a notice effect for giving notice of the internal winning state, all or some of the rotation reels 4a to 4c rotate irregularly. After that, normal rotation may be started. The notice effect means an effect of uncertainly informing the lottery result of the internal lottery process.

  At the time of such a notice effect, all or a part of the image effect on the display device 7, the lamp effect for blinking the LED lamp or the like, and the sound effect for driving the speaker are appropriately selected and executed.

  As shown in FIG. 1, below the front panel 2, a horizontally long tray 19 for accumulating medals and a medal outlet 20 communicating with the payout opening 5b of the payout device 5 are provided. Further, left and right lower speakers SPbL and SPbR for bass are arranged on the left and right of the medal outlet 20, and upper speakers SPtL and SPtR are also arranged on the left and right of the display device 7. Here, the lower speakers SPbL and SPbR are large speakers emphasizing heavy bass, and output monaural background music (BGM) and the like at the same left and right volumes.

  On the other hand, the upper speakers SPtL and SPtR output stereophonic music and effect sounds when necessary. Here, the music includes a background sound output as a stereo sound. Further, the notice effect by the effect sound includes operations such as sound output from only one of the upper speakers SPtL and SPtR, horizontal audio movement, and horizontal audio reciprocal movement.

  As shown in FIG. 3, on the back side of the front panel 2, a medal selecting device 21 for selecting the medals inserted into the medal inserting port 12, and a medal derivation port for medals determined to be inappropriate by the medal selecting device 21. A return passage 22 for guiding to 20 is provided. In addition, a board case 23 accommodating a production control board 60, a production interface board 61, and the like is arranged on the upper rear side of the front panel 2. A game relay board IM1 that relays signals between the various game members shown in FIG. 1 and the main control board 50 is provided on the top of the medal selecting device 21.

  FIG. 5 is a block diagram showing a circuit configuration of the slot machine SL according to the embodiment. As shown in the figure, this slot machine SL performs various effect operations based on a main control board 50 that controls the operation of various game members including the rotary reels 4a to 4c and a control command CMD received from the main control board 50. Mainly a production control board 60 to be realized and a power supply board 62 (62A, 62B) which receives a commercial power supply (100V), converts it into a DC voltage (5V, 12V, 18V, 24V, 36V) and supplies it to each part of the device. Is configured.

  As shown in the center of the lower part of FIG. 5, the power supply board 62 according to the present embodiment receives a commercial power supply (100V) directly from the first power supply board 62A, and receives AC 24V and DC 24V from the first power supply board 62A to reset the power supply. The second power supply board 62B that outputs the signal RES and the power interruption signals ABN1 and ABN2.

  Here, the power supply reset signal RES is transmitted to each part of the apparatus including the main control board 50 and the performance interface board 61 when the AC power supply is turned on. On the other hand, the power interruption signals ABN1 and ABN2 are output in synchronization when the AC power is shut off, the power interruption signal ABN1 is transmitted to the main control board 50, and the power interruption signal ABN2 is transmitted to the production interface board 61. ..

  As shown in the center of the upper part of FIG. 5, the production interface board 61 receives direct current voltages (5VB, 12VB, 18V, 36V) of various levels from the power supply boards 62A and 61B and a power supply reset signal via an appropriate relay board. It receives RES and the power interruption signal ABN2 (FIGS. 5 and 7).

  Further, the production interface board 61 receives the control command CMD and the strobe signal STB from the main control board 50 via an appropriate relay board. Then, various control signals (CMD, STB, ABN2) received by the performance interface board 61 are transferred to the performance control board 60 together with the DC voltage (5VB, 3.3V).

  The DC voltage 3.3V is generated in the converter circuit DC/DC of the performance interface board 61 based on the DC voltage 5VB received from the second power supply board 62B. In the performance interface board 61, the voice processor SDPR and the voice are generated. It becomes the power supply voltage of the memory SDROM (see FIG. 12).

  By the way, as shown by a broken line in the upper center of FIG. 5, the performance control board 60 and the performance interface board 61 are integrated by connector connection. Then, the computer circuit GEPR of the effect control board 60 comprehensively controls the image effect on the display device 7, the sound effect by the speakers SPt, SPb, and the lamp effect by the LED lamp or the like.

  That is, on the effect control board 60, a control processor (computer circuit) GEPR realized by a general-purpose one-chip microcomputer, and an image processor VDP (Video Display Processor) that realizes image effect on the display device 7 under the control of the control processor GEPR. ), a watchdog timer WDT that outputs an abnormal reset signal ERST during program runaway of the computer circuit GEPR, a control memory PROM that stores the control program of the control processor GEPR, and an image memory that stores image basic data of the image processor VDP. And a CGROM.

  On the other hand, on the production interface board 61, a voice processor (speech synthesis circuit) SDPR for realizing voice production based on the control of the control processor GEPR, a voice memory SDROM for storing sound source data of the voice processor SDPR, and a voice processor SDPR. The first and second digital amplifiers AMP1 and AMP2 for amplifying and outputting the audio signal output by the device, the audio memory SDROM, the image processor VDP, and the control processor GEPR by receiving the DC voltage 3.3V and the power supply reset signal RES. A first reset circuit RST1 for resetting the power supply, a second reset circuit RST2 for abnormally resetting the voice processor SDPR in response to the DC voltage 3.3V and the abnormal reset signal ERST, and a converter circuit DC/DC for level converting the DC voltage, Is installed (Fig. 12).

  As illustrated, the first digital amplifier AMP1 drives the upper speakers SPtL, SPtR, and the second digital amplifier AMP2 drives the lower speakers SPbL, SPbR.

  Further, the production interface board 61 is connected to the rotating body LED drive board DR1, the LED board DR1 and the inverter board DR2, and the boards DR1 to DR3 are connected to an LED group and a cold cathode ray tube discharge tube. Has been done. As described above, the performance control board 60 and the performance interface board 61 are integrated by connector connection, and the control processor GEPR of the performance control board 60 uses an LED lamp or a cold cathode ray tube discharge tube. The lamp effect is executed at an appropriate timing together with the image effect and the sound effect.

  Next, the main control board 50 will be described. The main control board 50 is connected to various game members of the slot machine through the game relay board IM1. Specifically, a start switch of the start lever 17, a stop switch of the stop buttons 18a to 18c, a close switch of the closing buttons 15 and 16, a clearing switch of the clearing button 14, a door sensor for recognizing opening/closing of the front panel 2, an upstream sensor. A lever detection sensor that constitutes S0, photo interrupters PH1 and PH2 that constitute medal passage sensors S1 and S2, a blocker solenoid SL that controls ON/OFF of a blocker that blocks the passage of illegal medals, and various LED elements 9 to 11, etc. It is connected to the.

  The medal selecting device 21 of the present embodiment is configured by incorporating an upstream sensor S0 (lever detecting sensor), medal passing sensors S1 and S2 (photo interrupters PH1 and PH2), and a blocker solenoid SL, An upstream sensor S0 is arranged in the most upstream position in the vicinity of the medal slot 12, and a pair of medal passage sensors S1, S2 are arranged in the downstream position thereof via a blocker.

  Specifically, the upstream sensor S0 is configured to include a lever LV that is pressed by the medal surface and swings, and a photo interrupter PH that is turned on/off in response to the swing of the lever LV. There is. The upstream sensor S0 is configured to be in the ON state when the medal surface passes the medal pressing the lever LV, and returns to the OFF state after the medal passes.

  The blocker is arranged at the downstream position of the above-described upstream sensor S0, and has an introduction posture that allows passage of a medal when the blocker solenoid SL is energized, and has a return posture that refuses passage of a medal when not energized.

  As shown in FIG. 5, the main control board 50 detects three stepping motors for rotating the rotary reels 4a to 4c and the reference positions of the rotary reels 4a to 4c via the spinning drum relay board IM2. It is connected to the index sensor. Then, by driving or stopping the stepping motor, the rotating operation of the rotating reels 4a to 4c and the stopping operation at the target position are realized.

  The main control board 50 is also connected to the medal payout device 5 through the payout relay board PAY. The medal payout device 5 is provided with a medal payout control board ME, a medal full sensor, a medal payout sensor, and a payout motor M. The medal payout control board ME receives a control command from the main control board 50. Based on this, the payout motor M is rotated to pay out a predetermined amount of medals.

  The medal full sensor detects an overflow abnormality when the medals are full in the auxiliary storage, and the medal payout sensor detects an insufficient shortage of the number of medals to be paid out or an abnormal payout without a payout operation by the gaming machine. ing. In addition, the main control board 50 is also connected to the external centralized terminal board OUT and the rotating body setting board SET. The external centralized terminal board OUT is connected to, for example, the hall computer HC, and the main control board 50 outputs the number of inserted medals, the number of paid out medals, etc. through the external centralized terminal board OUT.

  Further, the rotating cylinder setting board SET outputs a setting key signal or the like indicating a setting value set by the staff using the setting key. Here, the set value defines the winning probability of the lottery process executed in the gaming machine in six stages from setting 1 to setting 6, and is appropriately set based on the game hall business strategy. .. For example, the gaming machine set to the highest rank is the most advantageous to the player because the expected value of the number of paid-out medals is at the highest level.

  FIG. 6 illustrates a circuit configuration of the main control board 50. As shown in the figure, the main control board 50 includes a one-chip microcomputer 64, an I/O port circuit 65 for inputting/outputting 8-bit parallel data, a counter circuit 66 for generating a random number value by hardware, an effect control board 60, etc. It is mainly composed of an interface circuit with an external board. Here, the one-chip microcomputer 64 contains a CTC (Counter/Timer Circuit) 64b, an interrupt controller 64c, and the like in addition to the CPU core 64a, ROM, RAM, and the like of the Z80 equivalent product.

  The CTC 64b is a circuit in which an 8-bit counter and a timer are integrated, and provides the Z80 system with a periodic interrupt, a fixed period pulse output creation function (bit rate generator), and a time measurement function. Therefore, in this embodiment, the CTC 64b is used to cause the Z80CPU 64a to generate a timer interrupt at a time interval τ of 1.5 mS.

  As the interface circuit, an interface circuit 67 with the power supply circuit, an interface circuit 68 with the game relay board IM1, a spinning motor drive circuit 69, an interface circuit 70 with the effect control board 60, and the like are provided. There is. When the power is cut off (when the power is cut off), a voltage drop interrupt is applied to the Z80CPU64a through the interface circuit 67.

  The interface circuit 70 is an 8-bit parallel port for outputting a control command to the effect control board 60, and the spinning drum motor drive circuit 69 is a circuit for generating drive signals for the stepping motors of the rotary reels 4a to 4c. .. The three stepping motors that rotate the rotating reels 4a to 4c are two-phase motors each having two sets of drive windings, and are driven by 1-2-phase excitation that repeats one-phase excitation and two-phase excitation. There is.

  As shown in FIG. 6, the interface circuit 68 of the main control board 50 is connected to the medal selecting device 21 via the game relay board IM1. The sensor signal S0 of the upstream sensor S0 is input to the input circuit IN0, and the sensor signals S1 and S2 of the medal passage sensor S1 and the medal passage sensor S2 are input to the input circuits IN1 and IN2. The energization state of the blocker solenoid SL is controlled by the output circuit.

  FIG. 7 illustrates the internal configuration of the first power supply board 62A, the second power supply board 62B, and the effect interface board 61, mainly with respect to the power supply line. FIG. 8 is a circuit diagram showing a part of the first power supply board 62A.

  First, the first power supply board 62A includes a filter circuit including an input resistor R0 and an input capacitor C0, an overvoltage countermeasure circuit PRT in which varistor groups VR1, VR1 and VR2 are arranged, a common mode choke coil LL, and capacitor arrays C1 and C1. C2 and are provided.

  Here, the common mode choke coil is a choke coil in which the winding directions of two coil windings wound around a magnetic core are opposite to each other. Therefore, when a common mode noise current flows through each winding, the direction of the magnetic flux generated by each noise current becomes the same direction, and the counter electromotive force generated in each winding is strengthened, so that the noise current is suppressed. Will increase.

  The capacitor rows C1, C1, C2 are composed of a pair of capacitors C1, C1 arranged between the frame ground FG and the AC power supply line, and a capacitor C2 arranged between the AC power supply line. .. The capacitors C1 and C1 absorb common mode noise, and the capacitor C2 and the filter circuits C0 and R0 absorb normal mode noise.

  The overvoltage countermeasure circuit PRT functions to prevent surge voltage and other overvoltages from reaching the downstream side because the electrical resistances of the varistors VR1 and VR2 sharply decrease during overvoltage. Further, since the three varistor VR1, VR1, VR2 are arranged in the same manner as the capacitor arrays C1, C1, C2, when the varistor is not energized normally, the varistor functions as a capacitance element and operates in the common mode and the normal mode. It also functions as a noise countermeasure.

  Since such an anti-noise measure is applied to the input section of the first power supply board, the propagation noise to the commercial power supply line (100V) is effectively suppressed. Then, a step-down transformer is arranged on the downstream side of the capacitor arrays C1, C1, C2, and is stepped down from AC100V to AC24V to be distributed to the second power supply board 62B. The power supply reset signal RES and the power interruption signals ABN1 and ABN2 are generated based on this AC24V.

  On the other hand, 100 VAC is rectified by the full-wave rectifying circuit RECT, and then the power factor is improved in the power factor improving circuit 24 via the overcurrent prevention circuit RUSH. Then, the DC currents 36V, 18V, 24VA, 12VB are generated by the two LLC current resonance type DC/DC converters 25, 26. In the present specification, the symbols A and B added to the voltage values indicate the circuit boards to which power is to be distributed, and the DC voltage to which the additional symbol A is added is distributed to the main control board 50. The DC voltage with B is distributed to the production interface board 61.

  FIG. 8 is a circuit diagram showing an overcurrent prevention circuit RUSH, a power factor correction circuit 24, and LLC current resonance type DC/DC converters (hereinafter sometimes abbreviated as DC converters) 25 and 26. The LLC current resonance type DC converter 25 and the DC converter 26 have the same circuit configuration, and one output voltage is 36V, 18V, while the other output voltage is 24VB, 12VB. The details of the DC converter 26 are not shown in FIG. 8 because there is only a difference (see FIG. 7).

  First, the overcurrent prevention circuit RUSH is mainly composed of a current limiting resistor R0, a switching transistor Tr0, and a half-wave rectification circuit. The half-wave rectifier circuit rectifies the high-frequency voltage from the DC converter 25 and the sense transformers T2 and T2′ electromagnetically coupled to the high-frequency transformers TF1 and TF2 of the DC converter 26 to control the ON/OFF state of the switching transistor Tr0. is doing.

  That is, immediately after the power is turned on, the output level of the half-wave rectifier circuit is low, so that the switching transistor Tr0 is in the OFF state and the output current of the full-wave rectifier circuit RECT flows through the current limiting resistor R0. , The rush current is suppressed. Then, thereafter, the output level of the half-wave rectifier circuit rapidly rises, so that the switching transistor Tr0 is turned on, and the entire output current of the full-wave rectifier circuit RECT flows through the switching transistor Tr0. Therefore, power consumption in the current limiting resistor R0 does not continue.

  As shown in FIG. 9, the power factor correction circuit 24 includes a dedicated electronic element (IC) PFC, a choke coil L1, a switching transistor Tr1, current detection resistors RS1 and RS2, and a rectified voltage detection resistor. 9B includes a snubber circuit in which a resistor R1 and a capacitor C1 are connected in series, a smoothing circuit including a diode D1 and a capacitor C2, and output voltage detection resistors RO1 and RO2. ), it is operating in continuous current mode.

  The electronic element PFC includes a current detector (IL Dect), a multiplier (multiplier), a sawtooth wave generator (Saw tooth OSC) with a switching frequency of about 60 kHz, a comparator (PWM Com) that outputs a PWM wave, and a driver. And a portion Dr. Then, based on the rectified voltage specified by the detection resistors RV1 and RV2, the rectified current specified by the detection resistors RV1 and RV2, and the output voltage specified by the detection resistors RO1 and RO2, a PWM having a switching frequency of about 60 kHz is used. Outputting waves.

  As a result, the switching transistor Tr1 is turned on/off within an appropriate conduction time, and the on-current of the transistor Tr1 is smoothed by the choke coil L1 to improve the power factor as shown in FIG. 9(b). Will be the coil current. Further, since the spike-shaped energized current does not flow through the rectifier diode as in the case of only the full-wave rectifier circuit, the harmonic of the spike-shaped energized current does not become a noise source of the power supply circuit.

  However, by providing the power factor correction circuit 24, an ON current of the switching frequency flows in the transistor Tr1 (see the drain potential in FIG. 9B), and this ON current (PWM wave) may become a noise source. There is also. Therefore, in this embodiment, the snubber circuit including the resistor R1 and the capacitor C1 is provided between the drain and source of the transistor to effectively suppress the generation of high frequency noise.

  Next, the LLC current resonance type DC converters 25 and 26 will be described. Here, the LLC current resonance type DC converter is a DC converter in which a series resonance circuit is formed by an exciting inductance Lm and a leakage inductance Lr of the high frequency transformers TF1 and TF2 (see FIG. 11) and a resonance capacitor Cr. is there. Then, the switching transistors arranged in the half-bridge type or the full-bridge type are optimally turned on/off by the LLC resonance circuit, and the DC voltage is obtained from the rectification circuit provided on the output side of the high frequency transformers TF1 and TF2.

  A specific circuit configuration is as shown in FIG. 8 regarding the DC converter 25. The illustrated DC converter 25 includes a dedicated electronic element (IC) LLC and switching transistors Tr2 and Tr3 arranged in an asymmetric half bridge type. And a primary side T1 and secondary sides T5, T6 of the high frequency transformer TF1 and two rectifying circuits. The internal structure of the dedicated IC (LLC) is as shown in FIG.

  The rectifier circuit includes a first full-wave rectifier circuit including rectifier diodes D10, D11, D12, and D13 that receive a high-frequency voltage generated on the secondary sides T5 and T6 of the high-frequency transformer TF1, and a secondary side T5 and T6 of the high-frequency transformer TF1. It is divided into a second full-wave rectifier circuit including rectifier diodes D12 and D13 that receive the generated high-frequency voltage. Then, the bridge-type first full-wave rectifier circuit outputs 36 V DC, and the second full-wave rectifier circuit outputs 18 V DC.

  The operation content is as shown in FIGS. 11A to 11J regarding the principle diagram. As shown in the drawing, the high frequency transformer TF1 is an equivalent circuit in which a leakage inductance Lr and an exciting inductance Lm are connected in series, and the high frequency transformer TF1 is connected to the secondary side of the ideal transformer corresponding to the primary currents I2 and I3 of the ideal transformer. A secondary current (load current) Io corresponding to the winding ratio N2 flows.

  As shown in the figure, in the operation state of Tr2=ON and Tr3=OFF in FIGS. 11A and 11J, the LC resonance current I2 flows in the primary circuit, and the secondary current Io corresponding to the winding number ratio N2 is generated. It flows to the secondary circuit. 11(e) and 11(f) with Tr2=OFF and Tr3=ON, the LC resonance current I3 flows in the primary circuit, and the secondary current Io corresponding to the winding ratio N2 is secondary. Flowing into the circuit. Then, in each operating state, the full-wave rectifier circuit functions to generate a DC voltage of a predetermined level.

  The DC converters 25 and 26 of the first power supply board 62A shown in FIG. 7 have been described above. Next, the second power supply board 62B will be described based on FIG. 7. As illustrated, the second power supply board 62B receives DC 24V from the first power supply board and generates DC voltages 12VA, 5VA, 5VB of respective levels, and DC/DC converters 27A to 27C and DC/DC converters 27A to 27C. A voltage drop detection unit 28 that receives a detection voltage corresponding to the output voltage of 27C to detect an abnormality in any output voltage, and an AC monitor that receives AC24V from the first power supply board 29A to detect power-on and power-off. The circuit 29, a power-on state detection circuit 30, and a current interruption state detection circuit 31 are included.

  The AC monitoring circuit 29 includes a rectifier circuit that receives the AC 24 and a photocoupler, and the DC output of the rectifier circuit turns on the photodiode. Therefore, the phototransistor quickly turns on when the power is turned on, and the phototransistor quickly turns off when the power is cut off. Then, the detection circuit 30 outputs the power supply reset signal RES in response to the ON transition operation of the phototransistor, and the detection circuit 31 outputs the power interruption signals ABN1 and ABN2 in response to the OFF transition operation of the phototransistor. ..

  At the bottom of FIG. 7, a part of the effect interface board 61 is described. As shown, the production interface board 61 receives the power interruption signal ANB2, the power supply reset signal RES, and the DC voltage 5VB from the second power supply board 62B, and receives the DC voltages 12VB, 18V, and 5VB from the first power supply board 62A. Is configured.

  FIG. 12A is a circuit diagram for explaining the function of the effect interface board 61. As shown in FIG. 12A, the production interface board 61 receives the DC5VB received from the second power supply board 62B and generates DC 3.3V and DC 1.0V, and the first and second DC/DC converters 32A and 32B. A reset circuit RST1, a second reset circuit RST2, a voice processor (voice synthesis circuit) SDPR that realizes a voice effect based on the control of the control processor GEPR, and a voice memory SDROM that stores sound source data of the voice processor SDPR are shown. Has been done.

  The sound memory SDROM stores, as sound source data, a series of background music for one song (BGM) and a sound effect such as a set of notice sounds as phrase compression data corresponding to the phrase numbers. ing.

  The first reset circuit RST1 receives the DC voltage 3.3V and the power supply reset signal RES and resets the power supply of the audio memory SDROM, the image processor VDP, and the control processor GEPR (see FIG. 5). Further, the second reset circuit RST2 receives the DC voltage 3.3V and the abnormal reset signal ERST and abnormally resets the voice processor SDPR. As described above, the abnormal reset signal ERST is an output signal from the watchdog timer WDT that indicates that the control processor GEPR has runaway.

  The first and second reset circuits RST1 and RST2 are the same circuit except the capacitors Cd1 and Cd2, and have voltage dividing resistors R10 and R11 that divide the DC voltage VDD, a comparator CMP, a delay circuit Dely, and a delay time. It is configured to have capacitors Cd1 and Cd2 that define (reset periods T1 and T2), and complementary-connected output transistor CMOS.

  In the case of the first reset circuit RST1, the power supply reset signal RES received from the second power supply board 62B is supplied to the delay circuit Dely. Then, as shown in the time chart of FIG. 12B, after the power supply reset signal RES transits from the L level to the H level, the reset signal RESET1 that maintains the L level for the reset period T1 defined by the capacitor Cd1 is output. It

  Further, even when the DC voltage VDD exceeds the specified level, the reset signal RESET1 having the same reset period T1 is output. In the case of the present embodiment, the timing at which the DC voltage VDD exceeds the specified level and the timing at which the power supply reset signal RES transitions to the H level are close to each other, so either the later timing or the predetermined reset period T1 , The reset signal RESET1 that maintains the L level is output.

  In the case of this embodiment, the DC voltage VDD=3.3V is the power supply voltage of the audio processor SDPR and the audio memory SDROM, and the reset period T1 of the reset signal RESET1 is about 1 to 5 μS. Therefore, after the power supply voltage 3.3V of the normal level is supplied to the audio memory SDROM, the audio memory SDROM is brought into the activation start state after a reset period T1 of about 1 to 5 μS.

  Next, the second reset circuit RST2 outputs the reset signal RESET2 having the predetermined reset period T2 when the DC voltage VDD=3.3V exceeds the specified level. The reset period T2 is set to be three times or more as long as the reset period T1, and is preferably about 7 to 15 μS.

  In the case of the present embodiment, the power supply voltage of the audio processor SDPR is 3.3V and 1.0V, but since the two DC voltages reach the specified level at the close timing, the power supply voltage of the audio processor SDPR is 3.3V. , 1.0V has reached the specified level, the voice memory SDROM reaches the activation start state, and then the voice processor SDPR is activated. Therefore, even if the started voice processor SDPR immediately accesses the voice memory SDROM, no trouble occurs.

  In addition, the abnormal reset signal ERST received from the effect control board 60 is supplied to the delay circuit Dely of the second reset circuit RST2. Therefore, when the control processor GEPR runs out of control, the audio processor SDPR is abnormally reset together with the control processor GEPR and the image processor VDP based on the abnormal reset signal ERST. Therefore, the image effect, the lamp effect, and the sound effect by the control processor GEPR are synchronously returned to the initial state, and the unnatural effect is not continued.

  FIG. 13 is an internal configuration of a sequential access type audio memory SDROM (FIG. 13A) and a time chart (FIG. 13B) when the audio processor SDPR accesses (memory read) the audio memory SDROM. .. Here, the sequential access means an operation of reading a series of data following the head address at once in a memory read operation after transmitting the head address to the audio memory SDROM.

  As shown in FIG. 12, the audio processor SDPR, the audio memory SDROM, the 16-bit length I/O bus, the command latch enable signal CLE, the chip enable signal CE, the write enable signal WE, and the address latch. They are connected by an enable signal ALE, a read enable signal RE, and a ready/busy signal RB.

  The I/O bus is used for transmitting address information and transmitting/receiving 16-bit data. In the memory read operation, the audio processor SDPR first outputs command data (for example, 0000H) in synchronization with the command latch enable signal CLE, and then, in synchronization with the write enable signal WE at predetermined intervals. , The head address of the audio data read operation is sequentially output in 16-bit units (Address Write cycle).

  Then, the audio processor SDPR repeats the output operation of the read enable signal RE at a predetermined time interval to sequentially access the audio data after the head address. In the case of this embodiment, the audio memory SDROM has one page of N*16 bits and one block of M pages.

  By repeating the output operation of the read enable signal RE, the memory read operation for one block at the maximum can be realized. In this embodiment, one block has a length of M*N*16 bits, which has an advantage that a large amount of voice data can be obtained at a stretch without transmitting address information. Therefore, it is possible to quickly obtain a long-time effect sound.

  FIG. 14A shows the schematic internal configuration of the audio processor SDPR, the connection relationship between the control processor GEPR (host CPU), the audio memory SDROM, and the digital amplifier AMP. Further, FIG. 15 illustrates the internal configuration of the voice synthesis circuit in more detail.

  As shown in FIG. 14A, the audio processor SDPR includes a number of audio control registers 51 (RGi, RSj) accessed from the control processor GEPR, a sound control module 52 that controls the audio reproduction operation, and a sound control module 52. A main generator 53 that decodes the phrase compression data read from the memory SDROM and mixes the decoded data of the plurality of phrase reproduction channels CH0 to CH15 at an appropriate volume ratio, and a desired frequency characteristic by digital filtering. Effector 54 that realizes an equalizer function that realizes the above and a compressor function that changes the input/output gain characteristics, a total volume TV that defines the final volume, and four types of signals SCLK, LRCLK, SDO0, and SDO1 for serial transmission are generated. And a digital IF unit 55 that operates.

  The voice control register 51 performs write processing by the control processor GEPR in order to write the voice processor SDPR to function as intended, and read control processing by the control processor GEPR in order to grasp the operating state of the voice processor SDPR. Read register RSj.

  A register address of 1-byte length is given to each voice control register 51, an operation parameter (setting value) of 1-byte length can be written in the write register RGi, and a 1-byte length is read from the read register RSj. The status information of is acquired. Then, when the control processor GEPR makes a read access to the write register RGi, the voice command SND having a 2-byte length of register address+operation parameter is transmitted from the control processor GEPR to the voice processor SDPR.

  The write data (setting value) to the write register RGi includes (1) a phrase number that specifies a BGM sound or effect sound to be reproduced, (2) a volume (V1, V2) instruction of the reproduced sound, and (3) ) Loop instruction for defining the number of times of reproduction, (4) Operation instruction such as start and pause of reproduction, (5) Instruction of pan pot which is volume balance of upper and lower speakers and left and right speakers, (6) Final volume (TV) Includes instructions, etc.

  As shown in FIG. 14, the audio processor SDPR functions at the power supply voltage of 3.3V and 1.0V, receives the reset signal RESET2 of the reset period T2 from the reset circuit RST2, and is reset to the initial state. As described above, the reset circuit RST2 functions based on the power supply voltage 3.3V and the abnormal reset signal ERST, so that the audio processor SDPR does not only operate when the power is turned on but also when the control processor GEPR is abnormal. It is reset in synchronization with GEPR.

  Next, returning to FIG. 12, the connection relationship between the control processor GEPR and the voice processor SDPR will be described. As shown in FIG. 12, the control processor GEPR and the voice processor SDPR have parallel signal lines (data buses) CD0 to CD7 capable of transmitting/receiving 1-byte data and an operation management data line having a 2-bit length (data bus) capable of transmitting operation management data ( The address buses A0 to A1 are connected to the control signal lines WR and RD having a 2-bit length capable of controlling read/write operations, and the chip select signal line CS for selecting the audio processor SDPR.

  The parallel signal lines CD0 to CD7 are realized by the data bus of the control processor GEPR, and the operation management data lines A0 to A1 are realized by the address bus of the control processor GEPR. The audio processor SDPR is provided with three port numbers PORT having the upper 6 bits in common and the lower 2 bits of 00, 01, and 10, and the control processor GEPR gives the I/Os for these port numbers PORT. When the /OREAD command or the I/OWRITE command is executed, the chip select signal CS becomes the active level in any case.

  The data output to the lower 2 bits A0 to A1 of the address bus when the I/OREAD instruction or the I/OWRITE instruction is executed becomes the operation management data A0 to A1 for the audio processor SDPR, and these 2 bits A0 to A1. Based on this, whether the 1-byte data of the data buses CD0 to CD7 at that time is a register address, or write data or read data is specified.

  That is, if the address data A0 to A1 is [00], the data CD0 to CD7 of the data bus at that timing is evaluated as a register address, while if the address data A0 to A1 is [01], The data CD0 to CD7 on the timing data bus become write data or read data. Note that the case where the I/OREAD instruction is executed is the read data, and the case where the I/OWRITE instruction is executed is the write data.

  Therefore, the transmission operation (write operation) of the voice command SND for writing the predetermined setting value in the predetermined voice control register RGi is as shown in the time chart of FIG. 12C, and the port number PORT of the voice processor SDPR is set. It is realized by continuously executing the I/OWRITE instruction while shifting the lower 2 bits A0 and A1. Specifically, the lower 2 bits A0 to A1 of the address data are changed from [00] to [01], while the 1-byte data of the data bus is changed from [register address of voice control register RGi] to [voice control. [Write data to register RGi]], a predetermined voice command SND transmission operation is realized.

  When transmitting the SAC number (13 bits), sequence code number (13 bits), and control data (standby information, loop information, etc.) that accompanies this, the write data has a multi-byte length When the register addresses of the register are consecutive, the operation management data A0 to A1 of [01] are repeated in the order of [00]→[01]→[01]→[01], and the write data of a plurality of bytes is transmitted. ..

  The voice command transmitted in this manner is subsequently executed in the voice processor SDPR unless there is a communication abnormality. However, if a communication abnormality is recognized, such as when the data of a plurality of bytes does not match each other, the voice command SND is not activated. Then, the error flag of the voice control register RSj is set, and this error flag (status information STS) changes the operation management data A0 to A1 of the address bus from [01=1] to [10=2]. It can be received by executing the I/O READ command (see FIG. 12(e)).

  As described above, in this embodiment, in the final cycle in which the operation management data A0 to A1 are transited from [00]→[01]→... [01]→[10], error information (abnormality) of a plurality of bit lengths FFH) can be obtained. Then, by retransmitting the voice command SND that could not be legitimately transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to reliably eliminate the unnaturalness in which the voice effect suddenly stops.

  On the other hand, the data read operation by the I/OREAD operation is as shown in the time chart of FIG. 12D, and while the lower 2 bits A0 and A1 of the port number PORT of the audio processor SDPR are changed, the I/OWRITE instruction and , I/OREAD instructions are continuously executed. Here, the upper 6 bits of the port number PORT generate a chip select signal for the audio processor SDPR to enable the I/OWRITE command and I/OREAD to the audio processor SDPR.

  Specifically, first, as an I/OWRITE operation, for the port number PORT in which the lower two bits A0 to A1 of the address data are [00], [register address of the voice control register RSj for storing operation status etc. (1 byte length)] is output. Next, if the I/OREAD instruction is executed for the port number PORT in which the lower two bits A0 to A1 of the address data are [01], the necessary data such as the operation status can be obtained from the predetermined voice control register. You can When the read data has a length of a plurality of bytes, the I/OREAD instruction is made continuous for the required number of bytes.

  As shown in FIG. 14, the audio reproduced by the audio processor SDPR having the above-described configuration is converted into a digital audio signal of the audio processor SDPR in the form of a 4-bit signal (SCLK, LRO, SDO0, SDO1) and digital amplifier AMP1. , AMP2, is class D amplified by each digital amplifier, and is supplied to each speaker as an analog audio signal. Specifically, the amplified output (analog audio signal) of the digital amplifier AMP2 is supplied to the lower speakers SPbL and SPbR for bass, and the amplified output (analog audio signal) of the digital amplifier AMP1 is the upper speaker SPtL, It is supplied with SPtR.

  As shown in FIGS. 14A and 15, the main generator 53 includes a decoder 60 divided into 16 phrase reproduction channels (CH0 to CH15) that can be independently decoded, a primary volume V1, and a secondary volume. It has a volume V2 and a channel volume having a panpot section capable of adjusting a sound volume and a volume balance, and a channel mix section 61 for mixing sounds of 16 phrase reproduction channels (CH0 to CH15). Is configured.

  As shown in FIG. 15, the L0 signal, the R0 signal, the R1 signal, and the L1 signal are output for each phrase reproduction channel (CH0 to CH15). These four types of signals (16×4 in total) are The signals are mixed in the channel mix unit 61 and output as a mixed L0 signal, a mixed R0 signal, a mixed R1 signal, and a mixed L1 signal.

  Here, the mixed L0 signal is finally supplied to the left upper speaker SPtL, the mixed R0 signal is finally supplied to the right upper speaker SPtR, and the mixed R1 signal and the mixed L1 signal are finally It is supplied to the lower speakers SPbL and SPbR. At this stage, each of the signals (L0, R0, R1, L1) is digital data.

  In the case of the present embodiment, (1) phrase number designation, (2) volume (V1/V2) instruction, (3) loop instruction, (4) operation instruction, (5) voice transition mode instruction, and (6) All panpot instructions are configured to be performed by designating the phrase reproduction channels CH0 to CH15 of the decoder 60. Therefore, up to 16 types of phrase compression data corresponding to the phrase reproduction channels CH0 to CH15 are independently reproduced based on the above instructions (1) to (6) and mixed by the channel mix section 61. Will be output.

  By the way, the sound control module 52 causes each part of the device to function for each instruction based on the individual instruction from the control processor GEPR written in the control register RGi. In order to simplify the control operation of the control processor GEPR, The voice processor SDPR of this embodiment is provided with a simple access function and a sequencer function.

  Here, the simple access function means that a group of voice command strings (register address+set value) registered in advance in an external memory (specifically, a voice memory SDROM) is converted into a plurality of control registers RGi corresponding thereto. It is a function to write to. In order to implement the simple access function, the control processor GEPR issues a voice command of 2 bytes including a SAC number for identifying a group of voice command sequences and a register address of a dedicated control register to the voice processor SDPR. Just send it to.

  The sequencer function is also the same, and a plurality of groups of voice command strings (register address+set value) registered in advance in the voice memory SDROM are stored in a plurality of control registers RGi corresponding thereto. It is a function to write each. Then, after writing a group of voice command sequences, after a waiting time, by performing an operation such as writing the next group of voice command sequences, functions such as multiple phrase playback and volume/pan can be performed. It becomes possible to execute one after another. In order to implement this sequencer function, it is sufficient to send a voice command of a plurality of bytes including a sequence code number for specifying a group of voice command strings and a register address of a dedicated control register to the voice processor SDPR.

  As described above, the main generator 53 includes the decoder 60 divided into a plurality of phrase reproduction channels, and the channel volume having the primary volume section V1 and the secondary volume section V2 (FIG. 15). Therefore, corresponding to such a configuration, the control processor GEPR of the present embodiment uses the decoders of the phrase reproduction channels CH0 to CH1 to reproduce the BGM sound, and 13 phrases to reproduce the effect sound. One of the reproduction channels CH2 to CH14 is used in an idle state, and the decoder of the phrase reproduction channel CH15 is used for voice notification for notifying the occurrence of a serious abnormal situation.

  Then, by appropriately setting the volume balance of the primary volume V1 of the phrase reproduction channels CH0 to CH14 for realizing the sound effect, the effective sound effect is realized. Specifically, when the effect sound is output, the sound volume of the BGM sound is suppressed to prevent missing of the effect sound. In the present embodiment, the effect sound is, for example, a warning sound that gives a warning with a predetermined reliability (≦100%) that there is a possibility of shifting to the big hit state during a series of fluctuation operations, and the phrase reproduction channel CH0. By appropriately setting the volume balance of the primary volume V1 of CH14, it is possible to eliminate the possibility that the notice sound important to the player is hidden by the loud BGM sound.

  Further, in this embodiment, the upper and lower panpots can be set for each phrase reproduction channel, so that the control processor GEPR determines that the upper speaker has a slightly higher volume based on the positional relationship between the upper speaker and the lower speaker. Therefore, the volume balance is set for all phrase playback channels. Specifically, for all phrase reproduction channels, in order to set the upper and lower panpot settings to an appropriate volume ratio, write appropriate operating parameters in the control register for the upper and lower panpots, and set the upper and lower panpot ratios to, for example, It is set to +2 dB:-2 bB (FIG. 15).

  Further, in the present embodiment, the left and right panpots can be set for each phrase reproduction channel. Therefore, when reproducing stereo sound, a pair of adjacent phrase reproduction channels CHi and CHi+1 are used and the phrase reproduction channel is used. In CHi and CHi+1, the left/right panpot ratio is appropriately set.

  For example, for background music, the phrase reproduction channels CH0 and CH1 are used, and the left and right panpot ratio L0 of the phrase reproduction channel CH0 is set to supply the L0 signal (left audio) of CH0 to the left upper speaker SPtL: R0 is set to 0 dB: −∞ dB. Further, the left and right panpot ratio L0:R0 of the phrase reproduction channel CH1 is set to −∞ dB:0 dB: in order to supply the R0 signal (right audio) of CH1 to the right upper speaker SPtR.

  Since the left-right panpot ratio L1:R1 of CH0 and the left-right panpot ratio L1:R1 of CH1 are equal ratios of 0 dB:0 dB, the left side sound reproduced by CH0 and the right side sound reproduced by CH1 are In the channel mixing unit 61, the L1 output of CH0 and the L1 output of CH1 are mixed to become the background music L1 of monaural sound. Similarly, the left-side sound reproduced by CH0 and the right-side sound reproduced by CH1 are mixed with the R1 output of CH0 and the R1 output of CH1 in the channel mixing section 61 to become the background music R1 of monaural sound. ..

  Further, in the present embodiment, since the left and right panpots can be set for each phrase reproduction channel, the control processor GEPR sometimes causes the L0 signal for the reproduced sounds of the phrase reproduction channels CH2 to CH14 as part of the notice effect. And the volume balance of the R0 signal is different. In this case, the advance notice sound heard from the left and right upper speakers can be moved, for example, from left to right (pan to the right) or conversely, from right to left (pan to the left).

  As shown in FIG. 15, the output signals (mixing L0, mixing R0, mixing L1, mixing R1) of the channel mix 61 are digitally filtered by the effect unit 54 based on the operation parameters defined in the control register 51. After that, it is supplied to the total volume TV.

  Here, the total volume value TV is defined by the operation parameter written in the corresponding control register 51. In the present embodiment, this operation parameter is, in principle, defined based on the setting switch operated by the clerk. It However, when the player operates the volume switch during the game operation (however, during the sound effect standby), the total volume TV is defined based on the set value.

  The audio signals (PCM data) mixed L0, mixed R0, mixed L1, and mixed R1 that have passed through the total volume unit TV are stored in the output buffer BUF and converted into two types of serial signals SDO0 and SDO1 based on the digital IF unit 55. To be done. Here, the serial signal SDO0 is a serial signal that specifies PCM data regarding the stereo signals R and L that drive the left and right speakers arranged on the upper portion of the gaming machine, and the serial signal SDO1 is the deep bass sound arranged on the lower portion of the gaming machine. It is a serial signal that specifies PCM data relating to a monaural signal that drives a speaker.

  Then, these serial signals SDO0 and SDO1 are output from the digital IF unit 55 in synchronization with the bit clock signal BCO. Further, the digital IF unit 55 outputs the word clock signal LRO, and specifies whether the contents of the serial signals SDO0 and SDO1 currently being transmitted are the left side signals L0 and L1 or the right side signals R0 and R1. It is supposed to be done.

  As shown in FIG. 14B, these signals SDO0, SDO1, BCO, and LRO are transmitted to the digital amplifiers AMP1 and AMP2. Assume that the digital amplifier AMP of YDA171 (YAMAHA) is used for evaluation. The bit clock signal BCO means the serial clock SCLK, the word clock signal LRO means the channel control signal LRCLK, and the serial signals SDO0 and SDO1 mean SDATA0 and SDATA1.

  The operation of the audio processor SDPR is as shown in FIG. 14B, in which the left-channel audio signals L0 and L1 are transmitted while the word clock signal LRO (channel control signal LRCLK) is maintained at the L level, The right channel audio signals R0 and R1 are transmitted while the clock signal LRO (channel control signal LRCLK) is maintained at the H level. As described above, in the present embodiment, four types of audio signals R0, R1, L0, L1 can be transmitted by four cables, so that signal transmission without voice deterioration due to noise can be performed with the minimum number of cables.

  The serial signals SDO0 and SDO1 are acquired by the digital amplifier AMP in synchronization with the rising edge of the bit clock signal BCO (serial clock signal SCLK). Then, in the digital amplifier AMP, parallel conversion is performed for each predetermined bit length, DA conversion is performed, and then D-class amplification is performed and supplied to each speaker.

  17 and 18 show a case where YDA171 (YAMAHA) is used as a digital amplifier. As shown in the figure, each of the digital amplifiers AMP1 and AMP2 has two built-in class D amplifiers having the same characteristics for the left (L) channel and the right (R) channel.

  The digital amplifier AMP1 shown in FIG. 16 receives the serial clock signal SCLK (BCO), the audio serial signal SDATA0 (SDO0), and the channel control signal LRCLK (LRO), so that the audio signal L0 of the left channel and the right signal are received. The channel audio signal R0 is separated and separately output as analog signals.

  On the other hand, the digital amplifier AMP2 shown in FIG. 17 receives the serial clock signal SCLK (BCO), the audio serial signals SDATA0 and SDATA1 (both are SDO1), and the channel control signal LRCLK (LRO), so that the left channel The audio signals L0 and L1 and the right channel audio signals R0 and R1 are separated and separately output as analog signals.

  As illustrated, the serial signal SDO1 is supplied as the audio serial signal SDATA0 and the audio serial signal SDATA1. Further, in the present embodiment, the left/right panpot ratio for the L1 signal and the R1 signal is the uniform ratio 0 dB:0 dB in all reproduction channels (see FIG. 15 ), so that the mixing L1 after mixing in the channel mixing unit 61 is performed. The signal and the mixed R1 signal are monaural sounds having the same sound volume on the left and right sides and the same sound quality on the left and right sides.

  The mixed L1 and the mixed R1 are transmitted as a serial signal SDO1 for the left and right speakers and supplied to the digital amplifier AMP2 which is circuit-connected as shown in FIG. Therefore, the signals output from the four internal circuits (L0ch, L1ch, R0ch, R1ch) of the digital amplifier AMP2 are all the same sound.

  As shown in FIG. 16, in the digital amplifier AMP1, only the two internal circuits function among the four internal circuits (L0ch, L1ch, R0ch, R1ch) and function as audio signals transmitted to the left upper speaker SPtL. The audio signal R0 transmitted to L0 and the right upper speaker SPtR is output from the digital amplifier AMP1.

  An LC filter including a common mode choke coil CHL1 and capacitor arrays C10, C11, C12 is arranged on the output side of the digital amplifier AMP1. The applicant has so far used a ferrite core and a varistor on the output side of the digital amplifier (Patent Document 2). However, with the knowledge that this configuration cannot effectively suppress the propagation noise to the commercial power supply line, the above configuration was completed as a result of repeated experiments.

  Here, the common mode choke coil has a four-terminal structure in which two coil windings are wound around a ferrite core, and the winding directions of the pair of windings are opposite to each other. Therefore, when a common mode noise current flows through each winding, the direction of the magnetic flux generated by each noise current becomes the same direction, and the counter electromotive force generated in each winding is strengthened, so that the noise current is suppressed. Is increased (see FIG. 16B).

  On the other hand, with respect to the differential current in the differential direction, the direction of the magnetic flux generated by the differential current in each winding is opposite, so the counter electromotive force generated in each winding is canceled and it does not function as an inductor. , Does not disturb the differential current at all. That is, the choke coil CHL1 of the embodiment cooperates with the capacitor arrays C10, C11, and C12 to not only smooth the output signal from the digital amplifier AMP1 but also suppress common-mode noise to the commercial power line. Effectively suppresses the propagation noise of.

  Hereinafter, the LC filter that smoothes the output signal from the digital amplifier AMP1 will be described with reference to FIGS. As shown in FIG. 16C, on the output side of the digital amplifier AMP, a pair of upper and lower transistor groups Q1 and Q2 forming a CMOS structure are arranged. 16C, the common mode choke coil CHL1 is connected between the connection point OUTPL0 of the upper transistor groups Q1 and Q2 and the connection point OUTML0 of the lower transistor groups Q1 and Q2.

  In addition, the capacitor C10 is arranged between the two output terminals of the common mode choke coil CHL1, and the capacitors C11 and C12 are arranged between the two output terminals of the choke coil CHL1 and the ground, respectively. Has been realized. The circuit constant of each element is individually set based on the switching frequency Fs (250 KHz to 1.5 MHz) that defines the internal operation of the digital amplifier, but typically, the common mode choke coil is 10 to 30 μH. It is concluded that CHL1, a capacitor C11, C12 (C11=C12) of 0.05 to 0.2 μF, and a capacitor C10 having a capacitance about 2 to 3 times that of the capacitors C11, C12 should be used. is doing.

  Hereinafter, inside the digital amplifiers AMP1 and AMP2, the duty ratio τ of the PWM wave changes based on the digital audio signals L0 and R0 received from the audio processor SDPR, but on the basis of this PWM wave, the upper transistor group Q1, The transistor Q2 and the transistors of the lower transistor groups Q1 and Q2 are ON/OFF driven.

  FIG. 16C shows the case where the duty ratio τ of the PWM wave of the frequency Fs is 50%, and when the PWM wave is at the H level (left side), the transistor Q2 of the upper transistor group and the lower transistor The transistor Q1 of the group is turned on. Therefore, when the capacitor C11 is charged, the potential difference between the capacitor C11 and the ground tends to increase, while the charge in the capacitor C12 is discharged, the potential difference between the capacitor C12 and the ground tends to decrease.

  Next, when the PWM wave is at the L level (right side), the transistor Q1 of the upper transistor group and the transistor Q2 of the lower transistor group are turned on. Therefore, as the capacitor C12 is charged, the potential difference between the capacitor C12 and the ground tends to increase, while the charge in the capacitor C11 is discharged, the potential difference between the capacitor C11 and the ground tends to decrease.

  When the duty ratio τ of the PWM wave is 50%, the operating time on the left side of FIG. 16(c) is the same as the operating time on the right side of FIG. 16(c). The potential difference between the capacitor C12 and the ground is the same, the voltage across the capacitor C10 is 0 V, and no audio current flows through the speaker. Even if there is a common mode noise current that has passed through the common mode choke coil CHL1, the common mode current will charge the capacitors C11 and C12 having the same capacitance, so that the voltage across the capacitor C10 will be charged. And is not superposed on the voice current toward the speaker.

  Next, the operation when the duty ratio τ of the PWM wave is higher than 50% will be described with reference to FIG. In this case, the operating time on the left side of FIG. 18A is longer than the operating time on the right side of FIG. 18A, so that the potential of the capacitor C11 is higher than the potential of the capacitor C12 on average. As for the voltage across the capacitor C10, the upper terminal of the capacitor C10 has a lower relationship than the lower terminal, and the illustrated audio current flows.

  On the other hand, when the duty ratio τ of the PWM wave is less than 50%, the operating time on the right side of FIG. 18B is longer than the operating time on the left side of FIG. 18B, so on average, The potential of the capacitor C12 becomes higher than the potential of the capacitor C11, and the voltage across the capacitor C10 is such that the upper terminal of the capacitor C10 is higher than the lower terminal, and the illustrated audio current flows.

  As described above, in this embodiment, as the LC filter, the choke coil CHL1 is arranged with the capacitor rows C10, C11, C12, so that the common mode noise is prevented and the normal mode noise is absorbed in the capacitor C10. , Realizes high-quality audio output to the upper left speaker SPtL. The above points also apply to the upper right speaker SPtR. As described above, stereo can be output from the left and right speakers.

  On the other hand, since the monaural sound is always supplied to the lower speakers SPbL and SPbR, the common audio serial signal (L1+R1) is supplied to the SDATA0 terminal and the SDATA1 terminal of the digital amplifier AMP2, and the upper choke coil CHL1 in the figure is also supplied. In addition, the L0ch output and the R0ch output are overlapped and supplied to drive the lower left speaker SPbL.

  Further, the output of L1ch and the output of R1ch are overlapped and supplied to the lower choke coil CHL1 in the figure to drive the lower right speaker SPbR.

  By adopting such a driving method, the output power of the lower speakers SPbL and SPbR that output monaural sound is increased. Note that, regarding the upper and lower pan pot ratios shown in FIG. 15, the upper side is +0.2 dB and the lower side is −0.2 dB on the assumption of the circuit configuration in FIG.

  Although the embodiments of the present invention have been described in detail above, the specific description does not particularly limit the present invention. For example, although the slot machine has been described in the embodiment, the present invention can be suitably applied to other game machines such as a ball game machine.

50 main control means 60 production control means 62 power supply means GEPR control processor SDROM voice memory SDPR voice processor AMP1, AMP2 digital amplifier CHL1 choke coil C11 first capacitor C12 second capacitor C10 third capacitor

Claims (3)

A power supply means for executing a lottery process based on a predetermined switch signal and generating a DC voltage used by a main control means for integrally controlling a game operation based on the lottery result ,
First choke coil for receiving an AC voltage (LL), and a second rectifying a first circuit for noise countermeasures configured in the downstream side of the capacitor bank (C1, C2), the AC output of the first circuit generating a circuit (RECT), and the second circuit third circuit for improving the power factor by receiving a rectified output voltage of (RECT) (24), a DC output voltage on the basis of an output of said third circuit (24) And a fourth circuit (25) for
Said third circuit (24),
Rectified output voltage of said second circuit (RECT), and, with reference to the DC output voltage of the fourth circuit (25), and a PFC controller for outputting a PWM control signal,
A second choke coil (L1) for smoothing the output current of the second circuit (RECT);
A semiconductor device located downstream of said second choke coil (L1), a first terminal and a second terminal and a third terminal, when turned ON by receiving a PWM control signal to the first terminal, a switching element to between the third terminal and the second terminal is short-circuited,
A snubber circuit which is disposed between the second terminal and the third terminal of the switching element,
A gaming machine characterized by being configured with. The gaming machine according to claim 1 , wherein the snubber circuit includes a series circuit of a resistor and an absorption capacitor. The gaming machine according to claim 2 , wherein a fourth circuit in which a diode and an output capacitor are connected in series is connected in parallel to the snubber circuit.

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