JP6702145B2 - Processor - Google Patents

Description

  The present invention relates to a processing device, and more particularly to a processing device including a microcomputer.

  Conventionally, as this type of processing device, a device including a microcomputer and an IC has been proposed (for example, see Patent Document 1). The microcomputer transmits to the IC the setting information for controlling the engine and the internally generated communication clock. The IC includes a reference clock counter, a diagnostic counter, and a clock diagnostic processing circuit. The reference clock counter counts up with the communication clock. The diagnostic counter counts up with an internal clock generated internally. The clock diagnostic processing circuit stores the count value of the diagnostic counter at the timing when the count value of the reference clock counter becomes the first value, and counts the diagnostic counter at the timing when the count value of the reference clock becomes the second value. The value is stored and the two stored count values are compared. When the two count values are different, it is determined that the internal clock is normal, and when the two count values are the same, it is determined that the internal clock is abnormal, and the diagnostic result is output to the microcomputer. To do. The microcomputer that received the diagnosis result executes various fail-safe processing such as stopping the engine.

JP, 2010-61470, A

  However, in the above-described processing device, when some abnormality occurs in the microcomputer, an abnormality occurs in the communication clock, which causes a problem that the IC cannot operate properly. As a method of avoiding such an inconvenience, it is conceivable that the IC determines whether or not there is an abnormality in the communication clock, and when the abnormality occurs in the communication clock, a process of resetting the microcomputer is executed. However, in this method, the abnormality of the communication clock is caused by some abnormality of the microcomputer, for example, the abnormality of the circuit that generates the communication clock, and even when it is possible to recover without resetting the entire microcomputer, It resets the entire microcomputer. If the entire microcomputer is reset, the vehicle cannot run, so it is desirable to suppress unnecessary resets of the entire microcomputer.

  The processing apparatus of the present invention mainly aims to suppress unnecessary reset of the microcomputer.

  The processing apparatus of the present invention employs the following means in order to achieve the above-mentioned main object.

The processing device of the present invention is
A clock generation circuit that is driven by power from an oscillation power supply to generate an internal clock signal, and a timer signal that counts the generated internal clock signal and clears the count result at every predetermined cycle and has a cycle corresponding to the count result. A watchdog timer for outputting
A processing device comprising:
An instantaneous interruption circuit capable of instantaneously interrupting the power from the oscillation power supply,
A timer signal is input from the microcomputer, and the momentary interruption circuit is controlled so that the oscillation power supply is momentarily interrupted when the period of the input timer signal is out of a predetermined range including the predetermined period, After that, when the cycle of the input timer signal is out of the predetermined range, the microcomputer is reset, and when the cycle of the input timer signal is in the predetermined range, the microcomputer is not reset. ,
The main point is to provide.

  In the processing device of the present invention, the determination processing unit receives the timer signal from the microcomputer, and when the cycle of the input timer signal is outside the predetermined range including the predetermined cycle, the oscillation power supply is momentarily cut off. Control the instantaneous interruption circuit, and thereafter reset the microcomputer when the cycle of the input timer signal is outside the predetermined range, and do not reset the microcomputer when the cycle of the input timer signal is within the predetermined range. . When the cycle of the timer signal is out of the predetermined range including the predetermined cycle, it is considered that some abnormality has occurred in the generation of the internal clock signal. The abnormality includes an abnormality of the clock generation circuit and some abnormality of the microcomputer different from the abnormality of the clock generation circuit. The abnormality of the clock generation circuit may be resolved by momentarily cutting off the supplied power. Therefore, when the cycle of the timer signal is out of the predetermined range, the instantaneous power interruption circuit is controlled so that the oscillation power supply is interrupted, and after that, when the cycle of the input timer signal is out of the predetermined range, that is, When some abnormality of the microcomputer different from the abnormality of the clock generation circuit occurs, the abnormality can be appropriately dealt with by resetting the microcomputer. Further, when the cycle of the timer signal is out of the predetermined range, the instantaneous power interruption circuit is controlled so that the oscillation power supply is interrupted, and after that, when the cycle of the input timer signal is within the predetermined range, that is, The reason why the timer signal is out of the predetermined range is due to an abnormality in the clock generation circuit.When the clock generation circuit returns to normal due to a momentary interruption of the oscillation power supply, the microcomputer is not reset, and the microcomputer Unnecessary reset can be suppressed.

It is a block diagram which shows the outline of a structure of the hybrid vehicle 20 carrying the processing apparatus as an Example of this invention. It is a block diagram which shows the outline of a structure of an electric machine drive system containing motors MG1 and MG2. FIG. 4 is an explanatory diagram illustrating an outline of a configuration of a motor ECU 40. 7 is a flowchart showing an example of a monitoring processing routine executed by the boost control microcomputer 40b. FIG. 8 is an explanatory diagram for explaining an outline of a configuration of a motor ECU 140 of a modified example. 9 is a flowchart showing an example of a monitoring processing routine executed by a monitoring IC 40h of a motor ECU 140 of a modified example. FIG. 8 is an explanatory diagram for explaining an outline of a configuration of a motor ECU 240 of a modified example. 9 is a flowchart showing an example of a monitoring processing routine executed by a motor control microcomputer 40a of a motor ECU 240 of a modified example. It is a flowchart which shows an example of the monitoring process routine of a modification.

  Next, modes for carrying out the present invention will be described using examples.

  FIG. 1 is a configuration diagram showing an outline of a configuration of a hybrid vehicle 20 equipped with a processing device as an embodiment of the present invention. FIG. 2 is a configuration diagram showing an outline of a configuration of an electric machine drive system including motors MG1 and MG2. FIG. 3 is an explanatory diagram for explaining an outline of the configuration of the motor ECU 40. As shown in FIG. 1, the hybrid vehicle 20 of the embodiment includes an engine 22, a planetary gear 30, motors MG1 and MG2, inverters 41 and 42, a battery 50, a step-up/down converter 55, and a system main relay 56. , A hybrid electronic control unit (hereinafter referred to as “HVECU”) 70.

  The engine 22 is configured as an internal combustion engine that outputs power using gasoline, light oil, or the like as fuel. The operation of the engine 22 is controlled by an engine electronic control unit (hereinafter referred to as “engine ECU”) 24.

  Although not shown, the engine ECU 24 is configured as a microprocessor centered on a CPU, and includes, in addition to the CPU, a ROM for storing a processing program, a RAM for temporarily storing data, an input/output port, and a communication port. ..

  Signals from various sensors necessary for controlling the operation of the engine 22, for example, a crank angle θcr from a crank position sensor 23 that detects a rotational position of a crankshaft 26 of the engine 22 are input to the engine ECU 24 from an input port. Has been done.

  Various control signals for controlling the operation of the engine 22 are output from the engine ECU 24 through the output port. The engine ECU 24 is connected to the HVECU 70 via a communication port. The engine ECU 24 calculates the rotation speed Ne of the engine 22 based on the crank angle θcr from the crank position sensor 23.

  The planetary gear 30 is configured as a single pinion type planetary gear mechanism. The sun gear of the planetary gear 30 is connected to the rotor of the motor MG1. The ring gear of the planetary gear 30 is connected to a drive shaft 36 that is connected to the drive wheels 39a and 39b via a differential gear 38. The crankshaft 26 of the engine 22 is connected to the carrier of the planetary gear 30 via a damper 28.

  The motor MG1 is configured as, for example, a synchronous generator motor, and the rotor is connected to the sun gear of the planetary gear 30 as described above. The motor MG2 is configured as, for example, a synchronous generator motor, and the rotor is connected to the drive shaft 36. The inverters 41 and 42 are connected to the motors MG1 and MG2 as well as to the high voltage side power line 54a. The motors MG1 and MG2 are rotationally driven by switching control of a plurality of switching elements (not shown) of the inverters 41 and 42 by an electronic control unit for motor (hereinafter referred to as “motor ECU”) 40.

  The step-up/down converter 55 is connected to a high voltage side power line 54a to which the inverters 41 and 42 are connected and a low voltage side power line 54b to which the battery 50 is connected. The step-up/step-down converter 55 has two switching elements S1 and S2 and a reactor L. The switching element S1 includes a transistor T31 and a diode D31 connected in parallel to the transistor T31 in the opposite direction. The switching element S1 is connected to the positive side line of the high voltage side power line 54a. The switching element S2 includes a transistor T32 and a diode D32 connected in parallel to the transistor T32 in the opposite direction. The switching element S2 is connected to the switching element S1 and the negative-side lines of the high-voltage side power line 54a and the low-voltage side power line 54b. The reactor L is connected to a connection point between the switching elements S1 and S2 and a positive side line of the low voltage side power line 54b. The step-up/step-down converter 55 boosts the power of the low-voltage side power line 54b and supplies it to the high-voltage side power line 54a or the high-voltage side by adjusting the ON time ratio of the transistors T31 and T32 by the motor ECU 40. The power of the side power line 54a is stepped down and supplied to the low voltage side power line 54b. A smoothing capacitor 57 is attached to the positive and negative lines of the high voltage side power line 54a, and the positive and negative lines of the low voltage side power line 54b are provided for smoothing. A capacitor 58 is attached.

  As shown in FIG. 3, the motor ECU 40 includes a motor control microcomputer (hereinafter referred to as “motor control microcomputer”) 40a, a boost control microcomputer (hereinafter referred to as “boost control microcomputer”) 40b, a crystal oscillator 40c, 40f, power supplies 40d and 40e for oscillation, an instantaneous interruption circuit 40g, and a monitoring IC 40h.

  The motor control microcomputer 40a is configured as a microprocessor centered on a CPU (not shown), and in addition to the CPU, a ROM that stores a processing program, a RAM that temporarily stores data, an input/output port, and a communication. A port (neither is shown) and an oscillator circuit OSC1 are provided. The oscillation circuit OSC1 is driven by the power V5D1 from the oscillation power supply 40d. The oscillator circuit OSC1 operates in a normal operation mode in which an external clock signal CLK1 from the crystal oscillator 40c is used to generate an internal clock signal of a frequency f1 when the crystal oscillator 40c is normally oscillating. When some abnormality occurs in 40c, it operates in a self-excited oscillation mode in which an oscillation signal from a self-excited oscillator (not shown) is used to generate an internal clock signal having a frequency f2 slower than the frequency f1. The internal clock signal generated by the oscillator circuit OSC1 is supplied to a CPU, a ROM, a RAM, and the like (not shown).

  Signals from various sensors necessary for driving and controlling the motors MG1 and MG2 are input to the motor control microcomputer 40a via input ports. The signals input to the motor control microcomputer 40a include, for example, rotational positions θm1 and θm2 from rotational position detection sensors 43 and 44 that detect rotational positions of rotors of the motors MG1 and MG2. Further, a reset signal RESET1 from the monitoring IC 40h and a timer signal WDT3 from a boost control microcomputer 40b described later can be cited.

  From the motor control microcomputer 40a, switching control signals to switching elements (not shown) of the inverters 41 and 42 are output via output ports. The motor control microcomputer 40a is connected to the boost control microcomputer 40b and the HVECU 70 via a communication port. The motor control microcomputer 40a calculates the rotational speeds Nm1 and Nm2 of the motors MG1 and MG2 based on the rotational positions θm1 and θm2 of the rotors of the motors MG1 and MG2 from the rotational position detection sensors 43 and 44. The motor control microcomputer 40a measures the cycle T3 of the timer signal WDT3 from the boost control microcomputer 40b.

  The motor control microcomputer 40a also functions as a watchdog timer that counts the internal clock signal and clears the count value every time the count value of the internal clock signal reaches a predetermined value (eg, value 100, value 200, value 300, etc.). Function. When the motor control microcomputer 40a functions as a watchdog timer, the motor control microcomputer 40a becomes high while counting the internal clock signal, becomes low when the count value is cleared, and becomes high when the count value is started again after being cleared. The timer signals WDT1 and WDT2 are output via the output port.

  The boost control microcomputer 40b is configured as a microprocessor centered on a CPU (not shown), and in addition to the CPU, a ROM that stores a processing program, a RAM that temporarily stores data, an input/output port, and a communication. A port (neither is shown) and an oscillation circuit OSC2 are provided. The oscillator circuit OSC2 is driven by the electric power V5D2 from the oscillation power source 40e, and when the crystal oscillator 40f is normally oscillating, the internal clock signal of the frequency f1 is generated by using the external clock signal CLK2 from the crystal oscillator 40f. When the crystal oscillator 40f operates in the normal operation mode for generation and some abnormality occurs in the crystal oscillator 40f, a self-excited signal for generating an internal clock signal of a frequency f2 slower than the frequency f1 is generated using an oscillation signal from a self-excited oscillator (not shown). Operates in oscillation mode. The internal clock signal generated by the oscillator circuit OSC2 is used as a clock signal when the CPU, ROM, RAM, etc. (not shown) operate.

  Signals from various sensors necessary for driving and controlling the step-up/down converter 55 are input to the boost control microcomputer 40b through input ports. As the signal input to the boost control microcomputer 40b, for example, the voltage of the capacitor 57 (voltage of the high voltage side power line 54a) VH from the voltage sensor 57a mounted between the terminals of the capacitor 57 or the terminals of the capacitor 58 is used. The voltage of the capacitor 58 (voltage of the low-voltage side power line 54b) VL from the attached voltage sensor 58a and the reactor current IL from the current sensor 55a which detects the current of the reactor L can also be mentioned. As the signal input to the boost control microcomputer 40b, the timer signal WDT2 from the motor control microcomputer 40a can also be mentioned.

  From the step-up control microcomputer 40b, switching control signals to the transistors T31 and T32 of the step-up/step-down converter 55, a timer signal WDT3 from the watchdog timer, etc. are output via the output port. The boost control microcomputer 40b measures the cycle T2 of the timer signal WDT2 from the motor control microcomputer 40a.

  The boost control microcomputer 40b also functions as a watchdog timer that counts the internal clock signal and clears the count value each time the count value of the internal clock signal reaches a predetermined value (eg, value 100, value 200, value 300, etc.). Function. When the boost control microcomputer 40b functions as a watchdog timer, the boost control microcomputer 40b becomes high while counting the internal clock signal, becomes low when the count value is cleared, and becomes high when the count value is started again after being cleared. The timer signal WDT3 is output via the output port.

  The oscillation power supplies 40d and 40e are predetermined voltages (for example, 3.3V, 5V, etc.) from a power supply electronic control unit (hereinafter, referred to as "power supply ECU") that operates by low-voltage power supplied from a low-voltage battery (not shown). Is supplied to the oscillation circuits OSC1 and OSC2 of the motor control microcomputer 40a and the boost control microcomputer 40b. The low voltage battery is connected to the battery 50 via a DC/DC converter (not shown).

  The instantaneous interruption circuit 40g is attached to a power line from a power supply ECU (not shown) to the oscillation power supply 40d. The instantaneous cutoff circuit 40g is controlled by the boost control microcomputer 40b to supply and cut off power from the oscillation power supply 40d to the oscillation circuit OSC1.

  The monitoring IC 40h measures the cycle T1 of the timer signal WDT1 from the motor control microcomputer 40a.

  The battery 50 is configured, for example, as a lithium ion secondary battery or a nickel hydrogen secondary battery, and is connected to the low voltage side power line 54b. The battery 50 is managed by a battery electronic control unit (hereinafter referred to as “battery ECU”) 52.

  Although not shown, the battery ECU 52 is configured as a microprocessor centered on a CPU, and includes, in addition to the CPU, a ROM for storing a processing program, a RAM for temporarily storing data, an input/output port, and a communication port. .. Signals from various sensors necessary for managing the battery 50 are input to the battery ECU 52 via an input port. As the signal input to the battery ECU 52, for example, the battery voltage Vb from the voltage sensor installed between the terminals of the battery 50, the battery current Ib from the current sensor attached to the output terminal of the battery 50, the battery current Ib attached to the battery 50, etc. The battery temperature Tb from the provided temperature sensor can be mentioned. The battery ECU 52 is connected to the HVECU 70 via a communication port. The battery ECU 52 calculates the storage ratio SOC based on the integrated value of the battery current Ib from the current sensor. The charge ratio SOC is the ratio of the capacity of the electric power that can be discharged from the battery 50 to the total capacity of the battery 50.

  The system main relay 56 is provided closer to the battery 50 than the capacitor 58 in the low voltage side power line 54b. The system main relay 56 is ON/OFF controlled by the HVECU 70 to connect and disconnect the battery 50 and the buck-boost converter 55 side.

  Although not shown, the HVECU 70 is configured as a microprocessor centered on a CPU, and includes, in addition to the CPU, a ROM that stores a processing program, a RAM that temporarily stores data, an input/output port, and a communication port.

  Signals from various sensors are input to the HVECU 70 via input ports. Examples of the signal input to the HVECU 70 include an ignition signal from the ignition switch 80 and a shift position SP from a shift position sensor 82 that detects the operation position of the shift lever 81. Further, an accelerator opening Acc from the accelerator pedal position sensor 84 that detects the depression amount of the accelerator pedal 83, a brake pedal position BP from the brake pedal position sensor 86 that detects the depression amount of the brake pedal 85, and a vehicle speed sensor 88 from the vehicle speed sensor 88. The vehicle speed V can also be mentioned.

  As described above, the HVECU 70 is connected to the engine ECU 24, the motor ECU 40, and the battery ECU 52 via the communication port.

  The hybrid vehicle 20 of the embodiment thus configured travels in a traveling mode such as a hybrid traveling mode (HV traveling mode), an electric traveling mode (EV traveling mode), and a fail-safe traveling mode. The HV traveling mode is a traveling mode in which the vehicle travels with the operation of the engine 22 and the driving of the motors MG1 and MG2. The EV travel mode is a travel mode in which the engine 22 is stopped and the motor MG2 is driven to travel. The fail-safe drive mode is mainly a drive mode when some abnormality occurs in the vehicle. The fail-safe traveling mode includes a motor drive traveling mode (MD traveling mode) and a boost-less traveling mode. The MD travel mode is a travel mode in which the engine 22 is prohibited from starting and only the motor MG2 is driven to travel. In the boost-less running mode, the transistor T31 of the transistors T31 and T32 of the step-up/step-down converter 55 is fixed to be on and the transistor T32 is set to be off so that the step-up/step-down converter 55 does not perform the step-up operation and the engine 22 and the motor MG1. This is a traveling mode in which the MG2 is driven to travel.

  Further, in the hybrid vehicle 20 of the embodiment, the operation of the boost control microcomputer 40b is monitored by the motor control microcomputer 40a. The motor control microcomputer 40a measures the cycle T3 of the timer signal WDT3 from the boost control microcomputer 40b. When the cycle T3 exceeds a predetermined cycle Tref, it is determined that some abnormality has occurred in the boost control microcomputer 40b, and the boost control microcomputer 40b. The reset signal RESET2 is output to. Upon receiving the reset signal RESET2, the boost control microcomputer 40b restores the internal RAM to the initial state and executes the process of restarting (resetting) the startup process. The hybrid vehicle 20 runs in the boost-less running mode when only the boost control microcomputer 40b is reset.

  Further, in the hybrid vehicle 20 of the embodiment, data is exchanged between the motor control microcomputer 40a and the boost control microcomputer 40b of the motor ECU 40 by the asynchronous communication.

  Next, the operation of the hybrid vehicle 20 of the embodiment thus configured, particularly the operation when the operation of the motor control microcomputer 40a is monitored by the boost control microcomputer 40b will be described. FIG. 4 is a flowchart showing an example of a monitoring processing routine executed by the boost control microcomputer 40b. This routine is executed when the timer signal WDT2 is input from the motor control microcomputer 40a to the boost control microcomputer 40b. The reset signal RESET from the monitoring IC 40h has a cycle T1 of the measured timer signal WDT1 that is the same as or longer than the cycle of the timer signal WDT1 when the oscillation circuit OSC1 of the motor control microcomputer 40a operates in the normal operation mode. It is output when a slightly longer predetermined period Tref is exceeded, that is, when some abnormality occurs in the motor control microcomputer 40a.

  When this routine is executed, the boost control microcomputer 40b executes a process of determining whether or not the oscillation circuit OSC1 of the motor control microcomputer 40a is operating in the self-excited oscillation mode (step S100). In this processing, there are two conditions: a first condition in which the cycle T2 of the timer signal WDT2 from the motor control microcomputer 40a is a predetermined cycle T2ref or more, and a second condition in which communication with the motor control microcomputer 40a is abnormal. When both are satisfied, it is determined that the oscillation circuit OSC1 is operating in the self-excited oscillation mode. The predetermined period T2ref is a predetermined value that is the same as or slightly longer than the period of the timer signal WDT2 when the oscillation circuit OSC1 of the motor control microcomputer 40a is operating in the self-excited oscillation mode. The abnormality in the communication between the boost control microcomputer 40b and the motor control microcomputer 40a is caused when the sum value calculated by the data receiving side microcomputer does not match the calculated value by the transmitting side microcomputer or when the data is received by the receiving side. If an overrun occurs in which the stop bit cannot be received within the specified period, the microcomputer determines that an abnormality has occurred.

  When it is determined in step S100 that the oscillation circuit OSC1 is not operating in the self-excited oscillation mode, it is determined that some abnormality different from the abnormality of the crystal oscillator 40c has occurred in the motor control microcomputer 40a, A reset request signal is output to the motor control microcomputer 40a (step S110), and this routine ends. When the reset request signal RREQ is input, the motor control microcomputer 40a transmits a vehicle stop command to the HVECU 70 and executes a process of returning (resetting) the internal circuit to the initial state. The HVECU 70 that has received the vehicle stop command executes various processes for stopping the vehicle. Through such processing, the motor control microcomputer 40a can be reset and the vehicle can be stopped.

  When it is determined in the process of step S100 that the oscillation circuit OSC1 is operating in the self-excited oscillation mode, the instantaneous interruption circuit 40g is set so that the supply of the power V5D1 from the oscillation power supply 40d to the oscillation circuit OSC1 is interrupted. Control (step S120). At this time, the voltage of the capacitor 57 from the voltage sensor 57a (voltage of the high voltage side power line 54a) VH may be stored in the RAM or the like for use in various failure diagnosis.

  Then, it is determined whether the oscillation circuit OSC1 of the motor control microcomputer 40a has returned to the normal operation mode (step S130). In this determination, the third condition that the cycle T2 of the timer signal WDT2 from the motor control microcomputer 40a is within the predetermined range TA centered on the predetermined cycle T2ref is satisfied, and the second step used in the process of step S100 is performed. When the condition is not satisfied, it is determined that the oscillation circuit OSC1 has returned from the self-excited oscillation mode to the normal operation mode. The predetermined range TA is a range of the cycle T2 of the timer signal WDT2 that can determine that the oscillation circuit OSC1 of the motor control microcomputer 40a has returned to the normal operation mode. For example, the cycle (T2-0.1·T2) to the cycle (T2+0). The range may be, for example, .1·T2).

  When it is determined in step S130 that the oscillation circuit OSC1 of the motor control microcomputer 40a has not returned to the normal operation mode, it is determined that the abnormality of the crystal oscillator 40c has not been eliminated even when the power of the oscillation circuit OSC1 is turned off. Then, the process proceeds to step S110, the reset request signal RREQ is output to the motor control microcomputer 40a (step S110), and this routine is finished. As a result, the motor control microcomputer 40a can be reset and the vehicle can be stopped.

  When it is determined in step S130 that the oscillator circuit OSC1 of the motor control microcomputer 40a has returned from the self-excited oscillation mode to the normal operation mode, it is determined that the abnormality of the crystal oscillator 40c has been resolved by executing the process of step S120. After making a determination, the FS request FSREQ is output to the motor control microcomputer 40a (step S140), and this routine is ended. The motor control microcomputer 40a that has input the FS request FSREQ transmits an FS traveling command to the HVECU 70. The HVECU 70 that has received the FS traveling command executes various processes for traveling the vehicle in the fail-safe traveling described above. As a result, the vehicle can be run without resetting the motor control microcomputer 40a, so that unnecessary resetting of the motor control microcomputer 40a can be suppressed and the vehicle can continue running.

  According to the hybrid vehicle 20 of the embodiment described above, when the cycle T2 of the timer signal WDT2 is equal to or longer than the predetermined cycle T2ref, the instantaneous power interruption circuit 40g is controlled so that the oscillation power supply 40d is momentarily disconnected, and thereafter, When the cycle of the timer signal WDT2 is outside the predetermined range TA, the motor control microcomputer 40a is reset so that the cycle T2 of the timer signal WDT is within the predetermined range TA and the communication between the motor control microcomputer 40a and the boost control microcomputer 40b is abnormal. Since the motor control microcomputer 40a is not reset when it does not occur, unnecessary reset of the motor control microcomputer 40a can be suppressed.

  In the hybrid vehicle 20 of the embodiment, in the process of step S130, the third condition that the cycle T2 of the timer signal WDT2 from the motor control microcomputer 40a is within the predetermined range TA centered on the predetermined cycle T2ref is satisfied, and When the second condition used in the process of step S100 is not satisfied, it is determined that the oscillation circuit OSC1 has returned from the self-excited oscillation mode to the normal operation mode, but it is determined whether the third condition is satisfied. It may be determined that the oscillation circuit OSC1 has returned from the self-excited oscillation mode to the normal operation mode when the third condition is satisfied.

  In the hybrid vehicle 20 of the embodiment, the monitoring processing routine illustrated in FIG. 4 is executed by the boost control microcomputer 40b. However, as illustrated in the motor ECU 140 of the modification of FIG. 5, the timer control signal WDT2 is generated by the motor control microcomputer 40a. Alternatively, the instantaneous interruption circuit 40g may be controlled by the monitoring IC, and the monitoring processing routine may be executed by the monitoring IC 40h.

  FIG. 6 is a flowchart showing an example of a monitoring processing routine executed by the monitoring IC 40h of the motor ECU 140 of the modified example. This routine is the same as the monitoring processing routine illustrated in FIG. 4 except that the processing of step S100 of the monitoring processing routine illustrated in FIG. 4 is not executed and that the processing of step S130B is executed instead of the processing of step S130. Is processed. In the monitoring processing routine illustrated in FIG. 6, when it is determined that the cycle T1 of the timer signal WDT1 measured by the monitoring IC 40h exceeds the predetermined cycle T2ref, that is, the oscillation circuit OSC1 of the motor control microcomputer 40a operates in the self-excited oscillation mode. It is executed when it detects that the has started.

  When this routine is executed, the monitoring IC 40h executes the process of step S120 to cut off the power supply from the oscillation power supply 40d to the oscillation circuit OSC1, and then the oscillation circuit OSC1 of the motor control microcomputer 40a normally operates. It is determined whether or not the operation mode has been restored (step S130B). In this determination, when the cycle of the timer signal WDT1 from the motor control microcomputer 40a is the predetermined cycle T2ref, it is determined that the normal operation mode is restored. When not returning to the normal operation mode, the process proceeds to step S110, the reset request signal RREQ is output to the motor control microcomputer 40a, and this routine ends. As a result, the motor control microcomputer 40a can be reset and the vehicle can be stopped. When it is determined in step S130B that the operation mode has returned to the normal operation mode, the process proceeds to step S140, the FS request FSREQ is output to the motor control microcomputer 40a, and the routine ends. As a result, the vehicle can be run without resetting the motor control microcomputer 40a, so that unnecessary resetting of the motor control microcomputer 40a can be suppressed and the vehicle can continue running.

  In the hybrid vehicle 20 of the embodiment, the operation of the motor control microcomputer 40a is monitored in the monitoring processing routine illustrated in FIG. 4, but the operation of the boost control microcomputer 40b may be monitored. In this case, the motor control microcomputer 40a may not generate the timer signal WDT2 as illustrated in the modified motor ECU 240 of FIG. The instantaneous interruption circuit 40g is attached to the power line from the power supply ECU (not shown) to the oscillation power supply 40e, and is controlled by the motor control microcomputer 40a, so that the power from the oscillation power supply 40e to the oscillation circuit OSC2 is transmitted. The supply and the supply of electric power may be cut off.

  FIG. 8 is a flowchart showing an example of a monitoring processing routine executed by the motor control microcomputer 40a of the motor ECU 240 of the modified example. In this routine, in the monitoring processing routine illustrated in FIG. 4, the motor control microcomputer 40a is the boost control microcomputer 40b, the boost control microcomputer 40b is the motor control microcomputer 40a, and the oscillation circuit OSC1 of the motor control microcomputer 40a is the boost control microcomputer 40b. The oscillator circuit OSC2 is used, the timer signal WDT3 is used as the timer signal WDT2, and the oscillation power supply 40d is used as the oscillation power supply 40e, and the processes of steps S110 to S140 are executed. It is assumed that the processing of step S100 is not executed in the monitoring processing routine illustrated in FIG. 4, and the monitoring processing routine illustrated in FIG. 8 is performed by setting the cycle T2 of the timer signal WDT2 measured by the motor control microcomputer 40a to the predetermined cycle Tref. Executes when it is determined that the number has been exceeded. By executing such a monitoring processing routine, unnecessary resetting of the boost control microcomputer 40b can be suppressed, and the traveling of the vehicle can be continued. In this case, the motor control microcomputer 40a that has output the reset request signal RREQ to the step-up control microcomputer 40b in the process of step S110 may send a step-upless travel command to the HVECU 70 to drive the vehicle in the step-upless travel mode. In this way, the stopping of the vehicle can be suppressed and the running can be continued for a longer time.

  The hybrid vehicle 20 of the embodiment includes the monitoring IC 40h, but may not include the monitoring IC 40h. In this case, the monitoring processing routine illustrated in FIG. 9 may be executed instead of the monitoring processing routine illustrated in FIG. The monitoring processing routine illustrated in FIG. 9 is executed in step S110 when it is determined in the processing in step S100 of the monitoring processing routine illustrated in FIG. 4 that the oscillation circuit OSC1 of the motor control microcomputer 40a is not operating in the self-excited oscillation mode. The same process as the monitoring process routine illustrated in FIG. 4 is executed, except that the process of step S100 is not executed before proceeding to the process of FIG.

  The monitoring processing routine illustrated in FIG. 9 is executed when a predetermined time has elapsed since the ignition was turned on. In this routine, when it is determined in step S100 that the oscillation circuit OSC1 of the motor control microcomputer 40a is not operating in the self-excited oscillation mode, it is determined that the motor control microcomputer 40a is normal and the oscillation circuit OSC1 The process of step S100 is repeatedly executed until it is determined that the operation is in the self-oscillation mode. With this configuration, even if the monitoring IC 40h is not provided, the operation of the motor control microcomputer 40a can be related to the step-up control microcomputer 40b, unnecessary reset of the motor control microcomputer 40a can be suppressed, and the vehicle travels. Can continue.

  In the embodiment, the case where the present invention is applied to the hybrid vehicle 20 is illustrated, but the present invention may be applied to any processing device provided with a microcomputer having a clock generation circuit and a watchdog timer. Absent.

  Correspondence between the main elements of the embodiment and the main elements of the invention described in the column of means for solving the problem will be described. In the embodiment, the oscillation circuit OSC1 corresponds to the “clock generation circuit”, the watchdog timer corresponds to the “watchdog timer”, the motor control microcomputer 40a corresponds to the “microcomputer”, and the instantaneous interruption circuit 40g performs the “instantaneous interruption”. This corresponds to the "break circuit", and the boost control microcomputer 40b corresponds to the "determination processing unit".

  The correspondence between the main elements of the embodiment and the main elements of the invention described in the column of means for solving the problem is the same as that of the embodiment described in the section of means for solving the problem. This is an example for specifically explaining the mode for carrying out the invention, and does not limit the elements of the invention described in the column of means for solving the problem. That is, the interpretation of the invention described in the column of means for solving the problem should be made based on the description in that column, and the embodiment is the invention of the invention described in the column of means for solving the problem. This is just a specific example.

  Although the embodiments for carrying out the present invention have been described above with reference to the embodiments, the present invention is not limited to these embodiments, and various embodiments are possible within a range not departing from the gist of the present invention. Of course, it can be implemented.

  INDUSTRIAL APPLICABILITY The present invention can be used in the processing device manufacturing industry and the like.

  20 hybrid vehicle, 22 engine, 23 crank position sensor, 24 engine electronic control unit (engine ECU), 26 crankshaft, 28 damper, 30 planetary gear, 36 drive shaft, 38 differential gear, 39a, 39b drive wheel, 40, 140 , 240 motor electronic control unit (motor ECU), 40a motor control microcomputer (motor control microcomputer), 40b step-up control microcomputer (step-up control microcomputer), 40d, 40e oscillation power supply, 40c, 40f crystal oscillator, 40g instantaneous interruption circuit, 40h monitoring IC, 41,42 inverter, 43,44 rotational position detection sensor, 50 battery, 52 battery electronic control unit (battery ECU), 54a high voltage side power line, 54b low voltage side power line, 55 buck-boost converter, 56 system main relay, 57, 58 condenser, 57a, 58a voltage sensor, 70 hybrid electronic control unit (HVECU), 80 ignition switch, 81 shift lever, 82 shift position sensor, 83 accelerator pedal, 84 accelerator Pedal position sensor, 85 brake pedal, 86 brake pedal position sensor, 88 vehicle speed sensor, D31, D32 diode, L reactor, MG1, MG2, motor, OSC1, OSC2 oscillation circuit, S1, S2 switching element, T31, T32 transistor.

Claims (1)

A clock generation circuit that is driven by power from an oscillation power supply to generate an internal clock signal, and a timer signal that counts the generated internal clock signal and clears the count result at every predetermined cycle and has a cycle corresponding to the count result. A watchdog timer for outputting
A processing device comprising:
An instantaneous interruption circuit capable of instantaneously interrupting the power from the oscillation power supply,
A timer signal is input from the microcomputer, and the momentary interruption circuit is controlled so that the oscillation power supply is momentarily interrupted when the period of the input timer signal is out of a predetermined range including the predetermined period, After that, when the cycle of the input timer signal is out of the predetermined range, the microcomputer is reset, and when the cycle of the input timer signal is in the predetermined range, the microcomputer is not reset. ,
A processing device comprising.

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