JP6705693B2 - Optical semiconductor device and semiconductor monolithic optical circuit - Google Patents

Description

The present invention provides an optical semiconductor device such as a ridge-loaded semiconductor optical amplifier, an injection current type optical modulator, or a reverse bias addition type electro-absorption optical modulator, and an optical semiconductor device together with other circuits on the same substrate. The present invention relates to a semiconductor monolithic optical circuit integrated in.

Conventionally, as an optical semiconductor element, a ridge-loaded semiconductor optical amplifier (SOA), an injection current type optical modulator, or a reverse bias addition type electro-absorption (EA) optical modulator. Etc. have been proposed and put into practical use. As a semiconductor monolithic optical circuit using these optical semiconductor elements, for example, a high-speed chaotic optical signal generation optical circuit (Patent Document 1) that generates a high-speed chaotic signal exceeding 10 Gb/s, and outputs by adding a delay to the optical signal. There is an optical signal buffer memory circuit (Patent Document 2) and the like.

FIG. 11 is a block diagram illustrating the configuration of the high-speed chaotic optical signal generation optical circuit disclosed in Patent Document 1. The high-speed chaotic optical signal generation optical circuit was output from the Mach-Zehnder interferometer type optical intensity modulator MZ-1 and the optical output port P-MZ-1-cross of the Mach-Zehnder interferometer type optical intensity modulator MZ-1 described later. An optical demultiplexing unit SP-1 that demultiplexes RZ (Return to Zero) type clock signal light into two systems, and two systems of RZ type clock signal light demultiplexed by the optical demultiplexing unit SP-1 interfere with Mach-Zehnder interference. Two types of RZ type, which are input to the optical phase modulators R1 and L1 with a delay corresponding to the difference in optical propagation delay until reaching optical phase modulators R1 and L1 described later in the optical intensity modulator MZ-1 Of the clock signal lights, the optical propagation delay difference adding unit D-D-1 is added to the RZ type clock signal light having the longer optical propagation delay until reaching the optical phase modulators R1 and L1.

The Mach-Zehnder interferometer type optical intensity modulator MZ-1 includes an optical input port P-MZ-1-1 for receiving an RZ type clock signal light having a constant peak optical power output from a clock signal light source (not shown), and an optical input port P-MZ-1-1. Two optical interference arms that transmit the RZ-type clock signal light input to the input port P-MZ-1-1 and two optical output ports P-MZ- provided at the ends of the two optical interference arms. 1-cross, P-MZ-1-bar, and two optical signals demultiplexed by the optical demultiplexing unit SP-1 will be described later in the two optical interference arms of the Mach-Zehnder interferometer type optical intensity modulation unit MZ-1. The optical input ports P-R1 and P-L1 for controlling the phase modulation for inputting to the optical phase modulators R1 and L1 and the RZ that is provided for each of the two optical interference arms and transmitted by the optical interference arms. Optical phase modulators R1 and L1 that phase-modulate the type clock signal light according to the light intensity of the RZ type clock signal light input from the optical input ports P-R1 and P-L1.

In FIG. 11, reference numeral 100 denotes an optical waveguide whose one end is connected to the optical input port P-MZ-1-1 and whose other end is connected to the input of the optical phase modulator L1, and 101 is arranged so that one end is close to the optical waveguide 100. An optical waveguide having the other end connected to the input of the optical phase modulator R1, and 102, an optical waveguide having one end connected to the output of the optical phase modulator L1 and the other end connected to the optical output port P-MZ-1-bar. , 103 are optical waveguides, one end of which is connected to the output of the optical phase modulator R1 and the other end of which is connected to the optical output port P-MZ-1-cross, and a part of which is arranged close to the optical waveguide 102.

The optical waveguides 100 and 102 constitute one optical interference arm of the Mach-Zehnder interference type optical intensity modulator MZ-1, and the optical waveguides 101 and 103 the other optical interference arm of the Mach-Zehnder interference type optical intensity modulator MZ-1. Is composed of. An optical signal leaks between the optical waveguide 100 and the optical waveguide 101, and the optical signal input to the optical waveguide 100 is also input to the optical waveguide 101. Optical signals leak mutually between the optical waveguides 102 and 103.

Further, 104 is an optical waveguide whose one end is connected to the optical output port P-MZ-1-cross and the other end is connected to the input of the optical demultiplexing unit SP-1, and 105 is one end of the optical demultiplexing unit SP-1. An optical waveguide connected to the first output and the other end connected to the input of the optical propagation delay difference providing unit DD-1. One end of 106 is connected to the second output of the optical demultiplexing unit SP-1. An optical waveguide whose end is connected to the optical input port P-R1, and 109 is an optical waveguide whose one end is connected to the output of the optical propagation delay difference providing unit D-D-1 and whose other end is connected to the optical input port P-L1. Is.

FIG. 12 is a block diagram showing a configuration example of the optical phase modulator R1. The optical phase modulator R1 is a Mach-Zehnder interferometer circuit, and is an RZ-type clock signal transmitted by the optical interference arm (101 in FIG. 11) of the Mach-Zehnder interferometer type optical intensity modulator MZ-1 and input to the optical input port 1007. RZ-type clock signal light (hereinafter referred to as phase modulation) that is demultiplexed by light (hereinafter referred to as phase-modulated signal light) and is input to the optical input port 1008 (P-R1 in FIG. 11). Output from the multi-mode interference coupler b1 and the multi-mode interference coupler (MMI) b1 which is an optical interference type coupling/dividing means for demultiplexing the multiplexed signal light into two systems. Optical waveguide type that transmits two signal lights that are transmitted and two signal lights that are transmitted by the two optical waveguide arms are multiplexed, and the combined signal light is demultiplexed into two systems. A multi-mode interference coupler b2, which is a coupling/splitting unit, and an optical phase modulation controller c1 that is provided in each of the two optical waveguide arms and that phase-modulates the phase-modulated signal light according to the light intensity of the phase-modulation control signal light. , C2, a phase adjuster d1 provided on one of the two optical waveguide arms and capable of adjusting the phase of the signal light in accordance with the amount of injected current supplied from the outside, and the multimode interference coupler b2. The light receiving portion f1 is connected to one of the light output ports. Reference numeral 1009 in FIG. 12 denotes an optical output port of the optical phase modulator R1 connected to the optical waveguide 103 shown in FIG. The configuration of the optical phase modulator L1 is the same as that of the optical phase modulator R1.

In the high-speed chaotic optical signal generation optical circuit shown in FIGS. 11 and 12, an SOA or EA optical modulator is used as the optical phase modulation control units c1 and c2, and an injection current type optical modulator is used as the phase adjustment unit d1. To be done.
Since the operation of the high-speed chaotic optical signal generation optical circuit is disclosed in Patent Document 1, detailed description thereof will be omitted.

FIG. 13 is a block diagram illustrating the configuration of the optical signal buffer memory circuit disclosed in Patent Document 2. In the optical signal buffer memory circuit, P-OCLK-In is an external optical input port for the clock signal light CLK-1. The clock signal light CLK-1 is a clock light pulse output from the clock signal light source and is an RZ type clock signal light having a constant peak light power. P-Data-In is an external optical input port of the optical signal train Data-1. The optical signal sequence Data-1 is an optical signal sequence for data input for the purpose of storing it in the optical signal buffer memory circuit.

P-FF-In is an external optical input port of the optical signal train FF-1. The optical signal sequence FF-1 is input when performing a so-called flip-flop operation, which inverts all the information marks (1) and spaces (0) of the data optical signal sequence stored in the optical signal buffer memory circuit. Is an optical signal sequence for flip-flop control. P-ERS-In is an external optical input port of the optical signal train ERS-1. The optical signal sequence ERS-1 is an erase control optical signal sequence that is input when the information stored in the optical signal buffer memory circuit is reset.

C-2 has optical input ports P-C2-1, P-C2-2 and optical output ports P-C2-3, P-C2-4, and is guided from the external optical input port P-Data-In. The input optical signal sequence Data-1 input to the optical input port P-C2-1 via the waveguide 116 and the external optical input port P-ERS-In to the optical input port P-C2-2 via the optical waveguide 117. The input optical signal sequence ERS-1 that has been input is output from the same optical output port P-C2-4 and is output to one optical input port P-C1-1 of the 2×2 optical branching unit C-1 at the subsequent stage. It is a 2×1 optical multiplexer for coupling to the guiding optical waveguide 118.

Further, R1-1, R1-2, L1-1, and L1-2 are input to the Mach-Zehnder interferometer type optical intensity modulator MZ-1 from the external optical input port P-OCLK-In, and the Mach-Zehnder interferometer type optical intensity is input. Clock optical signal train propagating in the two left and right optical interference arms of the modulation unit MZ-1 (the optical interference arm configured by the optical waveguides 111R, 112R, 113R and the optical interference arm configured by the optical waveguides 111L, 112L, 113L). It is an optical phase modulator that modulates the phase of.

The optical phase modulators R1-1, R1-2, L1-1, L1-2 are arranged between the two directional couplers. Specifically, the optical phase modulator R1-1 is the optical waveguide 111R. Between the optical waveguide 112R and the optical waveguide 112R, the optical phase modulator R1-2 between the optical waveguide 112R and the optical waveguide 113R, and the optical phase modulator L1-1 between the optical waveguide 111L and the optical waveguide 112L. The phase modulator L1-2 is arranged between the optical waveguide 112L and the optical waveguide 113L. That is, the optical phase modulator R1-2 is located on the rear side of the optical phase modulator R1-1 and the optical phase modulator L1-2 is located on the rear side of the optical phase modulator L1-1.

Further, C-1 has optical input ports P-C1-1 and P-C1-2 and optical output ports P-C1-3 and P-C1-4, and the optical output of the optical multiplexer C-2. The optical signal train from the port P-C2-4 is input and branched from the optical input port P-C1-1 via the optical waveguide 118, and is branched to obtain the optical output ports P-C1-3 and P-C1-4. And the optical signal train from the optical output port P-MZ-1-bar of the Mach-Zehnder interferometer type optical intensity modulator MZ-1 is transmitted through the optical waveguide 114 to the optical input port P-C1-. 2 is an optical branching unit for inputting and branching from 2 and outputting from optical output ports P-C1-3 and P-C1-4.

P-R1-1 and P-L1-1 pass optical signal trains output from the optical output ports P-C1-4 and P-C1-3 of the optical branching unit C-1 via the optical waveguides 115R and 115L. Is an optical input port for inputting into the optical phase modulators R1-1 and L1-1 in the two optical interference arms of the Mach-Zehnder interferometer type optical intensity modulator MZ-1.

C-3 has optical input ports P-C3-1 and P-C3-2 and optical output ports P-C3-3 and P-C3-4, and is guided from the external optical input port P-FF-In. It is an optical branching unit for branching the optical signal train input via the waveguide 121 and outputting it from the optical output ports P-C3-3 and P-C3-4.

The P-R1-2 and P-L1-2 pass the optical signal trains output from the optical output ports P-C3-4 and P-C3-4 of the optical branching unit C-3 via the optical waveguides 122R and 122L. Is an optical input port for inputting into the optical phase modulators R1-2 and L1-2 in the two optical interference arms of the Mach-Zehnder interferometer type optical intensity modulator MZ-1.

The D-D-1 is branched by the optical branching unit C-1, and is divided into two optical signal trains output from the optical output ports P-C1-3 and P-C1-4, respectively. An optical propagation delay difference providing unit for providing the optical propagation delay difference until reaching L1-1 so as to be “greater than or equal to the pulse width of the clock optical signal CLK-1 and less than the pulse repetition period”, and here, An optical waveguide portion having an optical path length that causes a difference in optical propagation delay is arranged in the optical waveguide 115L.

D-D-2 is the optical phase modulators R1-2 and L1 in the two optical signal trains branched by the optical splitter C-3 and output from the optical output ports P-C3-3 and P-C3-4, respectively. -2 is an optical propagation delay difference providing unit for providing the optical propagation delay difference until reaching -2 so as to be "greater than or equal to the pulse width of the clock optical signal CLK-1 and less than the pulse repetition period". An optical waveguide portion having an optical path length that causes a propagation delay difference is arranged in the optical waveguide 122L.

14A, 14B, and 14C are block diagrams showing configuration examples of the optical phase modulator R1-1. 14A, 14B, and 14C, a1 and a2 are two optical input/output ports on one side of the optical phase modulator R1-1, and a3 and a4 are optical phase modulator R1. -1 are two optical input/output ports on the other side, b1 and b2 are multimode interference couplers (first and second optical interference type coupling/branching means), and a9 and a10 are one of the multimode interference coupler b1. Output ports, a5 and a6 are the other optical input/output ports of the multi-mode interference coupler b1, a7 and a8 are one optical input/output ports of the multi-mode interference coupler b2, and a11 and a12 are the other optical input/output ports of the multi-mode interference coupler b2. Input/output ports, e1 and e2 are two optical input/output waveguides on one side of the optical phase modulator R1-1, e3 and e4 are two optical input/output waveguides on the other side of the optical phase modulator R1-1, c1 and c2 are two optical phase modulation control units, and d1 and d2 are phase adjustment units. The optical waveguides e5 and e7 form one optical waveguide arm in the optical phase modulator R1-1, and the optical waveguides e6 and e8 form the other optical waveguide arm in the optical phase modulator R1-1.

The optical input/output ports a1 and a2 of the optical phase modulator R1-1 are connected to the optical input/output ports a9 and a10 of the multimode interference coupler b1 via the optical input/output waveguides e1 and e2, respectively. The optical input/output ports a5 and a6 of the multi-mode interference coupler b1 are connected to one port of the optical phase modulation control units c1 and c2 via the optical waveguides e5 and e6, respectively. The other ports of the optical phase modulation control units c1 and c2 are connected to the optical input/output ports a7 and a8 of the multimode interference coupler b2 via the optical waveguides e7 and e8, respectively. That is, the optical phase modulation controllers c1 and c2 are provided in each of the two optical waveguide arms of the optical phase modulator R1-1. The optical input/output ports a11, a12 of the multi-mode interference coupler b2 are connected to the optical input/output ports a3, a4 of the optical phase modulator R1-1 via two optical input/output waveguides e3, e4, respectively. The configurations of the optical phase modulators R1-2, L1-1, L1-2 are similar to those of the optical phase modulator R1-1.

Also in the optical signal buffer memory circuits shown in FIGS. 13 and 14A to 14C, the SOA or EA optical modulator is used as the optical phase modulation control units c1 and c2, and the phase adjusting units d1 and d2 are used. An injection current type optical modulator is used as the above, and an SOA is used as the optical signal amplification units BA-1 and BA-2 in FIG.
Since the operation of the optical signal buffer memory circuit is disclosed in Japanese Patent Application Laid-Open No. 2004-242242, detailed description will be omitted.

Ridge-loaded SOA, injection current type optical modulator or reverse bias addition type EA optical modulation used in the above semiconductor monolithic optical circuit (high-speed chaotic optical signal generation optical circuit or optical signal buffer memory circuit) An optical semiconductor element such as a container has a semiconductor mesa structure that guides the amplified signal light to be amplified and, at the same time, serves as a conduction path for an injection current to the active layer region. This semiconductor mesa structure does not have a semiconductor clad layer that is in contact with both side walls of the semiconductor mesa structure, and the both side walls are in contact with air or an insulating protective film. Therefore, heat generated by current injection into the active layer is radiated to the outside as compared with a semiconductor optical amplification device having a buried structure and a core for guiding the amplified signal light surrounded by a semiconductor cladding layer. There is a problem that the heat dissipation efficiency is poor.

As a technique used in LEDs or the like as a technique for improving heat dissipation efficiency, a structure in which both the p-electrode and the n-electrode can be arranged on the upper surface side of the element, and then by flip-chip mounting, There has been proposed a technique for reducing the distance between a heat source and an electrode terminal or heat sink (see Non-Patent Document 1).

JP, 2014-052948, A JP, 2014-174303, A

C. F. Shen, et al., “Nitride-Based High-Power Flip-Chip LED With Double-Side Patterned Sapphire Substrate”, IEEE PHOTONICS TECHNOLOGY LETTERS, VOL.19, NO.10, pp.780-782, 2007

As described above, the optical semiconductor device having the semiconductor mesa structure including the active layer (or the phase adjustment layer or the absorption layer) radiates the generated heat to the outside as compared with the device in which the core is surrounded by the semiconductor clad layer. There is a problem that the heat dissipation efficiency is poor. Further, due to the heat generated in such an active layer, the density of carriers generated by current injection into the active layer is reduced due to the overflow of carriers caused by a large temperature rise in the peripheral portion of the active layer. However, there is a problem that the characteristics of (1) deteriorate.

In a semiconductor monolithic optical circuit in which such an optical semiconductor element is integrated with other circuits, since a plurality of optical semiconductor elements may be arranged close to each other, heat dissipation efficiency is further reduced, and the characteristics of the optical semiconductor element are reduced. There is a problem that the deterioration becomes more remarkable. Further, in the semiconductor monolithic optical circuit, there is a problem that heat generated from the optical semiconductor element hinders the operation of other circuits. For example, in the above-described high-speed chaotic optical signal generation optical circuit or optical signal buffer memory circuit, the Mach-Zehnder interferometer type optical intensity modulator is monolithically integrated on the same substrate as the optical semiconductor element, and is generated from the optical semiconductor element. There is a problem that the heat remarkably hinders the optical interference operation of the Mach-Zehnder interferometer type optical intensity modulator.

Further, the technique disclosed in Non-Patent Document 1 is applied to an optical semiconductor element such as a ridge-loaded SOA, an injection current type optical modulator, or a reverse bias addition type EA optical modulator to apply heat to other circuits. In order to suppress the interference, the semiconductor mesa structure is turned over and flip-chip mounted on the substrate. In this case, the force is concentrated and applied to the semiconductor mesa structure, which is extremely thin and vulnerable to a mechanical external force of the order of μm, and a large stress is applied to the semiconductor mesa structure. There is a problem in that the operating characteristics are deviated, or in the worst case, the semiconductor mesa structure is broken.
Note that the above problems may occur not only in the high-speed chaotic optical signal generation optical circuit and the optical signal buffer memory circuit but also in other semiconductor monolithic optical circuits.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide an optical semiconductor element and a semiconductor monolithic optical circuit which are more excellent in heat dissipation effect than conventional ones and have less characteristic deterioration and thermal interference.
It is another object of the present invention to provide an optical semiconductor element and a semiconductor monolithic optical circuit capable of preventing deterioration of operation characteristics and element destruction when flip-chip mounting is performed to improve heat dissipation efficiency.

The optical semiconductor device of the present invention includes a semiconductor mesa structure formed on top of the first cladding layer, a support structure formed on both sides of the semiconductor mesa structure on the first cladding layer, said semiconductor mesa structure A thermal interference suppressing groove structure formed so as to be separated from the support structure on both sides thereof, a first electrode made of a metal film formed in contact with an upper portion of the semiconductor mesa structure, and the semiconductor mesa. A second electrode made of a metal film formed so as to be in contact with a semiconductor layer different from the structure, and the semiconductor mesa structure of the groove structure for suppressing thermal interference except between the semiconductor mesa structure and the support structure. An organic material formed so as to close the region of the peripheral portion, and further, between the semiconductor mesa structure and the support structure and the first cladding layer, or a part of the semiconductor mesa structure from the outside. An active layer, a phase adjustment layer, or an absorption layer as a semiconductor layer through which a current flows by current injection or light incident from the outside, and the first electrode is formed from a region above the semiconductor mesa structure to Is formed so as to extend along the region on the insulating film covering the surface of the organic material in the region of the peripheral portion of the region to the region on the insulating film covering the surface of the supporting structure on both sides of the semiconductor mesa structure. It is characterized by.

In one configuration example of the optical semiconductor device of the present invention, the semiconductor mesa structure has at least an etch stop layer formed on the first cladding layer and the etch stop layer formed on the etch stop layer. An active layer, a phase adjustment layer or an absorption layer, and a second cladding layer formed on the active layer, the phase adjustment layer or the absorption layer and having a conductivity type different from that of the first cladding layer, The support structure is composed of at least the etch stop layer and a third clad layer of the same conductivity type as the second clad layer formed on the etch stop layer. The groove structure is formed to a depth at which a semiconductor layer different from the semiconductor mesa structure is exposed, and the semiconductor layer different from the semiconductor mesa structure is a core layer formed between the first cladding layer and the etch stop layer. , Or the first clad layer.
In one configuration example of the optical semiconductor device of the present invention, the active layer, the phase adjustment layer, or the absorption layer is formed on an etch stop layer formed on the first cladding layer, and the semiconductor mesa is formed. The structure and the support structure are composed of at least a second clad layer having a conductivity type different from that of the first clad layer formed on the active layer, the phase adjusting layer or the absorption layer, and the thermal interference The suppression groove structure is formed to a depth at which a semiconductor layer different from the semiconductor mesa structure is exposed, and the semiconductor layer different from the semiconductor mesa structure includes the active layer, the phase adjustment layer or the absorption layer, and the first cladding layer. It is characterized in that it is either the core layer formed between the etch stop layer and the first clad layer.

In one configuration example of the optical semiconductor element of the present invention, the support structure further includes a support formed on the upper surface of the support structure such that the upper surface of the semiconductor mesa structure is lower than the upper surface of the support structure. It is characterized by having layers.
The semiconductor monolithic optical circuit of the present invention is characterized in that the optical semiconductor element, are integrated on the same substrate together with a circuit other than the optical semiconductor device.

According to the present invention, by providing the groove structure for suppressing thermal interference between the semiconductor mesa structure and the supporting structure, it is possible to prevent heat generated in the active layer, the phase adjusting layer or the absorbing layer from interfering with other circuits. can do. Further, in the present invention, the first electrode covers the surface of the organic material formed so as to cover at least a part of the thermal interference suppressing groove structure adjacent to the semiconductor mesa structure from the upper region of the semiconductor mesa structure. The active layer, the phase adjustment layer, or the absorption layer is formed by being formed so as to extend along the region on the insulating film and extend to the region on the insulating film covering the surface of the support structure adjacent to the thermal interference suppressing groove structure. The heat generated can be efficiently radiated from the first electrode. As a result, in the present invention, it is possible to suppress the characteristic deterioration of the optical semiconductor element due to the temperature rise and further suppress the thermal interference with other circuits.

Further, in the present invention, when a support layer is formed on the upper surface of the support structure so that the upper surface of the semiconductor mesa structure is lower than the upper surface of the support structure, the optical semiconductor element is turned over and flip-chip mounted on the substrate. Since the semiconductor mesa structure does not come into contact with the substrate, the operation characteristics of the optical semiconductor element will not be displaced and the optical semiconductor element will not be broken.

FIG. 3 is a plan view and a cross-sectional view of the optical semiconductor element according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a method of flip-chip mounting the optical semiconductor element according to the first embodiment of the present invention. It is a top view and sectional view of an optical semiconductor device concerning a 2nd embodiment of the present invention. It is sectional drawing explaining the method of flip-chip mounting the optical-semiconductor element which concerns on the 2nd Embodiment of this invention. It is a top view and a sectional view of an optical semiconductor device concerning a 3rd embodiment of the present invention. It is a top view and sectional view of an optical semiconductor device concerning a 4th embodiment of the present invention. It is a top view which shows the structure of the semiconductor monolithic type optical circuit which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows the structure of the MMI coupler of the semiconductor monolithic optical circuit which concerns on the 5th Embodiment of this invention. It is sectional drawing which shows another structure of the MMI coupler of the semiconductor monolithic optical circuit which concerns on the 5th Embodiment of this invention. It is a top view which shows the structure of the semiconductor monolithic type optical circuit which concerns on the 6th Embodiment of this invention. It is a block diagram explaining the structure of a high-speed chaotic optical signal generation optical circuit. It is a block diagram which shows the structural example of the phase modulation part in a high-speed chaotic optical signal generation optical circuit. It is a block diagram explaining the composition of an optical signal buffer memory circuit. It is a block diagram which shows the structural example of the phase modulation|alteration part in an optical signal buffer memory circuit.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A is a plan view of an optical semiconductor element according to a first embodiment of the present invention, and FIG. 1B is a sectional view of the optical semiconductor element of FIG. 1A cut along a cutting plane CS perpendicular to a substrate. A cross-sectional view and FIG. 1C are cross-sectional views of the optical semiconductor element of FIGS. 1A and 1B taken along a cutting plane SF horizontal to the substrate.

The optical semiconductor element of the present embodiment is formed on the lower clad layer (semiconductor substrate) 10 made of, for example, n-InP, the core layer 11 made of, for example, InGaAsP on the lower clad layer 10, and the core layer 11. The semiconductor mesa structure 12 formed on the core layer 11, supporting structures 13a and 13b formed around the semiconductor mesa structure 12 on the core layer 11, and the semiconductor mesa structure 12 and the supporting structures 13a and 13b are formed so as to be separated from each other. Thermal interference suppression groove structures 14a, 14b, semiconductor mesa structure 12, support structures 13a, 13b, insulating film 15 formed to cover the surfaces of thermal interference suppression groove structures 14a, 14b, and thermal interference suppression groove An organic material 16 made of, for example, BCB (benzocyclobutene) formed so as to fill one of the thermal interference suppressing groove structures 14b of the structures 14a and 14b, and a metal formed so as to be in contact with the upper portion of the semiconductor mesa structure 12. A p-electrode 17 made of a film and an n-electrode 18 made of a metal film formed so as to contact the core layer 11 exposed at the bottom of the thermal interference suppressing groove structure 14a.

Note that the insulating film is formed in each of the step before the organic material 16 is formed and the step after the organic material 16 is formed. In FIGS. 1A to 1C, the insulating film is formed in two steps. Both of these films are shown as the insulating film 15. The insulating film 15 is similarly used in the following embodiments.

The semiconductor mesa structure 12 is formed on the core layer 11 by an etch stop layer 19 made of, for example, GaInAlAs, an active layer 20 made of, for example, InGaAsP on the etch stop layer 19, and an active layer 20. For example, the upper clad layer 21 made of p-InP and the contact layer 22 made of, for example, InGaAs, are formed on the upper clad layer 21. In the semiconductor mesa structure 12, the mesa widths of the etch stop layer 19 and the active layer 20 (dimensions in the left-right direction in FIGS. 1A to 1C) are wider than the mesa widths of the upper cladding layer 21 and the contact layer 22. It has a two-step mesa structure.

The support structures 13 a and 13 b are formed on the etch stop layer 19, the upper clad layer 23 formed on the etch stop layer 19, the contact layer 24 formed on the upper clad layer 23, and the contact layer 24. For example, the support layer 25 is made of p-InP.

In the present embodiment, one of the thermal interference suppressing groove structures 14a and 14b is entirely filled with the organic material 16, and the organic material 16 and the semiconductor mesa structure 12 are supported. A p-electrode 17 is formed on the structure 13b via an insulating film 15. An opening is formed in the insulating film 15 on the surface of the contact layer 22 of the semiconductor mesa structure 12, and the contact layer 22 exposed in the opening is in contact with the p-electrode 17.

On the other hand, the etch stop layer 19 at the bottom of the thermal interference suppression groove structure 14a is removed, and the core layer 11 is exposed. The n-electrode 18 is formed so as to come into contact with the core layer 11 exposed at the bottom of the thermal interference suppression groove structure 14a.

In this embodiment, when a voltage is applied between the p-electrode 17 and the n-electrode 18, the p-electrode 17→contact layer 22→upper clad layer 21→active layer 20→etch stop layer 19→core layer 11→n. -A current flows through the active layer 20 through the path of the electrode 18.

As described above, in the present embodiment, by providing the groove structure 14a for suppressing thermal interference between the semiconductor mesa structure 12 and the support structure 13a, heat generated in the active layer 20 of the semiconductor mesa structure 12 is not generated. Interference with the circuit can be suppressed. In the present embodiment, the p-electrode 17 in contact with the contact layer 22 above the semiconductor mesa structure 12 is provided from the region on the semiconductor mesa structure 12 to the thermal interference suppressing groove structure 14b adjacent to the semiconductor mesa structure 12. So as to extend along a region on the insulating film 15 covering the surface of the organic material 16 formed so as to cover the surface of the insulating film 15 covering the surface of the support structure 13b adjacent to the thermal interference suppressing groove structure 14b. By forming it in the above manner, the heat generated in the active layer 20 of the semiconductor mesa structure 12 can be efficiently radiated from the p-electrode 17. As a result, in the present embodiment, the characteristic deterioration of the optical semiconductor element due to the temperature rise can be suppressed, and the thermal interference with other circuits can be further suppressed.

FIG. 2 is a cross-sectional view illustrating a method of flip-chip mounting the optical semiconductor element of this embodiment. In FIG. 2, 26 is a substrate, 27 and 28 are electrodes formed on the substrate 26, and 29 and 30 are bumps. In this embodiment, the support structures 13a and 13b do not include the active layer 20, and the upper clad layer 21 of the semiconductor mesa structure 12 and the upper clad layer 23 of the support structures 13a and 13b are formed at the same time. Since the contact layer 22 of the semiconductor mesa structure 12 and the contact layer 24 of the support structures 13a and 13b are formed at the same time, the height of the upper surface of the contact layer 24 is the same as that of the upper surface of the contact layer 22 as shown in FIG. It is lower than the height. Therefore, in the present embodiment, the support layer 25 thicker than the active layer 20 is formed on the contact layer 24 so that the upper surface of the support layer 25 is higher than the upper surface of the contact layer 22 of the semiconductor mesa structure 12. I have to. As a result, as shown in FIG. 1B, the upper surface of the p-electrode 17 formed on the semiconductor mesa structure 12 becomes lower than the upper surface of the n-electrode 18 formed on the surfaces of the support structures 13a and 13b. ..

Therefore, when the optical semiconductor element of the present embodiment is turned over and flip-chip mounted on the substrate 26 as shown in FIG. 2, the semiconductor mesa structure 12 does not come into contact with the substrate 26. There will be no deviation of the optical semiconductor element or breakage of the optical semiconductor element.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. 3A is a plan view of an optical semiconductor element according to a second embodiment of the present invention, and FIG. 3B is a sectional view of the optical semiconductor element of FIG. 3A cut along a cutting plane CS perpendicular to the substrate. 3(C) is a cross-sectional view of the optical semiconductor element of FIGS. 3(A) and 3(B) taken along a cutting plane SF horizontal to the substrate, and FIGS. 1(A) to 1(C). The same reference numerals are given to the same components as those in FIG.

In the first embodiment, one of the thermal interference suppressing groove structures 14a and 14b is entirely filled with the organic material 16 and the insulating film 15 is formed so as to cover the organic material 16. Although the p-electrode 17 is formed on the above, the optical semiconductor element of the present embodiment has a bilaterally symmetrical structure centered on the semiconductor mesa structure 12. For this reason, in the thermal interference suppressing groove structures 14a and 14b, the region where the active layer 20 is not provided at the bottom (the peripheral region of the optical semiconductor element) is filled with the organic material 16, and the top of the organic material 16 and the semiconductor mesa. The p-electrode 17a is formed on the structure 12 and the supporting structures 13a and 13b with the insulating film 15 interposed therebetween. Similar to the first embodiment, an opening is formed in the insulating film 15 on the surface of the contact layer 22 of the semiconductor mesa structure 12, and the contact layer 22 and the p-electrode 17a exposed in this opening are separated from each other. Contact.

Further, in the present embodiment, not only the etch stop layer 19 at the bottom of the thermal interference suppression groove structure 14a but also the etch stop layer 19 at the bottom of the thermal interference suppression groove structure 14b is removed. Similar to the first embodiment, the n-electrode 18 is formed on the surface of the support structure 13a and the sidewall of the thermal interference suppression groove structure 14a via the insulating film 15, and the bottom portion of the thermal interference suppression groove structure 14a is formed. The exposed core layer 11 is exposed. The n-electrode 18b is formed on the surface of the support structure 13b and the sidewall of the thermal interference suppression groove structure 14b via the insulating film 15 and is in contact with the core layer 11 exposed at the bottom of the thermal interference suppression groove structure 14b. Other configurations are as described in the first embodiment.

As described above, in the present embodiment, the p-electrode 17a that is in contact with the contact layer 22 above the semiconductor mesa structure 12 is provided for suppressing thermal interference on both sides of the semiconductor mesa structure 12 from the region on the semiconductor mesa structure 12. The surface of the supporting structure 13a, 13b next to the thermal interference suppressing groove structure 14a, 14b along the region on the insulating film 15 covering the surface of the organic material 16 formed so as to block a part of the groove structure 14a, 14b. The heat generated in the active layer 20 of the semiconductor mesa structure 12 can be efficiently radiated from the p-electrode 17a by being formed so as to extend to the region on the insulating film 15 that covers the.

FIG. 4 is a cross-sectional view illustrating a method of flip-chip mounting the optical semiconductor element of this embodiment. In FIG. 4, reference numeral 26 is a substrate, 28 is an electrode formed on the substrate 26, and 30 is a bump connecting the n-electrodes 18 and 18b to the electrode 30. Although bumps and electrodes connected to the p-electrode 17a are not shown in FIG. 4, the p-electrode 17a and the electrode 27 formed to extend to the regions of the support structures 13a and 13b are bumps as in FIG. It goes without saying that they are connected via 29. According to FIG. 4, it can be seen that the same effects as those of the first embodiment can be obtained also in the present embodiment.

Further, in the first embodiment, since the thermal interference suppressing groove structure 14b is filled with the organic material 16, the thermal interference with the circuit on the left side of FIGS. 1A to 1C is effective. In contrast to this, in the present embodiment, since the thermal interference suppressing groove structures 14a and 14b are provided on the left and right sides of the optical semiconductor element, the thermal interference to the circuits on the left and right sides of the optical semiconductor element is effective. Can be suppressed.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. 5A is a plan view of an optical semiconductor element according to a third embodiment of the present invention, and FIG. 5B is a sectional view of the optical semiconductor element of FIG. 5A cut along a cutting plane CS perpendicular to the substrate. 5C is a cross-sectional view of the optical semiconductor element of FIGS. 5A and 5B taken along a cutting plane SF that is horizontal to the substrate, and FIGS. The same components as those in () are denoted by the same reference numerals.

The optical semiconductor device according to the present embodiment includes a lower cladding layer 10, a core layer 11, an etch stop layer 19, an active layer 20, a semiconductor mesa structure 12c formed on the active layer 20, and an active layer 20. Support structures 13c and 13d formed around the semiconductor mesa structure 12c, thermal interference suppression groove structures 14c and 14d, an insulating film 15, and thermal interference suppression groove structures 14c and 14d. An organic material 16 made of, for example, BCB formed so as to fill the groove structure 14d for use, a p-electrode 17 made of a metal film formed so as to be in contact with an upper portion of the semiconductor mesa structure 12c, and a groove structure 14a for suppressing thermal interference. And an n-electrode 18c made of a metal film formed so as to be in contact with the active layer 20 exposed at the bottom of the.

In the first and second embodiments, the active layer 20 having a quadrangular shape in plan view is formed only in the semiconductor mesa structure 12, and the active layer 20 in the regions of the support structures 13a and 13b is removed. On the other hand, in the present embodiment, the active layer 20 is left without being removed, and the semiconductor mesa structure 12c and the support structures 13c and 13d are formed on the active layer 20.

The semiconductor mesa structure 12 c includes an upper clad layer 21 formed on the active layer 20 and a contact layer 22 formed on the upper clad layer 21.
The support structures 13c and 13d are composed of an upper clad layer 23 formed on the active layer 20, a contact layer 24 formed on the upper clad layer 23, and a support layer 25 formed on the contact layer 24. It

Similar to the first embodiment, one of the thermal-interference suppressing groove structures 14c and 14d is filled with the organic material 16 in all of the thermal-interference suppressing groove structures 14d, and the insulation is formed so as to cover the organic material 16. A p-electrode 17 is formed on the film 15.

On the other hand, in the present embodiment, the active layer 20 is exposed at the bottom of the thermal interference suppression groove structure 14c. The n-electrode 18c is formed on the surface of the support structure 13c and the sidewall of the thermal interference suppression groove structure 14c via the insulating film 15, and is in contact with the active layer 20 exposed at the bottom of the thermal interference suppression groove structure 14c.
When a voltage is applied between the p-electrode 17 and the n-electrode 18c, a current flows through the active layer 20 through the route of p-electrode 17→contact layer 22→upper cladding layer 21→active layer 20→n-electrode 18c. Other configurations are as described in the first embodiment.

In the present embodiment, the p-electrode 17 in contact with the contact layer 22 above the semiconductor mesa structure 12c is covered with the thermal interference suppressing groove structure 14d adjacent to the semiconductor mesa structure 12c from the region on the semiconductor mesa structure 12c. The organic material 16 is formed so as to extend along the region on the insulating film 15 covering the surface of the organic material 16 to reach the region on the insulating film 15 covering the surface of the support structure 13d adjacent to the thermal interference suppressing groove structure 14d. By doing so, the heat generated in the active layer 20 below the semiconductor mesa structure 12c can be efficiently radiated from the p-electrode 17.

Further, in the present embodiment, the semiconductor mesa structure 12c and the support structures 13c and 13d are formed on the active layer 20, and the upper clad layer 21 of the semiconductor mesa structure 12c and the upper clad layers of the support structures 13c and 13c are formed. 23 and the contact layer 22 of the semiconductor mesa structure 12c and the contact layer 24 of the support structures 13c and 13d are simultaneously formed. Therefore, as shown in FIG. The height is the same as the upper surface of the contact layer 22. Therefore, similarly to the first embodiment, the support layer 25 is formed on the contact layer 24 so that the upper surface of the support layer 25 is higher than the upper surface of the contact layer 22 of the semiconductor mesa structure 12. There is. As a result, as shown in FIG. 5B, the upper surface of the p-electrode 17 formed on the semiconductor mesa structure 12c becomes lower than the upper surface of the n-electrode 18c formed on the surfaces of the support structures 13c and 13d. .. Therefore, as in the case of the first embodiment, when the optical semiconductor element is turned over and flip-chip mounted on the substrate, the semiconductor mesa structure 12c does not come into contact with the substrate, so that the operation characteristics of the optical semiconductor element are deviated. There is no possibility that the optical semiconductor element will be lost or broken.

In the first and second embodiments, since the upper surface of the contact layer 24 is lower than the upper surface of the contact layer 22, it is an essential condition that the support layer 25 is thicker than the active layer 20. In the above embodiment, since the upper surface of the contact layer 24 and the upper surface of the contact layer 22 are at the same height, it is not essential that the support layer 25 be thicker than the active layer 20, and the upper surface of the support layer 25 is the contact layer 22. It only needs to be higher than the top surface.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. 6A is a plan view of an optical semiconductor element according to a fourth embodiment of the present invention, and FIG. 6B is a sectional view of the optical semiconductor element of FIG. 6A cut along a cutting plane CS perpendicular to a substrate. 6C is a cross-sectional view of the optical semiconductor element of FIGS. 6A and 6B, taken along a cutting plane SF that is horizontal to the substrate, and FIGS. The same reference numerals are given to the same components as those in FIG.

In the third embodiment, one of the thermal interference suppressing groove structures 14c and 14d is entirely filled with the organic material 16 and the insulating film 15 is formed so as to cover the organic material 16. Although the p-electrode 17 was formed on top of the above, the optical semiconductor element of the present embodiment has a bilaterally symmetrical structure centered on the semiconductor mesa structure 12c. Therefore, the peripheral region of the optical semiconductor element in the thermal interference suppressing groove structures 14c and 14d is filled with the organic material 16, and the organic material 16 and the semiconductor mesa structure 12c and the supporting structures 13c and 13d are formed. A p-electrode 17c is formed on top of this via an insulating film 15. Similar to the third embodiment, an opening is formed in the insulating film 15 on the surface of the contact layer 22 of the semiconductor mesa structure 12c, and the contact layer 22 and the p-electrode 17c exposed in this opening are separated from each other. Contact.

In the present embodiment, the active layer 20 is exposed not only at the bottom of the thermal interference suppression groove structure 14c but also at the bottom of the thermal interference suppression groove structure 14d. Similar to the third embodiment, the n-electrode 18c is formed on the surface of the support structure 13c and the sidewall of the thermal interference suppression groove structure 14c via the insulating film 15, and the bottom portion of the thermal interference suppression groove structure 14c is formed. And contact the active layer 20 exposed to the outside. The n-electrode 18d is formed on the surface of the support structure 13d and the sidewall of the thermal interference suppression groove structure 14d via the insulating film 15, and is in contact with the active layer 20 exposed at the bottom of the thermal interference suppression groove structure 14d. Other configurations are as described in the third embodiment.

In the present embodiment, the p-electrode 17c in contact with the contact layer 22 above the semiconductor mesa structure 12c is provided from the region on the semiconductor mesa structure 12c to the thermal interference suppressing groove structures 14c and 14d on both sides of the semiconductor mesa structure 12c. An insulating film 15 covering the surface of the organic material 16 formed so as to cover a part of the insulating film 15 and covering the surface of the supporting structures 13c and 13d adjacent to the thermal interference suppressing groove structures 14c and 14d. By forming so as to extend to the upper region, heat generated in the active layer 20 below the semiconductor mesa structure 12c can be efficiently radiated from the p-electrode 17c. In this way, in this embodiment, the same effects as those of the first and third embodiments can be obtained.

Further, in the third embodiment, since the thermal interference suppressing groove structure 14d is filled with the organic material 16, the thermal interference to the circuits on the left side of FIGS. 5A to 5C is effective. In contrast to this, in the present embodiment, thermal interference with the circuits on the left and right sides of the optical semiconductor element can be effectively suppressed.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 7 is a plan view showing the configuration of a semiconductor monolithic optical circuit according to the fifth embodiment of the present invention. The semiconductor monolithic optical circuit of the present embodiment is one in which the optical semiconductor element described in the first to fourth embodiments is integrated with other circuits on the same substrate.

In FIG. 7, A-01 to A-08 are optical waveguides, B-01 and B-02 are MMI (Multi-Mode-Inteference) couplers, C-01 is an optical semiconductor element, and D-01, D. Reference numeral -02 is a groove structure for suppressing thermal interference of the optical semiconductor element C-01, and E-01 is a Mach-Zehnder interference type optical circuit.

Examples of such a semiconductor monolithic optical circuit include, for example, the high-speed chaotic optical signal generation optical circuit described with reference to FIGS. 11 and 12, and the optical signal described with reference to FIGS. 13 and 14A to 14C. There is a buffer memory circuit and the like. For example, the optical semiconductor element C-01 corresponds to the optical signal amplifiers BA-1 and BA-2 in FIG. 13, and the optical waveguides A-01 and A-02 correspond to the optical waveguides 115L and 115R in FIG. The Mach-Zehnder interferometer type optical circuit E-01 corresponds to the Mach-Zehnder interferometer type optical intensity modulator MZ-1 in FIG.

In the example of FIG. 7, as the optical semiconductor element C-01, the one having the thermal interference suppressing groove structures D-01 and D-02 on both sides of the semiconductor mesa structure is described. Therefore, as the optical semiconductor element C-01, the optical semiconductor element described in the second and fourth embodiments is used. In this case, the horizontal direction in FIGS. 3A to 3C and 6A to 6C corresponds to the vertical direction in FIG. 7, and the thermal interference suppressing groove structures 14a and 14b (14c). , 14d) correspond to the thermal interference suppressing groove structures D-01 and D-02, and the optical waveguide including the lower clad layer 10, the core layer 11, the etch stop layer 19 and the upper clad layer 21 is the optical waveguide A-01. , A-02.

By using the optical semiconductor element described in the second and fourth embodiments as the optical semiconductor element C-01, the heat generated in the optical semiconductor element C-01 is transferred to the Mach-Zehnder interference type optical circuit E-01. Interference can be suppressed. In particular, when a plurality of Mach-Zehnder interferometer type optical circuits E-01 are lined up on the substrate as in the example of FIG. 7, it is possible to effectively suppress thermal interference with the circuits on both sides of the optical semiconductor element C-01. The configurations as shown in FIGS. 3 and 6 capable of performing the above are effective. Needless to say, the optical semiconductor elements described in the first and third embodiments are also applicable, although the heat radiation effect is inferior to those in the second and fourth embodiments.

Here, FIG. 8 and FIG. 9 are cross-sectional views showing an example of the configuration of the MMI couplers B-01 and B-02, and FIGS. 1(A) to 1(C) and 3(A) to 3 (C), FIG. 5(A)-FIG. 5(C), and FIG. 6(A)-FIG. 6(C) are attached with the same reference numerals. In the example of FIG. 8, the groove structure 33 formed on both sides of the semiconductor mesa structure 32 similar to the optical semiconductor element is filled with the organic material 16, and the electrode 34 is formed on the insulating film 15 formed so as to cover the organic material 16. Is forming.

In the example of FIG. 8, the groove structure 33 has a mesa (ridge) type structure that does not reach the core layer 11, but in the example of FIG. 9, the groove structure 33 extends to the lower clad layer 10 deeper than the core layer 11. It has a high mesa (deep ridge) type structure. As the configuration of the MMI couplers B-01 and B-02, it is possible to use either a mesa type or a high mesa type, but in general, the use of the high mesa type has an advantage of less bending loss and radiation loss. .. On the other hand, the mesa type has an advantage that it is easy to manufacture.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 10 is a plan view showing the configuration of the semiconductor monolithic optical circuit according to the sixth embodiment of the present invention. Similar to the fifth embodiment, the semiconductor monolithic optical circuit according to the present embodiment is one in which the optical semiconductor element described in the first to fourth embodiments is integrated with other circuits on the same substrate. Is.

In FIG. 10, A-09 to A-24 are optical waveguides, B-03 to B-06 are MMI couplers, C-02 to C-05 are optical semiconductor elements, and D-03 to D-07 are optical semiconductor elements C. -02 to C-05 thermal interference suppressing groove structures, and F-01 and F-02 are Mach-Zehnder interference type optical circuits.

Examples of such a semiconductor monolithic optical circuit include, for example, the high-speed chaotic optical signal generation optical circuit described in FIGS. 11 and 12, and the optical described in FIGS. 13 and 14A to 14C. There is a signal buffer memory circuit and the like. For example, the optical semiconductor elements C-02 to C-05 correspond to the optical phase modulation control units c1 and c2 in FIGS. 12 and 14A to 14C, and the MMI couplers B-03 and B-05 are MMI. The MMI couplers B-04 and B-06 correspond to the MMI coupler b2, the optical waveguides A-10 and A-18 correspond to the optical waveguides 1012 and e5, and the optical waveguides A-11 and A- correspond to the coupler b1. Reference numeral 19 corresponds to the optical waveguides 1014, 1016, e7, optical waveguides A-14, A-22 correspond to the optical waveguides 1013, e6, and optical waveguides A-15, A-23 correspond to the optical waveguides 1015, e8. . The Mach-Zehnder interferometer type optical circuits F-01 and F-02 correspond to the optical phase modulators R1, L1, R1-1, R1-2, L1-1 and L1-2.

In the fifth embodiment, the optical semiconductor element C-01 is arranged adjacent to the Mach-Zehnder interference type optical circuit E-01, whereas in the present embodiment, the Mach-Zehnder interference type optical circuit F- is used. 01 and F-02 include optical semiconductor elements C-02 to C-05.

In this embodiment, as in the fifth embodiment, the optical semiconductor elements described in the second and fourth embodiments are used as the optical semiconductor elements C-02 to C-05. That is, the horizontal direction in FIGS. 3A to 3C and 6A to 6C corresponds to the vertical direction in FIG. 10, and the thermal interference suppressing groove structures 14a and 14b (14c, 14c, 14d) corresponds to the thermal interference suppressing groove structures D-03 to D-07, and the optical waveguide including the lower cladding layer 10, the core layer 11, the etch stop layer 19 and the upper cladding layer 21 is the optical waveguide A-10, It corresponds to A-11, A-14, A-15, A-18, A-19, A-22, and A-23.

In this way, in this embodiment, the same effect as that of the fifth embodiment can be obtained. Note that the example of FIG. 10 shows an example in which adjacent optical semiconductor elements share the thermal interference suppression groove structure between them. For example, the optical semiconductor elements C-02 and C-03 share the thermal interference suppressing groove structure D-04, and the optical semiconductor elements C-03 and C-04 share the thermal interference suppressing groove structure D-05. ing. As described above, if the adjacent optical semiconductor elements share the thermal interference suppressing groove structure, the area of the semiconductor monolithic optical circuit can be reduced. It goes without saying that each optical semiconductor element may have a structure having a groove structure for suppressing thermal interference, one on each side of the semiconductor mesa structure, as described in the embodiment. Further, it is needless to say that the optical semiconductor elements described in the first and third embodiments can also be applied, although the heat radiation effect is inferior to those in the second and fourth embodiments.

In the first to sixth embodiments, since the structure of SOA is assumed as the optical semiconductor element, the layer 20 is the active layer. However, the optical semiconductor element described in the first to sixth embodiments is used. Is an injection current type optical modulator, the layer 20 is a phase adjusting layer, and when the optical semiconductor element is a reverse bias addition type EA optical modulator, the layer 20 is an absorbing layer. In the case of the reverse bias addition type EA optical modulator, when light enters the EA optical modulator, a current flows in the absorption layer and heat is generated, so that it is effective to apply the present invention.

Further, in the first to sixth embodiments, the example in which the thermal interference suppressing groove structure reaches the active layer 20 or the core layer 11 is shown, but the thermal interference suppressing groove structure extends to the lower clad layer 10. It may be a high-mesa (deep ridge) type structure that reaches. In this case, each of the semiconductor mesa structure and the support structure has a structure including a part on the upper surface side of the lower cladding layer 10 and the core layer 11 in addition to the structures described in the first and second embodiments. .. Further, the n-electrode may be formed so as to be in contact with the lower clad layer 10 exposed at the bottom of the thermal interference suppressing groove structure.

Further, in the first to sixth embodiments, the example in which the core layer 11 is formed under the active layer (or the phase adjustment layer or the absorption layer) 20 has been described, but the present invention is not limited to this, and the active layer is not limited thereto. (Or phase adjustment layer or absorption layer) 20, the core layer 11 is formed in the same layer, and the active layer (or phase adjustment layer or absorption layer) 20 formed in the region of the optical semiconductor element is the core outside the region. It may be adapted to be optically coupled to the layer 11. In this case, the n-electrode may be formed so as to contact the core layer 11 exposed at the bottom of the thermal interference suppression groove structure or the lower clad layer 10 exposed at the bottom of the thermal interference suppression groove structure.

INDUSTRIAL APPLICABILITY The present invention can be applied to an optical semiconductor element such as a ridge-loaded semiconductor optical amplifier, an injection current optical modulator, or a reverse bias addition type electroabsorption optical modulator.

10... Lower clad layer, 11... Core layer, 12... Semiconductor mesa structure, 13a, 13b, 13c, 13d... Support structure, 14a, 14b, 14c, 14d... Thermal interference suppressing groove structure, 15... Insulating film, 16... Organic material, 17, 17a... P-electrode, 18, 18b, 18c... N-electrode, 19... Etch stop layer, 20... Active layer, 21, 23... Upper cladding layer, 22, 24... Contact layer, 25... Support Layer, A-01 to A-24... Optical waveguide, B-01 to B-06... MMI coupler, C-01 to C-05... Optical semiconductor element, D-01 to D-07... Thermal interference suppressing groove structure , E-01, F-01, F-02... Mach-Zehnder interference type optical circuit.

Claims (5)

A semiconductor mesa structure formed on the first cladding layer,
Support structures formed on both sides of the semiconductor mesa structure on the first cladding layer;
A thermal interference suppressing groove structure formed so as to separate the semiconductor mesa structure and the supporting structures on both sides thereof,
A first electrode made of a metal film formed so as to contact the upper portion of the semiconductor mesa structure;
A second electrode made of a metal film formed so as to contact a semiconductor layer different from the semiconductor mesa structure;
Of the thermal interference suppression groove structure, an organic material formed so as to close the region of the peripheral portion of the semiconductor mesa structure except between the semiconductor mesa structure and the support structure,
Further, as a semiconductor layer in which a current flows by current injection from the outside or incidence of light from the outside between the semiconductor mesa structure and the support structure and the first cladding layer, or in a part of the semiconductor mesa structure. An active layer or a phase adjustment layer or an absorption layer is provided,
The first electrode travels from an upper region of the semiconductor mesa structure to a region on an insulating film covering a surface of the organic material in a peripheral region of the semiconductor mesa structure, and is formed on both sides of the semiconductor mesa structure. An optical semiconductor device, which is formed so as to extend to a region on an insulating film covering the surface of the support structure. The optical semiconductor element according to claim 1 ,
The semiconductor mesa structure is
At least an etch stop layer formed on the first cladding layer,
The active layer or the phase adjustment layer or the absorption layer formed on the etch stop layer,
Formed on the active layer, the phase adjusting layer or the absorption layer, the first cladding layer and the second cladding layer having a different conductivity type,
The support structure is
At least the etch stop layer,
A third cladding layer of the same conductivity type as the second cladding layer formed on the etch stop layer,
The thermal interference suppressing groove structure is formed to a depth at which a semiconductor layer different from the semiconductor mesa structure is exposed,
The semiconductor layer different from the semiconductor mesa structure is either a core layer formed between the first cladding layer and the etch stop layer or the first cladding layer. element. The optical semiconductor element according to claim 1 ,
The active layer, the phase adjustment layer, or the absorption layer is formed on the etch stop layer formed on the first cladding layer,
The semiconductor mesa structure and the support structure,
At least a second clad layer having a conductivity type different from that of the first clad layer formed on the active layer, the phase adjusting layer or the absorption layer,
The thermal interference suppressing groove structure is formed to a depth at which a semiconductor layer different from the semiconductor mesa structure is exposed,
The semiconductor layer different from the semiconductor mesa structure includes the active layer, the phase adjustment layer, or the absorption layer, the core layer formed between the first cladding layer and the etch stop layer, or the first cladding layer. An optical semiconductor device characterized by being any one of the above. The optical semiconductor element according to any one of claims 1 to 3 ,
The optical semiconductor device according to claim 1, wherein the supporting structure further includes a supporting layer formed on the upper surface of the supporting structure such that the upper surface of the semiconductor mesa structure is lower than the upper surface of the supporting structure. A semiconductor monolithic optical circuit comprising the optical semiconductor element according to any one of claims 1 to 4 integrated on the same substrate together with circuits other than the optical semiconductor element.