JP6707688B2 - Luminous display panel - Google Patents

Description

The present invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

In recent years, attention has been focused on a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundreds nm) formed on a substrate having an insulating surface. The thin film transistor is I
It is widely applied to electronic devices such as C and electro-optical devices, and its development as a switching element for image display devices is particularly urgent. Further, as a semiconductor thin film, a metal oxide has been attracting attention, and various metal oxides exist and are used for various purposes. In particular, indium oxide is a well-known material as a metal oxide, and is used as a transparent electrode material required for liquid crystal displays and the like.

Some metal oxides have semiconductor characteristics. Examples of the metal oxide having semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide, and a thin film transistor including such a metal oxide having semiconductor characteristics as a channel formation region is already known. (Patent document 1 and patent document 2).

JP, 2007-123861, A JP, 2007-96055, A

In the active matrix type display device, the electrical characteristics of the thin film transistors forming the circuit are important, and the electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of thin film transistors, power consumption during non-operation (power consumption during standby) due to increase in off current (also referred to as leak current, Ioff, etc.) is important.

In the case of an n-channel thin film transistor, a thin film transistor in which a channel is formed and a drain current starts flowing only after a positive voltage is applied to a gate voltage is desirable. A thin film transistor through which an off current flows when the voltage applied to the gate is negative is not suitable for a thin film transistor used for a circuit.

For example, when the off-state current of a thin film transistor included in a circuit in a semiconductor device is large,
There is a possibility that current leakage may occur due to the increase in the off current. Therefore, it is an object of one embodiment of the present invention to provide a thin film transistor which operates stably in a wide temperature range and a semiconductor device including the thin film transistor. Note that in this specification and the like, the off-state current of a thin film transistor refers to a current value when a voltage applied to a gate is a negative voltage.

One embodiment of the present invention disclosed in this specification includes a gate electrode layer over a substrate having an insulating surface, a gate insulating layer over the gate electrode layer, and an oxide semiconductor layer over the gate insulating layer. An insulating layer that has a source electrode layer and a drain electrode layer over the oxide semiconductor layer and is in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer Have
A semiconductor device having a channel width of 1×10 ⁻¹² A or less per 1 μm in a temperature range of −25° C. or higher and 150° C. or lower.

In the above structure, the channel length of the oxide semiconductor layer may be 1.5 μm or more and 100 μm or less. The channel length of the oxide semiconductor layer may be 3 μm or more and 10 μm or less.

According to one embodiment of the present invention disclosed in this specification, a gate electrode layer is formed over a substrate having an insulating surface, a gate insulating layer is formed over the gate electrode layer, and an oxide semiconductor is formed over the gate insulating layer. After forming a layer and an oxide semiconductor layer, first heat treatment and second heat treatment are performed to form a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a gate insulating layer, and an oxide layer. An insulating layer which is in contact with part of the oxide semiconductor layer is formed over the semiconductor layer, the source electrode layer, and the drain electrode layer, and after the insulating layer is formed, third heat treatment is performed, so that a semiconductor device is manufactured. Is the way.

In the above structure, the first heat treatment is preferably performed in a nitrogen atmosphere or a rare gas atmosphere. In addition, the first heat treatment is preferably performed at a temperature of 350 °C to 750 °C.

In the above structure, the second heat treatment is preferably performed in an air atmosphere or an oxygen atmosphere.
In addition, the second heat treatment is preferably performed at 100 °C or higher and the first heat treatment temperature or lower.

The above configuration solves at least one of the above problems.

A thin film represented by InMO ₃ (ZnO) _m (m>0) is formed using the oxide semiconductor used in this specification, and a thin film transistor using the thin film as an oxide semiconductor layer is manufactured. However, m is not necessarily an integer. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M may be Ga or may include the above metal elements other than Ga such as Ga and Ni or Ga and Fe. Further, in the above oxide semiconductor, Fe, Ni, another transition metal element, or an oxide of the transition metal may be contained as an impurity element in addition to the metal element contained as M. In this specification, in the oxide semiconductor layer having a structure represented by InMO ₃ (ZnO) _m (m>0), an oxide semiconductor having a structure containing Ga as M is oxidized by In—Ga—Zn—O-based oxidation. A thin film semiconductor is also called an In—Ga—Zn—O-based non-single-crystal film.

In addition to the above, as an oxide semiconductor applied to the oxide semiconductor layer, In-Sn-Zn-
O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S
n-Al-Zn-O system, In-Zn-O system, In-Ga-O system, Sn-Zn-O system, Al
A -Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor can be applied. Further, silicon oxide may be contained in the above oxide semiconductor layer. By including silicon oxide (SiOx (X>0)) that inhibits crystallization in the oxide semiconductor layer, crystallization is suppressed when heat treatment is performed after the oxide semiconductor layer is formed in the manufacturing process. can do. Note that the oxide semiconductor layer is preferably in an amorphous state and may be partly crystallized.

Further, depending on the conditions of heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be changed from an amorphous state to a microcrystalline film or a polycrystalline film. Even when a microcrystalline film or a polycrystalline film is formed, switching characteristics can be obtained as a TFT.

A thin film transistor having a small fluctuation range of off-state current and stable electric characteristics can be manufactured and provided. Therefore, a semiconductor device including a thin film transistor with favorable electric characteristics and high reliability can be provided.

6A to 6C are diagrams illustrating a manufacturing process of a semiconductor device. 7A to 7C each illustrate a semiconductor device. 6A and 6B are diagrams illustrating an analysis method and a hydrogen concentration in an oxide semiconductor layer. 3 is a graph showing off-current characteristics of the thin film transistor of Example 1. FIG. 10 is a diagram showing a cross-sectional structure used for calculation of a semiconductor device. 6A and 6B illustrate a structure assumed in calculation of a semiconductor device. FIG. 8 illustrates a block diagram of a semiconductor device. 6A and 6B are diagrams illustrating a structure and an operation of a signal line driver circuit. FIG. 6 is a circuit diagram illustrating a structure of a shift register. 7A and 7B are a structure and a timing chart illustrating operation of a shift register. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. FIG. 6 illustrates a pixel equivalent circuit of a semiconductor device. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. FIG. 6 is a circuit diagram illustrating a structure of a semiconductor device. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. 7A to 7C each illustrate a semiconductor device. FIG. 6 is a circuit diagram illustrating a structure of a semiconductor device. FIG. 6 illustrates an example of an electronic book reader. The figure which shows the example of a television apparatus and a digital photo frame. The figure which shows the example of a game machine. The figure which shows the example of a portable computer and a mobile telephone. FIG. 16 illustrates calculation results of a semiconductor device. FIG. 16 illustrates calculation results of a semiconductor device. FIG. 16 illustrates calculation results of a semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details thereof can be variously modified. The present invention should not be construed as being limited to the description of the embodiments below.

(Embodiment 1)
In this embodiment, one mode of a method for manufacturing the thin film transistor 150 illustrated in FIG. 1E will be described with reference to FIGS. 1A to 1E which are cross-sectional views of a manufacturing process of a thin film transistor. Note that FIG. 1F is a top view of the thin film transistor 150 illustrated in FIG. The thin film transistor 150 has one of bottom-gate structures called a channel-etch type.

First, a metal conductive film is formed over a substrate 100 having an insulating surface, and a gate electrode layer 101 is formed by performing a photolithography step and an etching step using a photomask in order to process the metal conductive film into a desired shape. Note that the resist mask may be formed by an inkjet method. When a resist mask is formed by an inkjet method, a photomask is not used,
Manufacturing cost can be reduced.

A glass substrate is preferably used as the substrate 100. As the glass substrate used as the substrate 100, a glass substrate having a strain point of 730° C. or higher is preferably used when the temperature of the heat treatment performed later is high. Further, for the substrate 100, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used. By containing more barium oxide (BaO) than boric acid, more practical heat-resistant glass can be obtained.
Therefore, it is preferable to use a glass substrate containing BaO in a larger amount than B ₂ O ₃ .

Instead of the substrate 100 described above, a substrate made of an insulator such as a ceramic substrate, a quartz glass substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, crystallized glass or the like can be used.

Further, an insulating film serving as a base film may be provided between the substrate 100 and the gate electrode layer 101. The base film has a function of preventing diffusion of an impurity element from the substrate 100, and has a stacked-layer structure including one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. Can be formed.

By including a halogen element such as chlorine or fluorine in the base film, the function of preventing diffusion of the impurity element from the substrate 100 can be further enhanced. Regarding the concentration of the halogen element contained in the underlayer film, the concentration peak obtained by the analysis using SIMS (secondary ion mass spectrometer) is 1×10 ¹⁵ atoms/cm ³ or more and 1×10 ²⁰ atoms/cm ³ or less. do it.

As the gate electrode layer 101, a metal conductive film can be used. As the material of the metal conductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, an alloy containing the above-mentioned element as a component, an alloy combining the above-mentioned elements, or the like is used. preferable. For example, a three-layer structure in which an aluminum layer is stacked over a titanium layer and a titanium layer is stacked over the aluminum layer, or a three-layer structure in which an aluminum layer is stacked over a molybdenum layer and a molybdenum layer is stacked over the aluminum layer. The structure is preferable. Needless to say, the metal conductive film may have a single layer structure, a two-layer structure, or a laminated structure of four or more layers.

Next, the gate insulating layer 102 is formed over the gate electrode layer 101.

The gate insulating layer 102 can be formed as a single layer or a stacked layer using a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer by a plasma CVD method, a sputtering method, or the like. For example, plasma CV using SiH ₄ , oxygen and nitrogen as film forming gas
The silicon oxynitride layer may be formed by the D method. The thickness of the gate insulating layer 102 is 100 nm
For example, in the case of stacking, the first gate insulating layer has a thickness of 50 nm to 200 nm and the second gate insulating layer has a thickness of 5 nm to 300 nm on the first gate insulating layer. And

In addition, before forming the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon,
The gate insulating layer 102 may be formed by performing heat treatment (400° C. or higher and lower than the strain point of the substrate) under argon or the like to remove impurities such as hydrogen and water contained in the layer.

Then, a film thickness of 5 nm or more and 200 nm or less, preferably 10 nm is formed over the gate insulating layer 102.
An oxide semiconductor film having a thickness of 50 nm or more is formed. The thickness of the oxide semiconductor film is preferably 50 nm or less so that the oxide semiconductor film is in an amorphous state even after heat treatment for dehydration or dehydrogenation is performed after the oxide semiconductor film is formed. By reducing the thickness of the oxide semiconductor film, crystallization can be suppressed when heat treatment is performed after the oxide semiconductor layer is formed.

Note that before forming the oxide semiconductor film by a sputtering method, it is preferable that argon gas be introduced to generate plasma and perform reverse sputtering to remove dust attached to the surface of the gate insulating layer 102. .. The reverse sputtering is a method of applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to expose the substrate surface to plasma and modify the surface. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere.

The oxide semiconductor film is an In—Ga—Zn—O-based non-single-crystal film, In—Sn—Zn—O-based, In.
-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-
Zn-O system, In-Ga-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system
An In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film is used. In this embodiment, for example, a film is formed by a sputtering method using an In—Ga—Zn—O-based metal oxide target. For the oxide semiconductor film, an oxide semiconductor film is formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically argon) and oxygen. You can When using the sputtering method,
Dehydration or dehydration performed in a later step is performed by forming a film with a target containing SiO ₂ at 2 wt% to 10 wt% inclusive and including SiOx (X>0) which inhibits crystallization in the oxide semiconductor film. It is preferable to suppress crystallization during the heat treatment for crystallization. Note that it is preferable to use a pulsed direct-current (DC) power source as a power source because dust can be reduced and the film thickness can be uniform.

The relative density of the metal oxide in the metal oxide target is preferably 95% or more, more preferably 99% or more. Accordingly, the impurity concentration in the formed oxide semiconductor film can be reduced, and a thin film transistor with high electric characteristics or reliability can be obtained.
In this embodiment, a metal oxide target with a relative density of metal oxide of 97% is used.

As the sputtering method, there are an RF sputtering method in which a high frequency power source is used as a power source for sputtering, a DC sputtering method in which a direct current power source is used, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

There is also a multi-source sputtering apparatus in which a plurality of targets made of different materials can be set. In the multi-source sputtering apparatus, different material films can be stacked in the same chamber, or a plurality of kinds of materials can be simultaneously discharged in the same chamber to form films.

Further, there are a sputtering apparatus using a magnetron sputtering method having a magnet mechanism inside the chamber, and a sputtering apparatus using an ECR sputtering method using plasma generated by using microwaves without using glow discharge.

Further, as a film forming method using a sputtering method, a reactive sputtering method of chemically reacting a target substance and a sputtering gas component during film formation to form a thin film of these compounds, and a voltage is applied to a substrate during film formation There is also a bias sputtering method.

Alternatively, the gate insulating layer 102 and the oxide semiconductor film may be continuously formed without being exposed to the air. By forming the film without exposing it to the atmosphere, it is possible to form each stacking interface without being contaminated by atmospheric components such as water or hydrocarbons or impurity elements floating in the atmosphere. Can be reduced.

Next, the oxide semiconductor film is processed into the island-shaped oxide semiconductor layer 103 by a photolithography process (see FIG. 1A). Further, a resist mask for forming the island-shaped oxide semiconductor layer 103 may be formed by an inkjet method. When the resist mask is formed by an inkjet method, a photomask is not used, so that manufacturing cost can be reduced.

Next, first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer 103.
The temperature of the first heat treatment for dehydration or dehydrogenation is higher than or equal to 350 °C and lower than or equal to 750 °C, preferably higher than or equal to 425 °C. If the temperature is 425° C. or higher, the heat treatment time may be 1 hour or less, but if the temperature is lower than 425° C., the heat treatment time is longer than 1 hour. For example,
After the substrate is introduced into an electric furnace which is one of heat treatment apparatuses and heat treatment is performed on the oxide semiconductor layer 103 in a nitrogen atmosphere, water or oxygen for the oxide semiconductor layer 103 is not exposed to the air. It is possible to prevent re-mixing of hydrogen and obtain the oxide semiconductor layer 103. In this embodiment, the same furnace is used from a heating temperature T at which dehydration or dehydrogenation of the oxide semiconductor layer 103 is performed to a sufficient temperature at which water does not enter again. Gradually cool under a nitrogen atmosphere until the temperature drops to 100°C or more. In addition, the dehydration or dehydrogenation is not limited to the nitrogen atmosphere and is performed in an inert gas atmosphere (helium, neon, argon, or the like).

By the first heat treatment, atomic-level rearrangement of the oxide semiconductor included in the oxide semiconductor layer 103 is performed. The first heat treatment is important in that strain that blocks carrier movement in the oxide semiconductor layer 103 can be released.

Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more,
It is preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

The heat treatment device for the first heat treatment is not limited to the electric furnace, and may be provided with a device for heating the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, G
RTA (Gas Rapid Thermal Anneal) device, LRTA (Lam
p Rapid Thermal Anneal (RTA) such as a device
rmal Anneal) apparatus can be used. The LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen which does not react with an object to be processed by heat treatment is used.

The oxide semiconductor layer may be crystallized to be a microcrystalline film or a polycrystalline film depending on the condition of the first heat treatment or the material of the oxide semiconductor layer. Here, the oxide semiconductor layer might be a microcrystalline film with a crystallization rate of 80% or more. Further, depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may have no crystal.

The first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 103. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography step is performed.

Here, the hydrogen concentration analysis results with and without dehydrogenation in the oxide semiconductor layer will be described. FIG. 3A is a schematic view of the cross-sectional structure of the sample used in this analysis. The oxynitride insulating layer 401 is formed over the glass substrate 400 by a plasma CVD method, and the oxynitride insulating layer 4 is formed.
In, a In-Ga-Zn-O-based oxide semiconductor layer 402 having a thickness of approximately 40 nm was formed on the sample No. 01. The prepared sample was divided, one was not dehydrogenated, and the other was dehydrogenated by GRTA method in a nitrogen atmosphere at 650° C. for 6 minutes. For each sample, the effect of dehydrogenation by heat treatment was investigated by measuring the hydrogen concentration in the oxide semiconductor layer.

The hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS: Seconda).
The analysis was performed by ry Ion Mass Spectroscopy). FIG. 3B is a SIMS analysis result showing a hydrogen concentration distribution in the oxide semiconductor layer in the film thickness direction. The horizontal axis represents the depth from the sample surface, and the position of 0 nm depth at the left end corresponds to the sample outermost surface (the outermost surface of the oxide semiconductor layer). The analysis direction 403 shown in FIG. 3A indicates the analysis direction of SIMS analysis. The analysis was performed in the direction from the outermost surface of the oxide semiconductor layer toward the glass substrate 400. That is, the process was performed from the left end to the right end on the horizontal axis of FIG. Figure 3 (B
), the vertical axis represents the hydrogen concentration in the sample at a specific depth and the oxygen ion intensity on a logarithmic axis.

In FIG. 3B, a hydrogen concentration profile 412 shows a hydrogen concentration profile in the oxide semiconductor layer which has not been dehydrogenated, and a hydrogen concentration profile 413 is a hydrogen concentration profile after dehydrogenation by heat treatment. 5 shows a hydrogen concentration profile in an oxide semiconductor layer. The oxygen ion intensity profile 411 indicates the oxygen ion intensity acquired at the same time when the hydrogen concentration profile 412 is measured. Since the oxygen ionic strength profile 411 does not have an extreme change and a substantially constant ionic strength is obtained, it can be seen that SIMS analysis is being performed accurately. It should be noted that the oxygen ion intensity was also measured during the measurement of the hydrogen concentration profile 413, and an almost constant ion intensity was obtained here as well. The hydrogen concentration profile 412 and the hydrogen concentration profile 413 are quantified using a standard sample manufactured using the same In-Ga-Zn-O-based oxide semiconductor layer as the sample.

It is known that, in principle, SIMS analysis is difficult to accurately obtain data in the vicinity of the sample surface or in the vicinity of the interface between laminated films of different materials. In this analysis, it is considered that accurate data could not be obtained from the outermost surface of the sample to a depth of about 15 nm.
It evaluated using the profile after m.

From the hydrogen concentration profile 412, hydrogen is approximately 3×10 ²⁰ atoms/cm ³ or more and approximately 5×10 ²⁰ atoms/cm ³ or less in the oxide semiconductor layer which has not been dehydrogenated, and the average hydrogen concentration is approximately 4 or less. It can be seen that x10 ²⁰ atoms/cm ^{3 is} contained. In addition, from the hydrogen concentration profile 413, the average hydrogen concentration in the oxide semiconductor layer is about 2× due to dehydrogenation.
It can be seen that it can be reduced to 10 ¹⁹ atoms/cm ³ .

By this analysis, the hydrogen concentration could be reduced by SIMS analysis of the sample which was subjected to the heat treatment at 650° C. for 6 minutes in the nitrogen atmosphere by the GRTA method. Therefore, dehydrogenation from the oxide semiconductor layer was confirmed in this heat treatment step. did it.

Then, a second heat treatment is performed. The temperature of the second heat treatment is higher than or equal to 100° C. and lower than the temperature of the first heat treatment. For example, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the atmosphere is
Alternatively, heat treatment is performed in an oxygen atmosphere.

Next, a conductive film for forming a source electrode layer and a drain electrode layer is formed over the gate insulating layer 102 and the oxide semiconductor layer 103.

As the conductive film for forming the source electrode layer and the drain electrode layer, the gate electrode layer 101
Similarly, a metal conductive film can be used. As the material of the metal conductive film, Al, Cr,
It is preferable to use an element selected from Cu, Ta, Ti, Mo, W, an alloy containing the above-mentioned element as a component, an alloy in which the above-mentioned elements are combined, or the like. For example, a three-layer structure in which an aluminum layer is stacked over a titanium layer and a titanium layer is stacked over the aluminum layer, or a three-layer structure in which an aluminum layer is stacked over a molybdenum layer and a molybdenum layer is stacked over the aluminum layer. The structure is preferable. Of course, the metal conductive film has a single-layer structure, a two-layer structure, or four.
A laminated structure of more than one layer may be used.

A source electrode layer 105a and a drain electrode layer 105b are formed from a conductive film for forming a source electrode layer and a drain electrode layer by a photolithography process using a photomask (see FIG. 1B). At this time, part of the oxide semiconductor layer 103 is also etched, so that the oxide semiconductor layer 103 has a groove (a depression).

Note that a resist mask for forming the source electrode layer 105a and the drain electrode layer 105b may be formed by an inkjet method. When the resist mask is formed by an inkjet method, a photomask is not used, so that manufacturing cost can be reduced.

Further, an oxide conductive layer having lower resistance than the oxide semiconductor layer 103 may be formed between the oxide semiconductor layer 103 and the source electrode layer 105a and the drain electrode layer 105b. With such a stacked structure, the breakdown voltage of the thin film transistor can be improved. Specifically, the carrier concentration of the oxide conductive layer having low resistance is, for example, 1×10 ²⁰ /cm ³ or more and 1×10 ^3.
It is preferably within the range of ²¹ /cm ³ or less.

Next, the insulating layer 107 which covers the gate insulating layer 102, the oxide semiconductor layer 103, the source electrode layer 105a, and the drain electrode layer 105b and is in contact with part of the oxide semiconductor layer 103 is formed (
See FIG. 1C). The insulating layer 107 has a thickness of at least 1 nm or more and can be formed as appropriate by a method such as a CVD method or a sputtering method in which impurities such as water and hydrogen are not mixed into the insulating layer 107. Here, the insulating layer 107 is formed by a sputtering method. The insulating layer 107 formed in contact with part of the oxide semiconductor layer 103 does not contain moisture, hydrogen ions, oxygen ions, impurities such as OH ^−, or the like, and is an inorganic substance that blocks these from entering from the outside. An insulating film can be used, and typically, a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, a gallium oxide film, an aluminum oxide film, an aluminum oxynitride film, or an aluminum nitride film can be used.

The insulating layer 107 may have a structure in which a silicon nitride film or an aluminum nitride film is stacked over a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film. In particular, the silicon nitride film is preferable because it does not contain moisture, hydrogen ions, oxygen ions, or impurities such as OH ⁻ and it is easy to block these from entering from the outside.

The substrate temperature at the time of forming the insulating layer 107 may be higher than or equal to room temperature and lower than or equal to 300 °C. The silicon oxide film can be formed by a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or It can be performed under an atmosphere of a rare gas (typically argon) and oxygen. Further, a silicon oxide target or a silicon target can be used as the target.
For example, silicon oxide can be formed by a sputtering method in an oxygen atmosphere using a silicon target.

Then, a third heat treatment is performed. The third heat treatment is performed at 100° C. or higher and the temperature of the first heat treatment or lower. For example, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and heat treatment is performed in a nitrogen atmosphere. The third heat treatment may be performed at any time after the step of forming the insulating layer 107.

Through the above steps, the gate electrode layer 101 is provided over the substrate 100 which is a substrate having an insulating surface, the gate insulating layer 102 is provided over the gate electrode layer 101, and the oxide semiconductor layer is over the gate insulating layer 102. 103 is provided, and the source electrode layer 105 is provided over the oxide semiconductor layer 103.
a and the drain electrode layer 105b are provided, and the gate insulating layer 102 and the oxide semiconductor layer 103 are provided.
A channel-etch thin film transistor 150 in which an insulating layer 107 which covers the source electrode layer 105a and the drain electrode layer 105b and is in contact with part of the oxide semiconductor layer 103 is provided.
Can be formed (see FIG. 1E).

FIG. 1F is a top view of the thin film transistor 150 described in this embodiment. Figure 1 (E
) Shows the cross-sectional structure of the X1-X2 portion of FIG. In FIG. 1F, L represents the channel length and W represents the channel width. In addition, A indicates that the oxide semiconductor layer 103 is the source electrode layer 105a and the drain electrode layer 1 in a direction parallel to the channel width direction.
The length of the area that does not overlap with 05b is shown. Ls represents the length at which the source electrode layer 105a and the gate electrode layer 101 overlap, and Ld represents the drain electrode layer 105b and the gate electrode layer 10.
1 indicates the overlapping length.

In this embodiment mode, the thin film transistor 150 is described using a single-gate thin film transistor; however, a thin film transistor with a multi-gate structure having a plurality of channel formation regions or a second gate electrode layer over the insulating layer 107 is provided as needed. A thin film transistor having a structure having

Although the method for manufacturing the channel-etched thin film transistor 150 is described in this embodiment, the structure of this embodiment is not limited to this. A bottom contact type (also referred to as an inverted coplanar type) thin film transistor 160 having a bottom gate structure as shown in FIG. 2A, and a channel protection type (channel protection layer 110 having a channel protection layer 110 as shown in FIG. 2B). A thin film transistor 170 or the like (also referred to as a stop type) can be formed using a similar material and method. FIG. 2C shows another example of the channel-etch type thin film transistor. A width of the gate electrode layer 101 of the thin film transistor 180 illustrated in FIG. 2C is larger than that of the oxide semiconductor layer 103.

Note that the channel length of a thin film transistor (L in FIG. 1F) is defined by the distance between the source electrode layer 105a and the drain electrode layer 105b. It is defined by the width of the channel protective layer in the direction parallel to.

According to this embodiment, the off-state current per 1 μm in the channel width of the thin film transistor including an oxide semiconductor layer can be less than or equal to 1×10 ⁻¹² A.

In addition, the channel length of the thin film transistor is in the range of 3 μm to 10 μm, or 1.
In the range of 5 μm to 100 μm, the off-current per 1 μm of the channel width of the thin film transistor in the operating temperature range of −25° C. to 150° C. is 1×10 ⁻¹² A.
It can be: Channel length of thin film transistor is 1.5μm or more, or 3μ
A thickness of m or more is preferable because the short channel effect can be suppressed.

Here, a thin film transistor having a cross-sectional structure illustrated in FIG.
The evaluation results of the thin film transistor characteristics under the above environment will be described.

First, a tungsten layer having a thickness of 100 nm is formed as a gate electrode layer 802 over a glass substrate 801, and an oxynitride layer is formed as a gate insulating layer 803 over the gate electrode layer 802.
The oxide semiconductor layer 804 is formed to have a thickness of 0 nm, the In—Ga—Zn—O-based oxide semiconductor layer 804 is formed to have a thickness of 30 nm over the gate insulating layer 803, and the source electrode layer 805 is provided over the oxide semiconductor layer 804.
Then, a titanium layer was formed as the drain electrode layer 806 to manufacture a thin film transistor. The thin film transistor has a channel length L of 3 μm and a channel width W of 20 μm.

Next, for the thin film transistor, the substrate temperature at the time of measurement was set to -25°C, 0°C, 25°C, 50
C., 100.degree. C., and 150.degree. C., and the off-current of the thin film transistor at each substrate temperature (operating temperature) was measured. The off current characteristic is measured by measuring the voltage between the source and drain (
Hereinafter, the drain voltage or Vd was set to 10V, and the voltage between the source and the gate (hereinafter referred to as gate voltage or Vg) was set to -10V.

FIG. 4B shows the off-current measurement result obtained in this measurement. The measurement temperature on the horizontal axis represents the substrate temperature (operating temperature) at the time of measuring the off-current of the thin film transistor on a linear scale, and the vertical axis represents the off-current (Ioff) at each substrate temperature on the log scale.

In FIG. 4B, “□” in the drawing shows the off current when the amorphous silicon film is used as the semiconductor layer, and “●” in the drawing shows the off current when the oxide semiconductor film is used as the semiconductor layer. It shows off current.

From FIG. 4B, the off-state current when the amorphous silicon film is used as the semiconductor layer is
It can be seen that the off-current increases as the substrate temperature during measurement increases. It can be seen that when the oxide semiconductor film is used as the semiconductor layer, the off-state current is 1 pA, that is, 1×10 ⁻¹² A or lower, even when the substrate temperature during measurement rises.

Here, the temperature dependence of the off current (Ioff) will be considered below.

It is generally known that an off current of a thin film transistor flows due to generation of electrons and holes (hereinafter referred to as carrier generation) and recombination of electrons and holes (hereinafter referred to as carrier recombination). .. As the recombination of carriers, direct recombination in which electrons are excited from the valence band (Ev) to the conduction band (Ec) and excitation via the localized level (Et) in the band gap (Eg). There is indirect recombination done.

In the case of a semiconductor having a narrow band gap, thermal energy for exciting electrons is small, so that direct recombination and indirect recombination are likely to occur, but a band gap (E
In the case of a semiconductor having a wide g), it is assumed that direct recombination and indirect recombination are unlikely to occur because large thermal energy is required to excite electrons.

Further, when the band gap is wide, the intrinsic carrier concentration of the semiconductor is extremely low, and the total number of carriers is also extremely low. As a result of the small total number of carriers, the probability of carrier generation and carrier recombination is also reduced, and it is assumed that the off current is small.

An attempt was made to calculate the temperature dependence of the off-current of a thin film transistor in semiconductors having different band gaps (Eg).

The structure assumed in the calculation is shown in FIG. As the gate electrode layer 701, a tungsten layer having a thickness of 100 n
The gate insulating layer 702 is formed to have a thickness of m, an oxynitride layer is formed to have a thickness of 100 nm as the gate insulating layer 702, and the semiconductor layer 703 is formed to have a thickness of 30 nm on the gate insulating layer 702. Then, a thin film transistor in which the source electrode layer 704 and the drain electrode layer 705 are formed over the semiconductor layer 703 is assumed.

The size of the TFT was L/W=10/1 μm. Band gap of semiconductor Eg=1.1e
V, 1.8 eV, and 3.15 eV, and the oxide semiconductor has a bandgap Eg=3.
It is assumed to be 15 eV. Further, assuming that the electron affinity χ=4.3 eV, the source electrode layer 70
4 and the drain electrode layer 705 has a work function of 4.3 eV, which is the same as the electron affinity of the oxide semiconductor. Further, the calculation was performed under the temperature of three conditions of temperature T=25° C., 100° C., 150° C. For calculation, the device simulation software A manufactured by Silvaco
tlas was used.

In amorphous semiconductors, it is considered that the defect level has a strong influence on the temperature characteristics, and the calculation was carried out for the case where only direct recombination was assumed and the case where both direct recombination and indirect recombination were assumed. The level of indirect recombination was assumed to be in the center of the band gap. The structures assumed in the calculation are shown in FIGS. 6A and 6B. Calculations were made in two types, FIG. 6(A) assuming only direct recombination and FIG. 6(B) assuming both direct recombination and indirect recombination.

In FIGS. 6A and 6B, “Ev” indicates a valence band, “Ec” indicates a conductor, and “Et” indicates a localized level. Further, the solid line is assumed to generate carriers, and the broken line is assumed to be carrier recombination.

The calculation result is shown in FIG. 29 shows the calculation result when the band gap (Eg)=1.1 eV is assumed, and FIG. 29A shows the calculation result when only the direct recombination is assumed.
(B) is a calculation result when both direct recombination and indirect recombination are assumed.

Note that the spectrum 201 shown in FIG. 29A is 25° C., and the spectrum 202 is 100° C.
, Spectrum 203 is a calculation result when assuming 150° C., and spectrum 301 shows 25° C., spectrum 302 has 100° C., spectrum 303 has 150
This is the calculation result when assuming °C.

The calculation result is shown in FIG. 30 shows the calculation result when the band gap (Eg)=1.8 eV is assumed, and FIG. 30A shows the calculation result when only the direct recombination is assumed.
(B) is a calculation result when both direct recombination and indirect recombination are assumed.

Note that the spectrum 311 shown in FIG. 30A is 25° C. and the spectrum 312 is 100° C.
The spectrum 313 is the calculation result when 150° C. is assumed, and the spectrum 321 is 25° C., the spectrum 322 is 100° C., and the spectrum 323 is 150 in FIG. 30B.
This is the calculation result when assuming °C.

The calculation result is shown in FIG. FIG. 31 shows the calculation result when the band gap (Eg)=3.15 eV is assumed, and FIG. 31(A) shows the calculation result when only the direct recombination is assumed.
1(B) is a calculation result when both direct recombination and indirect recombination are assumed.

Note that in FIG. 31A, a spectrum 451 is 25° C. and a spectrum 452 is 100° C.
, Spectrum 453 is a calculation result when assuming 150° C., spectrum 461 is 25° C., spectrum 462 is 100° C., spectrum 463 is 150 in FIG. 31B.
This is the calculation result when assuming °C.

From FIG. 29B, assuming that the bandgap (Eg) is 1.1 eV, an off current of 1×10 ⁻¹³ A or higher was confirmed at 25° C., and 1×10 ⁻¹⁰ at 150° C. An off current of A or more has been confirmed, and it can be seen that there is temperature dependence.

When the band gap (Eg)=1.8 eV is assumed from FIG. 30(B), FIG. 29(B)
Compared with the band gap (Eg) of 1.1 eV, the off current at 25° C. is 1×10 ^−16.
An off current of 1×10 ⁻¹³ A or less was confirmed at A or lower and 150° C., which shows that there is temperature dependence.

If the band gap (Eg)=3.15 eV is assumed from FIG. 31(B), FIG.
) Band gap (Eg)=1.1 eV, and the band gap (Eg) of FIG.
)=1.8 eV, and at three calculated temperatures of 25° C., 100° C. and 150° C.,
The off current is 1×10 ⁻¹⁶ A or less, and the result has no temperature dependence.

As described above, in the case of a semiconductor having a narrow bandgap, heat energy for exciting electrons is small, so that direct recombination and indirect recombination are likely to occur, but the bandgap (Eg) is similar to that of an oxide semiconductor. In the case of a wide semiconductor, a large thermal energy is required to excite electrons, and therefore the calculation results that direct recombination and indirect recombination hardly occur have been obtained.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example in which at least part of a driver circuit and a thin film transistor arranged in a pixel portion are manufactured over the same substrate will be described below.

The thin film transistor provided in the pixel portion is formed according to Embodiment 1. In addition, since the thin film transistor described in Embodiment 1 is an n-channel TFT, part of the driver circuit which can be formed using an n-channel TFT in the driver circuit is formed over the same substrate as the thin film transistor in the pixel portion. ..

An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scan line driver circuit 5302, a second scan line driver circuit 5303, and a signal line driver circuit 5304 are provided over a substrate 5300 of a display device. In the pixel portion 5301, a plurality of signal lines are arranged so as to extend from the signal line driver circuit 5304, and a plurality of scan lines are provided in the first scan line driver circuit 5.
302 and the scan line driver circuit 5303. Pixels each having a display element are arranged in a matrix at each intersection of the scan lines and the signal lines. In addition, the substrate 5300 of the display device is an FPC (Flexible Printed Circuit).
It is connected to the timing control circuit 5305 (also referred to as a controller or a control IC) via a connection part such as t).

In FIG. 7A, the first scan line driver circuit 5302, the second scan line driver circuit 5303, and the signal line driver circuit 5304 are formed over the same substrate 5300 as the pixel portion 5301. for that reason,
Since the number of components such as a drive circuit provided outside is reduced, the cost can be reduced. In addition, when the driver circuit is provided outside the substrate 5300, the number of connections in the connection portion can be reduced by extending the wiring, so that reliability can be improved or yield can be improved.

Note that the timing control circuit 5305 supplies the first scan line driver circuit 5302 with the first scan line driver circuit start signal (GSP1) (start pulse) and the scan line driver circuit clock signal (GCK1) as an example. To supply. In addition, the timing control circuit 5305 supplies the second scan line driver circuit 5303 with, for example, a second scan line driver circuit start signal (GSP2) (also referred to as a start pulse) and a scan line driver circuit clock signal ( GCK2)
To supply. For the signal line driver circuit 5304, as an example, a signal line driver circuit start signal (SSP), a signal line driver circuit clock signal (SCK), and video signal data (DAT).
A) (also referred to as a video signal) and a latch signal (LAT) are supplied. Note that each clock signal (GCK1, GCK2, SCK) may be a plurality of clock signals having a different cycle, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that one of the first scan line driver circuit 5302 and the second scan line driver circuit 5303 can be omitted.

In FIG. 7B, a circuit with a low driving frequency (for example, the first scan line driver circuit 5302, the second scan line driver circuit
The scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver circuit 5304 is formed on a different substrate from the pixel portion 5301. With such a structure, a driver circuit formed over the substrate 5300 can be formed using a thin film transistor whose field-effect mobility is lower than that of a transistor including a single crystal semiconductor. Therefore, the size of the display device can be increased, the number of steps can be reduced, the cost can be reduced, or the yield can be improved.

Further, the thin film transistor described in Embodiment 1 is an n-channel TFT. FIG. 8(A)
In FIG. 8B, an example of the structure and operation of a signal line driver circuit including n-channel TFTs will be described.

The signal line driver circuit includes a shift register 5601 and a switching circuit portion 5602. The switching circuit portion 5602 includes a plurality of circuits called switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N are
Each includes a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number). The thin film transistors 5603_1 to 5603_k are n-channel TFTs.
Will be described.

The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k have wirings 5604_1, respectively.
Connected to ~5604_k. Second terminals of the thin film transistors 5603_1 to 5603_k are connected to the signal lines S1 to Sk, respectively. Thin film transistors 5603_1 to 5603_
The gate of k is connected to the wiring 5605_1.

The shift register 5601 sequentially outputs H-level signals (also referred to as an H signal and a high power supply potential level) to the wirings 5605_1 to 5605_N and the switching circuits 5602_1 to 5602.
02_N is selected in order.

The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk.
, A function of controlling the conduction state (conduction between the first terminal and the second terminal), that is, the wiring 5604_
It has a function of controlling whether to supply the potentials of 1 to 5604_k to the signal lines S1 to Sk.
As described above, the switching circuit 5602_1 has a function as a selector. The thin film transistors 5603_1 to 5603_N have wirings 5604_1 to 5604_k, respectively.
And a function of controlling electrical connection between the signal lines S1 to Sk, that is, wirings 5604_1 to 5604_k
Has a function of supplying the potential of 1 to the signal lines S1 to Sk. Thus, the thin film transistor 56
03_1 to 5603_N each have a function as a switch.

Note that video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal.

Next, operation of the signal line driver circuit in FIG. 8A is described with reference to a timing chart in FIG. In FIG. 8B, the signals Sout_1 to Sout_N and the signal Vda are shown.
An example of ta_1 to Vdata_k is shown. The signals Sout_1 to Sout_N are examples of output signals of the shift register 5601, and the signals Vdata_1 to Vdata_k are examples of signals input to the wirings 5604_1 to 5604_k. Note that one operation period of the signal line driver circuit corresponds to one gate selection period in the display device. As an example, one gate selection period is divided into a period T1 to a period TN. Each of the periods T1 to TN is a period for writing video signal data (DATA) to the pixels belonging to the selected row.

Note that signal waveform distortion and the like in each structure illustrated in drawings and the like in this embodiment are exaggerated for simplicity in some cases. Therefore, it should be added that the scale is not necessarily limited to this.

In the periods T1 to TN, the shift register 5601 transmits an H-level signal to the wiring 560.
It outputs to 5_1-5605_N in order. For example, in the period T1, the shift register 5
601 outputs a high-level signal to the wiring 5605_1. Then, the thin film transistors 5603_1 to 5603_k are turned on, so that the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are brought into conduction. At this time, the wirings 5604_1 to 5604_k have
Data(S1) to Data(Sk) are input. Data(S1) to Data(Sk
) Are written to the pixels in the first column to the k-th column among the pixels belonging to the selected row through the thin film transistors 5603_1 to 5603_k, respectively. Thus, in the periods T1 to TN, the video signal data (DATA) is sequentially written to the pixels in the selected row by k columns.

As described above, the number of video signal data (DATA) or the number of wirings can be reduced by writing the video signal data (DATA) into the pixels by a plurality of columns.
Therefore, the number of connections with external circuits can be reduced. In addition, by writing the video signal to the pixels for each of a plurality of columns, writing time can be extended and insufficient writing of the video signal can be prevented.

Note that as the shift register 5601 and the switching circuit portion 5602, Embodiment 1 is used.
A circuit including the thin film transistor shown in can be used. In this case, the polarities of all the transistors included in the shift register 5601 can be n-channel type.

Next, the configuration of the scanning line drive circuit will be described. The scan line driver circuit includes a shift register and a buffer. Further, in some cases, it may have a level shifter. In the scan line driver circuit, the shift register has a clock signal (CK) and a start pulse signal (SP).
Is input, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. Gate electrodes of transistors of pixels for one line are connected to the scanning lines. Since the transistors of the pixels for one line must be turned on all at once, a buffer capable of passing a large current is used.

One mode of the shift register used for part of the scan line driver circuit and/or the signal line driver circuit will be described with reference to FIGS.

Shift registers of the scan line driver circuit and the signal line driver circuit will be described with reference to FIGS. The shift register includes the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 9A). The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register illustrated in FIG.
A first clock signal CK1 from the first wiring 11, a second clock signal CK2 from the second wiring 12, a third clock signal CK3 from the third wiring 13, and a fourth clock signal from the fourth wiring 14. CK4 is supplied. In the first pulse output circuit 10_1, the fifth wiring 15
The start pulse SP1 (first start pulse) from is input. Further, in the second and subsequent n-th pulse output circuits 10_n (n is a natural number of 2 or more and N or less), the signal from the pulse output circuit of the preceding stage (referred to as the preceding stage signal OUT(n-1)) (n is 2 The above natural numbers) are input. Further, in the first pulse output circuit 10_1, the third pulse output circuit 10 in the second stage after the second stage
_3 or the signal from the (n+2)th pulse output circuit 10_n+2 of the second stage and the subsequent stage (referred to as the latter stage signal OUT(n+2)) is input to the nth pulse output circuit 10_n of the second and subsequent stages. Further, from the pulse output circuit of each stage, a first output signal OUT(1) (SR) for input to the pulse output circuit of the preceding stage and/or the subsequent stage, and a second output signal OUT(1 ) Is output. As shown in FIG. 9A, since the latter stage signal OUT(n+2) is not input to the final two stages of the shift register, as an example, the second start pulse SP2 and the third start pulse SP2 are separately provided. The configuration may be such that each start pulse SP3 is input.

Note that the clock signal (CK) is a signal that repeats H level and L level (also referred to as L signal or low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1/4 cycle. In this embodiment mode, driving control of the pulse output circuit and the like are performed using the first clock signal (CK1) to the fourth clock signal (CK4). The clock signal is GCK depending on the input drive circuit.
, SCK, but will be described as CK here.

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11
~ It is electrically connected to any of the fourth wirings 14. For example, in FIG. 9(B),
In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third The input terminal 23 is electrically connected to the third wiring 13. In the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, The third input terminal 23 is electrically connected to the fourth wiring 14.

Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, and a fifth input terminal 21. It has an input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 9B). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third input terminal 23 is input. The third clock signal CK3 is input, the start pulse SP1 is input to the fourth input terminal 24, the rear-stage signal OUT(3) is input to the fifth input terminal 25, and the first output terminal 26 outputs the first signal. Output signal OUT(1)(SR) of the second output terminal 27
Therefore, the second output signal OUT(1) is output.

Note that as the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N, a four-terminal thin film transistor can be used as well as a three-terminal thin film transistor. A transistor 28 illustrated in FIG. 9C means the 4-terminal thin film transistor described in Embodiment 1 and
It will be used below in the drawings and the like. The transistor 28 receives the In signal according to the first control signal G1 input to the first gate electrode and the second control signal G2 input to the second gate electrode.
It is an element that can perform electrical control between the terminal and the Out terminal.

For the threshold voltage of the transistor 28 illustrated in FIG. 9C, a gate electrode is provided above and below a channel formation region of the transistor 28 with a gate insulating film interposed therebetween to control the potential of the upper and/or lower gate electrodes. Can be controlled to a desired value.

Next, an example of a specific circuit structure of the pulse output circuit will be described with reference to FIG.

The first pulse output circuit 10_1 includes the first transistor 31 to the thirteenth transistor 4
3 (see FIG. 9D). In addition to the above-described first input terminal 21 to fifth input terminal 25, the first output terminal 26, and the second output terminal 27, the first high power supply potential VDD
From the power supply line 51 to which the second high power supply potential VCC is supplied and the power supply line 53 to which the low power supply potential VSS is supplied, the first transistor 31 to the thirteenth transistor 4
A signal or power supply potential is supplied to 3. Here, the magnitude relation of the power supply potentials of the power supply lines in FIG. 9D is as follows: first power supply potential VDD>second power supply potential VCC>third power supply potential VSS.
Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals in which the H level and the L level are repeated at regular intervals, and VDD at the H level and V at the L level.
Assume SS. Note that by setting the potential VCC of the power supply line 52 lower than the potential VDD of the power supply line 51, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, and the threshold voltage of the transistor can be reduced. Can be reduced and deterioration can be suppressed. Note that as illustrated in FIG. 9D, the first transistor 31, the sixth transistor 36 to the ninth transistor 39 among the first transistor 31 to the thirteenth transistor 43 have the same structure as in FIG. It is preferable to use the four-terminal transistor 28 shown in FIG. The operation of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 is required to switch the potential of the node to which one of the source and drain electrodes is connected by a control signal of the gate electrode. The transistor is capable of further reducing malfunctions of the pulse output circuit because the response to the control signal input to the gate electrode is fast (the on-current rises steeply). Therefore, the threshold voltage can be controlled by using the four-terminal transistor 28 illustrated in FIG. 9C, so that a pulse output circuit in which malfunction can be further reduced can be provided. Note that in FIG. 9C, the first
Although the control signal G1 and the second control signal G2 are the same control signal, different control signals may be input.

In FIG. 9D, the first terminal of the first transistor 31 is electrically connected to the power supply line 51, the second terminal of the first transistor 31 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (
The first gate electrode and the second gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the first terminal of the ninth transistor 39, and a gate electrode of the fourth transistor 34. It is electrically connected to the gate electrode. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the gate electrode of the second transistor 32 and a gate electrode of the fourth transistor 34, and a gate The electrode is electrically connected to the fourth input terminal 24. In the sixth transistor 36, the first terminal has the power supply line 5
2 and a second terminal electrically connected to a gate electrode of the second transistor 32 and a gate electrode of the fourth transistor 34, and a gate electrode (first gate electrode and second gate electrode).
Gate electrode) is electrically connected to the fifth input terminal 25. 7th transistor 3
7, the first terminal is electrically connected to the power supply line 52, the second terminal is electrically connected to the second terminal of the eighth transistor 38, and the gate electrode (first gate electrode and second gate The electrode) is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and has a gate electrode (first gate electrode and second gate electrode). Is the second input terminal 2
2 is electrically connected. A ninth terminal of the ninth transistor 39 is electrically connected to a second terminal of the first transistor 31 and a second terminal of the second transistor 32, and a second terminal of the ninth transistor 39 is a gate electrode of the third transistor 33. The tenth transistor 40 is electrically connected to the gate electrode, and the gate electrodes (the first gate electrode and the second gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal that is the first input terminal 21.
, The second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. Eleventh transistor 4
1, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is the gate electrode of the second transistor 32 and the fourth transistor. It is electrically connected to the gate electrode of 34. The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53, a second terminal electrically connected to the second output terminal 27,
The gate electrode is electrically connected to the gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37. The thirteenth transistor 43 has a first terminal which is a power line 53.
Electrically, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode (first gate electrode and second gate electrode) of the seventh transistor 37. Connected to each other.

In FIG. 9D, the gate electrode of the third transistor 33 and the tenth transistor 4
A connection point between the gate electrode of 0 and the second terminal of the ninth transistor 39 is referred to as a node A.
In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, A connection point between the gate electrode of the eleventh transistor 41 and the gate electrode is a node B (see FIG. 10A).

The thin film transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region,
A current can flow through the drain region, the channel region, and the source region. here,
Since the source and the drain are changed depending on the structure of the thin film transistor, operating conditions, and the like, it is difficult to determine which is the source or the drain. Therefore, a region functioning as a source and a drain may not be called a source or a drain. In that case, as an example, they may be referred to as a first terminal and a second terminal, respectively.

Note that in FIGS. 9D and 10A, a capacitor for performing a bootstrap operation by bringing the node A into a floating state may be additionally provided. In addition, in order to hold the potential of the node B, a capacitor in which one electrode is electrically connected to the node B may be provided separately.

Here, FIG. 10B is a timing chart of a shift register including a plurality of pulse output circuits illustrated in FIG. Note that when the shift register is a scan line driver circuit, a period 61 in FIG. 10B is a vertical blanking period and a period 62 is a gate selection period.

As shown in FIG. 10A, by providing the ninth transistor 39 to the gate of which the second power supply potential VCC is applied, the following advantages are obtained before and after the bootstrap operation. ..

In the case where the ninth transistor 39 to which the second potential VCC is applied to the gate electrode is not provided, the potential of the source that is the second terminal of the first transistor 31 rises when the potential of the node A rises due to the bootstrap operation. Then, it becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, which causes a large stress, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, the potential of the node A rises by the bootstrap operation, but the second terminal of the first transistor 31 It is possible to prevent a rise in potential. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced, so that the first bias due to stress can be reduced.
The deterioration of the transistor 31 can be suppressed.

Note that the second transistor of the first transistor 31 is provided in the second transistor of the first transistor 31.
Any configuration may be used as long as it is provided between the terminal and the gate of the third transistor 33 via the first terminal and the second terminal. Note that in the case of a shift register including a plurality of pulse output circuits in this embodiment, the ninth transistor 39 may be omitted in a signal line driver circuit having more stages than the scan line driver circuit, so that the number of transistors is reduced. That is an advantage.

Note that by using an oxide semiconductor for the semiconductor layers of the first to thirteenth transistors 31 to 43, off-state current of the thin film transistor can be reduced and on-state current and field-effect mobility can be increased, and the degree of deterioration can be high. Therefore, malfunctions in the circuit can be reduced. In addition, a transistor including an oxide semiconductor is less deteriorated by a high potential applied to its gate electrode than a transistor including amorphous silicon. Therefore, the same operation can be obtained even when the first power supply potential VDD is supplied to the power supply line which supplies the second power supply potential VCC, and the number of power supply lines which lead between the circuits can be reduced. The circuit can be miniaturized.

Note that the gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode)
The clock signal supplied by the third input terminal 23, and the clock signal supplied by the second input terminal 22 to the gate electrodes (first gate electrode and second gate electrode) of the eighth transistor 38, Gate electrode of the seventh transistor 37 (first gate electrode and second gate electrode
To the second input terminal 22 and the third input terminal 23 to the gate electrodes (first and second gate electrodes) of the eighth transistor 38.
Even if the connection relations are switched so that the clock signal is supplied by the above, the same operation is achieved. Note that in the shift register illustrated in FIG. 10A, the seventh transistor 37 and the eighth transistor 38 are both turned on, the seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. By turning off the seventh transistor 37 and turning off the eighth transistor 38, the second input terminal 22 and the third input terminal 23 are turned on.
The decrease in the potential of the node B, which occurs due to the decrease in the potential of the second transistor, occurs twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease of the potential of the gate electrode of the eighth transistor 38. Becomes On the other hand, in the shift register shown in FIG. 10A, the seventh transistor 37 and the eighth transistor 38 are both turned on as in the period of FIG. 10B.
The seventh transistor 37 is turned on, the eighth transistor 38 is turned off, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, whereby the second input terminal 22 and the second transistor 38 are turned off. The decrease in the potential of the node B caused by the decrease in the potential of the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 (the first gate electrode and the second electrode
Clock signal supplied by the third input terminal to the gate electrode of the eighth transistor 38, and the clock signal supplied by the second input terminal to the gate electrodes of the eighth transistor 38 (the first gate electrode and the second gate electrode). By setting the above, the fluctuation of the potential of the node B can be reduced, so that noise can be reduced, which is preferable.

As described above, the configuration is such that the signal of H level is regularly supplied to the node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at L level. A malfunction of the circuit can be suppressed.

By manufacturing the thin film transistor of the driver circuit by using the method for manufacturing the thin film transistor described in Embodiment 1, high speed operation of the thin film transistor of the driver circuit portion can be realized and power saving can be achieved.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, the case where a thin film transistor is manufactured and the thin film transistor is used for a pixel portion and a driver circuit to manufacture a semiconductor device having a display function (also referred to as a display device) will be described. Further, by using a thin film transistor, part or all of a driver circuit can be formed over the same substrate as a pixel portion, whereby a system-on-panel can be formed.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. A light-emitting element includes an element whose luminance is controlled by current or voltage in its category, and specifically, an inorganic EL (Electror).
Luminescence), organic EL, etc. are included. Further, a display medium whose contrast is changed by an electric action, such as electronic ink, can be applied.

Further, the display device includes a panel in which a display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel. Further, in the display device, an element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device is
Each of the plurality of pixels is provided with means for supplying an electric current to the display element. Specifically, the element substrate may be in a state in which only the pixel electrode of the display element is formed, or after the conductive film to be the pixel electrode is formed, the element substrate is etched to form the pixel electrode. It can be in the previous state, and all forms apply.

Note that a display device in this specification means an image display device or a light source (including a lighting device). In addition, a connector such as an FPC (Flexible printed c
module or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) attached module, a module provided with a printed wiring board in front of the TAB tape or TCP, or a COG (Chip On Glass) method for the display element. Therefore, all the modules in which an IC (integrated circuit) is directly mounted are included in the display device.

In this embodiment, an example of a liquid crystal display device is shown as a semiconductor device which is one embodiment of the present invention. First, an appearance and a cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIGS. FIG. 11 shows highly reliable thin film transistors 4010 and 4011 each including a In—Ga—Zn—O-based non-single-crystal film formed over a first substrate 4001 as a semiconductor layer, a liquid crystal element 4013, and a second substrate. 4006 and sealed by a sealant 4005,
FIG. 11B is a top view of the panel, and FIG. 11B corresponds to a cross-sectional view taken along line MN of FIGS. 11A1 and 11A2.

A sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are included in the first substrate 4001, the sealant 4005, and the second substrate 4006.
And are sealed together with the liquid crystal layer 4008. In addition, a signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted over a separately prepared substrate in a region different from a region surrounded by the sealant 4005 over the first substrate 4001. Has been done.

Note that a connection method of a driver circuit which is separately formed is not particularly limited and a COG method,
A wire bonding method, a TAB method, or the like can be used. Figure 11 (A1)
Is an example of mounting the signal line driver circuit 4003 by a COG method, and FIG.
In this example, the signal line driver circuit 4003 is mounted by the TAB method.

The pixel portion 4002 and the scan line driver circuit 4004 which are provided over the first substrate 4001 each include a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4010 included in the pixel portion 4002 and a scan line are included. Thin film transistor 401 included in line driving circuit 4004
1 is illustrated. Insulating layers 4020, 40 are formed on the thin film transistors 4010, 4011.
21 is provided.

As the thin film transistors 4010 and 4011, the highly reliable thin film transistor including the oxide semiconductor layer described in Embodiment 1 can be applied. In this embodiment mode, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

A conductive layer 4040 is provided over the insulating layer 4021 at a position overlapping with a channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driver circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. Also,
The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011 or a different potential, and can function as a second gate electrode layer. In addition, the conductive layer 4
The potential of 040 may be GND, 0V, or in a floating state.

The pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40.
It is formed on 06. A portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap with each other corresponds to a liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with an insulating layer 4032 and an insulating layer 4033 which function as alignment films, and the liquid crystal layer 4008 is sandwiched with the insulating layer 4032 and the insulating layer 4033 interposed therebetween.

Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, FRP (Fiberglass-Reinforced Plastics) plate, PV
An F (polyvinyl fluoride) film, a polyester film or an acrylic resin film can be used. Alternatively, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. .. A spherical spacer may be used. In addition, the counter electrode layer 4
031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. By using the common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected to each other through the conductive particles arranged between the pair of substrates. Note that the conductive particles are included in the sealant 4005.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which 5 wt% or more of a chiral agent is mixed is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has small viewing angle dependence.

Note that the liquid crystal display device described in this embodiment is an example of a transmissive liquid crystal display device, but the liquid crystal display device can be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

In addition, in the liquid crystal display device described in this embodiment, an example in which a polarizing plate is provided on the outer side (viewing side) of a substrate and a coloring layer and an electrode layer used for a display element are provided on the inner side in this order is shown. It may be provided inside. The laminated structure of the polarizing plate and the coloring layer is not limited to that in this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing steps. Further, a light-shielding film functioning as a black matrix may be provided if necessary.

In addition, in this embodiment mode, in order to reduce surface unevenness of the thin film transistor and to improve reliability of the thin film transistor, an insulating layer functioning as a protective film or a planarization insulating film (insulating layer 4020, insulating layer 4021). It is configured to be covered with. Note that the protective film is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the air, and is preferably a dense film. The protective film is a silicon oxide film, which is formed by a sputtering method.
The silicon nitride film, the silicon oxynitride film, the silicon nitride oxide film, the aluminum oxide film, the aluminum nitride film, the aluminum oxynitride film, or the aluminum nitride oxide film may be formed as a single layer or a stacked layer. In this embodiment mode, an example in which the protective film is formed by a sputtering method is shown; however, it is not particularly limited and various methods may be used.

Here, the insulating layer 4020 having a stacked structure is formed as a protective film. Here, the insulating layer 402
As the first layer of 0, a silicon oxide film is formed by the sputtering method. The use of the silicon oxide film as the protective film is effective in preventing hillocks in the aluminum film used as the source electrode layer and the drain electrode layer.

Further, an insulating layer is formed as the second layer of the protective film. Here, as the second layer of the insulating layer 4020, a silicon nitride film is formed by a sputtering method. When a silicon nitride film is used as the protective film, it is possible to prevent ions such as sodium from entering the semiconductor region and changing the electrical characteristics of the TFT.

Further, the semiconductor layer may be annealed (300° C. to 400° C.) after forming the protective film.

Further, the insulating layer 4021 is formed as the planarization insulating film. As the insulating layer 4021, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials)
, Siloxane resin, PSG (phosphorus glass), BPSG (phosphorus glass), or the like can be used. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed of these materials.

Note that a siloxane-based resin is a Si-OS containing a siloxane-based material as a starting material.
Corresponds to a resin containing i-bonds. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.

The method for forming the insulating layer 4021 is not particularly limited and may be a sputtering method or S depending on the material.
The OG method, spin coating, dip, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, the semiconductor layer may be annealed (300° C. to 400° C.) at the same time as the baking step. The semiconductor device can be efficiently manufactured by performing the baking step of the insulating layer 4021 and the annealing of the semiconductor layer.

The pixel electrode layer 4030 and the counter electrode layer 4031 are formed of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide,
Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO),
A light-transmitting conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10000 Ω/□ or less and a light transmittance of 7 at a wavelength of 550 nm.
It is preferably 0% or more. In addition, the resistivity of the conductive high molecule contained in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples thereof include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds of them.

In addition, a signal line driver circuit 4003 which is separately formed, a scan line driver circuit 4004, or a pixel portion 4
Various signals and potentials given to 002 are supplied from the FPC 4018.

In this embodiment mode, the connection terminal electrode 4015 is the pixel electrode layer 40 included in the liquid crystal element 4013.
It is formed of the same conductive film as 30, and the terminal electrode 4016 is formed of thin film transistors 4010, 40
The source electrode layer and the drain electrode layer 11 are formed of the same conductive film.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

11 illustrates an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 12 shows an example in which a TFT substrate 2600 is used for a liquid crystal display module corresponding to one mode of a semiconductor device.

FIG. 12 illustrates an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed to each other with a sealant 2602, a pixel portion 2603 including a TFT and the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, a polarizing plate between them. 2606 is provided to form a display area. The coloring layer 2605 is necessary when performing color display, and in the case of the RGB method, red, green,
A colored layer corresponding to each color of blue is provided corresponding to each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflection plate 2611. The circuit board 2612 is connected to the wiring circuit section 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and an external circuit such as a control circuit and a power supply circuit is incorporated. There is. Also with a polarizing plate,
You may laminate|stack with the state which has a retardation plate with a liquid crystal layer.

The liquid crystal display module has a TN (Twisted Nematic) mode, an IPS (I
n-Plane-Switching mode, FFS (Fringe Field S)
Witching) mode, MVA (Multi-domain Vertical A)
light mode), PVA (Patterned Vertical Alig)
Nent), ASM (Axially Symmetric aligned Mic)
ro-cell) mode, OCB (Optical Compensated Bire)
fringence) mode, FLC (Ferroelectric Liquid C)
Rystal mode, AFLC (Anti Ferroelectric Liquid)
Crystal mode or the like can be used.

Through the above steps, a highly reliable liquid crystal display device as a semiconductor device can be manufactured.

By manufacturing a thin film transistor in a pixel portion of a liquid crystal display device using the thin film transistor described in Embodiment 1, an increase in power consumption due to variation in off current of the thin film transistor in each pixel can be suppressed.

In addition, by manufacturing a thin film transistor in a driver circuit of a liquid crystal display device by using the method for manufacturing a thin film transistor described in Embodiment 1, high speed operation of the thin film transistor in the driver circuit portion can be realized and power saving can be achieved.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 4)
An example of electronic paper is shown as one mode of a semiconductor device.

The thin film transistor of Embodiment 1 may be used for electronic paper that drives electronic ink by using an element electrically connected to a switching element. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of readability similar to paper, lower power consumption than other display devices, and a thin and light shape. ing.

The electrophoretic display may have various morphologies, and is a plurality of microcapsules containing a first particle having a positive charge and a second particle having a negative charge dispersed in a solvent or a solute. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and do not move in the absence of an electric field. The color of the first particles and the color of the second particles are different (including colorless).

Thus, in an electrophoretic display, a substance having a high dielectric constant moves to a high electric field region,
It is a display utilizing the so-called dielectrophoretic effect.

A dispersion of the above-mentioned microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surface of glass, plastic, cloth, paper and the like. Color display is also possible by using a color filter or particles having a pigment.

Further, by arranging a plurality of the above-mentioned microcapsules on the active matrix substrate so as to be sandwiched between two electrodes, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. it can. For example, the active matrix substrate obtained by the thin film transistor of Embodiment 1 can be used.

The first particles and the second particles in the microcapsules are a conductor material, an insulator material,
A kind of material selected from a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof may be used.

FIG. 13 illustrates active matrix electronic paper as an example of a semiconductor device. A thin film transistor 581 used for the semiconductor device can be manufactured in a manner similar to that of the thin film transistor described in Embodiment 1 and is a highly reliable thin film transistor including an oxide semiconductor layer.

The electronic paper in FIG. 13 is an example of a display device using a twisting ball display system. The twisted ball display system is a method in which spherical particles coated in white and black are arranged between a first electrode layer and a second electrode layer, which are electrode layers used in a display element, and the first electrode layer and the second electrode layer are used. This is a method of displaying by controlling the orientation of spherical particles by generating a potential difference in the second electrode layer.

The thin film transistor 581 is a bottom-gate thin film transistor and is covered with an insulating film 583 which is in contact with the semiconductor layer. The source electrode layer or the drain electrode layer of the thin film transistor 581 is in contact with and electrically connected to the first electrode layer 587 through an opening formed in the insulating layer 585. A spherical particle 58 having a black region 590a and a white region 590b between the first electrode layer 587 and the second electrode layer 588, and including a cavity 594 filled with a liquid around.
9 is provided, and the periphery of the spherical particle 589 is filled with a filler 595 such as resin (
(See FIG. 13). The first electrode layer 587 corresponds to a pixel electrode and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 581. By using the common connection portion, the second electrode layer 588 and the common potential line can be electrically connected to each other through the conductive particles provided between the pair of substrates.

It is also possible to use an electrophoretic element instead of the twist ball. Diameter 10 μm to 20 in which transparent liquid, positively charged white fine particles and negatively charged black fine particles are enclosed
A microcapsule of about 0 μm is used. The microcapsules provided between the first electrode layer and the second electrode layer are such that, when an electric field is applied by the first electrode layer and the second electrode layer, white fine particles and black fine particles are in opposite directions. You can go to and see white or black. A display element to which this principle is applied is an electrophoretic display element and is generally called electronic paper. Since the electrophoretic display element has higher reflectance than a liquid crystal display element, an auxiliary light is unnecessary, power consumption is low, and the display portion can be recognized even in a dim place. In addition, even when power is not supplied to the display portion, an image that has been displayed once can be held, so that a semiconductor device with a display function (simply a display device or a semiconductor device including a display device) can be transmitted from a radio wave transmission source. It is possible to save the displayed image even when the device is called away).

Through the above steps, highly reliable electronic paper as a semiconductor device can be manufactured.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 5)
An example of a light emitting display device is shown as a semiconductor device. As a display element included in the display device, a light-emitting element utilizing electroluminescence is used here. A light-emitting element utilizing electroluminescence is distinguished depending on whether a light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, when a voltage is applied to the light emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light emitting organic compound, and a current flows. When the carriers (electrons and holes) are recombined, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light emitting element is called a current excitation type light emitting element.

The inorganic EL element is classified into a dispersion type inorganic EL element and a thin film type inorganic EL element depending on the element structure. The dispersion-type inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a light emitting layer sandwiched between dielectric layers,
Furthermore, it has a structure in which it is sandwiched by electrodes, and the light emission mechanism is localized light emission that utilizes the core electron transition of metal ions. Note that, here, an organic EL element is used as a light emitting element for description.

FIG. 14 is a diagram illustrating an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device.

A pixel configuration to which digital time grayscale driving can be applied and a pixel operation will be described. Here, an example is shown in which two n-channel transistors each including an oxide semiconductor layer for a channel formation region are used for one pixel.

The pixel 6400 includes a switching transistor 6401, a driving transistor 6402,
The light emitting element 6404 and the capacitor 6403 are included. Switching transistor 64
In 01, the gate is connected to the scan line 6406, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is the gate of the driving transistor 6402. It is connected to the. The driving transistor 6402 is
The gate is connected to the power supply line 6407 through the capacitor 6403, and the first electrode is connected to the power supply line 640.
7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404.
The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a potential satisfying the low power supply potential<high power supply potential with reference to the high power supply potential set in the power supply line 6407, and the low power supply potential is set to, for example, GND or 0V. Is also good. The potential difference between the high power source potential and the low power source potential is applied to the light emitting element 6404, and a current is passed through the light emitting element 6404 to cause the light emitting element 6404 to emit light. The respective potentials are set so as to be equal to or higher than the forward threshold voltage of.

Note that the capacitor 6403 can be omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 may be formed between the channel region and the gate electrode.

Here, in the case of the voltage input voltage driving method, the gate of the driving transistor 6402 is
A video signal is input so that the driving transistor 6402 is sufficiently turned on or turned off. That is, the driving transistor 6402 operates in the linear region.
Since the driving transistor 6402 operates in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that the signal line 6405 has
A voltage of (power line voltage+Vth of driving transistor 6402) or more is applied.

When analog gray scale driving is performed instead of digital time gray scale driving, the same pixel configuration as that in FIG. 14 can be used by changing a signal input method.

When analog grayscale driving is performed, the light emitting element 6404 is provided at the gate of the driving transistor 6402.
Forward voltage+voltage equal to or higher than Vth of the driving transistor 6402 are applied. Light emitting element 64
The forward voltage 04 indicates a voltage for obtaining a desired brightness, and includes at least a forward threshold voltage. Note that a current can be supplied to the light-emitting element 6404 by inputting a video signal such that the driving transistor 6402 operates in a saturation region. The potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402 in order to operate the driving transistor 6402 in the saturation region. When the video signal is analog, a current corresponding to the video signal can be supplied to the light-emitting element 6404 to perform analog grayscale driving.

Note that the pixel structure illustrated in FIG. 14 is not limited to this. For example, a switch, a resistance element, a capacitance element, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

Next, the structure of the light emitting element will be described with reference to FIG. Here, the driving TFT is n
The cross-sectional structure of a pixel will be described by taking the case of a mold as an example. TFTs 7001, 7011, and 7021 that are driving TFTs used for the light-emitting elements in FIGS. 15A, 15B, and 15C can be manufactured in a manner similar to that of the thin film transistor described in Embodiment 1 and reliability including an oxide semiconductor layer. It is a thin film transistor with high efficiency.

In order to take out light emission, at least one of the anode and the cathode of the light emitting element may be transparent. Then, a thin film transistor and a light-emitting element are formed over the substrate, and top emission that emits light from the surface opposite to the substrate, bottom emission that emits light from the surface on the substrate side, and surface opposite to the substrate and the substrate There is a light-emitting element having a dual emission structure that emits light from the pixel, and the pixel structure can be applied to any light-emitting element having an emission structure.

A light-emitting element having a bottom emission structure will be described with reference to FIG.

A cross-sectional view of a pixel in the case where the driving TFT 7011 is an n-type and light emitted from the EL layer 7014 is emitted to the cathode 7013 side is shown. In FIG. 15A, a cathode 7013 of a light emitting element 7012 is formed over a light-transmitting conductive film 7017 which is electrically connected to a driving TFT 7011, and an EL layer 7014 and an anode 7015 are formed over the cathode 7013. Are sequentially stacked.
Note that the light-transmitting conductive film 7017 is electrically connected to the drain electrode layer of the driving TFT 7011 through a contact hole formed in the oxide insulating layer 7031.

As the light-transmitting conductive film 7017, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide ( Hereinafter, a light-transmitting conductive film such as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

Although various materials can be used for the cathode 7013, a material having a low work function, for example, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr, and In addition to alloys containing these (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferable. In FIG. 15A, the thickness of the cathode 7013 is set so that light can be transmitted (preferably about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013.

Note that the light-transmitting conductive film 7017 and the cathode 7013 may be formed by stacking a light-transmitting conductive film and an aluminum film, and in this case, the same mask is used. It is preferable that it can be etched.

Further, the peripheral portion of the cathode 7013 is covered with a partition 7019. The partition 7019 is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. The partition 7019 is preferably formed using a photosensitive resin material, in which an opening is formed over the cathode 7013 and the side wall of the opening is an inclined surface having a continuous curvature. When a photosensitive resin material is used for the partition 7019, the step of forming a resist mask can be omitted.

Further, the EL layer 7014 formed over the cathode 7013 and the partition 7019 may be either a single layer or a plurality of layers stacked. EL layer 70
When 14 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the cathode 7013. Note that it is not necessary to provide all these layers.

Further, the stacking order is not limited, and the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, and the electron injecting layer may be stacked in this order on the cathode 7013. However, when comparing power consumption, it is preferable to stack an electron injecting layer, an electron transporting layer, a light emitting layer, a hole transporting layer, and a hole injecting layer over the cathode 7013 in order to reduce power consumption.

Although various materials can be used for the anode 7015 formed over the EL layer 7014, materials having a high work function, for example, titanium nitride, ZrN, Ti, W, Ni, Pt,
A transparent conductive material such as Cr, ITO, IZO (indium oxide zinc oxide), ZnO or the like is preferable. Further, a shielding film 7016, for example, a metal that blocks light, a metal that reflects light, or the like is formed over the anode 7015. In this embodiment mode, an ITO film is used as the anode 7015 and a Ti film is used as the shielding film 7016.

A region in which at least the EL layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light emitting element 7012. In the case of the element structure shown in FIG. 15A, light emitted from the light emitting element 7012 is emitted to the cathode 7013 side as indicated by an arrow.

Note that FIG. 15A illustrates an example in which a light-transmitting conductive film is used as a gate electrode layer, and light emitted from the light-emitting element 7012 passes through the color filter layer 7033 and is a driving TFT TFT11. And is ejected through the gate electrode layer and the source electrode layer. TF
The aperture ratio can be improved by using a light-transmitting conductive film for the gate electrode layer and the source electrode layer of T7011.

The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

The color filter layer 7033 is covered with the overcoat layer 7034, and the insulating layer 7
Cover with 035. Although the overcoat layer 7034 is illustrated with a small thickness in FIG. 15A, the overcoat layer 7034 has a function of flattening unevenness due to the color filter layer 7033.

Further, a contact hole which is formed in the insulating layer 7035 and reaches the drain electrode layer is
It is arranged at a position overlapping with the partition 7019. In FIG. 15A, a layout in which the contact hole reaching the drain electrode layer and the partition 7019 are overlapped with each other can improve the aperture ratio.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG.

In FIG. 15B, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 which is electrically connected to a TFT 7021 which is a driving TFT.
23, an EL layer 7024 and an anode 7025 are sequentially stacked. Note that the light-transmitting conductive film 7027 is provided in the TFT 70 through a contact hole formed in the oxide insulating layer 7041.
21 is electrically connected to the drain electrode layer.

As the light-transmitting conductive film 7027, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide ( Hereinafter, a light-transmitting conductive film such as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

Although various materials can be used for the cathode 7023, a material having a low work function, for example, an alkali metal such as Li or Cs, an alkaline earth metal such as Mg, Ca, or Sr, and In addition to alloys containing these (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferable. In this embodiment, the thickness of the cathode 7023 is set so that light can be transmitted (preferably about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the cathode 7023.

Note that the light-transmitting conductive film 7027 and the cathode 7023 may be formed by stacking a light-transmitting conductive film and an aluminum film by stacking, and in this case, the same mask is used. It is preferable that it can be etched.

In addition, the peripheral portion of the cathode 7023 is covered with a partition 7029. The partition 7029 is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. The partition 7029 is preferably formed using a photosensitive resin material, in which an opening is formed over the cathode 7023, and a sidewall of the opening is an inclined surface having a continuous curvature. When a photosensitive resin material is used for the partition 7029, the step of forming a resist mask can be omitted.

In addition, the EL layer 7024 formed over the cathode 7023 and the partition 7029 may be either a single layer or a plurality of layers stacked. EL layer 70
When 24 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7023. Note that it is not necessary to provide all these layers.

Further, the stacking order is not limited, and the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, and the electron injecting layer may be stacked in this order on the cathode 7023. However, when comparing the power consumption, it is preferable to stack the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer on the cathode 7023 in order because the power consumption is low.

Although various materials can be used for the anode 7025 formed over the EL layer 7024, a material having a high work function, for example, a transparent conductive material such as ITO, IZO, or ZnO is preferable. In this embodiment, an ITO film containing silicon oxide is used as the anode 7026.

A region sandwiching the EL layer 7024 between the cathode 7023 and the anode 7025 is a light emitting element 7022.
Equivalent to. In the case of the element structure illustrated in FIG. 15B, light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by arrows.

Note that FIG. 15B illustrates an example in which a light-transmitting conductive film is used as a gate electrode layer, and light emitted from the light-emitting element 7022 to the cathode 7023 side is a color filter layer 7043.
And is emitted through the gate electrode layer and the source electrode layer of the TFT 7021. TFT
By using a light-transmitting conductive film for the gate electrode layer and the source electrode layer of 7021, the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side can be substantially equal to each other.

The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

The color filter layer 7043 is covered with the overcoat layer 7044, and the insulating layer 7
Cover with 045.

Further, a contact hole which is formed in the insulating layer 7045 and reaches the drain electrode layer is
It is arranged at a position overlapping with the partition 7029. By arranging the contact hole reaching the drain electrode layer and the partition 7029 so as to overlap with each other, the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side can be substantially the same.

Further, the contact hole which is formed in the insulating layer 7045 and reaches the conductive film 7027 having a light-transmitting property is provided at a position overlapping with the partition 7029.

However, when using a light-emitting element with a dual emission structure and making both display surfaces full color display,
Light from the anode 7025 side does not pass through the color filter layer 7043, so that a sealing substrate provided with a color filter layer is preferably provided above the anode 7025.

Next, a light-emitting element having a top emission structure will be described with reference to FIG.

FIG. 15C shows a cross-sectional view of a pixel in the case where a TFT 7001 which is a driving TFT is an n-type and light emitted from a light emitting element 7002 escapes to the anode 7005 side. In FIG. 15(C),
The cathode 700 of the light emitting element 7002 electrically connected to the TFT 7001 through the connection electrode layer
3 is formed, and the EL layer 7004 and the anode 7005 are sequentially stacked on the cathode 7003.

Although various materials can be used for the cathode 7003, a material having a low work function, for example, an alkali metal such as Li or Cs and an alkaline earth metal such as Mg, Ca, or Sr, and In addition to alloys containing these (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferable.

In addition, the peripheral portion of the cathode 7003 is covered with a partition 7009. The partition 7009 is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. It is preferable that the partition 7009 be formed using a photosensitive resin material, in which an opening is formed over the cathode 7003 so that the side wall of the opening has an inclined surface with a continuous curvature. When a photosensitive resin material is used for the partition 7009, the step of forming a resist mask can be omitted.

Further, the EL layer 7004 formed over the cathode 7003 and the partition 7009 may be either a single layer or a plurality of layers stacked. EL layer 70
When 04 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. Note that it is not necessary to provide all these layers.

Further, the stacking order is not limited, and the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, and the electron injecting layer may be stacked in this order on the cathode 7003. When stacking in this order, the cathode 700
3 will function as an anode.

In FIG. 15C, a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer are laminated in this order on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order, and then Mg : A
Form a stack of g-alloy thin film and ITO.

However, when comparing the power consumption, an electron injection layer, an electron transport layer, a light emitting layer,
It is preferable to stack the hole transport layer and the hole injection layer in this order because power consumption is low.

The anode 7005 is formed using a light-transmitting conductive material, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A light-transmitting conductive film such as indium tin oxide containing indium tin oxide, indium tin oxide, indium tin oxide containing silicon oxide, or the like may be used.

A region in which the EL layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light emitting element 7002. In the case of the pixel shown in FIG. 15C, light emitted from the light emitting element 7002 is emitted to the anode 7005 side as indicated by an arrow.

15C illustrates an example in which the thin film transistor 150 is used as the TFT 7001, there is no particular limitation, and thin film transistors 160, 170, and 180 can be used.

In FIG. 15C, the drain electrode layer of the TFT 7001 is electrically connected to the connection electrode layer through the oxide insulating layer 7051, and the connection electrode layers are the insulating layer 7052 and the insulating layer 70.
It is electrically connected to the cathode 7003 via 55. The planarization insulating layer 7053 is made of polyimide,
A resin material such as acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above resin materials, low dielectric constant materials (low-k materials), siloxane-based resins, P
SG (phosphorus glass), BPSG (phosphorus glass), etc. can be used. Note that the planarization insulating layer 7053 may be formed by stacking a plurality of insulating films formed of these materials. A method for forming the planarization insulating layer 7053 is not particularly limited, and a sputtering method, an SOG method, a spin coating method, a dip method, a spray coating method, a droplet discharging method (inkjet method, screen printing, offset printing, or the like) depending on a material thereof. , Doctor knife, roll coater,
A curtain coater, a knife coater or the like can be used.

In addition, a partition 7009 is provided to insulate the cathode 7003 from the cathodes of adjacent pixels.
The partition 7009 is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like, an inorganic insulating film, or organic polysiloxane. It is preferable that the partition 7009 be formed using a photosensitive resin material, in which an opening is formed over the cathode 7003 so that the side wall of the opening has an inclined surface with a continuous curvature.

Further, in the structure of FIG. 15C, in the case of performing full-color display, for example, the light emitting element 70
02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other adjacent light emitting element is a blue light emitting element. In addition to the three types of light-emitting devices, white devices have been added.
A light-emitting display device which can perform full-color display with a variety of light-emitting elements may be manufactured.

In the structure in FIG. 15C, a plurality of light-emitting elements to be arranged are all white light-emitting elements, and a sealing substrate having a color filter or the like is arranged above the light-emitting element 7002,
A light emitting display device capable of full color display may be manufactured. Full-color display can be performed by forming a material that emits light of a single color such as white and combining it with a color filter or a color conversion layer.

Of course, monochromatic light emission display may be performed. For example, a lighting device may be formed using white light emission, or an area color type light emitting device may be formed using monochromatic light emission.

If necessary, an optical film such as a polarizing film such as a circularly polarizing plate may be provided.

Although the organic EL element is described as the light emitting element here, the inorganic EL element is used as the light emitting element.
It is also possible to provide an L element.

Although an example in which the thin film transistor (driving TFT) for controlling the driving of the light emitting element and the light emitting element are electrically connected is shown, the current control TFT is connected between the driving TFT and the light emitting element. It may be configured to be.

Next, an appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel) which is one mode of a semiconductor device will be described with reference to FIGS. 16A is a plan view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed with a sealant between the thin film transistor and the second substrate, and FIG. 16A corresponds to a cross-sectional view taken along line HI of FIG.

The pixel portion 4502 and the signal line driver circuits 4503a and 4503 provided over the first substrate 4501.
3b and the scanning line driving circuits 4504a and 4504b so as to surround the sealing material 4505.
Is provided. A second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuit 45.
04a and 4504b are sealed together with the filler 4507 by the first substrate 4501, the sealant 4505, and the second substrate 4506. In this way, it is preferable to package (enclose) a protective film (bonding film, ultraviolet curable resin film, etc.) or a cover material that has high airtightness and is less outgassed so as not to be exposed to the outside air.

In addition, the pixel portion 4502, the signal line driver circuits 4503a, 43 provided on the first substrate 4501.
Each of the scan line driver circuits 4504a and 4504b includes a plurality of thin film transistors, and in FIG. 15B, a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503a are illustrated. is doing.

As the thin film transistors 4509 and 4510, the highly reliable thin film transistor including the oxide semiconductor layer described in Embodiment 1 can be used. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

A conductive layer 4540 is provided over the insulating layer 4544 at a position overlapping with a channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for a driver circuit. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4509 before and after the BT test can be reduced. The conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509 or a different potential, and can function as a second gate electrode layer. In addition, the conductive layer 45
The potential of 40 may be GND, 0V, or a floating state.

In the thin film transistor 4509, an insulating layer 4541 is formed as an insulating film in contact with a semiconductor layer including a channel formation region. The insulating layer 4541 is the insulating layer 107 described in Embodiment 1.
It may be formed with the same material and method. Further, in order to reduce surface unevenness of the thin film transistor, the thin film transistor is covered with an insulating layer 4544 which functions as a planarization insulating film. Here, as the insulating layer 4541, like the insulating layer 107 described in Embodiment 1, a silicon oxide film is formed by a sputtering method.

Further, the insulating layer 4544 is formed as the planarization insulating film. The insulating layer 4544 may be formed using a material and a method similar to those of the insulating layer 4021 described in Embodiment 2. Here, acrylic is used as the insulating layer 4544.

Reference numeral 4511 corresponds to a light emitting element, and the first electrode layer 4517 which is a pixel electrode included in the light emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that the light-emitting element 4511 has a stacked-layer structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513; however, the structure is not limited to that shown. The structure of the light emitting element 4511 can be changed as appropriate in accordance with the direction of light extracted from the light emitting element 4511, or the like.

The partition 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane.
In particular, it is preferable to use a photosensitive material and form an opening over the first electrode layer 4517 so that the side wall of the opening is an inclined surface with a continuous curvature.

The electroluminescent layer 4512 may be formed of a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layer 4513 and the partition 4520 so that oxygen, hydrogen, moisture, carbon dioxide, and the like do not enter the light-emitting element 4511. As the protective film, a silicon nitride film,
A silicon nitride oxide film, a DLC film, or the like can be formed.

In addition, signal line driver circuits 4503a and 4503b, scan line driver circuits 4504a and 4504b.
, Or various signals and potentials applied to the pixel portion 4502 are FPCs 4518a and 4518.
It is supplied from b.

The connection terminal electrode 4515 is formed using the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511, and the terminal electrode 4516 is formed using the same conductive film as the source electrode layer and the drain electrode layer included in the thin film transistors 4509 and 4510. ing.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518a through an anisotropic conductive film 4519.

The substrate positioned in the light extraction direction of the light emitting element 4511 must be light-transmitting. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon, and PVC (polyvinyl chloride), acrylic,
Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV
A (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

If necessary, a polarizing plate or a circular polarizing plate (including an elliptically polarizing plate) on the emission surface of the light emitting element,
An optical film such as a retardation plate (λ/4 plate or λ/2 plate) or a color filter may be appropriately provided. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, it is possible to perform anti-glare treatment that diffuses reflected light due to unevenness on the surface and can reduce glare.

The signal line driver circuits 4503a and 4503b and the scan line driver circuits 4504a and 4504b may be mounted as a driver circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film over a separately prepared substrate. Further, only the signal line driver circuit or part thereof, or only the scan line driver circuit or part thereof may be separately formed and mounted, and the structure is not limited to that in FIG. 16.

Through the above steps, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

By manufacturing a thin film transistor in a pixel portion of a light-emitting display device using the method for manufacturing a thin film transistor described in Embodiment 1, power consumption due to variation in off-state current of the thin film transistor in each pixel can be reduced.

Further, by manufacturing the thin film transistor of the driver circuit of the light-emitting display device using the method of manufacturing the thin film transistor described in Embodiment 1, high speed operation of the thin film transistor in the driver circuit portion can be realized and power saving can be achieved.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, as an example of a semiconductor device, an example of a liquid crystal display device using the liquid crystal element including the thin film transistor described in Embodiment 1 will be described with reference to FIGS. FIG. 17
The thin film transistor described in Embodiment 1 can be applied to the TFT 628 and the TFT 629 used in the liquid crystal display device in FIGS. 20A to 20C, and a thin film transistor with high electric characteristics and high reliability which can be manufactured in a similar manner to the process described in Embodiment 1. is there. The TFT 628 and the TFT 629 are thin film transistors including an oxide semiconductor layer as a channel formation region. 17 to 20
Then, a case where the thin film transistor illustrated in FIG. 2C is used as an example of the thin film transistor is described; however, the present invention is not limited to this.

Hereinafter, a VA (Vertical Alignment) type liquid crystal display device will be described.
The VA liquid crystal display device is a kind of system for controlling the alignment of liquid crystal molecules of a liquid crystal display panel. The VA type liquid crystal display device is a system in which liquid crystal molecules are oriented in a direction perpendicular to a panel surface when no voltage is applied. In the present embodiment, in particular, the pixel (pixel) is divided into several regions (subpixels), and the molecules are tilted in different directions. This is called multi-domain design or multi-domain design. In the following description, a liquid crystal display device considering a multi-domain design will be described.

18 and 19 show a pixel electrode and a counter electrode, respectively. Note that FIG. 18 is a plan view of the substrate side on which the pixel electrodes are formed, and FIG. 17 shows a cross-sectional structure corresponding to a section line EF shown in the drawing. Further, FIG. 19 is a plan view of the side of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

FIG. 17 shows a state in which a substrate 600 in which a TFT 628, a pixel electrode 624 connected to the TFT 628, and a storage capacitor portion 630 are formed, and a counter substrate 601 in which a counter electrode 640 and the like are formed are stacked and liquid crystal is injected. Shows.

The first colored film 636 and the second colored film 636 are formed at the positions where the columnar spacers are formed on the counter substrate 601.
The colored film (not shown), the third colored film (not shown), and the counter electrode 640 are formed. With this structure, the height of the protrusion 644 for controlling the alignment of the liquid crystal and the height of the spacer are made different. An alignment film 648 is formed on the pixel electrode 624, and similarly, an alignment film 646 is also formed on the counter electrode 640. A liquid crystal layer 650 is formed between them.

The spacers are shown here as columnar spacers, but bead spacers may be dispersed. Here, the columnar spacer means an organic film or an inorganic film formed on one of the substrates, which is patterned and etched to a predetermined size by a photolithography process, or a positive or negative patternable organic film. The columnar spacer can control the thickness of the liquid crystal layer. Further, the spacer may be formed on the pixel electrode 624 formed on the substrate 600.

On the substrate 600, the TFT 628, the pixel electrode 624 connected to the TFT 628, and the storage capacitor portion 63.
0 is formed. The pixel electrode 624 includes the TFT 628, the wiring 616, and the storage capacitor portion 630.
A contact hole 623 penetrating the insulating film 620 that covers the insulating film 620 and the third insulating film 622 that covers the insulating film 620 is connected to the wiring 618. As the TFT 628, the thin film transistor described in Embodiment 1 can be used as appropriate. In addition, the storage capacitor portion 630 includes a capacitor wiring 604 which is a first capacitor wiring formed at the same time as the gate wiring 602 of the TFT 628, and the gate insulating film 60.
6 and a capacitance wiring 617 which is a second capacitance wiring formed at the same time as the wirings 616 and 618.

A liquid crystal element is formed by overlapping the pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640.

FIG. 18 shows a structure on the substrate 600. The pixel electrode 624 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide (hereinafter referred to as ITO). ), indium zinc oxide, and indium tin oxide to which silicon oxide is added, a light-transmitting conductive material can be used.

Alternatively, the pixel electrode 624 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω/□ or less and a light transmittance of 70% or more at a wavelength of 550 nm. In addition, the resistivity of the conductive high molecule contained in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples thereof include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds of them.

A slit 625 is provided in the pixel electrode 624. The slit 625 is for controlling the alignment of the liquid crystal.

The TFT 628 and the pixel electrode 626 and the storage capacitor portion 631 which are connected to the TFT 628 illustrated in FIG. 18 can be formed similarly to the TFT 628, the pixel electrode 624, and the storage capacitor portion 630, respectively. Both the TFT 628 and the TFT 629 are connected to the wiring 616. A pixel of this liquid crystal display panel is composed of a pixel electrode 624 and a pixel electrode 626. The pixel electrode 624 and the pixel electrode 626 form a sub pixel.

FIG. 19 shows the structure of the counter substrate side. The counter electrode 640 is preferably formed using a material similar to that of the pixel electrode 624. A protrusion 644 that controls the alignment of the liquid crystal is formed on the counter electrode 640.

An equivalent circuit of this pixel structure is shown in FIG. The TFTs 628 and 629 are both connected to the gate wiring 602 and the wiring 616. In this case, the potentials of the capacitor wiring 604 and the capacitor wiring 605 are different from each other, whereby the liquid crystal element 651 and the liquid crystal element 652 can have different operations. That is, the potentials of the capacitor wiring 604 and the capacitor wiring 605 are individually controlled to precisely control the orientation of the liquid crystal and widen the viewing angle.

When voltage is applied to the pixel electrode 624 provided with the slit 625, electric field distortion (oblique electric field) is generated in the vicinity of the slit 625. The slit 625 and the protrusion 6 on the counter substrate 601 side
By arranging the electrodes 44 and 44 so as to be alternately engaged with each other, an oblique electric field is effectively generated to control the alignment of the liquid crystal, so that the direction in which the liquid crystal is aligned varies depending on the place. That is, the viewing angle of the liquid crystal display panel is widened by making it multi-domain.

Next, a VA liquid crystal display device different from the above will be described with reference to FIGS.

21 and 22 show a pixel structure of a VA type liquid crystal display panel. FIG. 22 shows a substrate 600
FIG. 21 is a plan view of FIG. 21, and FIG. 21 shows a cross-sectional structure corresponding to the cutting line YZ shown in the drawing. The following description will be made with reference to these figures.

In this pixel structure, one pixel has a plurality of pixel electrodes, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. That is, in a pixel having a multi-domain design, the signal applied to each pixel electrode is independently controlled.

The pixel electrode 624 is connected to the TFT 628 through the wiring 618 in the contact hole 623. Further, the pixel electrode 626 is provided in the contact hole 627, and the wiring 619 is provided in the TFT.
629 is connected. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be given. On the other hand, the wiring 616 functioning as a data line is commonly used by the TFT 628 and the TFT 629. As the TFT 628 and the TFT 629, the thin film transistor described in Embodiment 1 can be used as appropriate. In addition, a capacitor wiring 690 is provided.

The pixel electrode 624 and the pixel electrode 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 spreading in a V shape. The timing of the voltage applied to the pixel electrode 624 and the pixel electrode 626 is set to the TFT 628.
And the TFT 629 are used to control the alignment of the liquid crystal. An equivalent circuit of this pixel structure is shown in FIG. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. By giving different gate signals to the gate wiring 602 and the gate wiring 603, the operation timings of the TFT 628 and the TFT 629 can be made different.

A colored film 636 and a counter electrode 640 are formed on the counter substrate 601. In addition, the colored film 6
A flattening film 637 is formed between the counter electrode 36 and the counter electrode 640 to prevent liquid crystal alignment disorder. FIG. 23 shows the structure on the counter substrate side. The counter electrode 640 is an electrode shared by different pixels, but has a slit 641 formed therein. The slit 641 and the pixel electrode 62
4 and the slits 625 on the side of the pixel electrode 626 are arranged so as to alternately engage with each other, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. As a result, the direction in which the liquid crystal is aligned can be changed depending on the location, and the viewing angle is widened.

A first liquid crystal element is formed by overlapping the pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640. Further, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 overlap with each other, so that a second liquid crystal element is formed. Further, it has a multi-domain structure in which the first liquid crystal element and the second liquid crystal element are provided in one pixel.

In this embodiment mode, as a liquid crystal display device including the thin film transistor described in Embodiment Mode 1,
Although the A type liquid crystal display device has been described, the present invention is also applicable to an IPS type liquid crystal display device, a TN type liquid crystal display device, and the like.

By manufacturing a thin film transistor in a pixel portion of a light-emitting display device using the method for manufacturing a thin film transistor described in Embodiment 1, power consumption due to variation in off-state current of the thin film transistor in each pixel can be reduced.

(Embodiment 7)
The semiconductor device disclosed in this specification can be applied to electronic paper. The electronic paper can be used for electronic devices in all fields as long as it displays information. For example, the electronic paper can be applied to an electronic book (electronic book), a poster, an advertisement in a vehicle such as a train, a display on various cards such as a credit card, and the like. Examples of electronic devices are shown in FIGS.

FIG. 25 illustrates an example of the electronic book reader 2700. For example, the electronic book 2700 has a housing 2
701 and a housing 2703. Housing 2701 and housing 27
03 is integrated by a shaft portion 2711, and it is possible to perform an opening/closing operation with the shaft portion 2711 as a shaft. With such a configuration, it is possible to perform an operation like a paper book.

A display portion 2705 is incorporated in the housing 2701, and a display portion 2707 is incorporated in the housing 2703. The display portion 2705 and the display portion 2707 may have a structure in which a continuous screen is displayed or a structure in which different screens are displayed. With the configuration in which different screens are displayed, for example, a sentence can be displayed on the right display portion (display portion 2705 in FIG. 25) and an image can be displayed on the left display portion (display portion 2707 in FIG. 25). ..

Further, FIG. 25 illustrates an example in which the housing 2701 is provided with an operation portion and the like. For example, housing 2
701 includes a power source 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned with the operation key 2723. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, a configuration may be provided in which a terminal for external connection (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like are provided on the back surface or side surface of the housing. .. Further, the electronic book reader 2700 may have a structure having a function as an electronic dictionary.

The electronic book reader 2700 may have a configuration capable of wirelessly transmitting and receiving data. By radio
It is also possible to purchase desired book data or the like from the electronic book server and download the book data.

(Embodiment 8)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a camera such as a digital camera and a digital video camera, a digital photo frame, a mobile phone (a mobile phone, a mobile phone). (Also referred to as a device), a portable game machine, a portable information terminal, a sound reproducing device, and a large game machine such as a pachinko machine.

FIG. 26A illustrates an example of the television device 9600. Television device 96
In the case of 00, a display portion 9603 is incorporated in a housing 9601. Images can be displayed on the display portion 9603. In addition, here, a housing 9601 is provided by a stand 9605.
The structure which supported was shown.

The television device 9600 can be operated with an operation switch included in the housing 9601 or a separate remote controller 9610. The operation keys 9609 provided in the remote controller 9610 can be used to operate a channel and volume, and an image displayed on the display portion 9603 can be operated. Further, the remote controller 9610 may be provided with a display portion 9607 for displaying information output from the remote controller 9610.

Note that the television device 9600 is provided with a receiver, a modem, and the like. The receiver can receive general TV broadcasts, and by connecting to a wired or wireless communication network via a modem, it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between the recipients, or between recipients).

FIG. 26B illustrates an example of the digital photo frame 9700. For example, in the digital photo frame 9700, a display portion 9703 is incorporated in a housing 9701. The display portion 9703 can display various images. For example, by displaying image data captured by a digital camera or the like, the display portion 9703 can function as a normal photo frame.

The digital photo frame 9700 includes an operation unit, an external connection terminal (USB terminal, US
A terminal that can be connected to various cables such as a B cable), a recording medium insertion portion, and the like are provided. These structures may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory in which image data captured by a digital camera is stored can be inserted into a recording medium insertion portion of a digital photo frame to capture image data, and the captured image data can be displayed on the display portion 9703.

Further, the digital photo frame 9700 may have a structure capable of wirelessly transmitting and receiving data. A desired image data may be wirelessly fetched and displayed.

FIG. 27A illustrates a portable game machine including two housings, a housing 9881 and a housing 9891, which are connected with a joint portion 9893 so that the portable game machine can be opened or folded. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. In addition, the portable game machine illustrated in FIG. 27A includes a speaker portion 9884, a recording medium insertion portion 988, and the like.
6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9
888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature,
It includes chemical substances, voice, time, hardness, electric field, electric current, voltage, electric power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), and a microphone 9889). Needless to say, the structure of the portable game machine is not limited to the above structure and may be at least the structure including the semiconductor device disclosed in this specification and may be a structure where other accessory equipment is provided as appropriate. The portable game machine illustrated in FIG. 27A has a function of reading a program or data recorded in a recording medium and displaying the program or data on the display portion or performing wireless communication with another portable game machine to share information. Have a function. Note that the function of the portable game machine illustrated in FIG. 27A is not limited to this and can have various functions.

FIG. 27B shows an example of a slot machine 9900 which is a large-sized game machine. In the slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 also includes operation means such as a start lever and a stop switch, a coin slot, a speaker, and the like. Of course, the configuration of the slot machine 9900 is not limited to the above-described one, and may be a configuration including at least the semiconductor device disclosed in this specification, and may be a configuration in which other auxiliary equipment is appropriately provided.

FIG. 28A is a perspective view illustrating an example of a portable computer.

In the portable computer in FIG. 28A, an upper housing 9301 having a display portion 9303 with a hinge unit which connects the upper housing 9301 and the lower housing 9302 closed and a lower housing 9302 having a keyboard 9304 are included. When the keyboard input is performed by the user, the hinge unit can be opened and the display unit 9303 can be operated for input operation.

In addition to the keyboard 9304, the lower housing 9302 has a pointing device 9306 for performing an input operation. Further, when the display portion 9303 is a touch input panel, an input operation can be performed by touching part of the display portion. Further, the lower housing 9302 has a calculation function unit such as a CPU and a hard disk. In addition, the lower housing 9302 is used for other devices such as U.
It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted.

In the upper housing 9301, a display portion 93 that can be slid into the upper housing 9301 and stored.
07, a wide display screen can be realized. In addition, the display unit 93 that can be stored
The user can adjust the orientation of the 07 screen. If the storable display portion 9307 is a touch input panel, an input operation can be performed by touching part of the storable display portion.

As the display portion 9303 or the storable display portion 9307, a video display device such as a liquid crystal display panel or a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element is used.

Further, the portable computer in FIG. 28A can be provided with a receiver and the like and can receive a television broadcast and display an image on the display portion or the display portion. In addition, the upper housing 93
01 and the lower housing 9302 are connected to each other while the display unit 930 is closed.
The user can also watch TV broadcast by sliding 7 to expose the entire screen and adjusting the screen angle. In this case, the hinge unit is opened and the display portion 9303 is not displayed, and only the circuit for displaying the television broadcast is started, so that the minimum power consumption can be achieved and the battery capacity is limited. It is useful in portable computers that are used.

Further, FIG. 28B is a perspective view showing an example of a mobile phone having a shape that can be worn on the arm of the user like a wristwatch.

This mobile phone includes a main body having at least a communication device having a telephone function and a battery, a band part for mounting the main body on an arm, and an adjusting part 92 for adjusting a fixing state of the band part with respect to the arm.
05, a display unit 9201, a speaker 9207, and a microphone 9208.

Further, the main body has an operation switch 9203, and in addition to a power input switch, a display changeover switch, an imaging start instruction switch, and a button, for example, a program for the Internet is activated.

The input operation of this mobile phone is performed by touching the display portion 9201 with a finger, an input pen, or the like, operating the operation switch 9203, or inputting voice into the microphone 9208. Note that FIG. 28B illustrates the display button 9202 displayed on the display portion 9201, and input can be performed by touching with a finger or the like.

Further, the main body has a camera unit 9206 having an image pickup means for converting a subject image formed through the taking lens into an electronic image signal. Note that the camera section may not be provided.

In addition, the mobile phone illustrated in FIG. 28B has a structure including a receiver of a television broadcast, can receive a television broadcast, display an image on the display portion 9201, and a storage device such as a memory. As a configuration including, a television broadcast can be recorded in the memory. In addition, FIG. 28(B)
The mobile phone shown in may have a function of collecting position information such as GPS.

As the display portion 9201, a video display device such as a liquid crystal display panel or a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element is used. Since the mobile phone shown in FIG. 28B is small and lightweight, its battery capacity is limited, and it is preferable that the display device used for the display portion 9201 be a panel which can be driven with low power consumption.

Note that FIG. 28B illustrates an electronic device of a type worn on an "arm", but the electronic device is not particularly limited as long as it has a shape that can be carried.

In this example, a thin film transistor was manufactured using the manufacturing method described in Embodiment Mode, −2.
The result of having evaluated the off-current of thin film transistor characteristics under the environment of 5°C to 150°C is shown.

In this example, a plurality of thin film transistors having a channel length L of 3 μm was manufactured over a glass substrate, and the off-state current of thin film transistor characteristics under the environment of −25° C. to 150° C. was evaluated. The channel width W was 20 μm. First, a method for manufacturing a thin film transistor will be described.

First, a 100-nm-thick silicon oxynitride film is formed as a base film over a glass substrate by a CVD method, and a 100-nm-thick film is formed as a gate electrode layer over the silicon oxynitride film by a sputtering method.
Of tungsten film was formed. Here, the tungsten film was selectively etched to form a gate electrode layer.

Next, a 100-nm-thick silicon oxynitride film was formed over the gate electrode layer as a gate insulating layer by a CVD method.

Next, the gate insulating layer, In-Ga-Zn-O-based oxide semiconductor target _(In 2 _{O 3}
:Ga ₂ O ₃ :ZnO=1:1:1) and the distance between the substrate and the target is 80 m.
m, pressure 0.4 Pa, direct current (DC) power supply 5 kW, argon and oxygen (argon:oxygen=5)
Film formation was performed at 200° C. in an atmosphere of 0 sccm:50 sccm to form an oxide semiconductor layer having a thickness of 30 nm. Here, the oxide semiconductor layer was selectively etched to form an island-shaped oxide semiconductor layer.

Next, the oxide semiconductor layer was subjected to first heat treatment at 650° C. for 6 minutes in a nitrogen atmosphere, and then second heat treatment was performed at 450° C. for 1 hour in an air atmosphere.

Then, a titanium film (having a thickness of 100) is formed as a source electrode layer and a drain electrode layer over the oxide semiconductor layer.
nm), an aluminum film (thickness 300 nm), and a titanium film (thickness 100 nm) were stacked at 100° C. by a sputtering method. Here, the source electrode layer and the drain electrode layer were selectively etched so that the channel length L of the thin film transistor was 3 μm and the channel width W was 20 μm.

Next, a film having a thickness of 300 n is formed as an insulating layer by a sputtering method so as to be in contact with the oxide semiconductor layer.
m silicon oxide film was formed at 200° C. Here, the silicon oxide film which is a protective layer was selectively etched to form openings over the gate electrode layer, the source electrode layer, and the drain electrode layer. After that, a third heat treatment was performed at 250° C. for one hour in a nitrogen atmosphere.

Through the above steps, a plurality of thin film transistors having a channel length L of 3 μm and a channel width W of 20 μm were formed on a glass substrate.

Subsequently, the off current of the thin film transistor was measured. The off-current characteristics were measured by setting the voltage between the source and the drain (hereinafter referred to as the drain voltage or Vd) to 10V and the voltage between the source and the gate (hereinafter referred to as the gate voltage or Vg) at -10V. .. Figure 4 (
In B), the substrate temperature at the time of measurement is changed to −25° C., 0° C., 25° C., 50° C., 100° C., 150° C., and the off-state current of the thin film transistor at each substrate temperature (operating temperature) is shown.
The measurement temperature on the horizontal axis represents the substrate temperature (operating temperature) at the time of measuring the off-current of the thin film transistor on a linear scale, and the vertical axis represents the off-current (Ioff) at each substrate temperature on the log scale.

The thin film transistor manufactured in this example has an environment of −25° C. or higher and 150° C. or lower,
It was confirmed that the off-current value was 1×10 ⁻¹² A or less.

10 pulse output circuit 11 wiring 12 wiring 13 wiring 14 wiring 15 wiring 21 input terminal 22 input terminal 23 input terminal 24 input terminal 25 input terminal 26 output terminal 27 output terminal 28 transistor 31 transistor 32 transistor 33 transistor 34 transistor 35 transistor 36 transistor 37 transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 Period 62 Period 100 Substrate 101 Gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 107 Insulating layer 110 Channel protective layer 150 Thin film transistor 160 thin film transistor 170 thin film transistor 180 thin film transistor 201 spectrum 202 spectrum 203 spectrum 301 spectrum 302 spectrum 303 spectrum 311 spectrum 312 spectrum 313 spectrum 321 spectrum 322 spectrum 323 spectrum 400 glass substrate 401 oxynitride insulating layer 402 In-Ga-Zn-O-based oxide semiconductor Layer 403 Analysis direction 411 Oxygen ion intensity profile 412 Hydrogen concentration profile 413 Hydrogen concentration profile 451 Spectrum 452 Spectrum 453 Spectrum 461 Spectrum 462 Spectrum 463 Spectrum 581 Thin film transistor 583 Insulating film 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particle 594 Cavity 595 Filling Material 600 Substrate 601 Counter substrate 602 Gate wiring 603 Gate wiring 604 Capacitive wiring 605 Capacitive wiring 606 Gate insulating film 616 Wiring 617 Capacitive wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating film 623 Contact hole 624 Pixel electrode 625 Slit 626 Pixel electrode 627 Contact Hall 628 TFT
629 TFT
630 Storage capacitor portion 631 Storage capacitor portion 636 Coloring film 637 Flattening film 640 Counter electrode 641 Slit 644 Protrusion 646 Alignment film 648 Alignment film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitive wiring 701 Gate electrode layer 702 Gate Insulating layer 703 Semiconductor layer 704 Source electrode layer 705 Drain electrode layer 801 Glass substrate 802 Gate electrode layer 803 Gate insulating layer 804 Oxide semiconductor layer 805 Source electrode layer 806 Drain electrode layer 105a Source electrode layer 105b Drain electrode layer 2600 TFT substrate 2601 Facing Substrate 2602 Sealing material 2603 Pixel portion 2604 Display element 2605 Coloring layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit portion 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflecting plate 2612 Circuit board 2613 Diffusing plate 2700 Electronic book 2701 Housing 2703 Housing 2705 Display portion 2707 Display portion 2711 Shaft portion 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel portion 4003 Signal line driving circuit 4004 Scanning line driving circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC
4019 anisotropic conductive film 4020 insulating layer 4020 insulating layer (insulating layer 4021 insulating layer 4030 pixel electrode layer 4031 counter electrode layer 4032 insulating layer 4040 conductive layer 4501 substrate 4502 pixel portion 4505 sealant 4506 substrate 4507 filler 4509 thin film transistor 4510 thin film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Partition wall 4540 Conductive layer 4541 Insulating layer 4544 Insulating layer 5300 On substrate 5300 Substrate 5301 Pixel portion 5302 Scanning line driving circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit portion 5602 Switching circuit 5603 Thin film transistor 5604 Wiring 5605 Wiring 590a Black area 590b White area 6400 Pixel 6401 Switching transistor 6402 Driving transistor 6403 Capacitance element 6404 Light emission Element 6405 Signal line 6406 Scanning line 6407 Power supply line 6408 Common electrode 7001 TFT
7002 light emitting element 7003 cathode 7004 EL layer 7005 anode 7009 partition 7011 TFT
7012 light emitting element 7013 cathode 7014 EL layer 7015 anode 7016 shielding film 7017 conductive film 7019 partition wall 7021 TFT
7022 light-emitting element 7023 cathode 7024 EL layer 7025 anode 7026 anode 7027 conductive film 7029 partition wall 7031 oxide insulating layer 7033 color filter layer 7034 overcoat layer 7035 insulating layer 7041 oxide insulating layer 7043 color filter layer 7044 overcoat layer 7045 insulating layer 704a Drain electrode layer 704b Source electrode layer 7051 Oxide insulating layer 7052 Insulating layer 7053 Flattening insulating layer 7055 Insulating layer 9201 Display unit 9202 Display button 9203 Operation switch 9205 Control unit 9206 Camera unit 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 display portion 9304 keyboard 9305 external connection port 9306 pointing device 9307 display portion 9600 television device 9601 housing 9603 display portion 9605 stand 9607 display portion 9609 operation keys 9610 remote controller 9700 digital photo frame 9701 housing 9703 display portion 9881 housing Reference numeral 9882 Display portion 9883 Display portion 9884 Speaker portion 9885 Input means (operation key 9886 Recording medium insertion portion 9878 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting portion 9900 Slot machine 9901 Housing 9903 Display portion 4503a Signal line drive circuit 4504a Scan line driver circuit 4518a FPC

Claims (2)

Has multiple pixels,
The pixel includes a transistor and a light emitting element on the transistor,
The transistor has an oxide semiconductor layer containing indium, gallium, and zinc, and a metal conductive film which is located below the oxide semiconductor layer and overlaps with the oxide semiconductor layer with an insulating layer interposed therebetween,
The oxide semiconductor layer is a microcrystalline film,
The transistor has a channel length of 1.5 μm or more and 100 μm or less,
The transistor has a light emitting display panel having a channel width of 1×10 ⁻¹² A or less per 1 μm in a temperature range of −25° C. or higher and 150° C. or lower. Has multiple pixels,
The pixel includes a transistor and a light emitting element on the transistor,
The transistor has an oxide semiconductor layer containing indium, gallium, and zinc, and a metal conductive film which is located below the oxide semiconductor layer and overlaps with the oxide semiconductor layer with an insulating layer interposed therebetween,
The oxide semiconductor layer is a microcrystalline film,
The transistor has a channel length of 3 μm or more and 10 μm or less,
The transistor has a light emitting display panel having a channel width of 1×10 ⁻¹² A or less per 1 μm in a temperature range of −25° C. or higher and 150° C. or lower.

Images