JP6727907B2 - Semiconductor integrated circuit and control method thereof - Google Patents

Description

The present invention relates to controlling the operating frequency of a semiconductor integrated circuit.

With the progress of semiconductor process technology, system LSIs are becoming faster and more sophisticated. Increasing the speed and functionality of the system LSI leads to an increase in the number of integrated transistors, an increase in input/output pins, and an increase in operating frequency, which directly leads to an increase in current consumption of the system LSI. If the current consumption increases due to the operation of the transistor in the system LSI, the fluctuation amount of the power supply voltage accompanying it increases, and the risk that the LSI itself malfunctions due to the fluctuation of the power supply voltage increases.

Further, when the semiconductor element is miniaturized, it is necessary to lower the operating voltage in order to maintain the element characteristics. The flow of lowering the voltage is preferable from the viewpoint of power saving and is not preferable from the viewpoint of voltage fluctuation tolerance, which is an allowable range of voltage fluctuation. The reason for this is that as the lowering of the voltage advances, the margin amount allowed in the allowable range of voltage fluctuation decreases, so that the risk of malfunction of the semiconductor element increases even if the voltage fluctuation is at the same level as in the conventional case.

Due to the increase in the fluctuation amount of the power supply voltage due to the increase of the consumption current and the reduction of the voltage fluctuation resistance due to the lower voltage of the semiconductor element, it is essential to suppress the fluctuation of the power supply voltage in the design of the system LSI. Become.

As a measure for suppressing the fluctuation of the power supply voltage, there is known a method of switching the power supply impedance so that the resonance frequency of the power supply impedance is separated from the operating frequency of the semiconductor integrated circuit. For example, in Patent Document 1, the power supply voltage is monitored, and the power supply impedance is switched based on the fluctuation of the power supply voltage so that the operating frequency of the semiconductor integrated circuit and the resonance frequency of the power supply impedance do not overlap.

Furthermore, in recent years, power saving technologies such as PSO (Power Shut Off) have begun to be used. When the PSO technology is applied, it is possible to reduce the leak power of the LSI and thus save power. When the PSO technique is applied, the power supply to each unused circuit block inside the LSI is cut off, and the circuit block of which the power supply is cut off becomes non-conductive with the power supply. When the circuit block whose power supply is cut off is used, the non-conduction state between the circuit block and the power supply is switched to the conduction state in order to supply the electric power again. This switching is frequently performed according to the operation of the LSI. Before and after the switching, the number of power supply meshes connected to the main power supply, the number of transistors, and the number of decaps are different, so the impedance characteristics of the LSI fluctuate and the resonance frequency of the impedance of the LSI Fluctuates dynamically.

Japanese Patent Laid-Open No. 2009-94133

In Patent Document 1, in order to change the impedance of the power supply, a variable capacitance element or the like is inserted to control the impedance so that the resonance frequency of the impedance deviates from the operating frequency. However, when a power saving technique such as PSO is applied, the impedance itself dynamically changes. Therefore, the method of Patent Document 1 cannot intentionally make the resonance frequency of the impedance different from the operating frequency.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit that supplies a clock having an operating frequency different from the resonance frequency of the impedance of the LSI to the circuit block. Another object is to provide a method for controlling the semiconductor integrated circuit.

In order to solve the above problems, the semiconductor integrated circuit according to the present invention has the following configuration. That is, it corresponds to a combination of a switch that switches each of the circuit blocks to a conductive state or a non-conductive state with the power supply unit, and a circuit block of the plurality of circuit blocks that is in a conductive state with the power supply unit. From the storage means, a resonance frequency of the impedance corresponding to a combination of storage means for storing the resonance frequency of the impedance of the semiconductor integrated circuit and the circuit block switched to the conducting state or the non-conducting state by the switch is provided. It has an acquisition means for acquiring, and a generation means for generating a clock having an operating frequency different from the resonance frequency of the impedance acquired by the acquisition means and supplying the clock to the circuit block.

According to the present invention, even in an LSI to which a power saving technique such as PSO is applied, a clock having an operating frequency different from the resonance frequency of the impedance of the LSI can be supplied to the circuit block.

FIG. 3A is a diagram showing an example of a configuration of a semiconductor integrated circuit 111. (B) It is a figure which shows another example of a structure of the semiconductor integrated circuit 111. It is a simplified diagram showing an equivalent circuit of a power supply. It is a figure which shows the influence of a parasitic inductance. (A) It is a figure which shows an inductance characteristic. (B) It is a figure which shows the change of an inductance characteristic. It is a figure which shows the semiconductor integrated circuit 111 of 1st Embodiment. It is a figure which shows the power mode of the semiconductor integrated circuit 111 of 1st Embodiment. FIG. 5 is an image diagram when the power source of the semiconductor integrated circuit 111 of the first embodiment is turned on/off. 7 is a table showing resonance frequencies in the power mode shown in FIG. 6. 5 is a table showing an example of operating frequencies selected in the first embodiment and operating voltages corresponding thereto. 7 is an operation flowchart of the power saving management unit 101 when the power of the power mode 1 is switched to the power mode 7 in the first embodiment. 7 is an operation flowchart of the power saving management unit 101 when the power is restored to the power mode 2 from the power mode 7 in the first embodiment. It is a figure which shows the structural example of 2nd Embodiment. It is a figure which shows the structural example of 2nd Embodiment.

<First Embodiment>
FIG. 1A is a diagram for explaining an example of the configuration of a system LSI (hereinafter, referred to as “semiconductor integrated circuit 111”) according to the present embodiment. The semiconductor integrated circuit 111 is a circuit in which many functions such as image processing, compression/expansion processing, encryption/decryption processing, and communication processing are integrated.

The configuration and operation of the semiconductor integrated circuit 111 will be briefly described below.

The first circuit block 109, the second circuit block 110, and the Nth circuit block 113 are circuits that realize many functions such as image processing, compression/decompression processing, encryption/decryption processing, and communication processing.

The first power switch 107, the second power switch 108, and the Nth power switch 112 are element groups that switch ON/OFF of the power supplied to the first circuit block 109, the second circuit block 110, and the Nth circuit block 113, respectively. Is. Each power switch switches ON/OFF of the power supplied to the circuit block by switching the conduction state or the non-conduction state between each circuit block and the power supply unit.

After receiving the power saving command from the system control unit 102, the power saving management unit 101 transmits a control command to the power supply unit 104, and controls the operating voltage supplied by the power supply unit 104 to the semiconductor integrated circuit 111. To do. The power saving management unit 101 also controls the first power switch 107, the second power switch 108, and the Nth power switch 112. Whether the first power switch 107, the second power switch 108, and the Nth power switch 112 conduct the power supplied by the power supply unit 104 to the first circuit block 109, the second circuit block 110, and the Nth circuit block 113. Or switch.

The storage unit 103 such as a non-volatile memory (ROM) stores (stores) a power mode-resonance frequency correspondence table. The power mode-resonance frequency correspondence table stores information on the resonance frequency of the impedance of the semiconductor integrated circuit. The clock generation unit 105 generates a clock having an operating frequency different from the impedance resonance frequency and supplies the clock to the circuit block.

FIG. 1B is a diagram for explaining another example of the configuration of the semiconductor integrated circuit 111 according to this embodiment. Here, description of portions having the same configuration as that shown in FIG. 1B and the configuration shown in FIG. 1A will be omitted. In the configuration shown in FIG. 1B, the clock generation unit 105 generates a plurality of clocks having different operating frequencies, and the clock selection unit 106 selects a clock having an operating frequency different from the impedance resonance frequency from the plurality of clocks. , Supply to the circuit block. That is, the semiconductor integrated circuit 111 shown in FIG. 1A generates a clock and supplies it to the circuit block, but the semiconductor integrated circuit 111 shown in FIG. 1B selects a clock from a plurality of clocks generated in advance. Supply to the circuit block. Hereinafter, the present embodiment will be described focusing on the semiconductor integrated circuit 111 shown in FIG. 1A, but it is apparent that the semiconductor integrated circuit 111 shown in FIG.

FIG. 2 is a diagram schematically illustrating a circuit that supplies power from the power supply unit 104 to the semiconductor integrated circuit 111 in a simple RLGC equivalent circuit model. In order to ensure the quality of the operating voltage of the power supplied by the power supply unit 104, a low-frequency/high-frequency compatible two-stage bypass capacitor is usually arranged on the printed circuit board in many cases. Therefore, two capacitors are added on the printed circuit board of FIG. Further, in order to remove further high frequency noise that cannot be completely removed on the printed circuit board, it is possible to arrange a bypass capacitor on the semiconductor package and insert an on-die decap inside the semiconductor integrated circuit 111. Therefore, those elements are also included in FIG. Further, the resistance and the inductance arranged in series in FIG. 2 indicate the parasitic resistance and the parasitic inductance of the wiring and Via. The capacitor and the inductance arranged in parallel represent the bypass capacitor and the parasitic inductance of the bypass capacitor.

FIG. 3 is a diagram showing frequency-impedance characteristics of the bypass capacitor of FIG. Bypass capacitors are originally used to reduce impedance in order to suppress fluctuations in power supply voltage. However, when the frequency exceeds a certain frequency, the influence of the parasitic inductance of the bypass capacitor and the wiring becomes remarkable, and the impedance is increased in the opposite direction to the original role. The gray line in FIG. 3 shows the impedance characteristic of the bypass capacitor when the capacitance is 1000 pF and the inductance is 0.1 nH.

FIG. 4A is a diagram schematically showing impedance characteristics when a plurality of types of bypass capacitors having the impedance characteristics of FIG. 3 are used. In FIG. 4A, the impedance curves of the capacitive element A and the capacitive element B are shown by dotted lines, and their combined impedances are shown by solid lines.

Generally, the resonance shown in FIG. 4A is caused by a parasitic inductance and a bypass capacitor existing in series in each of the printed circuit board, the semiconductor package, and the semiconductor integrated circuit, and the resonance frequency is the series resonance frequency. The anti-resonance shown in FIG. 4A is caused by a bypass capacitor and a parasitic inductance arranged in parallel, and the frequency at which the anti-resonance occurs is the parallel resonance frequency. In the present embodiment, the series resonance frequency and the parallel resonance frequency are collectively referred to as a resonance frequency. The resonance point indicated by the solid line in FIG. 4A is caused by the series resonance of the capacitive element A and the capacitive element B, and the anti-resonance point is caused by the parallel resonance of the capacitive element A and the capacitive element B.

When a power saving technique called PSO that cuts off power supply to an unused circuit block in the LSI is applied, the capacitive element connected to the power supply and the parasitic inductance fluctuate, so that impedance as shown in FIG. The characteristic (resonance frequency) changes. The dotted line in FIG. 4B shows the impedance characteristic when the power supply to some circuit blocks is cut off, and the practice in FIG. 4B does not cut off the power supply to the circuit blocks. The impedance characteristic in the case is shown. The change in the impedance characteristic shown in FIG. 4B is an example.

Next, the detailed configuration and operation of the semiconductor integrated circuit 111 will be specifically described with reference to FIG. FIG. 5 is a diagram showing the semiconductor integrated circuit 111 from a physical viewpoint. In the present embodiment, the number of circuit blocks such as the first circuit block 109 and the second circuit block 110 will be described as 25. Further, the power saving management unit 101, the system control unit 102, the clock generation unit 105, the clock selection unit 106, and the storage unit 103 that stores the power mode-resonance frequency correspondence table are included in the chip top block 501 of FIG. I shall. Although not shown in the figure, power switches such as the first power switch 107 and the second power switch 108 are often placed around a circuit block that is a target of power shutoff. For example, a power switch that switches between conduction and non-conduction between the first circuit block 109 and the power supply unit 104 is placed around the block indicated as the first circuit block 109 in the drawing. Although the number of circuit blocks is set to 25 in this embodiment, the number is not particularly limited.

FIG. 6 is a diagram showing a power mode in which the power supply of each circuit block is in the ON/OFF state when the semiconductor integrated circuit 111 proceeds with processing. Note that FIG. 6 is an example of the power mode in this embodiment, and combinations of ON/OFF states are not comprehensively shown in FIG. 6. As an example in which the power of the two circuit blocks is turned on, in the power mode 4 shown in FIG. 6, the power of the two circuit blocks of the first circuit block and the second circuit block is in the on state, and other The power of the circuit block is off. As another example in which the power of the two circuit blocks is turned on, although not shown in FIG. 6, the power of the two circuit blocks, that is, the second circuit block and the eleventh circuit block, is in the on state, and There is a power mode in which the power supply of the circuit block is OFF.

The power saving management unit 101 controls the power ON/OFF state of each circuit block based on an instruction from the system control unit 102. Basically, only the circuit blocks required for the processing of the semiconductor integrated circuit 111 are controlled to be in the power-on state, and the circuit blocks not required for the processing are controlled to be in the power-off state.

FIG. 7 is an image diagram showing the semiconductor integrated circuit 111 when each circuit block of the semiconductor integrated circuit 111 is in a power-on state and a power-off state. Normally, when the power supply of each circuit block is in the ON state, the impedance of the entire semiconductor integrated circuit is lowered by the power supply mesh and decap cells (capacitance cells) that are spread over the entire surface of the semiconductor integrated circuit 111. Designed. However, when the power supply to some circuit blocks is turned off, the power supply mesh and the decap cells (capacitance cells) around the cutoff circuit block are separated from the power supply mesh that is spread over the entire circuit block. The impedance of the entire semiconductor integrated circuit becomes high. As an intuitive image, the gray-filled portion shown in FIG. 7 is an image of being hollowed out from the entire power supply mesh. The impedance of the semiconductor integrated circuit 111 is higher in the power-off state of the circuit blocks except the chip top block than in the power-on state.

FIG. 8 is a part of the power mode-resonance frequency correspondence table stored in the storage unit 103 of the semiconductor integrated circuit 111. Specifically, the power mode 1, the power mode 2, and the power mode 7 shown in FIG. The resonance frequency (resonance point/anti-resonance point) of the impedance at is shown. The value of the resonance frequency in the power mode-resonance frequency correspondence table is obtained by actual device evaluation or simulation.

Since the resonance frequency of the impedance of the semiconductor integrated circuit varies for each power mode, the power mode-resonance frequency correspondence table has a resonance frequency table corresponding to each power mode. However, if the resonance frequencies are the same or almost the same in different power modes, it is possible to use a common correspondence table for those power modes. Although not shown in FIG. 8, the power mode-resonance frequency correspondence table may include a half frequency of each resonance frequency and a one-third frequency of each resonance frequency.

FIG. 9 is a table showing an example of operating frequencies and operating voltages of clocks supplied to the circuit blocks in this embodiment. The operating frequency of the clock supplied to each circuit block has a predetermined operating frequency range according to whether each circuit book requires high-speed processing or low-speed processing. A plurality of processing modes corresponding to respective operating frequency ranges are preset. In this embodiment, a six-step processing mode including an ultra-high speed mode, a high speed mode, a normal mode, a low speed mode, an ultra low speed mode, and a power cutoff mode is prepared. If the number of processing modes is increased, power saving control can be realized with a finer granularity. However, if the number of processing modes is excessively increased, system control becomes complicated and system performance deteriorates. Therefore, it is necessary to estimate in advance the number of processing modes with the granularity that can achieve the power saving effect without degrading the performance.

The power saving management unit 101 refers to the power mode-resonance frequency correspondence table of FIG. 8 from the frequency range of the processing mode set in each circuit block, and generates the operating frequency of the circuit block different from the impedance resonance frequency. The clock generation unit 105 is instructed to do so. Here, in order to suppress power consumption, it is desirable to generate a clock having an operating frequency closest to the lower limit frequency of the frequency range of the processing mode set in each circuit block.

Further, the power supply unit 106 controls the voltage so as to supply the operating voltage corresponding to the operating frequency of the clock to the circuit block. FIG. 9 shows an example of the operating voltage in each processing mode and the operating voltage corresponding to each operating frequency. The operating frequency of the circuit block is the frequency of the clock supplied to the circuit block.

Further, in the present embodiment, in order to more reliably suppress the fluctuation of the power supply voltage, a clock having an operating frequency different from half the resonance frequency of the impedance is further generated and supplied to the circuit block. Here, it is further desirable to generate a clock having an operating frequency of which one-third of the resonance frequency of the impedance is different from the operating frequency of the circuit block and supply the clock to the circuit block.

Hereinafter, the detailed operation of the power saving management unit 101 will be described by taking as an example the case where the system control unit 102 controls the power mode of the semiconductor integrated circuit 111 from the power mode 1 state to the power mode 7 state shown in FIG. Will be described. The description will be given using the flowchart of FIG. Hereinafter, it is assumed that the flowchart is realized by the CPU executing the control program.

In step S1000, in the power mode 1 state, under the instruction of the system control unit 102, the power saving management unit 101 controls all the circuit blocks inside the semiconductor integrated circuit 111 to be in a power-on state, and performs all function processing. Is going.

In step S1001, the system control unit 102 prefetches the next process from the operation program, grasps the next process, and then sends an instruction to the power saving management unit 101. In the present embodiment, the description will be continued on the assumption that the next process is the power mode 7.

In step S1002, the power saving management unit 101 receives a command to shift to the power mode 7 from the system control unit 102. After that, the power saving management unit 101 uses an isolation cell (not shown) to cut off data exchange between the input/output ports of the sixth circuit block to the twenty-fifth circuit block and the outside.

Next, in step S1003, the power saving management unit 101 instructs a reset generation unit (not shown) to assert a reset signal to each of the sixth circuit block to the twenty-fifth circuit block.

Next, in step S1004, the power saving management unit 101 sends an instruction to the clock generation unit 105 to stop the clock supply from the sixth circuit block to the twenty-fifth circuit block, and cuts off the clock supply.

After performing the above steps, in step S1005, the power saving management unit 101 causes the storage unit 103 to determine the resonance point/anti-resonance point (resonance frequency of series resonance/resonance frequency of parallel resonance) in the power mode-resonance frequency correspondence table. ) To read the information. In the present embodiment, it is read from FIG. 8 that the resonance points in the power mode 7 are 411 MHz, 563 MHz, 751 MHz and 1028 MHz, and the anti-resonance points are 487 MHz, 657 MHz and 890 MHz. The data of the power mode-resonance frequency correspondence table may be written in the storage unit 103 when the power of the system is turned on. In addition, data can be rewritten as needed.

Subsequently, in step S1006, the power saving management unit 101 instructs the clock generation unit 105 to generate the clock having the operating frequency and the operating voltage shown in FIG. The clock generated by the clock generation unit 105 is supplied to the circuit block.

Here, as an example of the present embodiment, the system control unit 102 performs high-speed processing for the first circuit block 109 and the second circuit block 110, and for the third circuit block, the fourth circuit block, and the fifth circuit block. It is assumed that low-speed processing is required as a request. As described above, in the present embodiment, the first circuit block 109 and the second circuit block 110 are supplied with the operating frequency of 600 MHz/operating voltage of 1 V in the high speed mode. Further, it is assumed that the third circuit block, the fourth circuit block, and the fifth circuit block are supplied with an operating frequency of 250 MHz/operating voltage of 0.9 V in the low speed mode.

In the present embodiment, one criterion is that the operating frequency deviates by 5% or more from the resonance frequency and the frequency of half the resonance frequency. Note that the criterion of 5% is not fixed and must be adjusted according to the system specifications.

After that, in step S1007, the system control unit 102 communicates with each circuit block and grasps the processing status of each circuit block. In step S1008, the power saving management unit 101 sends an instruction to the power supply unit 104 to supply a desired operation voltage, and instructs the clock generation unit 105 to output a desired operation clock to each circuit block. To send. At the same time, the power saving management unit 101 controls the twenty-fifth power switch from the sixth power switch to cut off the power supply from the sixth circuit block to the twenty-fifth circuit block.

After the above steps S1002 to S1008, the transition from the power mode 1 to the power mode 7 is completed in step S1009.

The above is the description of the operation example of the case where the power saving management unit 101 performs the power saving control.

Continuing on, the system control unit 102 restores the power mode of the semiconductor integrated circuit 111 from the power mode 2 shown in FIG. 6 to the power mode 1 from the power saving mode. The detailed operation will be described. The description will be given using the flowchart of FIG.

In step S1100, in the power mode 2, the circuit blocks other than the chip top block inside the semiconductor integrated circuit 111 are in the power-off state, and the power saving management unit 101 and the system control unit 102 exchange commands at a low operating frequency. It is about the extent of going.

In step S1101, after the system control unit 102 recognizes from the operation program that the next process is the process of all the functions of all circuit blocks, the power control unit 101 instructs the power saving management unit 101 to switch the power mode to the power mode 1. Send a return command.

In step S1102, after the power saving management unit 101 receives the power restoration command, it first controls the reset signal generation unit (not shown) to assert the reset signal from the first circuit block to the twenty-fifth circuit block.

Next, in step S1103, the resonance frequency at the resonance point/anti-resonance point in the power mode-resonance frequency correspondence table is read from the storage unit 103. In the present embodiment, FIG. 8 shows an example of the resonance frequency in the power mode 1.

Next, in step S1104, the power saving management unit 101 determines an operating voltage/operating frequency. In this embodiment, since the resonance point and the anti-resonance point overlap at an operating frequency of 400 MHz or higher, the operating frequency of 250 MHz/operating voltage of 0.9 V in the low speed mode is set to the power saving management unit 101 for all circuit blocks. Is determined by.

Next, in step S1105, the power saving management unit 101 sends an instruction to the power supply unit 104 to supply a desired operating voltage. In addition, the power saving management unit 101 controls the twenty-fifth power switch from the first power switch to turn on the power of the first circuit block to the twenty-fifth circuit block.

Thereafter, in step S1106, the power saving management unit 101 waits until the operating voltage supplied to each circuit block reaches a desired value. When the operating voltage reaches a desired value, the power saving management unit 101 then sends an instruction to the clock generation unit 106 to output a desired operating clock to each circuit block.

After that, in step S1107, the power saving management unit 101 waits for the frequency of the operation clock to stabilize, and then controls the reset signal generation unit (not shown) to change the first circuit block to the twenty-fifth circuit block. Deassert the reset signal. Subsequently, in step S1108, the power saving management unit 101 controls an isolation cell (not shown) to release the data transfer block from the first circuit block to the outside of the twenty-fifth circuit block.

In the present embodiment, the step of performing the process of step S1108 is performed after step S1107, but the order is not limited, and the step of performing the process of step S1107 after step S1108 may be performed.

After the steps S1101 to S1108, the power recovery operation from the power mode 2 to the power mode 1 is completed in step S1109.

The above is the description of the operation example of the case where the power saving control unit 101 controls the power recovery.

That is, the power saving management unit 101 of the present embodiment acquires the resonance frequency of the impedance after the power saving mode transition, and the operating frequency of the circuit block after the power saving mode transition is the resonance frequency or ½ of the resonance frequency. Control so that the frequencies do not overlap. By controlling the semiconductor circuit of the present embodiment, voltage fluctuations can be suppressed, so that malfunction of the circuit due to power supply voltage fluctuations can be suppressed.

<Second Embodiment>
In the first embodiment, a power saving management unit 101, a power mode-resonance frequency correspondence table 103, a power supply unit 104, a clock generation unit 105, and a clock selection unit 106 are provided inside the semiconductor integrated circuit 111. However, these configurations may be provided outside the semiconductor integrated circuit 111 as long as they are configured in the same system. For example, the configuration shown in FIG. 12 may be used. A main system 1201 in FIG. 12 is a printed circuit board or a semiconductor package board. The power saving management unit 101, the power mode-resonance frequency correspondence table 103, the power supply unit 104, the clock generation unit 105, and the like are provided outside the semiconductor integrated circuit 1202.

Further, although the power supply unit 104 is placed inside the semiconductor integrated circuit 111 in the first embodiment, the power supply unit may be placed separately as shown in FIG. For example, the configuration shown in FIG. 13 may be used. The second power supply unit 1303 placed inside the semiconductor integrated circuit receives the voltage generated by the first power supply unit 1302 placed outside the semiconductor integrated circuit and generates a plurality of voltages.

<Other embodiments>
The present invention provides a program for implementing one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and one or more processors in the system or device read and execute the program. But it is possible. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101 Power Saving Management Unit 102 System Control Unit 103 Power Mode-Resonance Frequency Correspondence Table 104 Power Supply Unit 105 Clock Generation Unit 106 Clock Selection Unit 107 First Power Switch 108 Second Power Switch 109 First Circuit Block 110 Second Circuit Block 111 Semiconductor circuit integrated circuit 112 Nth power switch 113 Nth circuit block 501 Chip top block 1201 Main system 1202 Semiconductor integrated circuit 1301 when a power saving management unit is provided outside 1301 Semiconductor integrated circuit when a power supply unit is incorporated 1302 One power supply unit 1303 Second power supply unit

Claims (10)

A semiconductor integrated circuit having a plurality of circuit blocks and power supply means for supplying power to each of the circuit blocks,
A switch for switching each of the circuit blocks to a conductive state or a non-conductive state with the power supply means,
Of the plurality of circuit blocks, a storage unit that stores a resonance frequency of the impedance of the semiconductor integrated circuit, which corresponds to a combination of circuit blocks that are in a conductive state with the power supply unit,
An acquisition unit that acquires the resonance frequency of the impedance corresponding to the combination of the circuit blocks switched to the conductive state or the non-conductive state by the switch from the storage unit,
Generating means for generating a clock having an operating frequency different from the resonance frequency of the impedance acquired by the acquiring means and supplying the clock to the circuit block;
A semiconductor integrated circuit comprising: The storage means further stores a processing mode corresponding to a frequency range of an operating frequency of the clock supplied to each of the circuit blocks,
The semiconductor integrated circuit according to claim 1, wherein the generation unit generates a clock having an operating frequency different from the resonance frequency of the impedance in the frequency range. 3. The semiconductor integrated circuit according to claim 2, wherein the generating unit further generates a clock having an operating frequency closest to the lower limit value of the frequency range. 4. The power supply unit controls the operating voltage supplied to the circuit block according to the operating frequency of the clock generated by the generating unit. Semiconductor integrated circuit. 5. The generating unit further generates a clock having an operating frequency different from a half frequency of the resonance frequency of the impedance acquired by the acquiring unit. The semiconductor integrated circuit according to 1. The semiconductor integrated circuit according to claim 5, wherein the generating unit further generates a clock having an operating frequency different from a frequency of one third of the resonance frequency of the impedance acquired by the acquiring unit. 7. The semiconductor integrated device according to claim 1, wherein the plurality of circuit blocks are circuits that realize at least functions of image processing, compression/decompression processing, encryption/decryption processing, and communication processing. circuit. A semiconductor integrated circuit having a plurality of circuit blocks and power supply means for supplying power to each of the circuit blocks,
A switch for switching each of the circuit blocks to a conductive state or a non-conductive state with the power supply means,
Of the plurality of circuit blocks, a storage unit that stores the resonance frequency of the impedance of the semiconductor integrated circuit, which corresponds to a combination of circuit blocks that are in a conductive state with the power supply unit,
An acquisition unit that acquires the resonance frequency of the impedance corresponding to the combination of the circuit blocks switched to the conductive state or the non-conductive state by the switch from the storage unit,
Generating means for generating a plurality of clocks having different operating frequencies;
From the plurality of clocks generated by the generating means, selecting a clock having an operating frequency different from the resonance frequency of the impedance acquired by the acquiring means, and supplying to the circuit block,
A semiconductor integrated circuit comprising: A semiconductor integrated circuit having a plurality of circuit blocks, power supply means for supplying power to each of the circuit blocks, and a switch for switching each of the circuit blocks to a conductive state or a non-conductive state with the power supply means. Control method of
Of the plurality of circuit blocks, a storage step of storing in the storage means the resonance frequency of the impedance of the semiconductor integrated circuit, which corresponds to the combination of the circuit blocks that are in conduction with the power supply means,
An acquisition step of acquiring the resonance frequency of the impedance from the storage means when the circuit block is switched to the conductive state or the non-conductive state by the switch;
A generation step of generating a clock having an operating frequency different from the resonance frequency of the impedance acquired by the acquisition step and supplying the clock to the circuit block;
A method comprising: A semiconductor integrated circuit having a plurality of circuit blocks, power supply means for supplying power to each of the circuit blocks, and a switch for switching each of the circuit blocks to a conductive state or a non-conductive state with the power supply means. Control method of
Of the plurality of circuit blocks, a storage step of storing in the storage means the resonance frequency of the impedance of the semiconductor integrated circuit, which corresponds to the combination of the circuit blocks that are in conduction with the power supply means,
An acquisition step of acquiring the resonance frequency of the impedance from the storage means when the circuit block is switched to the conductive state or the non-conductive state by the switch;
A generation process for generating a plurality of clocks having different frequencies,
From the plurality of generated clocks, selecting a clock of an operating frequency different from the acquired resonance frequency of the impedance, and supplying to the circuit block,
A method comprising:

Images