JP6732413B2 - Liquid crystal display - Google Patents

Description

The present invention relates to a liquid crystal display device.

2. Description of the Related Art Conventionally, there is known a holographic memory that records an information signal by irradiating an optical information recording medium with signal light modulated by a spatial light modulator such as LCOS (Liquid Crystal On Silicon) to form a hologram. For the spatial light modulator, for example, a liquid crystal display device using a liquid crystal cell is used. In a liquid crystal display device, a certain high voltage is required to drive a liquid crystal cell, and therefore a pixel circuit that drives the liquid crystal cell is required to have a configuration capable of outputting a high voltage drive signal to the liquid crystal cell.

In addition, FLC (Ferroelectric Liquid Crystal) has a large reversal current, and pixel data cannot be held in a DRAM (Dynamic Random Access Memory). ) Cells are used. In addition, in a liquid crystal display device using an SRAM for a pixel circuit, a configuration is known in which a level shifter is provided in a horizontal driver to operate a bit line and a pixel at a high voltage (for example, refer to Patent Document 1 below).

JP, 2014-215496, A (Drawing 1)

However, in the above-described conventional technique, for example, the entire SRAM of the pixel circuit is operated at a high voltage, and therefore a high breakdown voltage element is used for each transistor of the SRAM of the pixel circuit, which increases the area per pixel. There is. Further, for example, since the voltage amplitude of the bit line becomes large, there is a problem that the power consumption becomes large due to the charging and discharging of the bit line.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of reducing power consumption while suppressing an increase in area per pixel in order to solve the above-mentioned problems of the related art.

In order to solve the above-mentioned problems and achieve the object, a liquid crystal display device according to the present invention is a CMOS (Complementary Metal Oxide Semiconductor) type SRAM (Static Random Access Memory) cell provided for each display pixel. A protection MOS transistor is provided between the load resistance circuit section and the storage circuit section, and the transistor of the storage circuit section is resistant to a higher voltage than the transistors of the load resistance circuit section and the protection MOS transistor. And a liquid crystal display section that performs liquid crystal display based on a signal output from between the load resistance circuit section and the protection MOS transistor in each of the SRAM cells.

As a result, the maximum voltage applied to the memory circuit unit in the SRAM can be lowered while outputting a high voltage signal required for liquid crystal display to the liquid crystal display unit, and a small element can be used in the memory circuit unit in the SRAM. Become.

According to one aspect of the present invention, it is possible to reduce power consumption while suppressing an increase in area per pixel.

FIG. 1 is a diagram showing an example of a liquid crystal drive circuit according to an embodiment. FIG. 2 is a diagram showing an example of a liquid crystal display device to which the liquid crystal drive circuit according to the embodiment is applied. FIG. 3 is a diagram illustrating an example of a gate-grounded circuit imitating the pixel circuit according to the embodiment. FIG. 4 is a diagram showing an example of control of the voltage of the drive signal according to the embodiment. FIG. 5 is a diagram showing another configuration example 1 of the liquid crystal drive circuit according to the embodiment. FIG. 6 is a diagram showing another configuration example 2 of the liquid crystal drive circuit according to the embodiment. FIG. 7 is a diagram showing another configuration example 3 of the liquid crystal drive circuit according to the embodiment.

Embodiments of a liquid crystal display device according to the present invention will be described in detail below with reference to the drawings.

(Embodiment)
(Liquid crystal drive circuit according to the embodiment)
FIG. 1 is a diagram showing an example of a liquid crystal drive circuit according to an embodiment. As shown in FIG. 1, the liquid crystal drive circuit 100 according to the embodiment includes a plurality of pixel circuits 110, a replica circuit 120, and a differential amplifier 130. The liquid crystal drive circuit 100 is a circuit that drives a liquid crystal display unit using a liquid crystal cell (for example, the liquid crystal display unit 210 shown in FIG. 2) to display an image on the liquid crystal display unit.

The pixel circuit 110 is a circuit that is provided for each pixel of the liquid crystal display unit driven by the liquid crystal drive circuit 100 and that drives the pixel of the liquid crystal display unit. In FIG. 1, one pixel circuit 110 of the pixel circuits 110 provided for each pixel will be described, but the same applies to the other pixel circuits 110 of the pixel circuits 110 provided for each pixel.

The pixel circuit 110 includes eight transistors (MOS transistors 111 to 118). In the pixel circuit 110, a CMOS (Complementary Metal Oxide Semiconductor) type SRAM cell is configured by six MOS transistors (MOS transistors 111 to 116). Such an SRAM may be called a full CMOS type SRAM cell or a full CMOS type SRAM, for example. The MOS transistors 111, 112, 115 and 116 are N-type MOS transistors. The MOS transistors 113 and 114 are P-type MOS transistors.

In the pixel circuit 110, the MOS transistors 111 and 113 form a first inverter. In the pixel circuit 110, the MOS transistors 112 and 114 form a second inverter. Then, the SRAM cell is configured by connecting the input of the first inverter and the output of the second inverter, and connecting the output of the first inverter and the input of the second inverter.

In the SRAM cell, flip-flops are formed by the MOS transistors 111 and 112 as drive transistors and the MOS transistors 113 and 114 as load transistors. Further, in the SRAM cell, the MOS transistors 115 and 116 are used as selection transistors.

Further, the MOS transistors 113 and 114 operate as load transistors to form a load resistance circuit section 131 that functions as a load between the power supply and the storage circuit section 132 in the SRAM cell. Further, in the MOS transistors 111, 112, 115, and 116, the MOS transistors 111 and 112 operate as drive transistors, and the MOS transistors 115 and 116 operate as selection transistors, thereby storing information in the SRAM cell. 132 is formed.

The latch node A is the output of the first inverter formed by the MOS transistors 111 and 113, and the input of the second inverter formed by the MOS transistors 112 and 114. The latch node B is the output of the second inverter formed by the MOS transistors 112 and 114, and the input of the first inverter formed by the MOS transistors 111 and 113.

The paired bit line (bit) and inverted bit line (/bit) are bit lines that have mutually opposite logic states (for example, "H" and "L"). “H” is a voltage higher than “L”. “L” is a voltage lower than “H”. For example, "H" and "L" are signals having different polarities.

When the latch node B is "H", "L" is output to the latch node A. As a result, the second inverter formed by the MOS transistors 112 and 114 keeps the latch node B at the original "H". On the other hand, when the latch node B is "L", "H" is output to the latch node A. As a result, the second inverter formed by the MOS transistors 112 and 114 keeps the latch node B at the original "L".

In order to write "H" in the pixel circuit 110, the word line (word line) is set to "H" and the bit lines (bit) are set to "H" while the gates of the MOS transistors 115 and 116 are opened (turned on). " As a result, the inverted bit line (/bit) becomes "L", the latch node A becomes "L", and the latch node B becomes "H".

On the contrary, in order to write "L" in the pixel circuit 110, the word line is set to "H" and the bit line (bit) is set to "L" with the gates of the MOS transistors 115 and 116 opened. As a result, the inverted bit line (/bit) becomes "H", the latch node A becomes "H", and the latch node B becomes "L".

After the value is written in the pixel circuit 110, the word line is set to “L” and the gates of the MOS transistors 115 and 116 are closed (turned off), so that the written value is stabilized by the flip-flop. And held.

Further, in particular, the pixel circuit 110 includes protection MOS transistors 117 and 118 (shield elements). The MOS transistor 117 is provided between the MOS transistor 111 and the MOS transistor 113. The MOS transistor 118 is provided between the MOS transistor 112 and the MOS transistor 114. The gates of the MOS transistors 117 and 118 are connected to the output of the differential amplifier 130. In the example shown in FIG. 1, the MOS transistors 117 and 118 are N-type MOS.

The output terminal 119 (out) is provided between the drain of the MOS transistor 114 and the source of the MOS transistor 118. The value written in the pixel circuit 110 is output as a drive signal from the output terminal 119 to the pixel of the liquid crystal display unit. The voltage of this drive signal becomes the voltage VDDH of the voltage source connected to the sources of the MOS transistors 113 and 114. The voltage VDDH is a voltage required to drive the liquid crystal in the liquid crystal display section.

As described above, in the liquid crystal drive circuit 100 according to the embodiment, the P-type MOS transistors (MOS transistors 113, 114) and the N-type MOS transistors (MOS transistors 111, 112, 115, 116) that form the SRAM cell are formed. Protective transistors (MOS transistors 117 and 118) are provided between them.

As the P-type MOS transistors (MOS transistors 113 and 114) and the protection transistors (MOS transistors 117 and 118), transistors having relatively high resistance to high voltage (deterioration or destruction resistance) are used. In addition, the N-type MOS transistors (MOS transistors 111, 112, 115, 116) have P-type MOS transistors (MOS transistors 113, 114) and protection transistors (MOS transistors 117) that have high voltage resistance (breakdown resistance). , 118). The resistance of the transistor to high voltage can be adjusted by, for example, the device structure itself such as the gate oxide film thickness and the concentration of the well, and the design such as the width of the gate.

For example, the MOS transistors 113, 114, 117 and 118 are high breakdown voltage elements that can sufficiently withstand the maximum voltage VDDH of the drive signal output from the output terminal 119. As a result, the drive signal output from the output terminal 119 is divided between the voltage VDDH and GND (0 [V]) while avoiding the destruction of the MOS transistors 113, 114, 117, 118 due to the maximum voltage VDDH of the drive signal. It can be a high voltage signal that swings between.

On the other hand, the MOS transistors 111, 112, 115 and 116 are standard breakdown voltage elements that cannot sufficiently withstand the maximum voltage VDDH of the drive signal output from the output terminal 119. As a result, the MOS transistors 111, 112, 115, 116 can be realized by elements smaller than the MOS transistors 113, 114, 117, 118. Therefore, the number of high breakdown voltage elements can be reduced and the pixel circuit 110 can be downsized as compared with the case where high breakdown voltage elements are used for all of the MOS transistors 111 to 118, for example.

Further, by providing the MOS transistors 117 and 118 as shield elements, the maximum VDDH (first voltage) current flows through the P-type MOS transistors 113 and 114, while the N-type MOS transistors 111 and 112, The maximum voltage applied to 115 and 116 can be limited to VDD (second voltage) lower than VDDH. For example, even if the pixel circuit 110 latches "H", the latch nodes A and B can be suppressed to the voltage VDD lower than the voltage VDDH, and the destruction of the MOS transistors 111, 112, 115 and 116 can be avoided.

Therefore, it becomes possible to miniaturize the MOS transistors 111, 112, 115, 116 while driving the pixels of the liquid crystal display unit connected to the output terminal 119 with a high voltage (VDDH). Therefore, each of the plurality of pixel circuits 110 can be downsized, and the liquid crystal drive circuit 100 can be downsized.

Further, the maximum voltage of the control signal input to the bit line or word line of the liquid crystal drive circuit 100 can be set to the voltage VDD lower than the voltage VDDH. As a result, the power supply of the peripheral circuit (for example, the peripheral circuit 230 shown in FIG. 2) that transfers the control signal to the bit line and the word line of the liquid crystal drive circuit 100 is supplied with the voltage VDD lower than the voltage VDDH required for driving the liquid crystal display unit. Can be used. Therefore, it is possible to reduce the power consumption in the peripheral circuit that transfers the control signal to the bit line and the word line of the liquid crystal drive circuit 100.

As described above, according to the liquid crystal drive circuit 100, a high-voltage drive signal required for liquid crystal display is output to the liquid crystal display unit and is applied to the N-type MOS transistors 111, 112, 115, and 116 in the CMOS SRAM. It is possible to reduce the maximum voltage for the MOS transistors 111, 112, 115 and 116 and use small elements. Therefore, it is possible to reduce power consumption while suppressing an increase in area per pixel.

The replica circuit 120 and the differential amplifier 130 operate as a bias circuit that controls the gate voltages of the MOS transistors 117 and 118. The replica circuit 120 is a replica circuit of the pixel circuit 110. The differential amplifier 130 is an adjustment circuit that adjusts the gate voltages of the MOS transistors 117 and 118 of the pixel circuit 110 using the replica circuit 120.

Specifically, the replica circuit 120 includes MOS transistors 121 to 128 that form a CMOS type SRAM cell. The MOS transistors 121 to 128 correspond to the MOS transistors 111 to 118 of the pixel circuit 110, respectively, and have the same electrical characteristics as the MOS transistors 111 to 118, respectively.

Further, a power supply of a voltage VDD lower than the voltage VDDH is connected to each gate of the MOS transistors 125 and 126. Further, a power supply of the voltage VDD is connected to a position corresponding to a bit line (bit) in the SRAM cell composed of the MOS transistors 121 to 128. Further, the position corresponding to the inverted bit line (/bit) in the SRAM cell formed by the MOS transistors 121 to 128 is grounded. That is, the SRAM cell configured by the MOS transistors 121 to 128 is a replica circuit that imitates a state in which “H” is written in the SRAM of the pixel circuit 110.

The differential amplifier 130 adjusts the gate voltages of the MOS transistors 127 and 128 of the replica circuit 120 and the MOS transistors 117 and 118 of the pixel circuit 110. Specifically, the differential amplifier 130 outputs a voltage indicating the difference between the voltage of the latch node C of the replica circuit 120 and the voltage VDD. The latch node C of the replica circuit 120 is a node corresponding to the latch node B of the pixel circuit 110. The output from the differential amplifier 130 is input to the gates of the MOS transistors 127 and 128 of the replica circuit 120 and the MOS transistors 117 and 118 of the pixel circuit 110.

As a result, the MOS transistors 127 and 128 of the replica circuit 120 are controlled so that the voltage of the latch node C of the replica circuit 120 and the voltage VDD become equal. Further, the MOS transistors 117 and 118 of the pixel circuit 110 are controlled so that the latch node B becomes the voltage VDD when “H” is latched in the pixel circuit 110.

Therefore, it is possible to suppress errors and fluctuations in the voltages at the latch nodes A and B due to manufacturing errors (for example, variations between wafers and lots) in the plurality of pixel circuits 110 and variations in the power supply voltage. Therefore, the liquid crystal drive circuit 100 can be stably operated.

As described above, in the differential amplifier 130, the maximum voltage (the voltage of the latch node C) between the MOS transistors 121, 122, 125, 126 of the replica circuit 120 and the MOS transistors 127, 128 of the replica circuit 120 is the maximum. The gate voltages of the MOS transistors 127 and 128 are adjusted so as to approach VDD. Further, the differential amplifier 130 adjusts the gate voltage of the MOS transistors 117 and 118 to the same gate voltage as the gate voltage of the MOS transistors 127 and 128. As a result, the maximum voltage of the latch node B in the pixel circuit 110 can be accurately controlled to the voltage VDD, and the operation of the liquid crystal drive circuit 100 can be stabilized.

Further, the replica circuit 120 and the differential amplifier 130 are shared by a plurality of pixel circuits 110 of the pixel circuits 110 of the liquid crystal drive circuit 100. That is, the set of the replica circuit 120 and the differential amplifier 130 controls the gate voltages of the MOS transistors 117 and 118 of the plurality of pixel circuits 110.

For example, one set of replica circuit 120 and differential amplifier 130 is provided for all pixel circuits 110 of the liquid crystal drive circuit 100. Alternatively, the pixel circuit 110 of the liquid crystal drive circuit 100 may be divided into a plurality of groups, and the replica circuit 120 and the differential amplifier 130 may be provided for each group. As a result, it is possible to suppress an increase in the size and power consumption of the device due to the provision of the replica circuit 120 and the differential amplifier 130.

(Liquid crystal display device to which the liquid crystal drive circuit according to the embodiment is applied)
FIG. 2 is a diagram showing an example of a liquid crystal display device to which the liquid crystal drive circuit according to the embodiment is applied. The liquid crystal drive circuit 100 shown in FIG. 1 can be applied to the liquid crystal display device 200 shown in FIG. 2, for example. As shown in FIG. 2, the liquid crystal display device 200 includes a liquid crystal display unit 210, a bias circuit 220, and a peripheral circuit 230.

The liquid crystal display unit 210 is, for example, a liquid crystal display unit having a plurality of signal lines and a plurality of scanning lines, and pixels are arranged in a matrix corresponding to the intersections of the plurality of signal lines and the plurality of scanning lines. Further, the liquid crystal display unit 210 displays an image corresponding to each signal input to the plurality of signal lines and the plurality of scanning lines by each pixel in a matrix.

In the liquid crystal display unit 210, the pixel circuits 110 shown in FIG. 1 are provided in a matrix as a circuit for driving each pixel. Each of the pixel circuits 110 included in the liquid crystal display unit 210 drives each pixel of the liquid crystal display unit in the liquid crystal display device 200.

For example, the liquid crystal display unit 210 may be a liquid crystal panel such as LCOS. For example, a column-direction column line in the liquid crystal display unit 210 is a signal line, and a row-direction row line in the liquid crystal display unit 210 is a scanning line.

In the bias circuit 220, a replica circuit 120 and a differential amplifier 130 are provided for each row of the liquid crystal display section 210 so as to be connected to the plurality of pixel circuits 110 provided in the row. For example, the nth replica circuit 120 and the nth differential amplifier 130 in the bias circuit 220 are connected to the gates of the MOS transistors 117 and 118 of the plurality of pixel circuits 110 in the nth row of the liquid crystal display unit 210. It

However, the relationship between the pixel circuit 110 and the replica circuit 120 and the differential amplifier 130 is not limited to this. For example, only one set of the replica circuit 120 and the differential amplifier 130 is provided in the bias circuit 220, and the replica circuit 120 and the differential amplifier 130 are provided. All the pixel circuits 110 of the liquid crystal display section 210 may be connected to the amplifier 130. Further, the replica circuit 120 and the differential amplifier 130 may be provided for each column of the liquid crystal display unit 210.

Data and a clock for displaying an image on the liquid crystal display unit 210 are input to the peripheral circuit 230. For example, the peripheral circuit 230 includes a timing control unit 231, a row selection unit/row driver 232, a column selection unit 233, and a column driver 234.

The timing control unit 231 controls each operation timing in the row selection unit/row driver 232, the column selection unit 233, and the column driver 234 based on the clock input to the peripheral circuit 230.

The row selection unit/row driver 232 inputs a signal to one of the scanning lines provided for each row of the liquid crystal display unit 210 under the control of the timing control unit 231, thereby causing the liquid crystal display unit The line to be rewritten in 210 is set.

The column selection unit 233 outputs, to the column driver 234, each data signal input to the signal line provided for each column of the liquid crystal display unit 210 based on the data input to the peripheral circuit 230. The column driver 234 inputs each data signal output from the column selection unit 233 to a signal line provided for each column of the liquid crystal display unit 210. As a result, the liquid crystal display unit 210 is instructed to rewrite each column. At this time, the pixels of the liquid crystal display unit 210 that are actually rewritten are the pixels of each column in the row set as the rewriting target by the row selection unit/row driver 232.

The voltage VDDH required for driving the liquid crystal of each pixel is supplied to the liquid crystal display unit 210. The bias circuit 220 is supplied with a voltage VDDH and a voltage VDD which is lower than the voltage VDDH and which does not damage the MOS transistors 111, 112, 115 and 116 shown in FIG. 1, for example. The voltage VDD is supplied to the peripheral circuit 230.

The liquid crystal display device 200 shown in FIG. 2 is a liquid crystal display device that displays an image using the liquid crystal display unit 210, but has a side surface as a spatial light modulator that spatially modulates light using the liquid crystal display unit 210. .. For example, in a holographic memory that records information by irradiating an image on an optical information recording medium to form a hologram, the liquid crystal display device 200 is used as a spatial light modulator that generates an image by spatially modulating light. You can However, the liquid crystal display device 200 is not limited to the holographic memory, but can be applied to, for example, a projector or an electronic viewfinder.

(Gate-grounded circuit simulating the pixel circuit according to the embodiment)
FIG. 3 is a diagram illustrating an example of a gate-grounded circuit imitating the pixel circuit according to the embodiment. In FIG. 3, the principle of shielding the MOS transistors 111, 112, 115, 116 from the high voltage by the MOS transistors 117, 118 will be described. The simulation circuit 300 shown in FIG. 3 is a gate-grounded circuit imitating one pixel circuit 110 and one replica circuit 120 in the liquid crystal drive circuit 100 shown in FIG. The simulation circuit 300 includes a transistor 301, a variable resistor 302, a load 303, and a voltage source 304.

The transistor 301 corresponds to the MOS transistors 117 and 118 (shield element) shown in FIG. The variable resistor 302 (Rs) connected to the source (s) of the transistor 301 corresponds to the MOS transistors 111 and 112 shown in FIG. The change in the resistance value Rs of the variable resistor 302 (the source resistance of the transistor 301) corresponds to the change in the signal latched by the pixel circuit 110 shown in FIG. The load 303 connected to the drain (d) of the transistor 301 corresponds to the MOS transistors 113 and 114 shown in FIG.

The DC voltage source 304 (Vb) connected to the gate (g) of the transistor 301 corresponds to the bias circuit including the replica circuit 120 and the differential amplifier 130 shown in FIG. The node 305 is a node connected between the source of the transistor 301 and the variable resistor 302, and corresponds to the latch nodes A and B (input/output units of memory cells) shown in FIG.

In this way, a case where the gate voltage of the transistor 301 is fixed to the voltage Vb by the voltage source 304 and the source resistance of the transistor 301 is changed by the variable resistor 302 will be described.

When the source resistance Rs is high, current flows through the transistor 301 until the voltage between the gate and the source of the transistor 301 becomes approximately equal to the threshold voltage VTH of the transistor 301. Therefore, the voltage Vs at the node 305 becomes Vs≈Vb−VTH. When the source resistance Rs is low, the voltage between the gate and the source of the transistor 301 increases and the transistor 301 becomes conductive. Therefore, the voltage Vs at the node 305 becomes Vs≈0.

That is, by appropriately setting the voltage Vb from the voltage source 304, the change width of the voltage Vs at the node 305 can be limited. In the pixel circuit 110 shown in FIG. 1, when the threshold voltage of the MOS transistors 117 and 118 is VTH, the voltage Vb from the voltage source 304 is Vb≈VDD+VTH.

For example, in the pixel circuit 110 shown in FIG. 1, the MOS transistors 117 and 118 as shield elements corresponding to the transistor 301 are the P-type MOS (MOS transistors 113 and 114) and the N-type MOS (MOS transistors 111 and 112, 115, 116). As a result, the voltage in the low voltage system (for example, the MOS transistors 111, 112, 115, 116) of the pixel circuit 110 fluctuates between 0 and VDD [V]. Therefore, the low voltage system of the pixel circuit 110 can be protected from the high voltage while maintaining the latch function of the pixel circuit 110.

Further, since the sources of the MOS transistors 117 and 118 have the function of the low voltage SRAM, they can be directly connected to the low voltage peripheral circuits. For example, the pixel circuit 110 can be directly connected to a peripheral circuit (for example, the peripheral circuit 230 shown in FIG. 2) that controls the pixel circuit 110 without using a level conversion circuit or the like. Therefore, for example, the liquid crystal display device 200 shown in FIG. 2 can be downsized. In addition, it is possible to suppress an increase in power consumption.

Further, since the output terminals 119 on the drain side of the MOS transistors 117 and 118 can output a high voltage (0 to VDDH [V]), for example, a level conversion circuit or the like is not provided between the output terminals 119 and the display pixels. However, it becomes possible to directly drive the display pixels. Therefore, for example, the liquid crystal display device 200 shown in FIG. 2 can be downsized. In addition, it is possible to suppress an increase in power consumption.

(Control of Voltage of Drive Signal According to Embodiment)
FIG. 4 is a diagram showing an example of control of the voltage of the drive signal according to the embodiment. Here, a case where the liquid crystal display device 200 shown in FIG. 2 is applied to a holographic memory will be described. In FIG. 4, the horizontal axis represents time.

The control signal 410 is a control signal input from the peripheral circuit 230 shown in FIG. 2 to the liquid crystal display unit 210. The maximum voltage of the control signal 410 is the voltage VDD (1.8 [V] as an example), which is lower than the voltage VDDH. The drive signal 420 is a drive signal applied to the display pixel from the output terminal 119 shown in FIG. The maximum voltage of the drive signal 420 is VDDH (5 [V] as an example).

Further, as shown in FIG. 4, the maximum voltage of the drive signal 420 may be variable. The data transfer period 401 is a period in which data is transferred from the peripheral circuit 230 shown in FIG. 2 to the plurality of pixel circuits 110 of the liquid crystal display unit 210, that is, a data rewriting period in the SRAM. The liquid crystal response period 402 is a period in which the liquid crystal of the display pixel responds according to each value read from the plurality of pixel circuits 110. The recording medium writing period 403 is a period in which the information displayed by the display pixels is written in the recording medium of the holographic memory.

When the liquid crystal display device 200 is applied to a holographic memory, a data transfer period 401, a liquid crystal response period 402, and a recording medium writing period 403 are periodically repeated. At this time, in the liquid crystal display device 200, as shown in FIG. 4, the maximum voltage VDDH of the drive signal 420 is set to the voltage required to drive the display pixels in the liquid crystal response period 402 and the recording medium writing period 403 (as an example, The voltage may be lower than the voltage required to drive the display pixels during the data transfer period 401 (1.8 [V] as an example), while the voltage is 5 [V]).

As a result, the maximum voltage VDDH of the drive signal 420 is lowered to the same level as the power supply voltage VDD of the peripheral circuit during the data transfer, and the maximum voltage VDDH of the drive signal 420 is returned to the voltage required for driving the display pixel after the data transfer. be able to. As a result, the shoot-through current during data transfer can be suppressed and the power consumption of the liquid crystal display device 200 can be reduced.

Even when the voltage VDDH of the drive signal 420 is variable, the voltage VDDH input to the differential amplifier 130 may be a constant voltage (5 [V] as an example). This makes it possible to stabilize the operation.

In this way, the maximum voltage VDDH applied to the P-type MOS transistors 113 and 114 is displayed during the liquid crystal display based on the signal read from the pixel circuit 110 (the liquid crystal response period 402 and the recording medium writing period 403). ) Is controlled to a first voltage (5 [V] as an example) higher than the voltage VDD, and a third voltage (one example) lower than the first voltage during a signal transfer period (data transfer period 401) to the pixel circuit 110. For example, a control circuit for controlling the voltage to 1.8 [V] may be provided in the liquid crystal display device 200.

As a result, the shoot-through current at the time of data transfer to the pixel circuit 110 can be suppressed, and the power consumption of the liquid crystal display device 200 can be reduced. A control circuit for controlling the maximum voltage VDDH applied to the P-type MOS transistors 113 and 114 can be provided in the peripheral circuit 230 shown in FIG. 2, for example.

Although the case where the voltage VDDH of the drive signal 420 is variable has been described with reference to FIG. 4, the voltage VDDH of the drive signal 420 may be constant (5 [V] as an example). Also in this case, the power consumption in the peripheral circuit can be reduced.

(Other Configuration Example of Liquid Crystal Driving Circuit According to Embodiment)
FIG. 5 is a diagram showing another configuration example 1 of the liquid crystal drive circuit according to the embodiment. 5, the same parts as those shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Although the configuration in which the gate voltage of the MOS transistors 117 and 118 of the pixel circuit 110 is controlled using the replica circuit 120 and the differential amplifier 130 has been described with reference to FIG. 1, the configuration is not limited to such a configuration.

For example, as shown in FIG. 5, the liquid crystal drive circuit 100 may include a bias circuit 510 instead of the replica circuit 120 and the differential amplifier 130 shown in FIG. The bias circuit 510 includes a transistor 511, a DC constant current source 512, and a DC voltage source 513.

The transistor 511 is a MOS transistor provided between the constant current source 512 and the voltage source 513. The gate of the transistor 511 is connected to the constant current source 512 and the gates of the MOS transistors 117 and 118 of the pixel circuit 110. As a result, a constant gate voltage can be supplied to each gate of the MOS transistors 117 and 118.

In the configuration shown in FIG. 5, as in the configuration shown in FIG. 1, it is possible to reduce the power consumption while suppressing an increase in the area per pixel. Further, in the configuration shown in FIG. 5, the maximum drive voltage may be variable as shown in FIG.

FIG. 6 is a diagram showing another configuration example 2 of the liquid crystal drive circuit according to the embodiment. This example corresponds to, for example, a liquid crystal drive circuit formed on an N-type silicon substrate. 6, parts that are functionally similar to the parts shown in FIG. 1 are assigned the same reference numerals and explanations thereof are omitted. In the configuration shown in FIG. 6, in the pixel circuit 110, the MOS transistors 111 and 112 are connected to the power supply (VSSH), and the MOS transistors 113 and 114 are grounded. In this case, as protection MOS transistors, P-type MOS transistors 611 and 612 are provided instead of the N-type MOS transistors 117 and 118 shown in FIG. The protection MOS transistor 611 is connected between the MOS transistor 111 and the MOS transistors 113 and 115, and the protection MOS transistor 612 is connected between the MOS transistor 112 and the MOS transistors 114 and 116.

Also, in the replica circuit 120, P-type MOS transistors 621 and 622 are provided instead of the N-type MOS transistors 127 and 128 shown in FIG. 1 as protection MOS transistors. The protection MOS transistor 621 is connected between the MOS transistor 121 and the MOS transistors 123 and 125, and the protection MOS transistor 622 is connected between the MOS transistor 122 and the MOS transistors 124 and 126.

The output terminal 119 of the pixel circuit 110 is provided between the MOS transistor 112 and the MOS transistor 612. Further, the inverted signal (/WL) of the word line is input to each gate of the MOS transistors 115 and 116.

In the configuration shown in FIG. 6 as well, similar to the configuration shown in FIG. 1, it is possible to reduce the power consumption while suppressing the increase in the area per pixel and stabilize the operation. Further, in the configuration shown in FIG. 6, as shown in FIG. 5, a bias circuit 510 (see FIG. 5) may be provided instead of the replica circuit 120 and the differential amplifier 130. Further, in the configuration shown in FIG. 6, the maximum drive voltage may be variable as shown in FIG.

FIG. 7 is a diagram showing another configuration example 3 of the liquid crystal drive circuit according to the embodiment. 7, the same parts as those shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 7, in the pixel circuit 110, load resistances 711 and 712 are provided in place of the MOS transistors 113 and 114 in the load resistance circuit unit 131 shown in FIG. Good. In this case, also in the replica circuit 120, load resistors 721 and 722 are provided instead of the MOS transistors 123 and 124.

In the configuration shown in FIG. 7 as well, similar to the configuration shown in FIG. 1, it is possible to reduce the power consumption while suppressing an increase in the area per pixel and stabilize the operation. Further, in the configuration shown in FIG. 7, the maximum drive voltage may be variable as shown in FIG. Further, in the configuration shown in FIG. 7, as shown in FIG. 5, a bias circuit 510 (see FIG. 5) may be provided instead of the replica circuit 120 and the differential amplifier 130.

Further, in the configuration shown in FIG. 7, as shown in FIG. 6, the MOS transistors 111 and 112 may be connected to the power supply (VSSH) and the load resistors 711 and 712 may be grounded. In this case, P-type MOS transistors 611 and 612 are provided as the protection MOS transistors instead of the N-type MOS transistors 117 and 118, and P-type MOS transistors are provided as the protection transistors instead of the MOS transistors 127 and 128. 621 and 622 are provided.

As described above, according to the liquid crystal display device, it is possible to reduce power consumption while suppressing an increase in area per pixel.

INDUSTRIAL APPLICABILITY As described above, the liquid crystal display device according to the present invention is useful for a liquid crystal display device that displays an image using a liquid crystal panel such as LCOS, and particularly, an optical information recording medium is irradiated with the image to form a hologram. This makes it suitable for holographic memory that records information.

100 Liquid crystal drive circuit 110 Pixel circuit 111-118, 121-128, 611, 612, 621, 622 MOS transistor 119 Output terminal 120 Replica circuit 130 Differential amplifier 131 Load resistance circuit part 132 Storage circuit part 200 Liquid crystal display device 210 Liquid crystal display Part 220,510 Bias circuit 230 Peripheral circuit 231 Timing control part 232 Row selection part/row driver 233 Column selection part 234 Column driver 300 Simulation circuit 301,511 Transistor 302 Variable resistance 303 Load 304,513 Voltage source 305 Node 401 Data transfer period 402 Liquid crystal response period 403 Recording medium writing period 410 Control signal 420 Drive signal 512 Constant current source 711, 712, 721, 722 Load resistance

Claims (5)

A CMOS (Complementary Metal Oxide Semiconductor) type SRAM (Static Random Access Memory) cell provided for each display pixel,
A protection for limiting the maximum voltage applied to the storage circuit unit to a second voltage lower than the first voltage between the load resistance circuit unit to which the maximum voltage of the first voltage is applied and the storage circuit unit. Has a MOS transistor for
An SRAM cell using, as a transistor of the memory circuit section, a transistor having lower resistance to a high voltage than the transistor of the load resistance circuit section and the protection MOS transistor,
A liquid crystal display section for performing liquid crystal display based on a signal output from between the load resistance circuit section and the protection MOS transistor in each of the SRAM cells;
A replica circuit of the SRAM cell,
The protection circuit is configured so that the maximum voltage between the transistor of the replica circuit corresponding to the memory circuit section and the transistor of the replica circuit corresponding to the protection MOS transistor approaches the second voltage. The gate voltage of the transistor of the replica circuit corresponding to the MOS transistor is adjusted so that the same gate voltage as the gate voltage of the transistor of the replica circuit corresponding to the MOS transistor for protection is applied to the gate of the MOS transistor for protection in the SRAM cell. An adjusting circuit for applying a voltage,
A liquid crystal display device comprising: The liquid crystal display device according to claim 1, wherein a P-type MOS transistor is used for the load resistance circuit section, and an N-type MOS transistor is used for the storage circuit section. The liquid crystal display device according to claim 1, wherein an N-type MOS transistor is used for the load resistance circuit section, and a P-type MOS transistor is used for the storage circuit section. The liquid crystal display device according to claim 1, wherein the replica circuit and the adjustment circuit are circuits shared by a plurality of SRAM cells among the SRAM cells. A maximum voltage applied to the load resistance circuit unit is controlled to the first voltage during the liquid crystal display period, and a third voltage lower than the first voltage during the signal transfer period to the SRAM cell. The liquid crystal display device according to claim 1 , further comprising a control circuit for controlling the liquid crystal display device.

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