JP6736136B2 - Amusement machine - Google Patents

Description

The present invention is mainly intended for gaming machines such as rotating body type gaming machines and pachinko gaming machines used for sales of pachinko parlors as defined in Article 2, Paragraph 1 of the Act on Regulations of Customs Business and Adequacy of Business. Regarding

In Patent Document 1, when the power is turned on, it is confirmed whether or not the final storage content stored in the backup RAM area is normal based on the checksum stored in the backup RAM area when the power is turned off. In this case, a technique for performing control to restore the control state to the state before power-off based on the final stored contents is described.

JP-A-2002-95840

If the checksum is not the same before and after the power is turned off and becomes abnormal, there is a possibility that a fraudulent act may be involved in addition to a pure failure.From the viewpoint of preventing unauthorized modification and other changes, checksum confirmation processing etc. The security related processing is originally a regulation that combines the control area (4.5 KB etc.) and the data area (3.0 KB etc.) of the main board, that is, the main control unit, like the signal processing etc. related to the test defined by the gaming machine rules. It can be described in a different area which is a storage area different from the used area in the capacity, and it is considered that this is preferable, because the capacity devoted to the game control processing that can be described in the used area can be increased. In particular, the operation of the assist time AT that informs the correct pressing order of the pressing forward combination etc., which has been exclusively determined by the peripheral control device until now, is changed to the main AT decided by the main control device, Further savings are required.

An object of the present invention is to provide original game control, such as security-related and test-related, other than the game control processing for controlling the progress of the game, while ensuring the clarity and fairness of the division of roles between the use area and another area. Another object of the present invention is to provide a gaming machine that can appropriately describe another processing module provided for the purpose of optimization and can increase the capacity devoted to the game control processing in the usage area.

Reference numerals in the drawings are added in parentheses for illustration.
A memory (ROM, which divides a use area within a predetermined capacity that describes a predetermined module that is control related to a game) and another area that does not describe the predetermined module but describes a specific module (for example, E_SAMP1) A gaming machine having a CPU with RWM),
In the use area, a processing procedure (for example, another area call processing 1) that calls and executes the specific module (E_SAMP1) described in the another area after the interrupt is prohibited is described.
As described above, the stack pointer (SP) indicating the stack area of the use area is saved in the different area after the call from the use area, and the stack pointer indicating the stack area of the different area is set. , All the internal registers of the CPU are saved in the stack area of another area (for example, RWM addresses F230H to F246H), and after that, the specific module (E_SAMP1) is executed and immediately before returning to the use area. , A processing procedure (for example, another area processing 1) of restoring all the internal registers saved in the stack area of the another area and restoring the stack pointer of the used area is described.
The internal register does not include the stack pointer SP and the program counter PC. The R register (refresh register) is excluded because it does not need to be protected.

As a result, interrupts are prohibited during execution of a specific module described in another area, so that data in the used area is not rewritten from another area. Moreover, since the internal register is saved in the stack area of another area after the call from the used area, the used capacity of the stack area in the used area and the number of register save instructions in the used area can be reduced. After executing a specific module in another area, immediately before returning to the usage area, restore the internal register saved in the stack area of another area, and the content (data) of the internal register is destroyed by the execution of the specific module. Also, the sameness of the internal registers in the used area is maintained before and after the execution of a specific module. Since the internal register restore processing is also described in a separate area, the number of register restore instructions in the used area can be reduced. Therefore, while the number of instructions in the used area and the used capacity of the stack area can be reduced, execution of a specific module does not affect a predetermined module in the used area. Therefore, while ensuring the clarity and fairness of the division of roles between the usage area and another area, a specific module other than the specified module can be appropriately described in another area, and the capacity allocated to the specified module in the usage area is appropriate. Can be increased to

As described above, a predetermined register (AF) including the flag register of the CPU is saved in the different area after calling from the use area, and a plurality of internal registers (excluding the predetermined register of the CPU are (BC, DE, HL), after that, the specific module (E_SAMP1) is executed, and immediately before returning to the use area, a plurality of internal registers other than the predetermined registers are restored and the predetermined registers are restored. A processing procedure for restoring a register (for example, another area processing 1) is described.
As a result, it is possible to properly describe specific modules other than the predetermined module in another area while ensuring the clarity and fairness of the division of roles between the usage area and another area, and to allocate the capacity to be allocated to the predetermined module in the usage area. It can be increased appropriately.

As described above, the internal register of the CPU is saved in the different area by two exchange instructions (EX, EXX) for exchanging the front register and the back register after calling from the use area. , The specific module (E_SAMP1) is executed, and a processing procedure (for example, another area processing 1) for returning the internal register by the two exchange instructions is described immediately before the return to the use area.
The internal registers of the CPU include a front register and a back register capable of exchanging data with the front register.
This allows the contents of the front register to be saved to the back register during interrupt processing in the usage area, thus protecting the internal registers quickly with a small number of steps, but when executing a specific module, the back register is included. Since the internal registers used in the used area are saved and protected in the stack area of another area, it is possible to reliably exclude the influence of the specified module in the used area by executing a specific module. The purpose can be achieved effectively.

As described above, in the use area, a processing procedure (for example, another area call processing 1) for permitting (EI) interrupt after returning from the specific module is described.
As a result, after the return to the use area, the prohibited interrupt can be properly permitted.

The perspective view of the game machine of the present invention. The block diagram of the control device of the game machine. Memory map of the main CPU. The program block diagram of a use area and another area.

FIG. 1 shows a spinning drum type game machine to which the present invention is applied. The rotating body type gaming machine is generally called a pachi-slot, and has undergone revisions under the gaming machine rules, that is, the National Public Safety Commission Rule No. 1 of January 30, 2004 (1985) 2 It is a slot machine that complies with the National Public Safety Commission Regulation No. 4 of the 12th of March, “Rules concerning the authorization and type verification of gaming machines”. Hereinafter, terms and their technical contents are in accordance with the current gaming machine rules.

The gaming machine housing 8B includes a rear cabinet 8R, a cabinet frame 8W, and door-shaped upper and lower front cabinets 8E and 8F. In the upper front cabinet 8E, a liquid crystal display device 70, a reel panel 8, an upper decoration lamp 81, a left decoration lamp 82, a right decoration lamp 83, a liquid crystal display device, which constitutes an effect display device 7 for displaying a moving image or predetermined information in full color. Four accent decoration lamps 84 facing the corners of 70 and a panel decoration lamp 85 facing the top, left and right of the reel panel 8 are provided. The lower front cabinet 8F includes an operation unit 8S, a waist panel 8P, a lower left decoration lamp 86, and a lower right decoration lamp 87. The decorative lamps 88 are collectively referred to as 81 to 87. Reference numerals 91 to 94 are speakers for outputting BGM and various sound effects, 8M is a medal payout opening, 8G is a medal tray, and 8T is an ashtray. The left and right means the left and right in the player's line of sight facing the gaming machine. The same applies below.

Inside the transparent display window 80 of the reel panel 8, a left reel 1L, a middle reel 1C, and a right reel 1R, which are a plurality of variable display elements, are provided, and a total of 21 reels are provided on the outer circumference of each reel strip 10L, 10C, 10R. Three consecutive frames out of the symbols arranged in a frame or 20 frames are seen through the window. During normal forward rotation, including steady rotation, each symbol scrolls from top to bottom. A plurality of columns and a plurality of stages of symbol display positions displayed through the window of the display window 80, that is, three columns of left/middle/right reels 1L, 1C, 1R and respective upper/middle/lower three stages, In the 3×3=9 symbol display positions specified by rows and columns, for example, only the middle line (left middle-middle middle-right middle) is set as an effective line. Note that two or more lines including other lines may be effective lines.

The operation unit 8S has a medal insertion slot 2 for inserting a game medal which is a game medium, a push button PB and a jog dial JD having a dial DA for engaging the player's operation in the production, and an electromagnetic record of the storage device, that is, one time from a credit. Variable number (rotation) of bet button 3 for dropping a prescribed number of coins (3 BET), a settlement button 4 for dropping the remaining number of medals in the credit into the medal tray 8G, and reels 1L, 1C, 1R required for the game. Start lever 5, which is a start switch for starting, a left stop button 6L, which is a stop switch which is provided corresponding to each reel 1L, 1C, 1R and which individually stops the variable display (rotation) of the corresponding reel, a middle stop button 6C, a right stop button 6R, a medal return button 20 to be pressed when a medal is blocked downstream of the medal insertion slot 2, and a door key hole 8K.

On the reel panel 8, a credit indicator DL1 for displaying the current number of credits, a payout indicator DL2 for displaying the number of paid-out medals due to winning, and a light-up indicator 1 for every one, two, or three payout medals 1 〜3 pieces of lamps EL1 to 3, bet lamp ELb to be lit when the hanging medals are acceptable, start lamp ELs to be lit when the starting operation by the start lever 5 is possible, and is lit when a combination of symbols relating to re-play is displayed. The game basic lamps 30 including the replay lamp ELr are provided. In addition, when the correct answer is given in the order of pressing the stop buttons 6L, 6C, 6R, the push-out order for paying out the high-paid medals exceeding the number of inserted medals is pushed. The game effect lamps 700 that constitute the effect display device 70 include a left stop lamp 71, a middle stop lamp 72, and a right stop lamp 73 that are turned on together with the navigation notification on the liquid crystal display device 70.

When the bet lamp ELb is turned on, when one coin is inserted from the medal insertion slot 2 when the number of medals is 0, the one lamp EL1 is lit, when one more coin is inserted, the two lamp EL2 is lit, and one more coin is inserted. Then, the three-sheet lamp EL3 lights up, and the specified number is reached. When the prescribed number of medals is reached, the start lamp ELs is turned on and the starting operation by the start lever 5 becomes possible. If more medals are inserted into the medal insertion slot 2 without operating the start lever 5 from the state where the specified number has been reached, the counter of the credit indicator DL1 is advanced and it is possible to store up to the predetermined upper limit of 50 medals. Up to 50 medals paid out by winning the prize are also added to the credit, and medals paid out over 50 medals are received from the medal payout outlet 8M to the medal tray 8G.

As shown in FIG. 2, the control device CN incorporated inside the gaming machine housing 8B manages the progress of the game, internal lottery, payout of medals by winning, re-game operation, accessory operation, and assist time AT. Main controller MC corresponding to the main board in the so-called main side game machine rules for executing main game control related to player profit such as operation, and transmission from this main controller MC according to one-way communication specifications The peripheral control device SC corresponding to the peripheral board according to the gaming machine rule, which is a so-called sub-side, which receives the information to be performed and executes the effect control based on the decision items in the main control device MC. The one-way communication specification is a communication specification that satisfies "the peripheral board is not capable of receiving the signal transmitted by the peripheral board" defined in the gaming machine rules regarding the main board.

The main controller MC has an 8-bit main CPU composed of a Z80 compatible chip having a read-only read-only memory ROM and a readable/writable read/write memory RWM, and is used under a system clock operating environment of 12 MHz, for example. .. The main CPU applies a predetermined game machine extended specification to the basic Z80 specification.

At the input port I1 of the main CPU, the index sensors 11L, 11C, 11R (IDs) of the reels 1L, 1C, 1R, the stop buttons 6L, 6C, 6R, the bet button 3, the settlement button 4, the start lever 5, the medal. The signals of the input medal sensor 21 provided downstream of the insertion slot 2 and the payout medal sensor 23 provided at the exit of the medal payout device HP built in the gaming machine housing 8B are input. From the output port O1, the built-in LEDs 61, 62, 63 of the stop buttons 6L, 6C, 6R are connected to the reels 1L, 1C, 1R via the motor driver circuit Dr1, and the drive shafts SH are coupled to the stepping motors 12L, 12C, 12R (SM), the game basic lamps 30 via the LED driver circuit Dr2, the medal blocker 22 for dropping the medals additionally inserted after the reel start via the solenoid driver circuit Dr3 to the medal tray 8G, the motor driver circuit Dr4 The medal payout motor 24 of the medal payout device HP is controlled via the.

Each of the index sensors IDs detects an on-edge and an off-edge of a semicircular band-shaped index ID (1Li, 1Ci, 1Ri) attached to the inside of each reel for every half turn, and the first on-edge or off-edge is detected for all reels. After that, the stop buttons 6L, 6C, 6R can be accepted. Each stepping motor SM has a rotor Rm with a built-in permanent magnet having a large number of small rotor teeth on the outer circumference of an iron core, and a plurality of pairs of magnetic poles having a plurality of small stator teeth on the inner circumference of the magnetic poles of A phase, B phase, and C phase. (A bar phase (inverted phase of A)) and D phase (B bar phase (inverted phase of B)) are wound around the stator Sw, and one winding is turned on during steady rotation. Excitation pulse is generated by 1-2 phase excitation in which one-phase excitation and two-phase excitation for turning on one winding and another adjacent winding are alternately repeated at every interruption time, for example, every t=1.49 ms. In the step update of 504, it is displaced by a half step angle (1 step angle in the update of 2 steps) and is rotated once in the step update of 504. Further, by changing the step updating direction of the excitation pulse, it is possible to perform normal rotation and reverse rotation.

On the ROM of the main CPU, a random number value extracted from, for example, a 2-byte counter, which is updated at high speed on hardware or software in response to the operation of the start lever 5, is associated with a winning combination within a possible range of 0 to 65535. After the operation of the internal drawing means K and the start lever 5 for determining any winning combination or unwinning related to the winning, the re-game operation, and the operation of the role object, according to which one of the winning areas divided into In addition, after 4.1 seconds have elapsed from the start of the previous game, the spinning cylinder rotation device control means V1 for accelerating all the reels to the normal rotation side to reach the steady rotation speed and each reel are individually stopped by operating the corresponding stop button. Reel control means V including a rotation stop device control means V2 for allowing the display of a combination of symbols corresponding to the winning combination on the activated line, a medal payout means M for paying out a predetermined number of medals if the game result is a prize, If the game result is a re-game operation, a medal automatic insertion means N that automatically inserts the same number of medals for the next game, and a game state transition means that transitions the game state if the game result involves a shift to a working accessory etc. J, a freeze drawing means W for deciding whether or not a predetermined spinning drum effect for rotating each reel in reverse by a predetermined probability determined for each winning combination by a predetermined freeze drawing, and a spinning drum effect for executing the spinning drum effect related to the win Execution means G is provided.

Further, in the ROM of the main CPU, the AT operation determining means H1 for determining the operation of the assist time AT under a predetermined operating condition associated with the internal winning combination, and the number of continuous games for extending the operation of the assist time AT Etc. AT addition determining means H2 for determining additions such as internal wins and the like under a predetermined addition condition, AT continuation management means H3 for managing from the operation determination of the assist time AT to the end of operation, the correct answer for the pushing order small winning combination AT which causes AT instruction information such as a pressing order to be output to the main monitor MA constructed by borrowing the display function of the payout indicator DL2 managed by the main controller MC and to the liquid crystal display device 70 etc. managed by the peripheral controller SC. The instruction information output means H4 is provided.

The peripheral control device SC includes a sub CPU including an external read-only read-only memory ROM and a 32-bit RISC (Reduced Instruction Set Computer) chip microcomputer having a built-in and external readable/writable read/write memory RWM. For example, it is used under a system clock operating environment of about 200 MHz. The sub CPU enables appropriate and efficient parallel processing of tasks by controlling CPU time and priority assigned to tasks related to effect display and sound under the control of a real-time operating system RTOS (Real-Time Operating System). ing.

Transmission information from the main controller MC and a signal from the jog dial JD are input to the input port I2 of the sub CPU. The transmission information from the main control device MC, that is, the reception information of the peripheral control device NC includes main side initialization completion information, medal insertion information including operation information of the bet button 3, reel start information including operation information of the start lever 5, Winning flag information by internal drawing, operation information of stop buttons 6L, 6C, 6R, game result information, game state information, freeze and spinning effect information, AT operation information, AT instruction information, AT addition information, AT end information, error The information includes various information such as information to be detected by the main control device MC or to be determined or executed.

The sub CPU also functions as an I2C microcontroller, and connects the serial clock line SCL and serial data line SDA of the real-time clock RTC to the serial clock line SCL and serial data line SDA of the CPU built-in I2C. The serial clock line SCL and the serial data line SDA are pulled up to the main operating potential vdd=3.3V of the sub CPU via the resistor rp.

The time data of the real-time clock RTC is written at the time of production by a game machine maker, etc., based on the accurate current time based on the Japanese standard or international standard clock radio waves, for example, the time of writing, for example, Friday, December 25, 2015, 15:30. It is written as 45 seconds. After that, the time is continuously updated based on the reference clock by the crystal oscillator of the real-time clock RTC. Corrections for the major month of January 31, the minor month of January 30 or 28, and the leap year of February 29 once every four years are also automatically performed. The clock function of the real-time clock RTC is continuously maintained for a long period of, for example, 10 years or more by a backup power source BT such as a secondary battery, regardless of whether the gaming machine is powered on or off.

On the ROM of the sub CPU, based on the received information from the main controller MC, the navigation according to the AT instruction information output from the AT instruction information output means H4 to the liquid crystal display device 70 or the like, for example, the correct pressing sequence is "left middle. If it is "right", the navigation means X1 for displaying "123" or the like corresponding to the stop button position, and voice indicating whether the stop button to be operated from the speakers 91 to 94 is interlocked with the display of the navigation means X1 is left, middle or right. Voice navigation means X2 for informing, effect display means Y1 for changing and displaying the development of a moving image displayed on the liquid crystal display device 70 in accordance with the game state, spinning effect, AT period, etc., and in conjunction with this, sound effects from speakers 91-94. A sound effect output means Y2 for outputting BGM is provided.

The I2C controller I2Cn is connected to the CPU built-in bus of the sub CPU, and the serial clock line SCL and the serial data line SDA of the I2C controller I2Cn are connected to the nine symbols facing the display window 80 on the reel strips 10L, 10C, 10R. Connected to the serial clock line SCL and the serial data line SDA of the LDE driver Dr5 that controls the reel back lamps BL1 to 9 that illuminate from the back, and to the serial clock line SCL and the serial data line SDA of the LED driver Dr6 that controls the decoration lamp 88. It is connected to the serial clock line SCL and the serial data line SDA of the LED driver Dr7 that controls the game effect lamps 700. These LED-related I2C device tasks have a higher priority than the real-time clock RTC. The serial clock line SCL and the serial data line SDA are pulled up to the main operating potential vdd=3.3V of the sub CPU via the resistor rp. The liquid crystal display device 70 is controlled via a VDP (Video Display Processor), an output port O2, and an LCD driver circuit Dr8. The sound from the speakers 91 to 94 is controlled via the sound IC, the output port O2, and the power amplifier circuit Dr9.

FIG. 3 shows a memory map of the ROM and RWM of the main CPU of the main controller MC. Internal drawing means K, reel control means V, medal payout means M, automatic medal insertion means N, game state transition means J, freeze drawing means W, spinning cylinder effect execution means G, AT operation determination means H1, AT addition determination means H2. , AT continuation management means H3, AT instruction information output means H4 each function, the program command code of the game control processing for controlling the progress of the game, the address 0000H ~ within the specified capacity in the use area (control area 4.5KB) 11FFH, and the program data of the same game control process is described at addresses 1200H to 1DF3H in the specified capacity (data area 3.0KB) in the used area.

After the unused area and the comment area, addresses 1F00H to 2FBFH are assigned to other than game control processing, which is responsible for security-related processing from the viewpoint of preventing unauthorized modification and other changes, and test-related signal processing specified by the gaming machine rules. It describes the program instruction code and data of the processing module (specific module). After the program management area and the area having no hardware area, the RWM of the used area is provided in 512 bytes of addresses F000H to F1FFH, and the RWM of another area is provided in 512 bytes of addresses F200H to F3FFH. F400H to FFFFH are areas having no area in terms of hardware. The program instruction code of the game control processing in the usage area and the program instruction code of the different processing module in the different area are described in assembler language.

Of the RWM of the used area, work areas such as timers, counters, and flags related to programs in the used area are secured in F000H to F13FH, and a stack area of the used area is secured in F1C0H to F1FFH after the unused area. ..

In the RWM of another area, after the unused area of F200H to F20FH, secure work areas such as timers, counters, and flags related to programs in another area in F210H to F22FH, and stack area of another area in F230H to F246H. Have secured. F247H to F3FFH are unused areas, and F400H to FFFFH are areas having no area in terms of hardware.

As shown in FIG. 4, the game control process described in the use area is an interrupt process INT1 executed at each interrupt time, for example, every t=1.49 ms, and the above-mentioned respective means K to H4 are collectively managed to advance one game. Includes a plurality of different area calling processes 1, 2,... That respectively call the game main processing and the different area processing 1, 2,. Although not shown, in the use area, initialization processing at power-on, backup processing at power-off, etc. are also described. In this embodiment, the external interrupt and the non-maskable interrupt NMI are unused.

The internal registers of the main CPU used in the used area are as follows.
1) Q register: 8-bit dedicated register of extended specification for gaming machines. It is called a queue register.
The upper level is fixed at F0H and is used for RWM access from F000H to F0FFH.
2) I register; a dedicated register that stores the upper 8 bits of the interrupt destination address.
3) A register: 8-bit accumulator used for arithmetic processing and data transfer.

4) F register; an 8-bit flag register that holds various calculation results.
s (most significant bit) is a sign flag that is set to 1 when the operation result is negative.
z is a zero flag that is set to 1 when all bits are 0 as a result of the operation.
tz is a specific bit flag of the extended specification for gaming machines, which is set to 1 when all the bits are 0 (the value changes) by the execution of a data transfer instruction (LD; load). It is called a teaseed flag. Also called a second zero flag.
h is a half carry flag that programmers cannot participate in.
* Is undefined.
p/v is a parity overflow flag.
n is an addition/subtraction flag that the programmer cannot participate in.
c is a carry flag that is set to 1 when a carry or borrow occurs as a result of the operation.
The F register constitutes a register pair AF with the A register.

5) B, C, D, E, H, L registers: 8-bit general-purpose registers.
It becomes a 16-bit register pair of BC, DE, and HL.
6) IX and IY registers; 16-bit dedicated register for index addressing.
IXh and IYh indicate upper 8 bits, and IXl and IYl indicate lower 8 bits.
7) A', F', B', C', D', E', H', L'registers;
A, F, B, C, D, E, H, and L are front registers and back registers that can exchange data by an exchange instruction. A'and F'are AF' and B'and C'are BC' and D. 'And E'become a pair of back registers, DE' and H'and L'are HL'.

In the interrupt process INT1, the exchange instruction EX saves the data of the front register AF to the back register (step t1), and the exchange instruction EXX saves the data of the front register BC, DE, HL to the back register BC′, DE′, HL. After saving to'(step t2), various interrupt processes are executed (step t3). Various interrupt processes include a read process for the input port I1, a motor control process for the stepping motor SM, an output management process for the output port O1, a sub command transmission process for the peripheral control device SC, various sensor monitoring processes, and various timer updates. Includes processing and external signal output control processing to the island side where game machines are installed. After the execution of various interrupt processes, the data saved in the back registers BC', DE', HL' by the exchange instruction EXX are restored to the front registers BC, DE, HL (step t4), and are stored in the back register AF' by the exchange instruction EX. The saved data is returned to the table register AF (step t5), the interrupt is permitted (step t6), and the process returns from the interrupt process (step t7).

In SAMP1 of another area call processing 1, interrupts are prohibited (step S1), and the register pair AF including the flag register F is moved from the bottom F1FFH of the stack area of the used area to the one with a smaller address by the "PUSH AF" instruction. 2 bytes (16 bits) are saved toward the destination (step S2).

After step S2, another area process 1 is called and executed by "CALL E_SAMP1" (step S3). By the execution of the CALL instruction, the return address, that is, the upper 8 bits and the lower 8 bits of the address of "POP AF" next to the CALL instruction are recorded in the stack area of the used area.

After returning from the different area processing 1, the "POP AF" command restores the register pair AF including the flag register F saved in step S2 (step S4), and permits interruption (step S5).

In E_SAMP1 of the different area process 1 described in the different area, the stack pointer SP that was pointing to the stack area of the used area is saved in the storage area called EX_STCB secured in the RWM of the different area (step S6), and the stack of the different area is stacked. @SK2_ARE_BAS+1 (=F247H), which is the next address of the bottom address of the area, is set to the initial value of the stack pointer SP (step S7). As a result, the stack area changes from the used area to another area.

Next, the internal registers Q, I, A, F, B, C, D, E, H, L, IX, and IY used in the use area are defined by the "PUSH ALL" extended specification for gaming machines. By this, the data is collectively evacuated from the bottom F246H of the stack area of another area toward the smaller address (step S8), and AF and AF' are exchanged by the exchange instruction EX (step S9), and BC by the exchange instruction EXX. And BC', DE and DE', and HL and HL' are exchanged (step S10), and the instruction that is defined in the extended specification for gaming machine "PUSH GPR" is collectively followed by the stuffing in step S8. It is saved in the address (step S11).

Then, a predetermined different area process 1 is executed (step S12). In this separate area processing 1, backflow/dwelling/foreign matter detection processing when inserting medals, backflow/dwelling/foreign material detection processing when paying out medals, front door opening detection processing, abnormality checking processing for random numbers for internal drawing, winning of internal drawing Any one of security-related processes such as a setting value abnormality confirmation process that is a combination of probabilities, a RWM abnormality confirmation process, a backup abnormality confirmation process, or a combination process of two or more is executed. After the different area processing 2, security related processing other than the different area processing 1 or a test related signal output processing defined by the gaming machine rule is described. The different area processing 2,... Is called from the different area calling processing 2,.

After the end of the different area processing 1, the register that holds the contents of the back register packed in step S11 is collectively restored by the command defined in the extended specification for gaming machine "POP GPR" (step S13), and exchanged. Before executing the different area processing 1, the instruction EXX replaces BC′ and BC, DE′ and DE, HL′ and HL (step S14), and the exchange instruction EX replaces AF′ and AF (step S15). Returning to the contents of the back register of No., the front register packed in step S8 is collectively returned by the command defined in the extended specification for gaming machine "POP ALL" (step S16).

Subsequently, the stack pointer SP that has pointed to the stack area of the used area before calling the separate area process 1 is restored from the storage area EX_STCB of the RWM of the separate area (step S17). As a result, the stack area is changed from another area to the used area.

Thereafter, the area is returned to the use area by the "RET" command (step S18). By the "RET" instruction, the return to the return address stored in the stack area of the used area is restored, the stack pointer SP indicating the address of the stack area is incremented by 2, and "POP AF" in step S4 is executed.

The instruction code of the different area call processing 1 described in the used area is "DI", "PUSH AF", "POP AF", "EI" is 1 byte each, and "CALL E_SAMP1" is 3 bytes, totaling 7 bytes. When the separate area processing 1 is described by an instruction that exceeds 7 bytes, the capacity of the used area can be saved for the amount that exceeds 7 bytes. Since the number of different area processing is not limited to one and there are many cases, a large saving effect can be obtained in at least the total number of bytes saved in each processing.

In the above embodiment, the spinning drum type game machine is illustrated, but the same can be applied to the pachinko game machine. Needless to say, the specific numbers and addresses in the above description are merely examples.

1L; Left reel, 1C; Middle reel, 1R; Right reel 2; Medal slot, 3; Bet button, 4; Settlement button 5; Start lever, 6L, 6C, 6R; Each stop switch 7; Performance display device, 70 Liquid crystal display device 8; Reel panel, 80; Display window CN; Control device, MC; Main control device, SC; Peripheral control device K; Internal drawing means, V; Reel control means V1; Rotating cylinder rotation device control means, V2 ; Rotation stop device control means M: medal payout means, N: automatic medal insertion means, J: game state transition means W: freeze drawing means, G: spinning drum effect execution means H1, AT operation determination means, H2; AT addition determination Means H3; AT continuous management means, H4; AT instruction information output means X1; Navigation means, X2; Voice navigation means Y1; Effect display means, Y2; Sound effect output means

Claims (4)

In a gaming machine including a CPU having a memory in which a use area within a predetermined capacity for describing a predetermined module which is control related to a game and a separate area for not describing the predetermined module but for describing a specific module are divided ,
In the use area, after the interrupt is prohibited, the processing procedure for calling and executing the specific module described in the different area is described,
After calling from the use area, a stack pointer pointing to the stack area of the use area is saved in the different area, and a stack pointer pointing to the stack area of the different area is set, and all internal registers of the CPU are set. To the stack area of the separate area, after that, the specific module is executed, and immediately before returning to the use area, all the internal registers saved to the stack area of the separate area are restored, A game machine characterized by describing a processing procedure for restoring a stack pointer of a used area. In a gaming machine including a CPU having a memory in which a use area within a predetermined capacity for describing a predetermined module which is control related to a game and a separate area for not describing the predetermined module but for describing a specific module are divided ,
In the use area, after the interrupt is prohibited, the processing procedure for calling and executing the specific module described in the different area is described,
After calling from the use area, a predetermined register including a flag register of the CPU is saved in the different area, a plurality of internal registers of the CPU except the predetermined register are saved, and then the identification is performed. And executing a module of the above, restore a plurality of internal registers other than the predetermined register, and restore the predetermined register immediately before returning to the use area. .. A CPU having a memory in which a use area within a predetermined capacity for describing a predetermined module which is control related to a game and a separate area for describing a specific module without describing the predetermined module are provided, and the CPU The internal register of the gaming machine includes a table register and a back register capable of exchanging data with the table register,
In the use area, after the interrupt is prohibited, the processing procedure for calling and executing the specific module described in the different area is described,
After calling from the use area, the internal register of the CPU is saved in the different area by two exchange instructions for exchanging the front register and the back register, and then the specific module is executed, A game machine characterized in that a processing procedure for returning the internal register by the two exchange instructions is described immediately before the return to the use area. 4. The gaming machine according to claim 1, wherein a processing procedure for permitting interruption after returning from the specific module is described in the usage area.

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