JP6739488B2 - PAM decoder, PAM decoding method, error detection device, and error detection method - Google Patents

Description

The present invention relates to a PAM decoder and a PAM decoding method for decoding a PAM4 signal into a binary signal by a four-valued pulse amplitude modulation method (PAM4 method) in which the amplitude is divided into four types for each symbol, and an error detection device using the PAM decoder. And an error detection method using the PAM decoding method.

Various digital communication devices are required to have higher capacity transmission capacity as the number of users increases and multimedia communication spreads. A bit error rate, which is defined as a comparison between the number of code errors in received data and the total number of received data, is known as one of the indicators for quality evaluation of digital signals in these digital communication devices. There is.

Then, in the above-mentioned digital communication device, a test signal including fixed data is transmitted to a device under test such as a photoelectric conversion component to be tested, and the signal under test input via the device under test serves as a reference. A bit error measuring device disclosed in Patent Document 1 below, for example, is known as an error detecting device that measures the error rate of a signal under measurement by comparing it with a reference signal in bit units.

By the way, in recent years, with the spread of mobile terminals and cloud computing, the amount of data communication has been increasing and the transmission speed has been significantly increased. In addition, the international standard for high-speed data transmission has changed from the conventional NRZ transmission by the NRZ signal (binary signal) to PAM4 transmission by the PAM4 signal (four-valued signal) together with the electrical interface and the optical interface.

Then, in order to detect the error rate of this kind of PAM4 signal by the error detecting device, a decoder for the PAM4 signal is required. Conventionally, as a receiver including a decoder for decoding a PAM4 signal of this type into a binary signal, for example, a multilevel signal receiver disclosed in Patent Document 2 below is known.

JP, 2007-274474, A JP, 2009-231954, A

However, in the conventional PAM decoder, the eye opening is insufficient due to the thickness of the baseline of the waveform pattern of the obtained waveform, the turbulence of the baseline, etc., and there has been a demand for improvement. In addition, there is a problem that the reception sensitivity of the error detecting device is lowered by using the PAM decoder having an insufficient eye opening.

Therefore, the present invention has been made in view of the above problems, and provides a PAM decoder, a PAM decoding method, an error detection device, and an error detection method capable of improving the eye opening by narrowing the baseline. The purpose is to

In order to achieve the above object, the PAM decoder according to claim 1 of the present invention provides a high-level signal, a medium-level signal, and a low-level signal, which have different amplitude levels with respect to the baseline of the PAM4 signal, individually to 0/0. Three 0/1 discriminators 2a, 2b, 2c for discriminating 1;
In the three 0/1 discriminators, a first transmission line S4 is provided between the output of the 0/1 discriminator located on the input side and the output of the 0/1 discriminator located between the input side and the output side. OR is connected via the second transmission line S5 between the first transmission line and the output of the 0/1 discriminator located on the output side of the three 0/1 discriminators. A PAM decoder 1 configured by a wired OR composed of logic and provided with a decoding circuit 3 for decoding the discrimination signals from the three 0/1 discriminators into a most significant bit string signal MSB and a least significant bit string signal LSB,
When the load resistance on the input side in the wired OR is R1, the load resistance on the output side is R4, the characteristic impedance of the first transmission line is Z2, and the characteristic impedance of the second transmission line is Z3, R1≠R4 , |Z2-R1|<|Z3-R4|, Z2>Z3, the load resistances on the input side and the output side and the constants of the characteristic impedances of the first transmission line and the second transmission line are set. It is characterized by doing.

The PAM decoding method according to claim 2, wherein three 0/1 discriminations are made to individually discriminate 0/1 between a high level signal, a medium level signal and a low level signal having different amplitude levels with respect to the baseline of the PAM4 signal. Vessels 2a, 2b, 2c,
In the three 0/1 discriminators, a first transmission line S4 is provided between the output of the 0/1 discriminator located on the input side and the output of the 0/1 discriminator located between the input side and the output side. OR is connected via the second transmission line S5 between the first transmission line and the output of the 0/1 discriminator located on the output side of the three 0/1 discriminators. A PAM using a PAM decoder 1 constituted by a wired OR consisting of logic and provided with a decoding circuit 3 for decoding the discrimination signals from the three 0/1 discriminators into the most significant bit string signal MSB and the least significant bit string signal LSB. Decoding method,
When the load resistance on the input side in the wired OR is R1, the load resistance on the output side is R4, the characteristic impedance of the first transmission line is Z2, and the characteristic impedance of the second transmission line is Z3, R1≠R4 , |Z2-R1|<|Z3-R4|, Z2>Z3, the load resistances on the input side and the output side and the constants of the characteristic impedances of the first transmission line and the second transmission line are set. It is characterized by including the step of performing.

The error detecting device according to claim 3 is the error detecting device 21 using the PAM decoder according to claim 1,
The most significant bit string signal MSB and the least significant bit string signal LSB decoded by the decoding circuit 3 are input, the level of the most significant bit string signal, the 0 or 1 level of the least significant bit string signal, and the least significant bit string signal 2 , A level measuring unit 22 for measuring three levels respectively,
An error rate calculation unit 23 that calculates an error rate based on the measurement result by the level measurement unit is provided.

The error detecting method according to claim 4 is the error detecting method using the PAM decoding method according to claim 2,
The most significant bit string signal MSB and the least significant bit string signal LSB decoded by the decoding circuit 3 are input, the level of the most significant bit string signal, the 0 or 1 level of the least significant bit string signal, and the least significant bit string signal 2 , Measuring 3 levels respectively,
Calculating an error rate based on the result of the measurement.

According to the present invention, it is possible to realize a PAM decoder with a wide eye opening by extracting a decoded waveform with a relatively thin baseline from the output side of the decoding circuit. Further, it becomes possible to increase the reception sensitivity when measuring the error rate of the PAM signal.

FIG. 3 is a circuit configuration diagram of a PAM decoder according to the present invention. It is a figure which shows the truth table of the decoding circuit of FIG. It is a figure which shows the list of the constants of load resistance R1, R4 and characteristic impedance Z2, Z3 set by this invention and a comparative example (Examples 1-3) in the decoding circuit of FIG. It is a wave form diagram which shows an example of the pattern of an Upper signal of PRBS7, a Lower signal, and a Middle signal. It is a figure which shows the simulation result of this invention based on the constant of FIG. 3 when the pattern of FIG. 4 is input into the decoding circuit of FIG. 1, and a comparative example (examples 1-3). It is a figure which shows the other structural example of a decoding circuit. FIG. 7 is a diagram showing simulation results of the present invention and comparative examples (Examples 1 to 3) based on the constants of FIG. 3 when the pattern of FIG. 4 is input to the decoding circuit of FIG. 6. It is a block diagram of an error detection device using a PAM decoder according to the present invention. It is a schematic explanatory drawing of a PAM4 signal.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

[About PAM4 signal]
First, the PAM4 signal targeted by this embodiment will be described. The PAM4 system modulates a bit string composed of logic "0" and "1" as a pulse signal of four voltage levels or optical power as a pulse amplitude modulation signal in which the amplitude of an information signal is encoded by a sequence of pulse signals. It is a method of transmitting the data.

The PAM4 signal according to the PAM4 system is divided into four types of amplitude for each symbol, and has four different amplitude levels L0, L1, L2 and L3 as shown in FIG. An Upper signal (high level signal), which is divided into a low voltage range H1, a medium voltage range H2, and a high voltage range H3 from the line (L0:0 level) and has different amplitude levels with respect to the baseline (L0:0 level), The three eye pattern openings by the Middle signal (medium level signal) and the Lower signal (low level signal) are composed of signals in a continuous amplitude range.

[Configuration of PAM decoder]
Next, the configuration of the PAM decoder will be described with reference to FIG.
As shown in FIG. 1, the PAM decoder 1 determines 0/1 for the Upper signal (high level signal), the Middle signal (medium level signal) and the Lower signal (low level signal) of the PAM4 signal described above. A circuit 2 and a decoding circuit 3 (3A) for decoding the PAM4 signal into the most significant bit string signal (MSB) and the least significant bit string signal (LSB) from the discrimination signal determined by the 0/1 discrimination circuit 2 An amplifier 4 for amplifying and outputting the most significant bit string signal (MSB) decoded by the circuit 3 and an amplifier 5 for amplifying and outputting the least significant bit string signal (LSB) decoded by the decoding circuit 3 are generally configured. It

As shown in FIG. 1, the 0/1 discriminating circuit 2 includes three 0/1 discriminators (a first 0/1 discriminator 2a and a second 0/0 discriminator) for the transmission line S1 on which the PAM4 signal is transmitted. The 1 discriminator 2b and the third 0/1 discriminator 2c) are connected in parallel.

The first 0/1 discriminator 2a is connected to the transmission line S1 and discriminates 0/1 of the Upper signal of the PAM4 signal by comparison with the reference voltage Vth1. That is, as shown in FIG. 9, the first 0/1 discriminator 2a compares the Upper signal with the reference voltage Vth1, and if the Upper signal is equal to or higher than the reference voltage Vth1, DU=“1” is determined as the discrimination signal. When the Upper signal is output and the Upper signal is not higher than the reference voltage Vth1, DU=“0” is output as the determination signal.

The second 0/1 discriminator 2b is connected to the transmission line S1 via the transmission line S2 and discriminates 0/1 of the Lower signal of the PAM4 signal by comparison with the reference voltage Vth3. That is, as shown in FIG. 9, the second 0/1 discriminator 2b compares the Lower signal with the reference voltage Vth3, and if the Lower signal is equal to or higher than the reference voltage Vth3, DL=“1” is set as the discrimination signal. If the Low signal is not higher than the reference voltage Vth3, DL=“0” is output as the determination signal.

The third 0/1 discriminator 2c is connected to the transmission line S1 via the transmission line S2 and the transmission line S3, and discriminates 0/1 of the Middle signal of the PAM4 signal by comparison with the reference voltage Vth2. That is, as shown in FIG. 9, the third 0/1 discriminator 2c compares the Middle signal with the reference voltage Vth2, and if the Middle signal is equal to or higher than the reference voltage Vth2, DM=“1” is determined as the discrimination signal. Then, if the Middle signal is not higher than the reference voltage Vth2, DM=“0” is output as the determination signal.

In FIG. 1, the 0/1 discriminating circuit 2 includes a first 0/1 discriminator 2a for discriminating 0/1 of the Upper signal and a second 0/1 discriminator for discriminating 0/1 of the Lower signal. A configuration in which 2b and 2b are connected in reverse may be used.

As shown in FIG. 1, the decoding circuit 3A includes an amplifier circuit 11 on the output side of the 0/1 discriminating circuit 2 and connects the output signals of the three discriminators 2a, 2b, 2c of the 0/1 discriminating circuit 2. It is composed of a wired OR composed of OR logic.

The amplifier circuit 11 includes a first amplifier 11a, a second amplifier 11b, and an inverting amplifier 11c. The first amplifier 11a is connected to the first 0/1 discriminator 2a and amplifies and outputs the discrimination signal from the first 0/1 discriminator 2a.

The second amplifier 11b is connected to the second 0/1 discriminator 2b and amplifies and outputs the discrimination signal from the second 0/1 discriminator 2b.

The inverting amplifier 11c is connected to the third 0/1 discriminator 2c, and inverts and amplifies and outputs the discrimination signal from the third 0/1 discriminator 2c.

The output of the first amplifier 11a and the output of the second amplifier 11b are connected via a transmission line S4 having a characteristic impedance Z2. A load resistor R1 is connected to the input side of the transmission line S4.

The output of the second amplifier 11b and the output of the inverting amplifier 11c are connected via a transmission line S5 having a characteristic impedance Z3. A load resistor R4 is connected to the output side of the transmission line S5.

The PAM decoder 1 configured as described above, when the Upper signal, the Lower signal, and the Middle signal by the NRZ signal are input as the PAM4 signal, the PAM4 signal is decoded as shown in the truth table of FIG. (MSB) and the least significant bit string signal (LSB) are output.

By the way, when the decoding circuit 3 (3A) of the PAM decoder 1 described above is configured by a wired OR, there are design constraints due to the following (1) to (4).

(1) Due to layout problems, the transmission lines S2, S3, S4, and S5 are always required between the Upper signal/Lower signal/Middle signal (1 ps or more).
(2) It is necessary to set the load resistances R1 and R4 of the wired OR of the decoding circuit 3 to fixed values.
(3) It is difficult to increase the characteristic impedance of the transmission lines S4 and S5 of the decoding circuit 3 due to physical factors such as parasitic capacitance and line width.
(4) R1//R4 (=(R1×R4)/(R1+R4)) tends to be high in order to gain the amplitude.

Therefore, in the present embodiment, in order to maximize the wired OR waveform of the decoding circuit 3 under the above-mentioned constraint conditions, the matching on the input side is emphasized, and R1≠R4, |Z2-R1|<|Z3- The decode circuit 3 is configured by setting the constants of the load resistances R1 and R4 and the characteristic impedances Z2 and Z3 so as to satisfy R4|, Z2>Z3.

Specifically, as shown in the present embodiment of FIG. 3, when R1//R4=(R1×R4)/(R1+R4)=C, the input side load resistance R1=1.4C, the output side Load resistance R4=6C, characteristic impedance Z2=1.4C of input side transmission line S4, and characteristic impedance Z3=1.05C of output side transmission line S5.

Next, in order to verify the effect of the present embodiment, a single simulation of the decoding circuit 3A was performed based on the setting of the constants according to the present embodiment and Comparative Examples 1 to 3 shown in FIG. Here, an NRZ signal of 50 Gbit/s was input, the patterns of the Upper signal/Lower signal/Middle signal of PRBS7 shown in FIG. 4 were prepared, and a single simulation of the decoding circuit 3A was performed. Waveforms of simulation results of the present embodiment and Comparative Examples 1 to 3 are shown in FIG.

In the comparative example 1, as shown in FIG. 3, the load resistance R1 on the input side=the load resistance R4 on the output side=2C, the characteristic impedance Z2 of the transmission line S4 on the input side=the characteristic impedance Z3= of the transmission line S5 on the output side= This is the case when set to C. In Comparative Example 1, as shown in FIG. 5, it can be seen that the corrugated baseline is swollen and the eye opening is smaller.

In the comparative example 2, as shown in FIG. 3, the load resistance R1 on the input side=the load resistance R4 on the output side=2C, the characteristic impedance Z2 of the transmission line S4 on the input side=the characteristic impedance Z3= of the transmission line S5 on the output side= This is the case where it is set to 1.4 C, and the characteristic impedance is set to be larger than that of Comparative Example 1. In Comparative Example 2, as shown in FIG. 5, it can be seen that the waveform baseline is smaller than that in Comparative Example 1, but is still thick.

Comparative Example 3 places importance on impedance matching on the output side of the decoding circuit 3, and as shown in FIG. 3, load resistance R1=6C on the input side, load resistance R4=1.4C on the output side, and transmission line on the input side. This is a case where the characteristic impedance Z2 of S4=1.05C and the characteristic impedance Z3 of the transmission line S5 on the output side are set to Z3=1.4C. In Comparative Example 3, as shown in FIG. 5, it can be seen that the eye is deflated as compared with Comparative Examples 1 and 2.

Contrary to Comparative Example 3, in the present embodiment, the impedance matching on the input side of the decoding circuit 3 is emphasized, and as shown in FIG. 3, the input side load resistance R1=1.4C and the output side load resistance R4. =6C, the characteristic impedance Z2 of the input-side transmission line S4=1.4C, and the characteristic impedance Z3 of the output-side transmission line S5=1.05C. In this embodiment, as shown in FIG. 5, it can be seen that the baseline of the waveform is thinner than in Comparative Examples 1 and 2, and the eye opening is the largest.

As described above, in Comparative Example 1 and Comparative Example 2, the load resistors R1 and R4 are evenly arranged on the input side and the output side to have uniform characteristic impedance. Here, if the characteristic impedances Z2 and Z3 are increased, the baseline of the waveform becomes narrower and the eye opening expands. However, as described above, it is difficult to raise the characteristic impedances Z2 and Z3 due to physical restrictions, and Comparative Example 2 is the limit.

Comparative Example 3 shows a waveform when a constant that is a condition opposite to that of the present embodiment is set. In the third comparative example, the rampage of the waveform baseline becomes worse. On the other hand, in the present embodiment, the baseline of the waveform is further narrowed and the eye opening is better than in Comparative Example 2, which is an optimum constant within the constraint conditions.

Next, FIG. 6 shows another configuration example of the decoding circuit 3. It should be noted that the same components as those of the decoding circuit 3A of FIG.

In the decoding circuit 3B (3) of FIG. 6, the first amplifier 11a to which the Middle signal of the amplifier circuit 11 is input and the inverting amplifier 11c to which the Upper signal is input are opposite to those of the decoding circuit 3A of FIG. The other configurations are the same.

Next, similar to the decoding circuit 3A of FIG. 1, a single simulation was performed based on the setting of constants according to the present embodiment of the decoding circuit 3B of FIG. 6 and comparative examples (Examples 1 to 3). FIG. 7 shows waveforms of the decoding circuit 3B of FIG. 6 according to the present embodiment and simulation results of comparative examples (Examples 1 to 3).

As a result of performing a single simulation of the decoding circuit 3B under the same conditions as the decoding circuit 3A of FIG. 1, as shown in FIG. 7, the Middle signal input to the amplification circuit 11 of the decoding circuit 3B is opposite to that of the decoding circuit 3A. However, the same tendency result was obtained.

The PAM decoder 1 described above can be employed in the error detection device 21 of FIG. 8, for example. In this error detection device 21, when the most significant bit string signal (MSB) and the least significant bit string signal (LSB) are input from the PAM decoder 1, the level measuring unit 22 measures the level of the most significant bit string signal (MSB) and The 0 and 1 levels of the lower bit string signal (LSB) and the 2 and 3 levels of the least significant bit string signal (LSB) are measured. Then, the error rate calculation unit 23 calculates the error rate based on the levels of the most significant bit string signal (MSB) and the least significant bit string signal (LSB) measured by the level measurement unit 22, and the result is displayed by the display unit 24. To display.

As described above, according to the present embodiment, importance is attached to matching on the input side, and load resistances R1 and R4 are set so as to satisfy R1≠R4, |Z2-R1|<|Z3-R4|, Z2>Z3. The constants of the characteristic impedances Z2 and Z3 of the transmission lines S4 and S5 are set. As a result, it is possible to implement a PAM decoder with a wide eye opening by extracting a decoded waveform with a relatively thin baseline from the output side of the decoding circuit. Further, if the PAM decoder and PAM decoding method are adopted in the error detecting device and the error detecting method, it becomes possible to enhance the receiving sensitivity when measuring the error rate of the PAM signal.

By the way, in the above-mentioned embodiment, the constants of the load resistance R1 on the input side, the load resistance R4 on the output side, the characteristic impedance Z2 of the transmission line S4 on the input side, and the characteristic impedance Z3 of the transmission line S5 on the output side are the Upper signal. , Lower signal, and Middle signal.

The best mode of the PAM decoder, the PAM decoding method, the error detecting device, and the error detecting method according to the present invention has been described above, but the present invention is not limited to the description and drawings according to this mode. That is, it goes without saying that all other forms, examples, operation techniques, and the like made by those skilled in the art based on this form are included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 PAM decoder 2 0/1 discriminator 2a 1st 0/1 discriminator 2b 2nd 0/1 discriminator 2c 3rd 0/1 discriminator 3 (3A, 3B) decoding circuit 4,5 amplifier 11 amplification Circuit 11a First amplifier 11b Second amplifier 11c Inverting amplifier 21 Error detection device 22 Level measurement unit 23 Error rate calculation unit 24 Display unit S1, S2, S3, S4, S5 Transmission line R1, R4 Load resistance Z2, Z3 Characteristics Impedance Vth1 First reference voltage Vth2 Second reference voltage Vth3 Third reference voltage H1 Low voltage range H2 Medium voltage range H3 High voltage range L0, L1, L2, L3 Each level of PAM4 signal

Claims (4)

Three 0/1 discriminators (2a, 2b, 2c) for individually discriminating 0/1 between high level signals, medium level signals and low level signals having different amplitude levels with respect to the baseline of the PAM4 signal,
In the three 0/1 discriminators, a first transmission line (S4) is provided between the output of the 0/1 discriminator located on the input side and the output of the 0/1 discriminator located between the input side and the output side. ), and between the first transmission line and the output of the 0/1 discriminator located on the output side of the three 0/1 discriminators via the second transmission line (S5) . And a decode circuit (3) configured to be a wired OR composed of OR logics connected by the above, and which decodes the discrimination signals from the three 0/1 discriminators into the most significant bit string signal (MSB) and the least significant bit string signal (LSB). A PAM decoder (1) comprising:
When the load resistance on the input side in the wired OR is R1, the load resistance on the output side is R4, the characteristic impedance of the first transmission line is Z2, and the characteristic impedance of the second transmission line is Z3, R1≠R4 , |Z2-R1|<|Z3-R4|, Z2>Z3, the load resistances on the input side and the output side and the constants of the characteristic impedances of the first transmission line and the second transmission line are set. A PAM decoder characterized by: Three 0/1 discriminators (2a, 2b, 2c) for individually discriminating 0/1 between high level signals, medium level signals and low level signals having different amplitude levels with respect to the baseline of the PAM4 signal,
In the three 0/1 discriminators, a first transmission line (S4) is provided between the output of the 0/1 discriminator located on the input side and the output of the 0/1 discriminator located between the input side and the output side. ), and between the first transmission line and the output of the 0/1 discriminator located on the output side of the three 0/1 discriminators via the second transmission line (S5) . And a decode circuit (3) configured to be a wired OR composed of OR logics connected by the above, and which decodes the discrimination signals from the three 0/1 discriminators into the most significant bit string signal (MSB) and the least significant bit string signal (LSB). A PAM decoding method using a PAM decoder (1) having:
When the load resistance on the input side in the wired OR is R1, the load resistance on the output side is R4, the characteristic impedance of the first transmission line is Z2, and the characteristic impedance of the second transmission line is Z3, R1≠R4 , |Z2-R1|<|Z3-R4|, Z2>Z3, the load resistances on the input side and the output side and the constants of the characteristic impedances of the first transmission line and the second transmission line are set. A PAM decoding method comprising the steps of: An error detection device (21) using the PAM decoder according to claim 1,
The most significant bit string signal (MSB) and the least significant bit string signal (LSB) decoded by the decoding circuit (3) are input, the level of the most significant bit string signal, the 0, 1 level of the least significant bit string signal, A level measuring unit (22) for measuring the second and third levels of the least significant bit string signal,
An error detection apparatus comprising: an error rate calculation section (23) for calculating an error rate based on the result of measurement by the level measurement section. An error detection method using the PAM decoding method according to claim 2,
The most significant bit string signal (MSB) and the least significant bit string signal (LSB) decoded by the decoding circuit (3) are input, the level of the most significant bit string signal, the 0, 1 level of the least significant bit string signal, Measuring each of a few levels of the least significant bit string signal,
And a step of calculating an error rate based on the result of the measurement.

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