JP6739513B2 - Implementation of load get/store release instructions using load/store operations with DMB operations - Google Patents

Description

This disclosure relates to ordering memory operations in a computing environment.

In lock-free computing, there are two ways in which threads can manipulate shared memory, and threads can compete with each other for resources, or information can collaborate from thread to thread. There is a possibility to pass. Acquisition and release semantics are used to accomplish the cooperative passing of information from thread to thread. Acquisition and release semantics provide a structural system to ensure that memory operations are properly ordered to prevent errors. The store release instruction ensures that all previous instructions are completed, and the load acquisition instruction ensures that all subsequent instructions will only be completed after the load acquisition instruction is completed. Proper ordering of memory operations using the get and free semantics requires a complex combination of store free and load get instructions.

Disclosed herein are systems and methods for simplifying load acquisition and store release semantics used in reduced instruction set computing (RISC).

Implementations provide for ordering memory operations in connection with the instructions disclosed herein. A typical load with acquire instruction only requires that memory operations after a load with acquire be ordered after the load with acquire--the typical load with acquire instruction is Do not impose any order on the instruction before the load with acquisition (in relation to both the load with and subsequent instructions). In an embodiment, a load with acquire guarantees that all accesses before and including the load with acquire are ordered before all accesses from instructions after the load with acquire. Includes data memory barriers used in connection.

Similarly, a normal store with release instruction imposes an ordering between accesses from the store with release and all previous instructions (but not subsequent instructions). However, in an embodiment, the initial data memory barrier of the store with release provides a strong ordering between the previous access and the access associated with the store with release.

In one implementation, a system includes a processor that executes computer-executable instructions for performing operations. The instruction may include a load instruction with acquisition that performs an ordering of memory operations, and the load instruction with acquisition includes a load operation followed by a data memory barrier operation.

In another implementation, a method includes executing instructions in a processor. The method may include a load instruction with acquisition for performing an ordering of memory operations, and the step of executing the load instruction with acquisition includes performing a load operation followed by a data memory barrier operation.

In one implementation, a system includes a processor that executes computer-executable instructions for performing operations. The instruction may include a store with release instruction that performs an ordering of memory operations, the store with release instruction including a first data memory barrier operation followed by a second data memory barrier operation. Including.

In one implementation, a method includes executing instructions in a processor. The method may include a store with release instruction to perform ordering of memory operations, the step of executing the store with release instruction followed by the step of performing a second data memory barrier operation. Including performing a first data memory barrier operation, followed by performing the step.

FIG. 7 is a block diagram illustrating an embodiment of a system for filtering memory operations in accordance with various aspects set forth herein. FIG. 7 is a block diagram illustrating an embodiment of a system for filtering memory operations in accordance with various aspects set forth herein. FIG. 7 is a block diagram illustrating an embodiment of a system for filtering memory operations in accordance with various aspects set forth herein. FIG. 7 is a block diagram illustrating an embodiment of a system for filtering memory operations in accordance with various aspects set forth herein. 6 is a flow diagram of an embodiment of a method for executing a load instruction with acquisition. 6 is a flow diagram of an embodiment of a method for executing a store with release instruction. 6 is a flow diagram of an embodiment of a method for filtering memory operations using a data memory barrier. 1 is a block diagram of an electronic computing environment that may be implemented in connection with one or more aspects described herein. FIG. 7 is a block diagram of a data communication network that may potentially operate in connection with various aspects set forth herein.

Various embodiments provide a system that simplifies load acquisition and store release semantics used in reduced instruction set computing (RISC). In lock-free computing, there are two ways in which threads can manipulate shared memory, and threads can compete with each other for resources, or information can collaborate from thread to thread. There is a possibility to pass. However, these semantics are complex and replacing the special semantics with a simple data memory barrier may simplify the process of memory ordering. Translating the semantics into micro-operations or low-level instructions used to implement complex machine instructions may avoid the need to implement complex new memory operations. Using a data memory barrier in connection with load and store instructions can provide sufficient ordering using a simple brute force ordering operation.

As used in this disclosure, the terms “instruction”, “operation”, and “access” refer to separate processes and are not interchangeable. While an instruction consists of one or more operations, the operations may include zero or more memory accesses or barriers. As an example, the load instruction with acquisition generates two operations, a load operation and a barrier operation. This barrier divides all memory accesses into two groups. The first group includes accesses from all instructions before the load with acquire and accesses from load operations that belong to the load with acquire. The second group includes accesses from all instructions after the load with acquisition instruction.

FIG. 1 illustrates a system 100 for filtering memory operations using a data memory barrier within a RISC processor, processing environment or architecture. The RISC processor may include a variant of the ARM processor and, in particular, the ARMv8 processor in this embodiment. As shown, system 100 may be communicatively coupled to and/or operable with processor 104 to facilitate the operation and/or execution of computer-executable instructions and/or components by system 100. A load/store component 102 that may be connected to the processor, a memory 106 for storing data and/or computer-executable instructions and/or components for execution by the system 100 utilizing the processor 104, for example, a processor Storage component 108 for providing longer-term storage for data and/or computer-executable instructions and/or components that may be executed by system 100 using 104. Further, as shown, the system 100 may receive an input 110 that may be transformed from a first state to a second state by execution of one or more computer-executable instructions and/or components by the processor 104. Yes, the first condition may be distinguishable and/or distinguishable and/or different from the second condition. The system 100 may also generate an output 112 that may include different states or articles that have been transformed through processing by the system 100.

FIG. 2 illustrates a block diagram illustrating an embodiment of a system for filtering memory operations according to various aspects described herein. System 200 includes a data memory barrier 204 that enforces ordering constraints on prior instructions 202 and subsequent instructions 206. Data memory barrier 204 is a type of barrier operation that causes the CPU or compiler to enforce ordering constraints on memory operations issued before and after the barrier operation. Typically, this means that certain operations are guaranteed to be performed before the barrier and other operations are guaranteed to be performed after the barrier. The data memory barrier 204 ensures that the previous instruction 202 is executed and completed before the subsequent instruction 206 is executed. The preceding instruction 202 and the following instruction 206 respectively add to the basic load and store instructions a more complex variation of these instructions (e.g., load-exclusive with acquire, store exclusive with release ( store-exclusive with release) and the like).

In an embodiment, the previous instruction 202 and the subsequent instruction 206 may include load or store instructions configured to load the first set of data from memory and store the second set of data in memory. There is a nature. The data memory barrier 204 may be configured to order the memory operations associated with loading and storing data, the type of ordering achieved being one or more load instructions and stores. Based on the position in the program order of the data memory for the instruction.

FIG. 3 is a block diagram illustrating an embodiment of a system for filtering memory operations with load instructions with acquisition in accordance with various aspects set forth herein. The system 300 can include a data memory barrier 304 that orders the load operations 302 prior to the data memory barrier 304 in program order. The data memory barrier 304 ensures that the load operation 302 is executed and completed before subsequent instructions are executed. System 300 illustrates a simple load instruction with acquisition that includes load operations and data memory barrier operations. In other embodiments, other types of load operations may result in different load instructions such as load exclusive with acquisition and other variants.

FIG. 4 illustrates an embodiment of a system for performing store instructions with release instructions according to various aspects described herein. System 400 may include data memory barriers 402 and 406 on either side of store operation 404 in program order. The data memory barrier 402 ensures that all previous instructions/operations are done before the store operation 404 is initiated, while the data memory barrier 406 causes any subsequent memory instructions/operations to occur. Ensure that store operation 404 is completed before. In addition, the first data memory barrier 402 and the second data memory barrier 406 also provide an order to ensure that store with free and load with get instructions are observed in program order.

Methods that may be implemented in accordance with the subject matter described in connection with the flow charts of FIGS. 5-7 are shown and described as a series of blocks, and some blocks are not shown or described herein. It is to be understood that the claimed subject matter is not limited by the order of the blocks, as they may occur in different orders and/or concurrently with other blocks. Moreover, not all illustrated blocks may be required to implement the methods described below.

FIG. 5 shows a flow chart of an embodiment of a method for executing a load instruction with acquisition. The method 500 may begin at 502 where a load operation is performed, where the load operation specifies an address for accessing the data in memory.

At 504, a data memory barrier may be implemented. A data memory barrier is a type of barrier operation that causes the CPU or compiler to enforce ordering constraints on memory operations issued before and after the barrier operation. Typically, this means that certain operations are guaranteed to be performed before the barrier and other operations are guaranteed to be performed after the barrier. The data memory barrier ensures that the previous instruction is executed and completed before the subsequent instruction is executed. In this case, the data memory barrier operation ensures that the previous load operation has been executed and completed before the subsequent instruction is executed.

FIG. 6 shows a flow diagram of an embodiment of a method for executing a store with release instruction. Method 600 can begin at 602, where a first data memory barrier operation is performed. A data memory barrier is a type of barrier instruction that causes the CPU or compiler to enforce ordering constraints on memory operations issued before and after the barrier operation.

At 604, a store operation is performed. The store operation specifies an address for writing data to the memory. At 606, a second data memory barrier operation is performed. Having a store operation between two data memory barrier operations means that all other memory operations have been performed and completed before the store operation is performed, and then other operations until the store operation is completed. Guarantees that memory operations are not allowed. In this way, the store with release instruction performed ordering of memory operations using simple store and data memory barrier operations.

FIG. 7 is a flow diagram of an embodiment of a method for filtering memory operations using data memory barrier operations. The method 700 may begin at 702 where a first set of memory operations is performed before the barrier. The barrier ensures that all instructions are completed before step 704, where the second set of memory operations is performed after the data memory barrier.

The techniques described herein may be applied to any reduced instruction set computing environment in which it is desirable to perform ordering or filtering of memory operations. All types of handheld, portable, and other computing devices and computing objects are envisioned for use in any context that is relevant to various embodiments, that is, where the ordering of their memory operations may be performed. I want you to understand. The multipurpose remote computer below, described in FIG. 8 below, is an example and the disclosed subject matter may be implemented with any client having network/bus interoperability and interaction. Accordingly, the disclosed subject matter is an environment for networked hosted services, eg, a networked environment in which a client device, such as an object located within a home appliance, simply interfaces with the network/bus. Can be implemented on a chip or system within.

FIG. 8 illustrates an example of a suitable computing system environment 800 in which aspects of the disclosed subject matter may be implemented, the computing system environment 800 being merely one example of a suitable computing environment for a device. It is not intended to suggest any limitation as to the scope of use or function of the subject.

FIG. 8 is an exemplary device for implementing the disclosed subject matter, including a general purpose computing device in the form of a computer 810. The components of computer 810 may include a processing unit 820, a system memory 830, and a system bus 821 that couples various system components including the system memory to processing unit 820. The system bus 821 can be any of several bus structures including a memory bus or memory controller using any of a variety of bus architectures, a peripheral bus, and a local bus. Computer 810 typically includes a variety of computer readable media.

The system memory 830 may include computer storage media in the form of volatile and/or nonvolatile memory such as read only memory (ROM) and/or random access memory (RAM). A basic input/output system (BIOS), containing the basic routines that help to transfer information between elements within computer 810, such as during start-up, can be stored in memory 830. Computer 810 may also include other removable/non-removable, volatile/nonvolatile computer storage media.

A user can enter commands and information into computer 810 through an input device such as a keyboard and a pointing device commonly referred to as a mouse, trackball, or touchpad.

Computer 810 can operate in a networked or distributed environment that uses logical connections to one or more other remote computers, such as remote computer 870, and also those other remote computers. The computer may have different medium capabilities than device 810.

In addition to the above, the disclosed subject matter is typical for manufacturing hardware, firmware, software, or any suitable combination thereof for controlling an electronic device to implement the disclosed subject matter. It may be implemented as a method, apparatus, or product using manufacturing, programming, or engineering techniques. Computer-readable media can include hardware or software media, which can include non-transitory media or transfer media.

100 system
102 load/store components
104 processors
106 memory
108 Storage components
110 inputs
112 outputs
200 system
202 orders ahead
204 Data memory barrier
206 Subsequent instructions
300 system
302 Load operation
304 data memory barrier
400 system
402 Data memory barrier
404 store operation
406 Data memory barrier
800 computing system environment
810 computer
820 processing unit
821 system bus
830 system memory
840 inputs
850 output, eg display
860 network interface
870 remote computer
910, 912 Server object
920, 922, 928 Computing device
924,926 objects
940 Datastore(s)
942 Communication network/bus

Claims (10)

A processor executing computer-executable instructions for performing an operation, comprising:
The instructions include load instructions with acquisition that perform ordering of memory operations,
The load instruction with acquisition includes a load operation followed by a data memory barrier operation,
Said data memory barrier operation, instead taking a set of load acquisition semantics for ordering memory operations, the data memory barrier operation orders the memory operations that occur before and after the data memory barrier operation, the processor .. 2. The data memory barrier operation orders memory operations including a first set of memory operations performed before the barrier operation and a second set of memory operations performed after the barrier operation. Processor. The load operation specifies an address for accessing the first data in memory,
The processor of claim 1, wherein the load instruction with acquisition includes at least one of a load instruction with acquisition and a variation of the load instruction with acquisition . A method for executing instructions in a processor, the method comprising:
Including executing a load instruction with acquisition to perform ordering of memory operations,
Executing the load instruction with acquisition comprises executing a load operation followed by a data memory barrier operation,
Execution of the data memory barrier operation, instead taking a set of load acquisition semantics for ordering memory operations, the data memory barrier operation orders the memory operations that occur before and after the data memory barrier operation , Method. Further comprising executing a load instruction with acquisition and a variation of the load instruction with acquisition
The method of claim 4, wherein the load operation specifies an address for accessing the first data in memory. 5. The data memory barrier operation orders memory operations including a first set of memory operations performed before the barrier operation and a second set of memory operations performed after the barrier operation. the method of. A processor executing computer-executable instructions for performing an operation, comprising:
The instructions include store with release instructions that perform ordering of memory operations,
The store with release instruction comprises a first data memory barrier operation followed by a store operation followed by a second data memory barrier operation,
Wherein the instructions further viewing including the release with a store instruction and the change of the release with a store instruction,
A processor wherein the data memory barrier operation orders memory operations that occur before and after the data memory barrier operation . The first data memory barrier operation and the second data memory barrier operation include a first set of memory operations performed before the barrier operation and a second set of memory operations performed after the barrier operation. Ordering memory operations, including
8. The processor of claim 7, wherein the store operation specifies an address for writing first data in memory. A method for executing instructions in a processor, the method comprising:
Executing a store instruction with release to perform ordering of memory operations,
Performing a store with release instruction comprises performing a first data memory barrier operation, followed by performing a second data memory barrier operation, followed by performing a store operation,
Said method further seen including the step of performing the release with store instructions and change of the release with a store instruction,
The method, wherein the data memory barrier operation orders memory operations that occur before and after the data memory barrier operation . Performing the first data memory barrier operation and performing the second data memory barrier operation are performed after the first set of memory accesses and the barrier operation that are performed before the barrier operation. Order memory operations, including a second set of memory accesses,
10. The method of claim 9, wherein the step of performing the second data memory barrier operation before executing a load instruction with acquisition ensures that the instruction is observed in program order.

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