JP6748935B2 - Protection circuit for semiconductor switch with current sense - Google Patents

Description

The present invention relates to a protection circuit for detecting an abnormality of a power semiconductor switch and performing a protection operation.

Patent Document 1 describes a technique for protecting a power semiconductor switch from overcurrent.
In this prior art, when a voltage across the semiconductor switch, for example, an IGBT (collector voltage) is detected and a gate signal for turning on the IGBT is input but the voltage across the gate does not decrease, a load short circuit or the like occurs. The IGBT is protected from the overcurrent by considering that the overcurrent is flowing in the IGBT and operating the gate signal to cut off the overcurrent. Patent Document 1 also describes that the IGBT is turned off when an overcurrent is detected, and that abnormal information indicating the occurrence of an overcurrent is transmitted to a higher-order control circuit.

The prior art described in Patent Document 1 applies that the voltage across the semiconductor switch does not drop when an overcurrent flows through the semiconductor switch such as an IGBT. This means that from a different perspective, the occurrence of overcurrent cannot be detected unless a large current flows so that the voltage across the semiconductor switch does not drop.
Therefore, in designing the semiconductor switch, it is required to allow the overcurrent to continue flowing for a period until the overcurrent is generated and cut off. That is, it is necessary to secure a considerably large energy resistance of the semiconductor switch, and as a result, there is a problem that the semiconductor switch must be increased in size.

On the other hand, Patent Document 2 discloses overcurrent protection means for an IGBT with current sense. The current sense refers to a function of diverting a part of a current flowing through a semiconductor switch to a sense terminal provided in this semiconductor switch. The overcurrent that flows between the input and output terminals of the semiconductor switch is detected by using the voltage generated in the resistor connected to this sense terminal, and by operating the gate signal, the overcurrent is blocked and the semiconductor switch is protected. There is.
According to this method, the magnitude of the current flowing through the semiconductor switch can be equivalently detected by the voltage generated in the resistor. Therefore, it is possible to shorten the time until the overcurrent is detected, and it is possible to solve the problem of the technique described in Patent Document 1.

However, in the conventional technique described in Patent Document 2, although it is possible to detect and protect an overcurrent abnormality of a target semiconductor switch, when an open failure (open failure) occurs in the semiconductor switch, This cannot be detected. If an open failure cannot be detected, the system using the semiconductor switch will continue to operate abnormally, which may lead to a secondary failure of the system.

On the other hand, since the conventional technique described in Patent Document 1 detects the voltage across the semiconductor switch, when an open failure occurs in the semiconductor switch, an ON signal is input to the semiconductor switch. Since there is an open failure, the voltage at both ends does not drop. Therefore, a phenomenon equivalent to the case where an overcurrent flows is generated, and as a result, although it is not an overcurrent abnormality but an open failure, it is possible to detect the abnormality of the semiconductor switch and perform the protection operation. It is possible to transmit to the upper control circuit side.
That is, the control circuit can recognize the abnormality of the semiconductor switch regardless of the overcurrent abnormality or the open failure, and can stop the operation of the system using the semiconductor switch to perform the protection operation.

In addition, like patent document 3, when the open failure of the semiconductor switch generate|occur|produces in any of the several inverter which drives each several motor, the drive of the motor by the said inverter is stopped, There is also known a conventional technique in which an emergency measure such as driving a motor by another inverter is taken so that a good countermeasure can be taken although the system cannot operate completely.

Japanese Patent No. 2881755 (paragraph [0026], FIG. 1 etc.) Japanese Patent No. 3125622 (paragraphs [0015], [0016], FIG. 1, etc.) JP 2012-1398A (paragraph [0041], FIG. 3, etc.)

According to Patent Document 1, it is possible to detect an open failure of a semiconductor switch in the same manner as an overcurrent abnormality and detect the protection operation. However, as described above, the semiconductor switch becomes large due to the necessity of increasing the energy resistance of the semiconductor switch, which hinders downsizing and cost reduction of the device. In addition, it may be a problem to be solved depending on the application that even an open failure is erroneously recognized as an overcurrent abnormality.
Further, in Patent Document 2, since the time required for overcurrent protection can be shortened as compared with Patent Document 1, the semiconductor switch can be downsized, but there is a problem that an open failure cannot be detected.

Therefore, solving problems of the present invention, as well as reduce the size and cost of the semiconductor switch or device, overcurrent abnormality and a semiconductor switch both open failure is detected and the conditioned by current sense to allow a predetermined protection operation To provide a protection circuit.

In order to solve the above problems, the invention according to claim 1 includes a control terminal, an input terminal, an output terminal, and a sense terminal for detecting a current flowing between the input terminal and the output terminal, and a single unit. In the protection circuit for protecting the semiconductor switch with current sense formed as the element of
Current detecting means for detecting a current flowing through the sense terminal,
First comparison means for comparing the current detection value by the current detection means with a first threshold value;
Voltage detection means for detecting a voltage between the input terminal and the output terminal,
Second comparing means for comparing the voltage detection value by the voltage detecting means with a second threshold value;
An ON/OFF command for the semiconductor switch with current sense is in an ON state, the detected current value exceeds the first threshold value, and the detected voltage value is less than the second threshold value. A first abnormal event is detected when the state continues for a first mask period, the detected current value is less than the first threshold value, and the detected voltage value is the second threshold value. An abnormality detecting means for detecting a second abnormal event when the value exceeding the value continues for the second mask period ,
Driving means for turning off the abnormal said Ri by the detecting means a first abnormal event or the said current sense with the semiconductor switch during detects a second abnormal event,
It is characterized by having.

The invention according to claim 2 is the protection circuit for a semiconductor switch with current sense according to claim 1, wherein the first abnormal event is a state in which an overcurrent flows between the input terminal and the output terminal. And the second abnormal event is an open failure of the semiconductor switch with current sense .

According to a third aspect of the invention, in the protection circuit for a semiconductor switch with current sense according to the first or second aspect, when the first abnormal event or the second abnormal event is detected, the on/off command is issued. It is characterized in that it is provided with an output means for transmitting abnormality information to an external control circuit for generation .

According to a fourth aspect of the present invention, in the protection circuit for a semiconductor switch with current sense according to any one of the first to third aspects, there is provided a first output means for transmitting the first abnormal event to the control circuit. And second output means for transmitting the second abnormal event to the control circuit .

The invention according to claim 5 is the protection circuit for a semiconductor switch with current sense according to any one of claims 1 to 4 , wherein the semiconductor switch with current sense, the current detection means, the first comparison means, The voltage detecting means, the second comparing means, the abnormality detecting means, and the output means are housed in a single package .

According to the present invention, it is possible to detect a state in which an overcurrent flows in a semiconductor switch with current sense or a state in which a semiconductor switch has an open failure, and quickly perform a protection operation to turn off the semiconductor switch. Therefore, it is not necessary to increase the size of the semiconductor switch more than necessary, which contributes to downsizing of the device and cost reduction, and the abnormality of the semiconductor switch spreads to other parts of the system, causing secondary damage. Can be prevented.
Also, if necessary, if the overcurrent abnormality and the open failure are individually output as different types of abnormality information, the cause of the abnormality can be determined, and appropriate corrective measures can be taken according to the cause of the abnormality. ..
Furthermore, by incorporating the semiconductor switch with current sense and its abnormality detection function and protection function in a single package, it is possible to further reduce the size and improve the handleability, and to easily mount it on a power conversion device, etc. Become.

It is a block diagram showing a 1st embodiment of the present invention. 6 is a timing chart showing an operation when an overcurrent abnormality occurs in the first embodiment. 6 is a timing chart showing an operation when an open failure occurs in the first embodiment. It is a block diagram which shows the structure of the principal part in 2nd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a first embodiment of the present invention. In this embodiment, an IGBT with current sense is assumed as a semiconductor switch for electric power. The IGBT collector, emitter, and gate are referred to as an input terminal, an output terminal, and a control terminal, respectively.

In FIG. 1, the on/off command A output from the input circuit 1 is input to the gate drive circuit 2 and the first logic circuit 5. The output signal D of the second comparator 4 described later is also input to the logic circuit 5, and the output signal G of the logic circuit 5 is input to the second logic circuit 8. Further, the output signal F of the first comparator 7 described later is also input to the logic circuit 8, and the output signal J of the logic circuit 8 is input to the gate drive circuit 2 together with the on/off command A. .. The gate signal B generated by the gate drive circuit 2 is input to the gate of the IGBT 10.

The logic circuit 5 is composed of, for example, an AND circuit, and the logic circuit 8 is composed of, for example, an OR circuit.
Here, the gate drive circuit 2 constitutes the drive means in the claims, and the logic circuit 8 also constitutes the abnormality detection means.

The output current E of the sense terminal of the IGBT 10 is input to the current detection circuit 6, and the output signal of the current detection circuit 6 is input to the first comparator 7 together with the first threshold value TH ₁ . The output signal F of the comparator 7 is one input signal of the logic circuit 8 as described above.
Both ends (collector-emitter) of the IGBT 10 are connected to the both-end voltage detection circuit 3, and the output signal of the both-end voltage detection circuit 3 is input to the second comparator 4 together with the second threshold value TH ₂ . ing. The output signal D of the comparator 4 is one input signal of the logic circuit 5 as described above.
Further, the output signal J of the logic circuit 8 is input to the output circuit 9.

The input circuit 1 and the output circuit 9 are connected to, for example, a higher-order control circuit (not shown) provided outside, and the control circuit outputs the on/off command A output from the input circuit 1. Based on abnormality information, which is generated and transmitted from the output circuit 9, which will be described later, an alarm operation and a predetermined protection operation for other parts in the system are executed.

In this embodiment, the output signal F of the first comparator 7 based on the current E flowing through the sense terminal of the IGBT 10, the output signal D of the second comparator 4 based on the voltage C across the IGBT 10, and the ON/OFF command. Using A and A, the logic circuit 8 detects an abnormal event of the IGBT 10 such as an overcurrent abnormality or an open failure, and sends this abnormality detection signal J to the gate drive circuit 2 and the output circuit 9.
The gate drive circuit 2 operates the gate signal B so as to turn off the IGBT 10 when the abnormality detection signal J is input, and the output circuit 9 informs the external control circuit of abnormality information (overcurrent abnormality or open failure) of the IGBT 10. (Information indicating a) is transmitted.

Here, as the both-end voltage detection circuit 3, for example, the one described in Patent Document 1 may be used. Specifically, the cathode of the diode is connected to the collector of the IGBT 10, the resistor is connected between the anode and the positive electrode of the gate power supply, and the capacitor is connected between the anode and the negative electrode of the gate power supply (emitter of the IGBT 10). Then, the voltage across the capacitor may be detected and input to the comparator 4.
Further, the current detection circuit 6 may be configured to detect the sense current E from the voltage across a resistor connected between the sense terminal and the emitter of the IGBT 10, as described in Patent Document 2, for example. it can.

In order to avoid a malfunction, the logic circuit 8 can also prevent the abnormality detection signal J from being output for a certain period even when an abnormality is detected, and mask (prohibit) the gate signal B for turning off the IGBT 10. Further, when an abnormality is detected, the abnormality detection signal J is immediately output to shift the operation to turn off the IGBT 10, and the abnormality detection signal J may be held for a certain period even if the abnormal event is released. good.

FIG. 2 is a timing chart showing an operation when an overcurrent flows through the IGBT 10 with current sense , that is, when an overcurrent abnormality occurs as a first abnormal event in this embodiment. The operation will be described below with reference to FIGS.
The reference numerals A to J in FIG. 2 respectively correspond to the same reference numerals (command, signal, voltage, current) shown in FIG.

(1) Period I
The input circuit 1 outputs a command A for turning off the IGBT 10 (off command for logic “L”, on command for logic “H”). As a result, the gate signal B output from the gate drive circuit 2 also becomes “L”, and the IGBT 10 is turned off, so that the voltage C is generated across the IGBT 10.
At this time, if the threshold value TH ₂ is set so that the voltage C detected by the both-end voltage detection circuit 3 exceeds the second threshold value TH ₂ , the output signal D of the comparator 4 becomes “H”. Become.

Since the IGBT 10 is off now, no current flows in the sense terminal, and the current E detected by the current detection circuit 6 is almost zero and smaller than the first threshold value TH ₁ . Therefore, the output signal F of the comparator 7 becomes "L".
Further, since the command A is “L” and the signal D is “H”, the signal G is “L”. Since the logics of the input signals F and G of the logic circuit 8 are both "L", the output signal J of the logic circuit 8 is also "L".

(2) Period II
The input circuit 1 outputs a command A of logic “H” for turning on the IGBT 10, and the gate signal B output from the gate drive circuit 2 also becomes “H”.
When the IGBT 10 is turned on, the voltage C across it becomes almost 0 [V]. Therefore, the output signal D of the comparator 4 becomes "L".

Further, since the IGBT10 is turned on, current flows E proportional to the current _{I c} flowing between the input and output terminals of the IGBT10 to the sense terminal, by the current E is comparator 7 first threshold TH ₁ Compared to. At this time, if the threshold value TH ₁ is set so that the current E falls below the first threshold value TH ₁ , the output signal F of the comparator 7 becomes “L”.
On the other hand, since the output signal G of the logic circuit 5 is also "L", the output signal J of the logic circuit 8 is "L".

(3) Period III
The command A of logic “H” is continuously output from the input circuit 1, and the gate drive signal B remains “H”.
At this time, if a load short circuit or the like occurs and an overcurrent I _c flows through the IGBT 10, the voltage C across the IGBT 10 increases from almost 0 [V]. However, since the voltage C at both ends is less than the second threshold value TH ₂ , the output signal D of the comparator 4 remains “L”.

At this time, since the IGBT 10 is on, a current E that is substantially proportional to the current I _c flowing through the IGBT 10 flows through the sense terminal. When the current E exceeds the first threshold value TH ₁ , the output signal F of the comparator 7 becomes “H”.
The output signal G of the logic circuit 5 is "L", but the output signal J of the logic circuit 8 is about to be "H" because the signal F is "H". However, as described above, malfunction is avoided. By providing a mask period in the logic circuit 8 for the purpose, the output signal J holds "L".

(4) Period IV
The command A of logic “H” is continuously output from the input circuit 1.
Here, even if the mask period described in the period III has elapsed, since the signal F is “H” and the signal G is “L” at the end of the period III, the signal J is “H” in the period IV. .. At the same time, this signal J is sent to the output circuit 9, and the fact that the IGBT 10 has fallen into an abnormal event is transmitted from the output circuit 9 to an external control circuit.
The gate drive signal B becomes "L" as the signal J becomes "H", and the IGBT 10 is turned off. As a result, the voltage C and the signals D and G become "H".
The logic circuit 8 holds the abnormality detection signal J of logic “H” for turning off the IGBT 10 for a certain period, and accordingly, the gate drive signal B holds “L”. As a result, the signal transmitted from the output circuit 9 to the external control circuit also holds the same logic for a certain period.

As described above, in the present embodiment, the IGBT 10 is turned off when the comparator 7 detects an overcurrent based on the information of the current E flowing through the sense terminal of the IGBT 10, and the abnormality information is transmitted from the output circuit 9.
Note that, as described in the period III, the operation example of FIG. 2 is not sufficient to detect the magnitude of the voltage C at both ends when the overcurrent flows in the IGBT 10 by the voltage detection circuit 3 at both ends (both ends). (When the voltage C is less than the second threshold value TH ₂ ). In other words, even if the current that can be detected by the both-end voltage detection circuit 3 does not flow through the IGBT 10, it is possible to detect the overcurrent abnormality by using the IGBT 10 having the sense terminal.

Next, FIG. 3 is a timing chart showing an operation when the current sense IGBT 10 has an open failure as the second abnormal event in this embodiment. The operation will be described below with reference to FIGS. It should be noted that reference numerals A to J in FIG. 3 correspond to the same reference numerals (command, signal, voltage, current) shown in FIG. 1, respectively.

(1) Period I'
The logic of the command A and the signals B to J is the same as that of the period I in FIG. At this time, the IGBT 10 has an open failure, so that the voltage C has a predetermined magnitude and the current E is almost zero.

(2) Period II'
Similarly to the period II in FIG. 2, the command A and the signal B become “H”.
Although the IGBT 10 is turned on by the signal B, the voltage C across the IGBT 10 does not decrease because the IGBT 10 has an open failure. Therefore, the voltage C across the voltage exceeds the second threshold value TH ₂ , and the output signal D of the comparator 4 becomes “H”.
Since the current E at the sense terminal remains substantially zero and is smaller than the first threshold value TH ₁ , the output signal F of the comparator 7 remains “L”.

Further, since the command A is “H” and the signal D is also “H”, the signal G is “H”. At this time, since the signal F is "L" and the signal G is "H", the output signal J of the logic circuit 8 is about to be "H". Is provided, the output signal J holds "L".

(3) Period III'
The command A from the input circuit 1 remains “H”. Even after the mask period described in the period II′ has passed, the signal G is “H”, and thus the signal J is “H”. This signal J is sent to the output circuit 9, and the fact that the IGBT 10 has fallen into an abnormal event is transmitted from the output circuit 9 to an external control circuit.
The gate drive signal B becomes "L" as the signal J becomes "H", and the IGBT 10 is turned off.

The logic circuit 8 holds the abnormality detection signal J of logic “H” for turning off the IGBT 10 for a certain period, and accordingly, the gate drive signal B holds “L”. As a result, the signal transmitted from the output circuit 9 to the upper control circuit also holds the same logic for a certain period.
As described above, according to the present embodiment, with the circuit configuration of FIG. 1, not only the overcurrent abnormality but also the open failure of the IGBT 10 can be detected and transmitted as the abnormality information to the external control circuit.

In the operation examples of FIGS. 2 and 3 described above, it is not possible to determine whether the abnormality is due to an overcurrent abnormality or an open failure only by the state (logic) of the abnormality detection signal input to the output circuit 9. However, in any case, it is significant that the IGBT 10 can be quickly turned off to execute the protection operation when an abnormality occurs.
That is, in FIG. 2, when the on/off command A is in the on state, the current E exceeds the first threshold value TH ₁ , and the voltage C is less than the second threshold value TH _2. First, the logic circuit 8 detects the event as the first abnormal event, and the gate drive circuit 2 turns off the IGBT 10. Further, in FIG. 3, the on/off command A is in the on state, the current E is less than the first threshold TH ₁ , and the voltage C exceeds the second threshold TH ₂ . In this case, the logic circuit 8 detects the event as the second abnormality information, and the gate drive circuit 2 turns off the IGBT 10.
The second embodiment described below is effective for determining the cause of the abnormality.

FIG. 4 shows the configuration of the main part of the second embodiment of the present invention. In FIG. 4, a second logic circuit 8′ and first and second output circuits 9a and 9b are provided in place of the second logic circuit 8 and the output circuit 9 in FIG. It is possible to transmit different causes of abnormality from 9b.

In FIG. 4, the output signal G of the logic circuit 5 of FIG. 1 is applied to one input terminal of the AND gate 8a, and the output signal F of the comparator 7 of FIG. 1 is supplied to the other input terminal of the AND gate 8a via the NOT circuit 8b. Added to the input terminal.
The output signal of the AND gate 8a becomes the signal J ₁ via the timers 8c and 8d, and is applied to one input terminal of the OR gate 8g. The output signal F of the comparator 7 becomes the signal J ₂ via the timers 8e and 8f, and is applied to the other input terminal of the OR gate 8g. The signal J output from the OR gate 8g is input to the gate drive circuit 2 in FIG.
The signals J ₁ and J ₂ are input to the output circuits 9a and 9b, respectively, and the abnormality information is transmitted from these output circuits 9a and 9b to the external control circuit.

Here, in the timers 8c and 8d, when an abnormality occurs and the input once becomes "H", the abnormal event continues and the input is still "H" even after a certain period of time thereafter. In this case, "H" is output, and is mainly for preventing erroneous protection operation due to noise. In this case, a filter or the like can be used as a means other than the timer.

On the other hand, in the timers 8e and 8f, the input temporarily becomes "H" due to an abnormality, and then the protective action is activated to get out of the abnormal event, and even if the input is inverted to "L", the fixed time elapses. Until then, it has the function of continuously outputting "H".
This function is mainly for turning off the gate for a certain period of time when the IGBT 10 has an abnormal event, and for transmitting information indicating that an abnormal event has occurred to the upper control circuit for a certain period of time. is there. If this function is not provided, for example, when an overcurrent flows through the IGBT 10 due to an abnormality in the external circuit or the like, overcurrent protection and cancellation are repeated, and the IGBT 10 may be damaged.

In the configuration shown in FIG. 4, if the IGBT 10 has an open failure, the voltage C across the IGBT 10 does not drop even though the gate signal B is "H" due to the ON command A to the IGBT 10, so that the signal G becomes "H". On the other hand, since the IGBT 10 has an open failure, the current E does not flow to the sense terminal and the signal F becomes "L".

That is, in the state in which the signal F is “L” and the signal G is “H”, the voltage C across the IGBT 10 is reduced as in the period II′ in FIG. Since it is in the non-operation state, it can be determined that the IGBT 10 has an open failure. Therefore, it sends an output signal of the "H" level of the AND gate 8a, the timer 8c, 8d to the output circuit 9a as signal _{J 1} through. At the same time, the output signal J of the OR gate 8g is used to turn off the IGBT 10 via the gate drive circuit 2 of FIG.
The above-mentioned signal J ₁ is a signal indicating that the IGBT 10 has an open circuit failure, and transmits abnormality information indicating that the IGBT 10 has an open circuit failure to the control circuit via the output circuit 9a.

Moreover, if, when an overcurrent flows through the IGBT 10, becomes "H" signal F by the information of the current E of sense terminal, a timer 8e, even if the signal _{J 2} through 8f becomes "H".
Therefore, the output signal J of the OR gate 8g is used to turn off the IGBT 10 via the gate drive circuit 2 of FIG. 1, and the signal J ₂ is sent to the output circuit 9b to cause an overcurrent to the control circuit to the IGBT 10. Abnormality information indicating that there is is transmitted.

In FIG. 4, two output circuits 9a and 9b are provided as means for transmitting the occurrence of an abnormality in the IGBT 10 to a higher-order control circuit. It is also possible to change the type of signal according to current abnormality or open failure).
For example, the duty ratio of the signal whose logic repeats "H" and "L" may be changed according to the abnormal event, and the upper control circuit side may determine the abnormal event.

1: Input circuit 2: Gate drive circuit 3: Both end voltage detection circuits 4, 7: Comparators 5, 8, 8': Logic circuit 8a: AND gate 8b: Negation circuits 8c, 8d, 8e, 8f: Timer 8g: OR gate 6: Current detection circuit 9, 9a, 9b: Output circuit
10: IGBT with current sense

Claims (5)

To protect a semiconductor switch with a current sense, which includes a control terminal, an input terminal, an output terminal, and a sense terminal for detecting a current flowing between the input terminal and the output terminal, and which is formed as a single element. In the protection circuit of
Current detecting means for detecting a current flowing through the sense terminal,
First comparison means for comparing the current detection value by the current detection means with a first threshold value;
Voltage detection means for detecting a voltage between the input terminal and the output terminal,
Second comparing means for comparing the voltage detection value by the voltage detecting means with a second threshold value;
An ON/OFF command for the semiconductor switch with current sense is in an ON state, the detected current value exceeds the first threshold value, and the detected voltage value is less than the second threshold value. A first abnormal event is detected when the state continues for a first mask period, the detected current value is less than the first threshold value, and the detected voltage value is the second threshold value. An abnormality detecting means for detecting a second abnormal event when the value exceeding the value continues for the second mask period ,
Driving means for turning off the abnormal said Ri by the detecting means a first abnormal event or the said current sense with the semiconductor switch during detects a second abnormal event,
A protection circuit for a semiconductor switch with current sense, comprising: The protection circuit for a semiconductor switch with current sense according to claim 1,
The first abnormal event is a state in which an overcurrent is flowing between the input terminal and the output terminal, and the second abnormal event is an open failure of the semiconductor switch with current sense. A protection circuit for a semiconductor switch with current sensing. A protection circuit for a semiconductor switch with current sense according to claim 1 or 2,
A semiconductor with current sense , comprising an output means for transmitting abnormality information to an external control circuit for generating the ON/OFF command when the first abnormal event or the second abnormal event is detected. Switch protection circuit. A protection circuit for a semiconductor switch with current sense according to any one of claims 1 to 5,
Current sense , comprising: first output means for transmitting the first abnormal event to the control circuit; and second output means for transmitting the second abnormal event to the control circuit. Protection circuit for semiconductor switches with. A protection circuit for a semiconductor switch with current sense according to any one of claims 1 to 4 ,
The semiconductor switch with current sense, the current detecting unit, the first comparing unit, the voltage detecting unit, the second comparing unit, the abnormality detecting unit, and the output unit are housed in a single package. A protection circuit for a semiconductor switch with current sensing.

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