JP6749862B2 - Series multiple inverter device - Google Patents

Description

The present invention relates to a serial multiple inverter device including a plurality of unit inverters and having a failure diagnosis function.

In a power converter that outputs three-phase power, a plurality of unit inverters that output a single-phase AC voltage are connected in series in order to increase the capacity and voltage of the power converter and to improve the output waveform. A series multiple inverter device is known which is connected to obtain a voltage of one phase. In such a series multiple inverter device, when one of the unit inverters fails, the operation is usually stopped to identify the failed unit inverter. However, when the number of unit inverters is large, It took a lot of time to identify the failed inverter. Therefore, a serial multiple inverter device has been proposed in which a failure diagnosis gate signal is sequentially given to all unit inverters, and the unit inverters that have failed are identified by checking the outputs to the unit inverters (for example, patents). Reference 1.).

JP, 2006-217772, A (the whole)

According to the method of Patent Document 1, it is possible to identify the failed unit inverter by the failure diagnosis regardless of whether the failure mode of the unit inverter is an open failure or a short circuit failure. However, it takes time and trouble to give a gate signal to all the unit inverters one after another, and check the output of the gate signal to perform the failure diagnosis, which also increases the diagnosis time.

The present invention has been made in view of the above problems, and an object thereof is to provide a series multiple inverter device capable of realizing a failure diagnosis function by a relatively simple method.

In order to achieve the above object, the serial multiple inverter device of the present invention obtains a phase voltage of one phase by connecting in series the outputs of a plurality of unit inverters that convert a given DC voltage into a single-phase AC voltage. The three-phase serial multi-inverter, the auxiliary resistor for detecting the output voltage of the serial multi-inverter, and the controller for monitoring and controlling the serial multi-inverter are provided, and the controller includes A main control unit for controlling the serial multiple inverter, a gate circuit for giving a gate signal to each of the unit inverters according to a command from the main control unit, a voltage detection circuit for detecting the voltage of the auxiliary resistor, and an off-line Has a failure diagnosis unit that operates in
The failure diagnosis unit sequentially gives, to the gate circuit, gate commands of a plurality of modes in which the combinations of output voltages of the respective stages of the unit inverter are different from each other, and the failure detection unit of the voltage detection circuit in each of the modes. The feature is that the failed unit inverter is identified from the combination of the detected voltages.

According to the present invention, it is possible to provide a series multiple inverter device capable of realizing a failure diagnosis function by a relatively simple method.

1 is a circuit configuration diagram of a serial multiple inverter device according to a first embodiment of the present invention. 1 is a circuit configuration diagram of a unit inverter according to a first embodiment of the present invention. FIG. 1 is a fault diagnosis explanatory diagram 1 of the series multiple inverter device according to the first embodiment of the present invention. 3 is a flowchart of failure diagnosis of the serial multiple inverter device according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining failure diagnosis of the serial multiple inverter device according to the first embodiment of the present invention. FIG. 3 is a fault diagnostic explanatory diagram 3 of the serial multiple inverter device according to the first embodiment of the present invention. 2 is a circuit configuration diagram of a serial multiple inverter device according to a second embodiment of the present invention. FIG. Explanatory drawing of the serial multiple inverter apparatus which concerns on Example 2 of this invention.

Embodiments of the present invention will be described below with reference to the drawings.

Hereinafter, a serial multiple inverter device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 6. First Embodiment FIG. 1 is a circuit configuration diagram of a serial multiple inverter device according to a first embodiment of the present invention.

A three-phase AC voltage is supplied from the AC power supply 1 to the input transformer 2. The input transformer 2 has a plurality of sets of insulated three-phase secondary windings, nine sets in this embodiment. Each of these nine sets of secondary windings supplies three-phase AC power to the unit inverters 3U1, 3V1, 3W1, 3U2, 3V2, 3W2, 3U3, 3V3 and 3W3.

As shown in FIG. 2, for example, the unit inverter 3 includes a rectifier circuit 31 that converts an AC input into a DC, a DC capacitor 33 that smoothes the DC, and an inverter circuit 32 that converts the DC into a single-phase AC. .. The inverter circuit 32 forms a full bridge circuit by the positive side elements 32Up and 32Vp and the negative side elements 32Un and 32Vn. Diodes 32UpD and 32VpD and diodes 32UnD and 32VnD are connected in antiparallel to the positive side elements 32Up and 32Vp and the negative side elements 32Un and 32Vn, respectively.

The single-phase outputs of the unit inverters 3U1, 3U2 and 3U3 are connected in series, one end of which is connected to the neutral point N and the other end A is connected to the U-phase terminal of the AC electric motor 4 via the three-phase switch 5. There is. Similarly, the single-phase outputs of the unit inverters 3V1, 3V2, and 3V3 are connected in series, and one end thereof is connected to the neutral point N and the other end B is connected to the V-phase terminal of the AC electric motor 4 via the three-phase switch 5. The unit inverters 3W1, 3W2, and 3W3 are connected in series, and one end thereof is connected to the neutral point N and the other end C is connected to the W-phase terminal of the AC motor 4 via the three-phase switch 5. Connected. By connecting the nine unit inverters 3 in this manner, the nine unit inverters 3 constitute a serial multiple inverter of three-phase output. The neutral point N is not grounded.

A controller 7 is provided to monitor and control this serial multiple inverter. Further, in order to measure the voltage of each phase of the series multiple inverter, a voltage-monitoring three-phase voltage dividing auxiliary resistor 6 is star-connected to the input side of the switch 5, that is, the terminals A, B and C. The voltage that is provided and is applied to the voltage dividing portion of the resistor of each phase of the voltage dividing auxiliary resistor 6 is given to the voltage detection circuit 73 of the control device 7. The neutral point E of the voltage dividing auxiliary resistor 6 is grounded to the ground potential. The serial multiple inverter device composed of the nine unit inverters 3, the switch 5, the control device 7, and the voltage dividing auxiliary resistor 6 has a phase difference of 120° with respect to the AC motor 4 at a desired frequency. The phase voltage is applied.

Hereinafter, the internal configuration of the control device 7 will be described.

The main control circuit 71 gives to the gate circuit 72 a gate signal to give to the series multiplex inverter for controlling the AC electric motor 4 to operate at a desired operating speed, for example. The gate circuit 72 distributes and outputs gate signals to the unit inverters 3U1, 3U2 and 3U3, 3V1, 3V2 and 3V3, and 3W1, 3W2 and 3W3 that form a serial multiplex inverter. The voltage of each phase detected by the voltage detection circuit 73 is given to the failure diagnosis circuit 74. The failure diagnosis circuit 74, for example, when any one of the unit inverters 3 constituting the series multiple inverter fails and the protection of the apparatus is activated and stopped, a failure command such as a gate command to be described later is specified to identify the failed unit inverter. A corresponding detection phase voltage is obtained by supplying the voltage to the gate circuit 72 and the synchronization signal synchronized with the gate command to the voltage detection circuit 73. That is, it is the voltage between the terminals A, B, and C and the ground E. Then, the failed unit inverter 3 is specified by the value of the detected phase voltage when the gate command is changed. The fault diagnosis circuit 74 basically assumes the identification of a faulty unit inverter in the state where the upper and lower arms of any of the unit inverters 3 are short-circuited. Further, the failure diagnosis circuit 74 does not operate in the online state where the serial multiple inverter is normally operating, but operates in the offline state.

Here, the output voltage of each phase of the serial multiple inverter, that is, the voltage between A and N which is the U phase is Vu, the voltage between B and N which is the V phase is Vv, and the voltage between C and N which is the W phase. The voltage is Vw. Further, assuming that the detected phase voltage of the auxiliary voltage dividing resistor 6, that is, the voltage between the terminals A and E is Va, the voltage between the terminals B and E is Vb, and the voltage between the terminals C and E is Vc, the following equations (1) to ( 3) is established.

Va=(2Vu-Vv-Vw)/3 (1)
Vb=(2Vv-Vw-Vu)/3 (2)
Vc=(2Vw-Vu-Vv)/3 (3)
FIG. 3 shows the basic operation of the failure diagnosis performed by the failure diagnosis circuit 74. Although the failure diagnosis is performed for each of the U, V, and W phases, the U phase is shown here. Further, the unit inverter 3 is described by simply omitting 3U1 like U1. When performing a failure diagnosis on the U-phase, each unit inverter (3U1, 3U2, 3U3) of the U-phase is given a gate signal for outputting a voltage in a mode described later, but the V-phase and the W-phase are all unit inverters (3V1, 3V2, 3V3, 3W1, 3W2, 3W3) gives a gate signal that makes the voltage output zero (Vv=0 and Vw=0). In the circuit shown in FIG. 2, the method of setting the voltage output of the unit inverter 3 to zero is to turn on the switching elements 32Up and 32Vp and turn off the switching elements 32Un and 32Vn. Alternatively, even if the switching element 32Up and the switching element 32Vp are turned off and the switching element 32Un and the switching element 32Vn are turned on, the output voltage of the unit inverter 3 becomes zero.

By doing so, the detection voltage Va becomes the formula (4).

Va=2Vu/3 (4)
In FIG. 3, the meaning of the six modes from mode (A) to mode (F) is to output +1 to the unit inverters 3U1, 3U2 and 3U3 as described in the upper part of the figure. That is, the gate signals are provided in six combinations of whether to output 1. Further, + means that the unit inverter outputs when the load side is positive and the neutral point N side is negative and the unit inverter outputs, and the load side is negative and the neutral point N side is positive. Further, +1 and -1 are values obtained by normalizing the DC voltage of the unit inverter 3.

Then, the U-phase detection voltage Va of the auxiliary voltage dividing resistor 6 in each of these modes is divided into the cases of normal operation of one unit, abnormal operation of one unit, abnormal operation of two units, and abnormal operation of all units, and detection. When a plurality of voltages are considered, both of them are described above and below, and the unit inverter that is logically assumed to be abnormal from the detected voltage is described below the detected voltage. According to FIG. 3, by checking the three modes of modes (A), (B), and (C), the unit inverter in which the short-circuit fault has occurred can be specified. Further, in order to specify this, it is not limited to the modes (A), (B), and (C) of FIG. 3, and 3 units having the same polarity, 3 units having different polarities, and 3 units having different polarities. Any mode will do. Since the input voltage of the voltage detection circuit 73 is a value obtained by dividing the detection phase voltages Va, Vb, Vc of the auxiliary voltage resistor 6 into appropriate values, the voltage detection circuit 73 outputs the detection phase voltages Va, Vb, This is equivalent to detecting Vc. Therefore, hereinafter, the voltage division by the voltage dividing auxiliary resistor 6 and the detection by the voltage detection circuit 73 will be omitted, and will be simply expressed by the detected phase voltage.

Note that modes (E), (F), and (G) are modes in which each unit inverter outputs a voltage of −1 with opposite polarity. This check is performed when the upper and lower arms of the unit inverter are short-circuited. Is equivalent to the checks in modes (A), (B) and (C) and has no meaning. However, in a rare case where only one arm of the unit inverter has a short-circuit fault, if an on-gate is given to the fault arm and, for example, mode (A) is checked, the fault cannot be detected. It is understood that the failure can be detected by checking with ().

FIG. 4 is an example of a flowchart of failure diagnosis performed by the failure diagnosis circuit 74 based on FIG. This flow chart is a failure diagnosis procedure only for the U phase, and is basically a procedure for following the contents of the matrix display of FIG. 3 from the upper left portion to the lower right portion.

First, start in mode (A) (ST1). Then, it is checked whether the detected phase voltage value Va (hereinafter, simply referred to as a detected value) is +2 (ST2). If it is +2, it is judged that all unit inverters are normal (ST2A), and the flow exits. If it is other than +2 in step ST2, it is checked whether it is +4/3 (ST3). If it is +4/3, the failure diagnosis circuit 74 gives a gate command for mode (B) to the gate circuit 72 (ST4). Then, it is checked whether the detected value is 0 (ST5). If it is not 0 here, it is judged that the unit inverter 3U3 has a short circuit failure (ST5A), and the flow is exited. If the detected value is 0 in step ST5, the mode is shifted to the mode (C) (ST6), and it is checked whether the detected value is -2/3 (ST7). If the detected value is -2/3 in step ST7, it is determined that the unit inverter 3U2 has a short circuit failure (ST7A), and the flow exits. If the detected value is not −2/3, it is determined that the unit inverter 3U1 has a short circuit failure (ST7B), and the flow exits.

If the detected value is not +4/3 in step ST3, it is checked whether it is 2/3 (ST8). If it is 2/3 here, the failure diagnosis circuit 74 gives a gate command for mode (B) to the gate circuit 72 (ST4). Then, it is checked whether the detected value is -2/3 (ST9). If it is -2/3, it is determined that the unit inverters 3U1 and 3U2 have a short circuit failure (ST9A), and the flow is exited. If the detected value is not -2/3 in step ST9, the mode is changed to the mode (C) (ST6), and it is checked whether the detected value is 2/3 (ST10). If the detected value is 2/3 in step ST10, it is determined that the unit inverters 3U2 and 3U3 have a short circuit failure (ST10A), and the flow exits. If the detected value is not 2/3, it is determined that the unit inverters 3U1 and 3U3 have a short circuit failure (ST10B), and the flow exits.

It is a rare case when the detected value is not 2/3 in step ST8, but in this case, it is determined that all unit inverters have a short circuit failure or one or more unit inverters have an open failure (ST8A). Exit the flow.

This completes the failure diagnosis for the U phase. When the U phase ends, the other two phases are diagnosed by the same procedure. At first glance, the procedure seems complicated, but in most cases, one unit inverter of one phase or two phases usually fails, and if automatic detection is performed, failure diagnosis for three phases can be completed. Since it does not take as long as 1 second, it becomes possible to easily and quickly perform fault diagnosis.

FIG. 5 is a diagram corresponding to FIG. 3 of a series multiple inverter in which each phase has four unit inverters, that is, when the number of series stages is four. As shown in FIG. 5, U4 (unit inverter 3U4) is added, and the diagnostic contents are described even when three units are abnormal. In addition, the gate signal application modes are described in four modes A, B, C, and D in contrast to the three modes A, B, and C in FIG. In the case of FIG. 5 as well, it can be confirmed that the failure diagnosis can be performed by creating the flowchart of FIG. 4 corresponding to FIG. 3, but the illustration is omitted here.

As a general theory, when the number of series stages of the unit inverter of the series multiplex inverter is N, "all stages output +1", "only Nth stage outputs -1 and the other stages output +1" , "N-1st and Nth stages output -1 and the other stages output +1", ..., "2nd to Nth stages output -1, 1st stage It can be said that it is possible to identify a unit inverter that has failed as shown in FIGS. 3 to 4 by checking a total of N modes in which “only outputs +1”.

Next, a modification of the first embodiment will be described. In the description based on FIG. 3, the failed unit inverter 3 is specified by increasing the number of stages that invert the polarity of the output of the unit modules connected in series. However, it is also possible to identify the defective unit inverter by reversing the polarity of only one of the unit modules connected in series and changing the position of the reversing stage. FIG. 6 shows an example thereof. Although the failure diagnosis is performed for each of the U, V, and W phases, the U phase is shown here as in FIG. The voltage output of the unit inverters for the V phase and the W phase is arbitrary, but the voltage output is not changed while the failure diagnosis is being performed for the U phase. By doing so, the detection voltage when a gate signal for outputting a voltage of +1 is applied to all the unit inverters forming the U phase shown in mode (A) is set to Va (herein referred to as Vaa), and is set to a certain value. In the case of a mode (mode (B) to (D)) in which a gate signal that outputs a voltage of -1 is applied to the unit inverter (for example, U3) and a gate signal that outputs +1 is applied to another unit inverter (mode (B) to (D)) Then, if the unit inverter that gives the gate signal that outputs -1 is defective, then equation (5) holds. If the unit inverter that gives the gate signal that outputs -1 is normal, Becomes equation (6).

Van=Vaa (5)
Van=Vaa-2/3 (6)
That is, in the procedure of FIG. 6, the detection voltage Vaa in the mode (A) is compared with the detection voltage Va in the other modes (B to D), and if they are the same, a gate signal that outputs −1 in the mode is given. If the unit inverter is out of order and the detection voltage Van in the other mode is smaller than the detection voltage Vaa in the mode (A) by 2/3, the unit inverter that gives a gate signal that outputs -1 in the mode concerned Can be judged to be normal. In the case of FIG. 6 as well, it can be confirmed that the failure diagnosis can be performed by creating the flowchart of FIG. 4 corresponding to FIG. 3, but the illustration is omitted here.

In this way, according to the modified example of FIG. 6, when the number of series stages of the unit inverter of the series multiplex inverter is N, “all stages output +1” and “only the Nth stage outputs −1”. , The other stages output +1", "only the N-1th stage outputs -1 and the other stages output +1", ..., "only the Nth stage outputs -1 and the other The unit inverter that has failed can be specified by checking a total of N+1 modes in which the stage outputs +1.

In addition, when Vv and Vw, which are the total voltage outputs of the unit inverters of the V phase and the W phase, are known in advance, the mode of “all stages output +1” in mode A may be omitted. That is, in the mode in which the change in the detection point Va when the stage of the unit inverter given the gate command that outputs -1 only for one stage is changed is stored and a value that is 2/3 higher than the other is output, It is determined that the unit inverter that has given the gate signal that outputs is defective. Further, when Va is the same regardless of the mode, if Va at that time is formula (7), the U-phase unit inverter is in all stages failure, and if Va is formula (8), the U-phase unit inverter is It can be judged that all stages are normal,
Va=(-Vv-Vw)/3 (7)
Va=(2N-2-Vv-Vw)/3 (8)
Incidentally, even if all of the output polarities of the unit inverter, +1 and -1, are reversed, the present method is established.

Hereinafter, a serial multiple inverter device according to a second embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 is a circuit configuration diagram of a serial multiple inverter device according to a second embodiment of the present invention.

Regarding each part of the second embodiment, the same parts as those of the circuit configuration diagram of the serial multiple inverter device according to the first embodiment of the present invention shown in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. The second embodiment differs from the first embodiment in that the control device 7 is changed to a control device 7A.

In the control device 7 in the first embodiment, the failure diagnosis circuit 74 gives the gate command to the gate circuit 72, but the failure diagnosis circuit 74A in the second embodiment sends the monitoring command instead of the gate command to the main control circuit 71. To give to. Upon receiving the monitoring command from the failure diagnosis circuit 74A, the main control circuit 71 gives a gate command of a predetermined frequency to the gate circuit 72 for a predetermined short time. The gate circuit 72 outputs a gate signal to each unit inverter based on this gate command, and at the same time gives a synchronizing signal to the voltage detection circuit 73. The failure diagnosis circuit 74A performs failure diagnosis by analyzing the detected voltage that changes from time to time obtained from the voltage detection circuit 73. The point of the second embodiment is that the gate signal of the predetermined frequency is the same as the gate signal given to the gate circuit 72 by the main control circuit 71 during the normal operation.

FIG. 8 shows an example of the waveforms of the output voltages VU1, VU2 and VU3 of each unit inverter based on the gate signal and the output voltage Vu of the U phase obtained by combining these. As shown in the figure, when the phase of VU2 is delayed by φ1 with respect to VU3 and VU1 is delayed by φ2 with respect to VU2, the waveform of Vu is improved and becomes closer to a sine wave. Even when the PWM control is performed, if the phases are shifted and added as shown in FIG. 8, the harmonics are further reduced. Further, since the effective value of Vu changes when the phase differences φ1 and φ2 are changed, it is not necessary to perform PWM control. Incidentally, when PWM control is performed, it is desirable to cancel the modulation by the carrier at the time of failure diagnosis. It should be noted that the phase differences φ1 and φ2 are set to a phase difference sufficient for the voltage detection circuit 73 to accurately detect the voltage. When the failure diagnosis of the unit inverters 3U1, 3U2, 3U3 of the U phase is performed, the output voltages Vv and Vw of the other phases are not changed, and the failure diagnosis of the unit inverters 3V1, 3V2, 3V3 of the V phase is performed. Do not change the output voltages Vw and Vu of the other phase when performing the operation, and do not change the output voltages Vu and Vv of the other phase when performing the failure diagnosis of the unit inverters 3W1, 3W2, 3W3 of the W phase. To do.

The period of each mode of A, B, C, D, E, and F corresponding to the mode of FIG. 3 is shown above the waveform of Vu. As will be easily understood from now on, when a monitoring command as shown in the figure is given, if the monitoring period is set so as to operate from the state of mode (A) to start monitoring and complete in mode (C). It is apparent from the basic operation diagram of FIG. 3 or the flow chart of FIG. 4 that the failed unit inverter can be identified from the combination of the detected voltages in each mode.

It should be noted that the fault diagnosis for one phase may be performed in the monitoring period shown in FIG. 8. However, in the case of continuously performing fault diagnosis for three phases, the monitoring period is extended so as to be approximately one cycle, and each phase is set to the figure. The monitoring may be performed at the timing of the monitoring period of 8.

Although the embodiments of the present invention have been described above, they are presented as examples and are not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

For example, although the number of series stages of the unit inverter is three in FIG. 1, any number of stages may be used as long as it is two or more as described in the case of four stages in FIG.

Further, although the unit inverter 3 of FIG. 2 has three phases of inputs, it may have a single phase. Although the rectifier circuit 31 is composed of an uncontrollable diode rectifier, it may be a converter circuit using an element capable of controlling a DC voltage such as an IGBT or a thyristor.

Further, instead of the rectifier circuit and the converter circuit, another DC power supply, for example, a battery may be provided on the input side of the inverter circuit 32 to form a unit inverter.

The load of the serial multiple inverter does not necessarily have to be the AC motor 4, but may be, for example, a heater.

Further, the switch 5 is not always necessary even if the load is an AC motor.

Further, the voltage detection circuit 73 may be provided for three phases, or only one phase may be provided for switching.

Further, in the first and second embodiments, it is described that the failure diagnosis is performed when the failure as the device occurs, but the failure diagnosis of the present application is not limited to the time when the failure occurs, for example, before the start of the operation. By doing so, it becomes possible to detect a failure of the unit inverter that has not been detected as a failure of the device before operation.

1 AC power supply 2 Input transformer 3, 3U1, 3U2, 3U3, 3V1, 3V2, 3V3, 3W1, 3W2, 3W3 Unit inverter 4 AC motor 5 Switch 6 Voltage dividing auxiliary resistor 7, 7A Controller 31 Rectifier circuit 32 Inverter Circuits 32Up, 32Vp, 32Un, 32Vn Semiconductor elements 32UpD, 32VpD, 32UnD, 32VnD Diode 33 DC capacitor 71 Main control circuit 72 Gate circuit 73 Voltage detection circuit 74, 74A Fault diagnosis circuit

Claims (7)

A three-phase serial multiple inverter that connects the outputs of a plurality of unit inverters that convert a given DC voltage into a single-phase AC voltage in series to obtain a phase voltage of one phase,
An auxiliary resistor for detecting the output voltage of the series multiple inverter,
A controller for monitoring and controlling the serial multiple inverter,
The control device is
A main control unit for controlling the serial multiple inverter, a gate circuit for giving a gate signal to each of the unit inverters according to a command of the main control unit, a voltage detection circuit for detecting a voltage of the auxiliary resistor, and an off-line Has a failure diagnosis unit that operates in
The failure diagnosis unit,
With respect to the gate circuit, a combination of output voltages of each stage of the unit inverter is sequentially given a gate command in a plurality of modes for each phase, from a combination of detection voltages of the voltage detection circuit in each of the modes, A serial multi-inverter device characterized by identifying a failed unit inverter. The given DC voltage is converted into a single-phase AC voltage, and the outputs of a plurality of unit inverters whose output phases are shifted from each other by a predetermined value or more are connected in series to obtain a one-phase voltage. 3-phase serial multiple inverter,
An auxiliary resistor for detecting the output voltage of the series multiple inverter,
A controller for monitoring and controlling the serial multiple inverter;
The control device is
A main control unit for controlling the serial multiple inverter, a gate circuit for giving a gate signal to each of the unit inverters according to a command from the main control unit, a voltage detection circuit for detecting the voltage of the auxiliary resistor, and an off-line Has a failure diagnosis unit that operates in
The failure diagnosis unit,
An operation command is given to the main control unit for a predetermined time, and a failed unit inverter is identified from a combination of a gate signal to each unit inverter at that time and a time-series change of the detection voltage of the voltage detection circuit. A serial multiple inverter device characterized by the following.
The load of the series multiple inverter is an AC motor,
Provided with a switch that shuts off the input of the AC motor,
The serial multiple inverter device according to claim 1 or 2, wherein the switch is turned off when the fault diagnosis unit performs a fault diagnosis. The number of series stages of the unit inverter is N (N≧2),
When the gate signal is controlled so that the output voltage on the load side of the unit inverter becomes positive, the value is +1, and when the gate signal is controlled so that the output voltage on the load side becomes negative, the value is -1,
In the plurality of modes, all the stages are +1, only the Nth stage is -1, the other stages are +1, the N-1th and Nth stages are -1, and the other stages are +1... 2nd to Nth stage is -1 and only 1st stage is +1
2. The serial multiple inverter device according to claim 1, wherein the serial multiple inverter device comprises a total of N units. The failure diagnosis unit,
5. The serial multiple inverter device according to claim 4, wherein all the stages first check the +1 mode, and when the detected voltage is not +N, the other modes are checked. The failure diagnosis unit,
First, the mode in which all stages are +1 is checked, and when the detection voltage is +(N-1), the mode for recognizing the failed unit inverter as one unit and specifying the failed unit inverter is checked, The serial multiple inverter device according to claim 5, wherein the check when the detected voltage is not +(N-1) is performed after that. The number of series stages of the unit inverter is N (N≧2),
When the gate signal is controlled so that the output voltage on the load side of the unit inverter becomes positive, the value is +1, and when the gate signal is controlled so that the output voltage on the load side becomes negative, the value is -1,
In the plurality of modes, only the Nth stage is -1 and the other stages are +1; the N-1th stage is -1, the other stages are +1... Is +1
2. The serial multiple inverter device according to claim 1, wherein the serial multiple inverter device comprises a total of N units.