JP6750382B2 - Display driver, electro-optical device, and electronic device - Google Patents

Description

The present invention relates to a display driver, an electro-optical device, an electronic device and the like.

A conventional display driver includes a D/A conversion circuit that converts display data of each pixel into a voltage, and an amplifier circuit that drives each pixel with a data voltage based on the voltage. Since the amplifier circuit performs feedback control, the data voltage can be controlled to the target voltage even if the capacitance of each data line (for example, the parasitic capacitance between data lines) is different.

In recent years, the driving time per pixel has been shortened due to the progress in high definition of electro-optical panels. For example, in the phase expansion drive (for example, Patent Document 1) in which source lines are sequentially driven by several lines to several tens of lines, the number of pixels that can be driven at one time is several to tens, so that high definition is achieved. Driving time per pixel is extremely short. When the driving time is shortened as described above, it is necessary to increase the driving ability of the amplifier circuit (shorten the settling time), but when the driving ability of the amplifier circuit is increased, the accuracy of the output voltage is relatively reduced. In order to achieve both of these, it is necessary to increase the current consumption of the amplifier circuit, but heat generation (temperature rise) of the display driver becomes large, and it is becoming difficult to cope with high definition.

JP, 2001-324970, A

In order to deal with the above problems, a method of driving without feedback control and then settling to a highly accurate data voltage by an amplifier circuit (or a method of driving only with no feedback control) is considered. To be For example, a method of sharply changing the data voltage to the target voltage by connecting the output terminal to the power supply in a predetermined period with a transistor having a driving ability according to the gradation difference between the previous display data and the next display data. (Digital assist drive). Alternatively, a method (capacitance driving) of abruptly changing the data voltage to the target voltage by performing charge redistribution of the charge amount according to the display data between the capacitance of the data line or pixel and the capacitance of the drive circuit is possible. is there.

However, since feedback control is not performed in these methods, when the capacitance of each data line (for example, the parasitic capacitance between the data lines) is different, the error between the actually reached data voltage and the target voltage is different for each data line. However, there is a problem in that the display quality varies (display unevenness occurs). If an amplifier circuit tries to correct such an error between the data voltage and the target voltage, the amplifier circuit needs a driving capability for settling the data voltage in a short time, which eventually increases the power consumption of the amplifier circuit. become.

In addition, since the display driver may be generally used for various electro-optical panels, it is necessary to reduce display unevenness due to variations in the capacitance of the data line when used for various electro-optical panels. ..

According to some aspects of the present invention, it is possible to provide a display driver, an electro-optical device, an electronic device, and the like that can reduce display unevenness due to variations in the capacitance of data lines according to various electro-optical panels.

According to one embodiment of the present invention, a plurality of output terminals that output a plurality of data signals output to an electro-optical panel and a plurality of capacitance circuits in which each capacitance circuit is provided between adjacent output terminals of the plurality of output terminals. And a control circuit for setting the capacitance value of each capacitance circuit.

According to one embodiment of the present invention, a capacitance circuit is provided between adjacent output terminals, and the capacitance value of the capacitance circuit is controlled. This makes it possible to adjust the total of the parasitic capacitance between the data lines in the electro-optical panel and the capacitance value of the capacitance circuit to be substantially the same for each data line. Since the capacitance between the data lines is substantially the same for each data line, the variation of the data voltage due to the coupling of the capacitance is substantially uniform for each data line, and the display unevenness can be reduced. Although the variation in the parasitic capacitance between the data lines varies depending on the type of the electro-optical panel, according to one embodiment of the present invention, the above-described adjustment can be made in the capacitance circuit of the display driver, so that it can be applied to various electro-optical panels. It is possible to reduce display unevenness due to variations in the capacitance of the data lines.

Further, according to an aspect of the present invention, each capacitance circuit may include a capacitor group and at least one switch group that connects each capacitor of the capacitor group and the output terminal.

According to one aspect of the present invention, the connection between each capacitor of the capacitor group and the output terminal can be controlled by the switch group. As a result, the capacitance between adjacent output terminals can be adjusted by the capacitance circuit, and the capacitance between the data lines can be made uniform by correcting the variation in the parasitic capacitance between the data lines.

In one aspect of the present invention, each of the capacitance circuits includes a first switch group having one end connected to the i-th output terminal of the plurality of output terminals and the other end connected to one end of the capacitor group. A second switch group having one end connected to the (i+1)th output terminal adjacent to the ith output terminal and the other end connected to the other end of the capacitor group, as the at least one switch group. You may.

According to one aspect of the present invention, the capacitor group is connected between the adjacent output terminals by the first switch group and the second switch group. Accordingly, by controlling ON/OFF of each switch of the first and second switch groups, it is possible to control whether or not each capacitor of the capacitor group is connected between the adjacent output terminals.

Further, in one aspect of the present invention, the plurality of capacitance circuits include a first output terminal and a first output terminal (n is an integer of 2 or more) which are the plurality of output terminals, and an nth output terminal and a first output terminal. A capacitance circuit provided between the output terminal and the output terminal may be included.

In the phase expansion type electro-optical panel, there is also parasitic capacitance between the nth data line and the first data line, and this parasitic capacitance also causes display unevenness due to variations in parasitic capacitance between the data lines. In this regard, according to one embodiment of the present invention, since the capacitor circuit is provided between the nth output terminal and the first output terminal, the capacitance between the nth data line and the first data line is increased. Can be adjusted, and display unevenness can be reduced.

In one aspect of the present invention, the capacitance value of each of the capacitors in the capacitor group may be binary weighted.

With this configuration, the capacitance value of the capacitance circuit can be adjusted by controlling the switch group of the capacitance circuit with the binary code corresponding to the capacitance value set in the capacitance circuit.

Further, in one aspect of the present invention, the control circuit may include a register that stores capacitance value setting information that sets a capacitance value of each of the capacitance circuits.

According to one embodiment of the present invention, by having a register that stores capacitance value setting information, the capacitance value of the capacitance circuit can be variably adjusted by changing the capacitance value setting information. As a result, it is possible to adjust the capacitance between the data lines corresponding to various electro-optical panels having different parasitic capacitances between the data lines.

Further, in one aspect of the present invention, a measurement circuit that measures capacitance value information between a plurality of data lines of the electro-optical panel is included, and based on the capacitance value information measured by the measurement circuit, A capacity value may be set.

According to one embodiment of the present invention, by measuring capacitance value information between data lines, the capacitance value of the capacitance circuit is adjusted based on the capacitance value information so that the capacitance between the data lines becomes the same. Is possible.

Further, in one aspect of the present invention, the measurement circuit includes a comparison circuit in which a determination voltage is input to a first input terminal, and an output terminal of any one of the plurality of output terminals, which is a second input terminal of the comparison circuit. And a switch group connected to.

According to one aspect of the present invention, one of the output terminals is connected to the second input terminal of the comparison circuit by the switch group, and the voltage of the output terminal is compared with the determination voltage. As a result, the voltage fluctuation at the output terminal can be compared with the determination voltage, and the capacitance value information can be acquired from the comparison result.

In one aspect of the present invention, when the voltage of the i-th output terminal among the plurality of output terminals changes, the switch group sets the (i+1)th output terminal adjacent to the i-th output terminal to the second output terminal. The comparison circuit may connect the voltage of the (i+1)th output terminal to the determination voltage.

According to the aspect of the present invention, when the voltage of the i-th output terminal adjacent to the i+1-th output terminal is changed, the voltage fluctuation of the i+1-th output terminal can be compared with the determination voltage by the comparison circuit. Since the magnitude of the voltage fluctuation of the (i+1)th output terminal changes according to the capacitance value of the parasitic capacitance between the adjacent data lines, the capacitance value information of the parasitic capacitance can be measured based on the comparison result by the comparison circuit.

Further, according to one aspect of the present invention, a drive circuit that outputs the plurality of data signals to the plurality of output terminals may be included.

When the drive circuit changes the voltage of the data signal, the coupling of the parasitic capacitance between the data lines causes the voltage of the output terminal adjacent to the output terminal that has changed the voltage of the data signal to change. At this time, if the parasitic capacitance between the data lines varies, the voltage fluctuation due to the coupling also varies. In this respect, according to one embodiment of the present invention, since the capacitance between the data lines can be adjusted by the capacitance circuit, variation in voltage fluctuation due to coupling can be reduced. This makes it possible to reduce display unevenness.

Further, in one aspect of the present invention, the drive circuit includes an amplifier circuit provided corresponding to each output terminal of the plurality of output terminals, and a drive assist circuit for assisting driving by the amplifier circuit, The drive assist circuit may perform pre-driving based on the gradation change information of the data signal.

When the voltage reached by the pre-driving of the drive assist circuit deviates from the target voltage, it is corrected by driving the amplifier circuit. However, if the correction is large, a large driving capability is required for the amplifier circuit, which increases power consumption. If the parasitic capacitance between the data lines varies, the capacitance charged by the drive assist circuit will be different for each data line, which causes the deviation from the target voltage as described above. According to one embodiment of the present invention, since the capacitance between the data lines can be adjusted by the capacitance circuit, the capacitance charged in the pre-driving can be the same for each data line. As a result, it is possible to reduce the error between the voltage reached by the pre-driving and the target voltage and reduce the power consumption of the amplifier circuit.

In one aspect of the present invention, the drive circuit is provided corresponding to each output terminal of the plurality of output terminals, and the output terminal and the first to mth capacitor driving nodes (m is an integer of 2 or more). ), and a capacitor driving circuit that outputs first to mth capacitor driving voltages corresponding to grayscale data to the first to mth capacitor driving nodes. , May be included.

In one embodiment of the present invention, charge redistribution between capacitors is used in pre-driving; therefore, if the capacitance on the electro-optical panel side is different for each data line, the voltage after charge redistribution is also different. This error is corrected by driving the amplifier circuit, but if the correction is large, the amplifier circuit is required to have a large driving ability, and power consumption increases. According to one embodiment of the present invention, since the capacitance between the data lines can be adjusted by the capacitance circuit, the capacitance on the electro-optical panel side can be the same for each data line. Therefore, it is possible to reduce the error between the voltage reached by the pre-driving and the target voltage and reduce the power consumption of the amplifier circuit.

In one aspect of the present invention, the electro-optical panel includes a sample hold circuit that samples and holds a plurality of video signals that are the plurality of data signals, and the plurality of output terminals are provided at one end of the sample hold circuit. It may be a connectable terminal.

In the case of having such a sample hold circuit, if there is an error between the voltage and the target voltage at the timing when the voltage is held on the source line, it causes display unevenness. As a cause of such an error, there is a variation in parasitic capacitance between data lines. In this respect, according to one embodiment of the present invention, since the capacitance between the data lines can be adjusted by the capacitance circuit, display unevenness can be reduced.

Further, another aspect of the present invention relates to an electro-optical device including any one of the display drivers described above and the electro-optical panel.

In another aspect of the present invention, the electro-optical panel includes a sample and hold circuit that samples and holds a plurality of video signals that are the plurality of data signals, and a plurality of output terminals of the display driver. An input terminal; and the sample-hold circuit has a plurality of transistors in which a drain of each transistor is connected to the pixel and a source of each transistor is connected to one of the input terminals of the plurality of input terminals. The first transistor of the plurality of transistors is arranged in the order of the source and the drain along the first direction of the electro-optical panel, and the first transistor is adjacent to the first transistor along the first direction. The second transistor may be arranged in the order of drain and source along the first direction.

Still another aspect of the present invention relates to an electronic device including the display driver described in any of the above.

6 is a configuration example of a display driver of the present embodiment. Configuration example of an electro-optical panel. The figure which shows the parasitic capacitance between data lines typically. The figure which shows typically the capacitance value of the parasitic capacitance between data lines. An example of voltage fluctuation due to coupling of parasitic capacitance between data lines. Detailed configuration example of the capacitance circuit. A detailed configuration example of a display driver including a measurement circuit. 6A and 6B are diagrams illustrating a method of measuring a capacitance value of a parasitic capacitance and a method of adjusting a capacitance value of a capacitance circuit. 6A and 6B are diagrams illustrating a method of measuring a capacitance value of a parasitic capacitance and a method of adjusting a capacitance value of a capacitance circuit. The flowchart of the process which measures the capacitance value of parasitic capacitance. The detailed flowchart of the process which measures the capacitance value of parasitic capacitance. The flowchart of the process which adjusts the capacitance value of a capacitance circuit. 6 is a detailed flowchart of the process of adjusting the capacitance value of the capacitance circuit. The 1st detailed structural example of a drive circuit. FIG. 6 is a diagram illustrating an operation of the drive circuit of the first detailed configuration example. The 2nd detailed structural example of a drive circuit. An example of composition of an electro-optical device. The structural example of an electronic device.

Hereinafter, preferred embodiments of the present invention will be described in detail. Note that the present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Display Driver FIG. 1 shows a configuration example of the display driver 100 of this embodiment. The display driver 100 includes a plurality of output terminals TQ1 to TQn, a plurality of capacitance circuits CC1 to CCn, and a control circuit 30. The display driver 100 also includes a drive circuit 10. Here, n is an integer of 2 or more.

The plurality of output terminals TQ1 to TQn output a plurality of data signals DS1 to DSn (a plurality of data voltages) output to the electro-optical panel. Each capacitance circuit is provided between adjacent output terminals of the plurality of output terminals TQ1 to TQn. The control circuit 30 sets the capacitance value of each capacitance circuit.

Specifically, the plurality of output terminals TQ1 to TQn are first to nth output terminals. The plurality of capacitance circuits CC1 to CCn are first to nth capacitance circuits. The output terminal TQi and the output terminal TQi+1 are adjacent output terminals, one end of the capacitance circuit CCi is connected to the output terminal TQi, and the other end of the capacitance circuit CCi is connected to the output terminal TQi+1. Here, i is an integer of 1 or more and n-1 or less. The capacitance value of the capacitance circuit CCi can be variably adjusted, and the capacitance value is set by the control signal SCT from the control circuit 30. For example, as described with reference to FIG. 6, in the capacitance circuit CCi, the switch group selects whether or not to connect each capacitor of the capacitor group. In this case, the control signal SCT is a signal for controlling ON/OFF of the switch. Alternatively, the capacitance circuit CCi may include a varactor (variable capacitance diode). In this case, the control signal SCT is the varactor control voltage.

The display driver 100 is, for example, an integrated circuit device, and the output terminals TQi are pads (pads formed on a silicon substrate) of the integrated circuit device or terminals of the package (terminals for mounting on the circuit board). Adjacent output terminals TQi and TQi+1 are output terminals connected to adjacent data lines of a plurality of data lines (a plurality of video lines) of the electro-optical panel. No other output terminal is provided between the output terminals TQi and TQi+1 on the silicon substrate or the package. A terminal other than the output terminal may be provided between the output terminals TQi and TQi+1.

As described with reference to FIG. 2, in the electro-optical panel, the transistors for sampling the data signal on the source line are arranged so that the source, the drain, the drain, and the source are arranged in this order. Therefore, as described with reference to FIGS. 3 to 5, the parasitic capacitance between the data lines is different in each data line, and the variation of the data voltage due to the coupling of the parasitic capacitance varies in each data line. When the digital assist drive or the capacitive drive described in FIGS. 14 to 16 is used, the display quality may be deteriorated (longitudinal stripes or display unevenness may occur) due to the variation in the voltage fluctuation.

In this respect, according to the present embodiment, the capacitance circuit CCi is provided between the adjacent output terminals TQi and TQi+1, and the capacitance value of the capacitance circuit CCi is controlled. This makes it possible to adjust (correct) the total sum of the parasitic capacitance between data lines in the electro-optical panel and the capacitance value of the capacitance circuit CCi to be substantially the same for each data line. Since the capacitance between the data lines is substantially the same in each data line, the variation in the data voltage due to the coupling of the capacitance becomes substantially uniform in each data line, and the display quality can be improved.

Since the variation in the parasitic capacitance between the data lines can be adjusted in this way, the data voltage can be more accurately changed to the target voltage even in the drive without the feedback control. Then, when the amplifier circuit is settled to the target voltage thereafter, the error to be corrected can be reduced, and the accurate data voltage can be output while reducing the power consumption (driving capacity) of the amplifier circuit. It will be possible.

Further, the parasitic capacitance between the data lines depends on the product of the electro-optical panel (or the individual product of the same product). In this respect, in the present embodiment, since the display driver 100 is provided with the capacitance circuits CC1 to CCn so that the capacitance between the data lines can be adjusted on the display driver 100 side, the data line spacing is compatible with various electro-optical panels. It is possible to adjust the capacity of. Therefore, it is not necessary to provide an adjusting mechanism on the electro-optical panel side, and it is also possible to automatically adjust the capacitance value of the capacitance circuit CCi as described with reference to FIGS.

Further, in the present embodiment, the plurality of capacitance circuits CC1 to CCn are provided between the first output terminal TQ1 and the nth output terminal TQn among the first to nth output terminals TQ1 to TQn. CCn (nth capacitance circuit) is included. Specifically, one end of the capacitance circuit CCn is connected to the nth output terminal TQn, and the other end of the capacitance circuit CCn is connected to the first output terminal TQ1. The capacitance value of the capacitance circuit CCn is set by the control circuit 30.

In the phase expansion type electro-optical panel as described in FIG. 2, eight (n) data lines VL1 to VL8 are sequentially connected to eight transistors each. Therefore, parasitic capacitance is generated between the eighth data line VL8 and the first data line VL1. For example, the eighth transistor TR8 connected to the eighth data line VL8 and the ninth transistor TR9 connected to the first data line VL1 are adjacent to each other. Therefore, parasitic capacitance is generated between the wirings connected to the sources SS8 and SS9 of these transistors. Since such a parasitic capacitance exists for every eight transistors, the total thereof is included in the parasitic capacitance between the eighth data line VL8 and the first data line VL1.

As described above, in the electro-optical panel of the phase expansion type, there is a parasitic capacitance between the nth data line and the first data line, which causes display unevenness due to the above-mentioned variation in the parasitic capacitance between the data lines. .. In this respect, according to the present embodiment, since the capacitance circuit CCn is provided between the nth output terminal TQn and the first output terminal TQ1, the capacitance circuit CCn is provided between the nth data line and the first data line. The capacity can be adjusted (corrected), and display unevenness can be reduced.

Further, in the present embodiment, the control circuit 30 has a register 32 that stores capacitance value setting information that sets the capacitance value of each capacitance circuit (CC1, CC2,..., CCn). For example, when a capacitor circuit and a switch group constitute a capacitance circuit as described with reference to FIG. 6, information (data) for setting ON/OFF of each switch is capacitance value setting information. Alternatively, when the capacitance circuit includes a varactor, the information for setting the control voltage of the varactor (for example, the setting data when D/A converting the setting data to generate the control voltage) is the capacitance value setting information.

For example, capacity value setting information is transferred to the register 32 from the nonvolatile memory of the display driver 100 (for example, the storage unit 60 in FIG. 17). Alternatively, the capacitance value setting information may be written in the register 32 from the processing unit 310 in FIG. 18 via the interface circuit 70 in FIG. In these cases, for example, the parasitic capacitance between the data lines of the electro-optical panel is automatically measured or previously measured by an external measuring device, and the capacitance value setting information obtained thereby is stored in the nonvolatile memory or the storage unit 320 of FIG. To memorize. Alternatively, the register 32 may be written with the capacitance value setting information obtained by the automatic measurement described in FIGS. 7 to 13. In this case, for example, when the display driver 100 is powered on, the parasitic capacitance between the data lines of the electro-optical panel is automatically measured, and the capacitance value setting information obtained thereby is stored in the register 32.

According to the present embodiment, by having the register 32 that stores the capacitance value setting information, it is possible to variably adjust the capacitance values of the capacitance circuits CC1 to CCn by changing the capacitance value setting information. As a result, it is possible to adjust the capacitance between the data lines corresponding to various electro-optical panels having different parasitic capacitances between the data lines.

2. Electro-Optical Panel FIG. 2 is a configuration example of an electro-optical panel 200 driven by the display driver 100. Although an active matrix type phase expansion type liquid crystal display panel will be described below as an example, the application target of the display driver 100 of the present embodiment is not limited to this. That is, the display driver 100 of this embodiment can be applied to any type and drive type electro-optical panel in which display unevenness may occur due to variations in parasitic capacitance between data lines. Further, the electro-optical panel is not limited to the liquid crystal display panel, and may be a display panel using a self-luminous element (for example, an organic EL display panel).

The electro-optical panel 200 has a sample hold circuit that samples and holds a plurality of video signals, which are a plurality of data signals DS1 to DS8. The plurality of output terminals TQ1 to TQ8 of the display driver 100 are terminals connectable to one end of the sample hold circuit. Note that the case where n=8 will be described below as an example, but n is not limited to 8.

Specifically, the sample hold circuit is transistors TR1, TR2, TR3,... Connected to the source lines DL1, DL2, DL3,. Then, when the transistors TR1, TR2, TR3,... Are turned on, the video signal is sampled to the source lines DL1, DL2, DL3,..., When turned off, the video signal is source lines DL1, DL2, DL3,.・・Hold to. Here, the video signal is a drive signal for driving the electro-optical panel by the display driver in the phase expansion drive.

When such a sample hold circuit is provided, if there is an error between the voltage and the target voltage (the voltage corresponding to the display data) at the timing when the voltage is held on the source line, it causes display unevenness. One of the causes of such an error is a parasitic capacitance between data lines (video lines). In this respect, in the present embodiment, the capacitance between the data lines can be adjusted by the capacitance circuits CC1 to CC8, so that display unevenness can be reduced.

Further, in the present embodiment, the electro-optical panel 200 has a plurality of input terminals TI1 to TI8 connected to the plurality of output terminals TQ1 to TQ8 of the display driver 100. Each of the plurality of transistors TR1, TR2, TR3,... Has its drain connected to the pixel and its source connected to one of the plurality of input terminals TI1 to TI8. Then, the first transistor TR1 is arranged in the order of the source and the drain along the first direction D1 of the electro-optical panel 200. The second transistor TR2 adjacent to the first transistor TR1 along the first direction D1 is arranged in the order of drain and source along the first direction D1. In FIG. 2, the gate of the transistor is shown by a dotted rectangle.

Specifically, the data lines VL1 to VL8 (video lines) arranged along the first direction D1 are connected to the input terminals TI1 to TI8. The data lines VL1 to VL8 are connected to the sources SS1 to SS8 of the transistors TR1 to TR8, and thereafter, the data lines VL1 to VL8 are similarly connected to the sources of the eight transistors each. Source lines DL1, DL2, DL3,... Are connected to the drains DN1, DN2, DN3,... Of the transistors TR1, TR2, TR3,. Pixel circuit) is connected. The respective transistors are arranged such that the longitudinal direction (direction of the channel width) is a second direction D2 orthogonal (crossing) to the first direction D1.

In this way, the source and drain of the transistors are arranged in alternating order (source, drain, drain, source), so that the data line, source line, source line, data line The line will be placed. Then, there can be two source lines between two data lines and two data lines adjacent to each other. Therefore, a difference occurs in the parasitic capacitance between the data lines.

Further, in the transistor arrangement portion, both the data line and the source line are arranged in the same region. Since it is necessary to arrange the transistors and their wirings as close as possible in order to arrange the pixels and the source lines densely, the distance between the lines becomes very small in the portion where both the data lines and the source lines are arranged. Therefore, the parasitic capacitance between the data lines in the arrangement portion of the transistors occupies a large proportion of the parasitic capacitance between the data lines in the entire data line, and the above-mentioned difference in the parasitic capacitance between the data lines is caused. Will be affected.

FIG. 3 is a diagram schematically showing the parasitic capacitance between the data lines. Capacitances CP12, CP23, CP34, CP45, CP56, CP67, CP78, CP81 indicate parasitic capacitances between adjacent input terminals of the electro-optical panel 200 (adjacent output terminals of the display driver 100). For example, the capacitance CP12 is a parasitic capacitance between the input terminals TI1 and TI2.

FIG. 4 is a diagram schematically showing the capacitance value of the parasitic capacitance between the data lines. As described with reference to FIG. 2, the parasitic capacitance between the data lines varies depending on the arrangement of the transistors that are the sample and hold circuits. In FIG. 2, since the drains DN1 and DN2 are arranged between the sources SS1 and SS2 of the transistors TR1 and TR2, the drains DN1 and DN2 (source lines DL1 and DL2) are arranged between the data lines VL1 and VL2. Become. On the other hand, since the sources SS2 and SS3 of the transistors TR2 and TR3 are arranged adjacent to each other, the data lines VL2 and VL3 are arranged adjacent to each other. For these reasons, the capacitance value of the parasitic capacitance CP12 becomes smaller than the capacitance value of the parasitic capacitance CP23 as shown in FIG. Similarly, the capacitance values of the parasitic capacitances CP34, CP56, CP78 are relatively smaller than the capacitance values of the parasitic capacitances CP45, CP67, CP81. Note that FIG. 4 is an example of the characteristic of the parasitic capacitance, and various characteristics can be taken according to the design of the electro-optical panel.

FIG. 5 shows an example of voltage fluctuation due to coupling of parasitic capacitance between data lines. It shows the voltage fluctuation of the output terminal of high impedance when the voltage of the output terminal adjacent to the output terminal of high impedance (state not driven by an amplifier or the like) is changed. For example, “TQ2→TQ1” indicates a voltage fluctuation of the high impedance output terminal TQ1 when the voltage of the output terminal TQ2 is changed (for example, changed from the lowest gradation to the highest gradation). Although not shown, the voltage fluctuation of “TQ1→TQ2” is the same as the voltage fluctuation of “TQ2→TQ1”.

The larger the parasitic capacitance between the data lines, the larger the voltage fluctuation due to the coupling of the parasitic capacitance. That is, the characteristic of the voltage fluctuation is similar to the characteristic of the parasitic capacitance in FIG. For example, if the parasitic capacitance between the input terminals TI4 and TI5 (output terminals TQ4 and TQ5) is the maximum, the voltage fluctuation of “TQ5→TQ4” is the maximum. The maximum value of this voltage fluctuation (voltage difference) is VM. In the present embodiment, the data line is configured so that the voltage fluctuation between the adjacent output terminals becomes the same (including substantially the same) as the maximum value VM, that is, the capacitance between the data lines becomes the same as the maximum capacitance value. Adjust the capacity between. For example, the capacitance value of the capacitance circuit CC3 is adjusted so that the total capacitance value of the capacitance circuit CC3 and the parasitic capacitance CP34 becomes the same as the capacitance value of the parasitic capacitance CP45.

3. Capacitance Circuit FIG. 6 is a detailed configuration example of the capacitance circuit CC1. The capacitance circuits CC2 to CCn can be similarly configured. The capacitance circuit CC1 includes a capacitor group CG1 and at least one switch group SG1 and SG2 that connects each capacitor of the capacitor group CG1 and the output terminals TQ1 and TQ2.

According to this embodiment, the connection between each capacitor and the output terminals TQ1 and TQ2 can be controlled by the switch groups SG1 and SG2. As a result, the capacitance between the adjacent output terminals TQ1 and TQ2 can be adjusted by the capacitance circuit CC1, and variations in the parasitic capacitance between the data lines can be corrected to make the capacitances between the data lines uniform. ..

Specifically, the capacitance circuit CC1 includes the first switch group SG1 and the second switch group SG2 as at least one switch group. One end of the first switch group SG1 is connected to the first output terminal TQ1 (i-th output terminal TQi), and the other end is connected to one end of the capacitor group CG1. The second switch group SG2 has one end connected to the second output terminal TQ2 (i+1th output terminal TQi+1) adjacent to the first output terminal TQ1 and the other end connected to the other end of the capacitor group CG1. ..

More specifically, the switch group SG1 includes switches SA1 to SA9 (first to p-th switches in a broad sense, p is an integer of 2 or more), and the capacitor group CG1 includes capacitors CA1 to CA9 (first to first switches). The switch group SG2 includes switches SB1 to SB9 (first to p-th switches). One end of the switch SAj (j is an integer of 1 or more and 9 or less) is connected to the output terminal TQ1, and the other end thereof is connected to one end of the capacitor CAj. The switch SBj has one end connected to the output terminal TQ2 and the other end connected to the other end of the capacitor CAj. The switches SAj and SBj are, for example, transistors, and their on/off states are controlled by the control circuit 30 shown in FIGS.

According to this embodiment, the capacitor group CG1 is connected between the adjacent output terminals TQ1 and TQ2 by the first switch group SG1 and the second switch group SG2. Accordingly, by controlling the on and off of each switch, it is possible to control whether or not each capacitor is connected between the adjacent output terminals TQ1 and TQ2. That is, when the switches SAj and SBj are turned on, the capacitor CAj is connected between the output terminals TQ1 and TQ2, and when the switches SAj and SBj are turned off, the capacitor CAj is connected between the output terminals TQ1 and TQ2. Not connected to.

Further, in the present embodiment, the capacitance value of each capacitor of the capacitor group CG1 is binary weighted. That is, when the 1C capacity value of the capacitor CA1, the capacitance value of the capacitor CAj is ^{2 j-1} C.

In this way, by controlling the switch groups SG1 and SG2 with a binary code, it is possible to adjust the capacitance value of the capacitance circuit CC1 by 1C in the range of 1C to 256C (2p ^- 1C in a broad sense). Becomes

4. Measurement Circuit FIG. 7 is a detailed configuration example of the display driver 100 including the measurement circuit 20. The display driver 100 of FIG. 7 includes output terminals TQ1 to TQ5, capacitance circuits CC1 to CC5, switches SC1 to SC5, a measurement circuit 20, a control circuit 30, and a drive circuit 10. Note that the case where n=5 will be described below as an example, but n is not limited to 5.

The measurement circuit 20 measures capacitance value information between the plurality of data lines of the electro-optical panel 200. Then, the capacitance value of each capacitance circuit (CC1 to CC5) is set based on the capacitance value information measured by the measurement circuit 20.

Specifically, the measurement circuit 20 measures the capacitance values of the parasitic capacitances CP12, CP23, CP34, CP45, CP51 between the adjacent data lines, and acquires the capacitance value information corresponding to the capacitance values. The capacitance value information may be information (data) representing the capacitance value itself, or some information that varies according to the capacitance value, or information that is associated with each capacitance value in a one-to-one correspondence. Good.

According to this embodiment, by measuring the capacitance value information between the data lines, it is possible to adjust the capacitance value of the capacitance circuit based on the capacitance value information so that the capacitance between the data lines becomes the same. Becomes

Further, in the present embodiment, the measurement circuit 20 includes the comparison circuit 21 (comparator) to which the determination voltage VR (reference voltage) is input to the first input terminal (for example, the negative polarity terminal) and the plurality of output terminals TQ1 to TQ5. And a switch group 22 for connecting any one of the output terminals to a second input terminal (for example, a positive terminal) of the comparison circuit 21.

Specifically, the switch group 22 has switches SD1 to SD5. One ends of the switches SD1 to SD5 are connected to the output terminals TQ1 to TQ5, and the other ends thereof are connected to the second input terminal of the comparison circuit 21. The switches SD1 to SD5 are, for example, transistors, and their on and off are controlled by the control circuit 30. The determination voltage VR is supplied from the voltage generation circuit 50 shown in FIG. 17, for example.

According to the present embodiment, one of the output terminals is connected to the second input terminal of the comparison circuit 21 by the switch group 22, and the voltage of the output terminal and the determination voltage VR are compared. As a result, the voltage fluctuation at the output terminal can be compared with the determination voltage VR, and the capacitance value information can be obtained from the comparison result.

More specifically, when the voltage of the i-th output terminal TQi changes, the switch group 22 connects the (i+1)th output terminal TQi+1 adjacent to the i-th output terminal TQi to the second input terminal. The comparison circuit 21 compares the voltage of the (i+1)th output terminal TQi+1 with the determination voltage VR.

For example, when the voltage of the output terminal TQ3 (TQi) changes, the switches SD1 to SD3 and SD5 are turned off, the switch SD4 (SDi+1) is turned on, and the output terminal TQ4 (TQi+1) is the second one of the comparison circuit 21. Connected to the input terminal. At this time, the voltage CMI at the second input terminal becomes the voltage VQ4 at the output terminal TQ4. Then, the comparison circuit 21 compares the voltage CMI=VQ4 with the determination voltage VR, and outputs the signal CMQ as the comparison result to the control circuit 30. The control circuit 30 acquires the capacitance value information based on the signal CMQ.

The i-th output terminal and the i+1-th output terminal may be adjacent output terminals, and the order thereof does not matter. That is, in the above description, the case where the output terminals TQ1, TQ2,... Are numbered as first, second,... has been described, but the present invention is not limited to this and the output terminals TQ5, TQ4,. The numbers may be numbered 1, 2,...

According to this embodiment, when the voltage of the output terminal TQi adjacent to the output terminal TQi+1 is changed, the voltage fluctuation of the output terminal TQi+1 can be compared with the determination voltage VR by the comparison circuit 21. Since the magnitude of the voltage fluctuation of the output terminal TQi+1 changes according to the capacitance value of the parasitic capacitance between the adjacent data lines, the capacitance value of the parasitic capacitance can be measured based on the comparison result by the comparison circuit 21.

The data signals DS1 to DS5 (data voltages) from the drive circuit 10 are supplied to one ends of the switches SC1 to SC5, and the other ends of the switches SC1 to SC5 are voltages VQ1 to VQ5 of the output terminals TQ1 to TQ5. When the switch SCi is turned on, VQi=DSi. The switches SC1 to SC5 are, for example, transistors, and their on/off states are controlled by the control circuit 30.

8 and 9 are diagrams illustrating a method of measuring the capacitance value of the parasitic capacitance and a method of adjusting the capacitance value of the capacitance circuit.

FIG. 8 shows the voltage VQ4 of the output terminal TQ4 when the voltage VQ3 of the output terminal TQ3 is changed. In this case, the switches SC1, SC3, SC5 of FIG. 7 are turned on and the switches SC2, SC4 are turned off. Further, the switch SD4 is turned on, and the switches SD1 to SD3 and SD5 are turned off. Then, the drive circuit 10 gradually (stepwise) changes the voltage VQ3=DS3 with a predetermined voltage width. The voltage setting value is, for example, the count value of the counter, and the voltage VQ3=DS3 increases (or decreases) by a predetermined voltage width each time the count value increases by 1. The parasitic capacitance CP34 between the output terminals TQ3 and TQ4 causes the voltage VQ4 to gradually change as the voltage VQ3 changes. The voltage width of one step of this voltage fluctuation is determined by the capacitance value of the parasitic capacitance CP34. In the example of FIG. 8, when the voltage setting value changes from 7 to 8, the voltage VQ4 becomes larger than the determination voltage VR, and the logical level of the output signal CMQ of the comparison circuit 21 changes (for example, from low level to high level). Become).

FIG. 9 shows the voltage VQ5 of the output terminal TQ5 when the voltage VQ4 of the output terminal TQ4 is changed. In this case, the switches SC1, SC2, SC4 of FIG. 7 are turned on and the switches SC3, SC5 are turned off. Further, the switch SD5 is turned on and the switches SD1 to SD4 are turned off. Then, the drive circuit 10 gradually (stepwise) changes the voltage VQ4=DS4 with a predetermined voltage width. Due to the parasitic capacitance CP45 between the output terminals TQ4 and TQ5, the voltage VQ5 gradually changes as the voltage VQ4 changes. In the example of FIG. 9, when the voltage setting value changes from 3 to 4, the voltage VQ5 becomes larger than the determination voltage VR, and the logic level of the output signal CMQ of the comparison circuit 21 changes.

For example, it is assumed that the capacitance value of CP45 is the maximum among the parasitic capacitances CP12, CP23, CP34, CP45, and CP51. In this case, the logical level of the output signal CMQ of the comparison circuit 21 changes when the voltage VQ5 when the voltage VQ4 is changed is the smallest voltage setting value (4 in the example of FIG. 9). As shown in FIG. 8, when adjusting the capacitance value of the capacitance circuit CC3, the voltage VQ4 when the voltage VQ3 is changed is the smallest voltage setting value (4) described above, and the output signal CMQ of the comparison circuit 21. The capacitance value of the capacitance circuit CC3 is set so that the logic level of is changed. By performing such adjustment, the total of the capacitance values of the parasitic capacitance CP34 and the capacitance circuit CC3 becomes substantially equal to the maximum capacitance value of the parasitic capacitance CP45. Similar adjustments are made for the capacitance circuits CC1, CC2, CC5. The capacitance circuit CC4 is not changed, for example, from a predetermined capacitance value (for example, 0) set at the time of measurement.

FIG. 10 is a flowchart of the process of measuring the capacitance value of the parasitic capacitance. When this process is started, the measurement circuit 20 and the control circuit 30 sequentially measure the capacitance values of the parasitic capacitances CP12, CP23, CP34, CP45, CP51 (S1 to S5). That is, the control circuit 30 acquires the voltage setting value when the voltage of the output terminal reaches the determination voltage VR (the voltage setting value when the logic level of the output signal CMQ of the comparison circuit 21 changes) for each parasitic capacitance. To do. The measurement order of the parasitic capacitances CP12, CP23, CP34, CP45, and CP51 is not limited to this, and any order may be used. Next, the control circuit 30 extracts the minimum value among the voltage setting values obtained when the voltage at the output terminal reaches the determination voltage VR acquired for each parasitic capacitance (S6).

FIG. 11 is a detailed flowchart of the process (S3) of measuring the capacitance value of the parasitic capacitance CP34. The capacitance values of the parasitic capacitances CP12, CP23, CP45, CP51 can be measured by the same process. When this process is started, the control circuit 30 connects the output terminal TQ4 to the comparison circuit 21 (S11). That is, the control circuit 30 turns on the switch SD4. Next, the drive circuit 10 sets all outputs to the initial voltage VC (S12). That is, the control circuit 30 turns on the switches SC1 to SC5, and the drive circuit 10 outputs the initial voltage VC as the data signals DS1 to DS5. The initial voltage VC is, for example, a common voltage supplied to the common electrode of the electro-optical panel 200. Next, the control circuit 30 sets the outputs of the output terminals TQ2 and TQ4 to high impedance (S13). That is, the control circuit 30 turns off the switches SC2 and SC4. Next, the judgment voltage VR of the comparison circuit 21 is set (S14). For example, the determination voltage VR from the voltage generation circuit 50 in FIG. 17 is input to the first input terminal of the comparison circuit 21 by selection by the selector or the like.

Next, the control circuit 30 increments the voltage setting value of the output terminal TQ3 by +1 (S15). That is, the control circuit 30 increments the voltage setting value of the output terminal TQ3 by 1, and the drive circuit 10 outputs the voltage VQ3=DS3 corresponding to the voltage setting value. For example, the initial value of the voltage setting value is 0, and in the case of the initial value, the voltage VQ3=VC. The change in the voltage setting value in step S15 is not limited to +1 and may be changed so that the voltage VQ3 gradually increases (or decreases). Next, the comparison circuit 21 determines whether the voltage VQ4 of the output terminal TQ4 is higher than the determination voltage VR (S16). When it is determined that the voltage VQ4 is equal to or lower than the determination voltage VR, the control circuit 30 increments the voltage setting value of the output terminal TQ3 by +1 (S15). On the other hand, when it is determined that the voltage VQ4 is higher than the determination voltage VR, the control circuit 30 records the voltage setting value of the output terminal TQ3 at that time (S17).

FIG. 12 is a flowchart of processing for adjusting the capacitance value of the capacitance circuit. When this process is started, the control circuit 30 sequentially adjusts the capacitance values of the capacitance circuits CC1, CC2, CC3, CC4, CC5 (S21 to S25). The order of adjusting the capacitance values of the capacitance circuits CC1, CC2, CC3, CC4, and CC5 is not limited to this, and any order may be used.

FIG. 13 is a detailed flowchart of the process (S23) of adjusting the capacitance value of the capacitance circuit CC3. The capacitance values of the capacitance circuits CC1, CC2, CC4, CC5 can be adjusted by the same process. When this process is started, the control circuit 30 connects the output terminal TQ4 to the comparison circuit 21 (S31). That is, the control circuit 30 turns on the switch SD4. Next, the drive circuit 10 sets all outputs to the initial voltage VC (S32). That is, the control circuit 30 turns on the switches SC1 to SC5, and the drive circuit 10 outputs the initial voltage VC as the data signals DS1 to DS5. Next, the control circuit 30 sets the outputs of the output terminals TQ2 and TQ4 to high impedance (S33). That is, the control circuit 30 turns off the switches SC2 and SC4. Next, the judgment voltage VR of the comparison circuit 21 is set (S34). For example, the determination voltage VR from the voltage generation circuit 50 in FIG. 17 is input to the first input terminal of the comparison circuit 21 by selection by the selector or the like.

Next, the control circuit 30 sets the voltage setting value of the output terminal TQ3 to the minimum value extracted in step S6 (S35). That is, the control circuit 30 changes the voltage setting value (for example, 0) corresponding to the initial voltage VC to the minimum value (4 in the example of FIG. 9) extracted in step S6, and the drive circuit 10 sets the voltage setting. The voltage VQ3=DS3 corresponding to the value is output. Next, the comparison circuit 21 determines whether or not the voltage VQ4 at the output terminal TQ4 is higher than the determination voltage VR (S36). When it is determined that the voltage VQ4 is equal to or lower than the determination voltage VR, the drive circuit 10 sets the output terminal TQ3 to the initial voltage VC (S37). Next, the control circuit 30 increments the capacitance value of the capacitance circuit CC3 between the output terminals TQ3 and TQ4 by +1C (S38), and returns to step S35. The initial value of the capacitance value is, for example, 0C. On the other hand, when it is determined in step S36 that the voltage VQ4 is higher than the determination voltage VR, the control circuit 30 stores the capacitance value of the capacitance circuit CC3 at that time (S39).

As a modification of the measuring method and the adjusting method, for example, there is a method of measuring only the capacitance value of a part of the parasitic capacitance and adjusting the capacitance value of the capacitance circuit as follows. That is, as described with reference to FIG. 4, the capacitance value of the parasitic capacitance repeats large and small, and the ratio of the large and small is almost the same. Therefore, the parasitic capacitance having a small capacitance value and the parasitic capacitance having a large capacitance value are measured one by one (for example, S1, S2, and S6 of FIG. 10 are executed to measure CP12 and CP23). Next, the capacitance value of the capacitance circuit corresponding to the parasitic capacitance having the smaller capacitance value is adjusted so as to match the parasitic capacitance having the larger capacitance value (for example, when CP12<CP23, S21 of FIG. 12 is executed). Adjust the capacitance value of CC1). Then, the capacitance circuits corresponding to the other data lines having a small capacitance value of the parasitic capacitance are set to the same capacitance value (for example, when CP34 and CP51 are smaller than CP23 and CP45, the capacitance values of CC3 and CC5 are set to the capacitance of CC1). Set to the same capacity value as the value).

5. Drive Circuit FIG. 14 is a first detailed configuration example of the drive circuit 10. The drive circuit 10 of FIG. 14 includes an amplifier circuit 12 provided corresponding to the output terminal TQ1, and a drive assist circuit 14 that assists the drive by the amplifier circuit 12. The drive assist circuit 14 performs pre-driving based on the gradation change information of the data signal DS1. In the following, the amplifier circuit 12 and the drive assist circuit 14 provided corresponding to the output terminal TQ1 will be described as an example, but similar amplifier circuits and drive assist circuits correspond to the output terminals of the plurality of output terminals TQ1 to TQn. Is provided.

Specifically, the amplifier circuit 12 amplifies the output voltage VIN of the D/A conversion circuit (D/A conversion circuit 40 in FIG. 17) and outputs the amplified voltage to the output terminal TQ1. The drive assist circuit 14 includes P-type transistors TP1 to TP9 (first conductivity type transistors) provided between the node of the high potential side power supply voltage VDD and the output terminal TQ1, and a node of the low potential side power supply voltage VSS and the output. And N-type transistors TN1 to TN9 (second conductivity type transistors) provided between the terminal TQ1 and the terminal TQ1. When the driving capability of the transistors TP1 and TN1 is 1x, the driving capability of the transistors TPk and TNk (k is an integer of 1 or more and 9 or less) is 2 ^k-1 x. The driving capability is, for example, a drain current with respect to the same gate-source voltage, and is set by, for example, the channel width of the transistor (W of W/L) or the number of unit transistors. The transistors TP1 to TP9 and TN1 to TN9 are turned on and off by the control circuit 30. The control circuit 30 calculates the driving ability according to the voltage change of the data signal DS1 (gradation change of the display data), turns on the transistor corresponding to the driving ability, and performs the pre-driving by the turned-on transistor. Be seen. In the example of FIG. 14, the driving capability can be set in the range of 1x to 511x in 1x steps.

FIG. 15 is a diagram for explaining the operation of the drive circuit 10 in FIG. In FIG. 15, a case where the gradation is changed from 0 to 128 and a case where the gradation is changed from 128 to 64 will be described as an example. Further, here, it is assumed that the larger the gradation is, the larger the voltage of the data signal DS1 is.

When changing the gradation from 0 to 128, the drive assist circuit 14 changes the data signal DS1 from the voltage corresponding to the gradation 0 to the voltage corresponding to the gradation 128 (that is, the high-potential-side power supply voltage VDD in the pre-driving period TS1). Change to the side). In the amplifier driving period TA1 after the pre-driving period TS1, the amplifier circuit 12 outputs the voltage corresponding to the gradation 128 to the output terminal TQ1.

In the pre-driving, the control circuit 30 determines a voltage difference corresponding to the gradation difference from the difference (128-0=128) between the gradation of the display data in the previous driving and the gradation in the current driving (128-0=128). The drive capability generated in TS1 is calculated. For example, the larger the gradation difference is, the larger the driving capability is set. Further, the control circuit 30 calculates the driving ability according to the target voltage (voltage corresponding to the gradation 128). For example, when the voltage change of the data signal DS1 is positive, the closer the target voltage is to the high-potential side power supply voltage VDD (the closer the gradation is to the maximum gradation), the larger the driving capability is set. When the voltage change of the data signal DS1 is positive, the control circuit 30 controls ON/OFF of the P-type transistors TP1 to TP9 of the drive assist circuit 14 so as to have the calculated driving capability. The N-type transistors TN1 to TN9 are controlled to be off.

When changing the gradation from 128 to 64, the drive assist circuit 14 changes the data signal DS1 from the voltage corresponding to the gradation 128 to the voltage corresponding to the gradation 64 (that is, the low-potential-side power supply voltage VSS) in the pre-driving period TS2. Change to the side). In the amplifier driving period TA2 after the pre-driving period TS2, the amplifier circuit 12 outputs the voltage corresponding to the gradation 64 to the output terminal TQ1.

In this case, since the gradation difference is smaller than that in the pre-driving period TS1 (128−64=64), the driving capacity becomes small in terms of the driving capacity according to the gradation difference. Since the voltage change of the data signal DS1 is negative, the closer the target voltage is to the low-potential-side power supply voltage VSS (the closer the gradation is to the minimum gradation), the larger the driving capability is set. When the voltage change of the data signal DS1 is negative, the control circuit 30 controls ON/OFF of the N-type transistors TN1 to TN9 of the drive assist circuit 14 so as to have the calculated driving capability. The P-type transistors TP1 to TP9 are controlled to be off.

When the voltage reached by the pre-driving of the drive assist circuit 14 deviates from the target voltage (the voltage corresponding to the gradation 128 or the gradation 64), it is corrected by driving the amplifier circuit 12. However, if the correction is large, the amplifier circuit 12 is required to have a large driving ability, and power consumption increases. In the pre-driving of the drive assist circuit 14, the parasitic capacitance of the data line and the pixel capacitance are charged by the current passed by the transistor. At this time, if the charged capacity value is different, the required driving ability also becomes different. That is, if the parasitic capacitance between the data lines is different for each data line, the driving capability required for the same voltage change is also different. In this embodiment, since the capacitance between the data lines can be adjusted by the capacitance circuit, the capacitance charged in the pre-driving can be the same for each data line. Therefore, it is possible to perform pre-driving with the same driving ability for the same voltage change. As a result, the error between the voltage reached by the pre-driving and the target voltage can be reduced, and the power consumption of the amplifier circuit 12 can be reduced. Further, it is not necessary to make the calculation of the driving ability different for each data line, and the calculation of the driving ability can be simplified.

FIG. 16 is a second detailed configuration example of the drive circuit 10. The drive circuit 10 in FIG. 16 includes an amplifier circuit 12, a capacitor circuit 16, and a capacitor drive circuit 18. The capacitor circuit 16 has first to m-th capacitors C1 to Cm (m is an integer of 2 or more), and the first to m-th capacitors C1 to Cm are provided corresponding to the output terminal TQ1 and output thereof. It is provided between the terminal TQ1 and the first to mth capacitor driving nodes NDR1 to NDRm. The capacitor driving circuit 18 outputs the first to mth capacitor driving voltages corresponding to the display data GD[m:1] (grayscale data) to the first to mth capacitor driving nodes NDR1 to NDRm. In the following, the case of m=10 will be described as an example, but m is not limited to 10. Further, the amplifier circuit 12, the capacitor circuit 16, and the capacitor drive circuit 18 provided corresponding to the output terminal TQ1 will be described below. Is provided corresponding to each output terminal of.

One end of the capacitor Cq (q is an integer of 1 or more and m=10 or less) is connected to the capacitor driving node NDRq, and the other end of the capacitor Cq is connected to the node NVQ of the output terminal TQ1. The capacitors C1 to C10 have binary (power of 2) weighted capacitance values. That is, the capacitance value of the capacitor Cq is 2 ^(q-1) x C1.

The capacitor driving circuit 18 has first to tenth driving units DR1 to DR10 that output first to tenth capacitor driving voltages. The q-th bit GDq of the display data GD[10:1] is input to the input node of the drive unit DRq. The output node of the driving unit DRq is a capacitor driving node NDRq. The display data GD[10:1] is composed of first to tenth bits GD1 to GD10 (first to nth bits), the bit GD1 corresponds to the LSB, and the bit GD10 corresponds to the MSB.

The driving unit DRq outputs the first voltage level when the bit GDq is the first logic level, and outputs the second voltage level when the bit GDq is the second logic level. For example, the first logic level is “0” (low level), the second logic level is “1” (high level), the first voltage level is the low potential side power supply voltage VSS, and the second voltage level is the high potential side power supply voltage. It is VDD.

As described above, the capacitance values of the capacitors C1 to C10 are weighted by powers of 2 corresponding to the digits of the bits GD1 to GD10 of the display data GD[10:1]. Then, the drive units DR1 to DR10 output VSS or VDD according to the bits GD1 to GD10, so that the capacitors C1 to C10 are driven by the voltage. This driving causes charge redistribution between the capacitors C1 to C10 and the electro-optical panel side capacitance CX, and as a result, the data voltage (data signal DS1) is output to the output terminal TQ1.

The electro-optical panel side capacitance CX is the total capacitance seen from the output terminal TQ1. For example, the electro-optical panel side capacitance CX is the sum of the substrate capacitance CX1 which is the parasitic capacitance of the printed circuit board and the panel capacitance CX2 which is the parasitic capacitance in the electro-optical panel 200 and the pixel capacitance. The capacitance CO of the capacitor circuit 16 (total capacitance value of the capacitors C1 to C10) is set so that CO:CX has a predetermined ratio (for example, 1:2).

The operation of the drive circuit 10 will be described below. First, the drive circuit 10 initializes the voltage of the output terminal TQ1 to a common voltage (initial voltage). Next, in the pre-driving period, the control circuit 30 outputs the display data GD[10:1] to the capacitor drive circuit 18, and the capacitor drive circuit 18 outputs the capacitor drive voltage according to the display data GD[10:1]. Is output to the capacitor circuit 16. Then, the voltage based on the common voltage is output to the output terminal TQ1 by the charge redistribution. For example, in the case of CO:CX=1:2, the data signal DS1 is in the range from the common voltage to VDD/3. In the amplifier driving period after the pre-driving period, the amplifier circuit 12 amplifies the output voltage VIN of the D/A conversion circuit (D/A conversion circuit 40 in FIG. 17) and outputs the amplified voltage to the output terminal TQ1. Output. The voltage VIN is a voltage obtained by D/A converting the display data GD[10:1] by the D/A conversion circuit.

In the drive circuit 10 of FIG. 16, since charge redistribution between capacitors is used in pre-driving, if the capacitance CX on the electro-optical panel side is different for each data line, the voltage after charge redistribution also differs. This error is corrected by driving the amplifier circuit 12, but if the correction is large, the amplifier circuit 12 is required to have a large driving ability, and power consumption increases. In the present embodiment, since the capacitance between the data lines can be adjusted by the capacitance circuit, the electro-optical panel side capacitance CX can be made the same for each data line. Therefore, it is possible to reduce the error between the voltage reached by the pre-driving and the target voltage and reduce the power consumption of the amplifier circuit 12.

The drive circuit 10 may further include a variable capacitance circuit provided between each output terminal and the node of the reference voltage. The capacitance of the variable capacitance circuit is set so that the capacitance value obtained by adding the capacitance value of the variable capacitance circuit and the capacitance value of the electro-optical panel side and the capacitance value of the capacitor circuit 16 have a given capacitance ratio relationship. It That is, the substrate capacitance CX1 and the panel capacitance CX2 are different depending on the substrate design and the type (product) of the electro-optical panel 200, so that the voltage after charge redistribution varies. The variable capacitance circuit adjusts the capacitance ratio so that such variation does not occur. That is, when the capacitance value of the variable capacitance circuit is CAD, CAD is set so that CO:(CAD+CX) has a predetermined capacitance ratio (for example, 1:2).

Here, although the case where the drive circuit 10 includes the amplifier circuit 12 is described in FIG. 16, the present invention is not limited to this, and the amplifier circuit 12 may be omitted. In this case, only the charge redistribution of the capacitor circuit 16 drives the electro-optical panel 200.

6. Electro-Optical Device FIG. 17 is a configuration example of an electro-optical device 400 (display device) including the display driver 100 of the present embodiment. The electro-optical device 400 includes the display driver 100 and the electro-optical panel 200. The display driver 100 includes a drive circuit 10, a measurement circuit 20, a control circuit 30, a D/A conversion circuit 40, a voltage generation circuit 50, a storage unit 60 (memory), an interface circuit 70, and a capacitance circuit 80. The electro-optical panel 200 includes a pixel array 210 and a sample hold circuit 220. The capacitance circuit 80 corresponds to the capacitance circuits CC1 to CCn shown in FIG. The pixel array 210 is an array of a plurality of pixels in FIG. The sample hold circuit 220 corresponds to the transistors TR1, TR2, TR3,... Of FIG.

The interface circuit 70 performs communication between the display driver 100 and an external processing device (for example, the processing unit 310 in FIG. 18). For example, a clock signal and display data are input to the control circuit 30 from an external processing device via the interface circuit 70.

The control circuit 30 controls each unit of the display driver 100 based on a clock signal and display data input via the interface circuit 70. For example, the control circuit 30 controls display timing such as selection of horizontal scanning lines of the pixel array 210 and vertical synchronization control, and controls the drive circuit 10 in accordance with the display timing.

The voltage generation circuit 50 generates various voltages and outputs them to the drive circuit 10 and the D/A conversion circuit 40. For example, the voltage generation circuit 50 is a gradation voltage generation circuit (for example, a ladder resistor) that generates a plurality of voltages, a power supply circuit that generates power for the amplifier circuit of the drive circuit 10, and a voltage generation that generates the determination voltage VR of the measurement circuit 20. Including circuits etc.

The D/A conversion circuit 40 D/A converts the display data from the control circuit 30 and outputs the D/A converted voltage to the drive circuit 10. That is, the voltage corresponding to the display data is selected from among the plurality of voltages supplied from the gradation voltage generation circuit of the voltage generation circuit 50, and the selected voltage is output to the drive circuit 10.

The storage unit 60 stores various data (for example, setting data) used for controlling the display driver 100. For example, the storage unit 60 is composed of a non-volatile memory or a RAM (SRAM, DRAM, etc.).

7. Electronic Device FIG. 18 is a configuration example of an electronic device 300 including the display driver 100 of the present embodiment. Specific examples of the electronic device 300 include various types of display devices such as a projector, a head mounted display, a portable information terminal, an in-vehicle device (for example, a meter panel, a car navigation system, etc.), a portable game terminal, an information processing device, and the like. Can be assumed to be an electronic device.

The electronic device 300 includes a processing unit 310 (for example, a processor such as CPU or a gate array), a storage unit 320 (for example, memory, hard disk, etc.), an operation unit 330 (operation device), an interface unit 340 (interface circuit, interface device), It includes an electro-optical device 400 (display). The electro-optical device 400 includes the display driver 100 and the electro-optical panel 200 as shown in FIG.

The operation unit 330 is a user interface that receives various operations from the user. For example, a button, a mouse, a keyboard, a touch panel mounted on the electro-optical device 400 (electro-optical panel 200), or the like. The interface unit 340 is a data interface that inputs and outputs image data and control data. For example, it is a wired communication interface such as USB or a wireless communication interface such as a wireless LAN. The storage unit 320 stores the data input from the interface unit 340. Alternatively, the storage unit 320 functions as a working memory of the processing unit 310. The processing unit 310 processes the display data input from the interface unit 340 or stored in the storage unit 320 and transfers the display data to the electro-optical device 400 (display driver 100). The electro-optical device 400 displays an image on the pixel array based on the display data transferred from the processing unit 310.

Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications can be made without substantially departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the scope of the present invention. For example, a term described in the specification or the drawings at least once together with a different term having a broader meaning or the same meaning can be replaced with the different term in any place in the specification or the drawing. Further, all combinations of the present embodiment and modifications are also included in the scope of the present invention. The configurations and operations of the display driver, the electro-optical panel, the electro-optical device, the electronic device, etc. are not limited to those described in this embodiment, and various modifications can be made.

10... Driving circuit, 12... Amplifier circuit, 14... Driving assist circuit,
16... Capacitor circuit, 18... Capacitor drive circuit, 20... Measuring circuit,
21... Comparison circuit, 22... Switch group, 30... Control circuit, 32... Register,
40... D/A conversion circuit, 50... Voltage generation circuit, 60... Storage unit,
70... Interface circuit, 80... Capacitance circuit, 100... Display driver,
200... Electro-optical panel, 210... Pixel array, 220... Sample and hold circuit,
300... Electronic device, 310... Processing unit, 320... Storage unit, 330... Operation unit,
340... Interface unit, 400... Electro-optical device,
CC1 to CCn... Capacitance circuit, CG1... Capacitor group,
CX... Electro-optical panel side capacitance, D1... first direction, D2... second direction,
DS1 to DSn... data signal, SG1... first switch group,
SG2... second switch group, TI1 to TI8... input terminals,
TQ1 to TQn... Output terminals, VR... Judgment voltage

Claims (16)

A plurality of output terminals for outputting a plurality of data signals output to the electro-optical panel,
A plurality of capacitance circuits in which each capacitance circuit is provided between adjacent output terminals of the plurality of output terminals;
A control circuit for setting the capacitance value of each capacitance circuit,
Display driver characterized by including. In claim 1,
Each of the capacitance circuits is
A group of capacitors,
At least one switch group connecting between each capacitor of the capacitor group and the output terminal;
Display driver characterized by including. In claim 2,
Each of the capacitance circuits is
A first switch group having one end connected to the i-th output terminal of the plurality of output terminals and the other end connected to one end of the capacitor group;
A second switch group having one end connected to the (i+1)th output terminal adjacent to the ith output terminal and the other end connected to the other end of the capacitor group;
And a display driver having at least one switch group. In any one of Claim 1 thru|or 3,
The plurality of capacitance circuits are
A capacitance circuit is provided between the nth output terminal and the first output terminal of the first to nth output terminals (n is an integer of 2 or more) that are the plurality of output terminals. And display driver. In claim 2 or 3,
A display driver, wherein the capacitance value of each capacitor of the capacitor group is weighted in binary. In any one of Claim 1 thru|or 5,
The control circuit is
A display driver having a register for storing capacitance value setting information for setting a capacitance value of each capacitance circuit. In any one of Claim 1 thru|or 6,
A measuring circuit for measuring capacitance value information between a plurality of data lines of the electro-optical panel,
A display driver, wherein the capacitance value of each capacitance circuit is set based on the capacitance value information measured by the measurement circuit. In claim 7,
The measuring circuit is
A comparison circuit in which the judgment voltage is input to the first input terminal;
A switch group for connecting one of the output terminals of the plurality of output terminals to a second input terminal of the comparison circuit;
Display driver characterized by having. In claim 8,
When the voltage of the i-th output terminal among the plurality of output terminals changes, the switch group connects the (i+1)th output terminal adjacent to the i-th output terminal to the second input terminal, The comparison circuit compares a voltage of the (i+1)th output terminal with the determination voltage, and a display driver. In any one of Claim 1 thru|or 9,
A display driver comprising: a drive circuit that outputs the plurality of data signals to the plurality of output terminals. In claim 10,
The drive circuit is
An amplifier circuit provided corresponding to each output terminal of the plurality of output terminals,
A drive assist circuit for assisting drive by the amplifier circuit,
Have
The drive assist circuit,
A display driver characterized by performing pre-driving based on gradation change information of a data signal. In claim 10,
The drive circuit is
The first to mth output terminals are provided corresponding to the output terminals of the plurality of output terminals, and are provided between the output terminals and the first to mth capacitor driving nodes (m is an integer of 2 or more). A capacitor,
A capacitor driving circuit for outputting first to mth capacitor driving voltages corresponding to gradation data to the first to mth capacitor driving nodes;
Display driver characterized by having. In any one of Claim 1 thru|or 12,
The electro-optical panel is
A sample hold circuit for holding a plurality of video signals, which are the plurality of data signals,
The plurality of output terminals,
A display driver, which is a terminal connectable to one end of the sample-hold circuit. A display driver according to any one of claims 1 to 13,
The electro-optical panel,
An electro-optical device comprising: In claim 14,
The electro-optical panel is
A sample and hold circuit that samples and holds a plurality of video signals that are the plurality of data signals;
A plurality of input terminals connected to the plurality of output terminals of the display driver,
Have
The sample hold circuit is
The drain of each transistor is connected to the pixel, the source of each transistor has a plurality of transistors connected to any one of the input terminals of the plurality of input terminals,
A first transistor of the plurality of transistors is arranged in the order of a source and a drain along a first direction of the electro-optical panel, and a second transistor adjacent to the first transistor along the first direction. The electro-optical device, wherein the transistor is arranged in the order of the drain and the source along the first direction. An electronic device comprising the display driver according to claim 1.

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