JP6765952B2 - Image sensor control device, its control method, control program, and image sensor - Google Patents

Description

The present invention relates to an image sensor control device, a control method thereof, a control program, and an image pickup device, and more particularly to an image sensor control device that performs correlated double sampling.

Generally, a CMOS image sensor used in an imaging device such as a digital camera has a light-shielding pixel (OB pixel) that serves as a reference for a black level and an aperture pixel that outputs an image signal according to incident light. Then, the OB pixel is used as a correction value acquisition region for correcting the output level of the aperture pixel based on the black level.

However, when the OB pixel is affected by so-called random noise and the error in the correction value obtained by the OB pixel becomes large, when the output of the aperture pixel is corrected based on the output of the OB pixel, pattern noise occurs and the image quality is improved. May deteriorate.

As an image pickup device that reduces the influence of random noise as described above, for example, the image pickup device described in Patent Document 1 is known.

The CMOS image sensor used in the image pickup apparatus specified in Patent Document 1 is provided with a column processing unit having an AD conversion unit for each column. Then, the column processing unit AD-samples the pixel reset level and the signal level a plurality of times, and averages the results. As a result, random noise generated in the pixels and the AD conversion unit is reduced.

Japanese Unexamined Patent Publication No. 2012-4727

However, in the image pickup apparatus described in Patent Document 1, since the reset level and the signal level are AD-sampled a plurality of times, the reading time of the image signal inevitably increases. As a result, the time until the shooting is completed will increase. On the other hand, if sampling is performed in an attempt to reduce the readout time, the noise reduction effect of sampling cannot be sufficiently obtained.

Therefore, an object of the present invention is an image sensor control device, a control method thereof, a control program, and an image pickup device, which do not increase the reading time of an image signal, reduce the influence of random noise, and do not deteriorate the image quality. Is to provide.

In order to achieve the above object, in the image pickup element control device according to the present invention, a plurality of pixels are arranged in a two-dimensional matrix, and a first pixel region that receives light and a second pixel region that is shielded from light are provided. An image pickup element control device that performs readout control of the pixels of the image pickup element, the first pixel signal obtained by readout control of the pixels in the first pixel region is subjected to AD conversion, and the second While the reading means that performs AD conversion on the second pixel signal obtained by performing reading control on the pixels in the pixel region of No. 1 and the reading means that controls the reading means to perform AD conversion once on the first pixel signal. The second pixel signal is characterized by having a control means for performing AD conversion a plurality of times, and a calculation means for adding and averaging the AD conversion results obtained by the plurality of AD conversions.

According to the present invention, it is possible to prevent an increase in the reading time of an image signal, reduce the influence of random noise, and reduce the deterioration of image quality.

It is a block diagram which shows the structure of an example of the image pickup apparatus which uses the image pickup element control apparatus which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the structure about the pixel shown in FIG. It is a timing diagram for demonstrating the pixel reading operation shown in FIG. It is a figure which shows an example of the structure of the column circuit shown in FIG. It is a figure for demonstrating the operation corresponding to the signal reading of the OB pixel provided in the OB region in the column circuit shown in FIG. It is a figure for demonstrating the operation corresponding to the signal reading of the aperture pixel provided in the aperture pixel region in the column circuit shown in FIG. It is a figure which shows an example about the structure of the pixel in the image sensor used in the camera which concerns on 2nd Embodiment of this invention. It is a timing diagram for demonstrating the pixel reading operation shown in FIG. 7. It is a figure for demonstrating the operation corresponding to the signal reading of the OB pixel provided in the OB region in the column circuit used by the camera which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating the operation corresponding to the signal reading of the aperture pixel provided in the aperture pixel region in the row circuit used by the camera which concerns on 2nd Embodiment of this invention.

An example of the image sensor control device according to the embodiment of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of an example of an image pickup device in which the image pickup device control device according to the first embodiment of the present invention is used.

The illustrated imaging device is, for example, a digital camera (hereinafter, simply referred to as a camera) 100, and includes a pixel portion 101 in which a plurality of pixels 104 are arranged in a two-dimensional matrix. The pixel 104 includes an OB pixel 105, which is optically shaded and serves as a reference for a black level, and an aperture pixel 106, which receives incident light and outputs a signal (pixel signal) corresponding to the incident light. The pixel unit 101 has an OB region 102 and an aperture pixel region 103, and in the OB region 102, the OB pixels 105 are arranged in a two-dimensional matrix. Further, in the aperture pixel region 103, the aperture pixels 106 are arranged in a two-dimensional matrix.

Further, the camera 100 includes a vertical scanning circuit 108, a vertical signal line 107, a column circuit 109, and a column circuit control unit 110. The vertical scanning circuit 108 selects and sequentially scans the pixels 104 that output the pixel signals, and outputs the pixel signals to the vertical signal line 107. The column circuit 109 processes the pixel signal output to the vertical signal line 107 for each column under the control of the column circuit control unit 110.

Further, the camera 100 has a horizontal scanning circuit 111, a timing control unit 112, and an output unit 113. The horizontal scanning circuit 111 sequentially reads out the pixel signals processed by the column circuit 109 for each column. The timing control unit 112 controls the operation timing of the vertical scanning circuit 108 and the horizontal scanning circuit 111, and outputs an image signal from the output unit 113.

As will be described later, the column circuit control unit 110 queues the first switch signal P_SW1, the second switch signal P_SW2, the third switch signal P_SW3, the fourth switch signal P_SW4, and the fifth switch signal P_SW5. Output to 109. Further, the column circuit control unit 110 outputs a lamp signal Vram, a reference voltage Vref, a count reset signal P_rst_count, and a clock CLK to the column circuit 109.

FIG. 2 is a diagram showing an example of the configuration of the pixels shown in FIG.

The pixel 104 includes a photodiode (PD: photoelectric conversion unit) 201, a floating diffusion layer 202, a pixel transistor 203, a selection transistor 204, a transfer transistor 205, and a reset transistor 206. The PD201 outputs an electric charge according to the incident light by photoelectric conversion. The transfer transistor 205 transfers the electric charge of the PD 201 to the floating diffusion layer 202. The floating diffusion layer 202 converts the charge into a voltage. The pixel transistor 203 outputs a voltage signal corresponding to the voltage of the floating diffusion layer 202 as a pixel signal. The selection transistor 204 selectively connects the pixel transistor 203 to the vertical signal line 107. The reset transistor 106 is a transistor for resetting the electric charge of the floating diffusion layer 202.

The selection signal SEL, the transfer signal TX, and the reset signal RES are sent from the vertical scanning circuit 108 to the selection transistor 204, the transfer transistor 205, and the reset transistor 206, respectively. Here, the pixel signal output from the pixel transistor 203 to the vertical signal line 107 is referred to as Vpix.

FIG. 3 is a timing diagram for explaining the pixel reading operation shown in FIG.

In the period T300, the vertical scanning circuit 108 sets the transfer signal TX and the reset signal RES to a high level (H level) under the control of the timing control unit 112. As a result, the transfer transistor 205 and the reset transistor 206 are turned on, and the PD 201 and the stray diffusion layer 202 are reset to potentials corresponding to the power supply voltage VDD.

During the T301 period, light is incident on the pixel unit 101 to accumulate electric charges. Here, under the control of the timing control unit 112, the vertical scanning circuit 108 sets the selection signal SEL to the H level. As a result, the selection transistor 204 is turned on, and the reset level is output as the pixel signal Vpix via the vertical output line 107. The pixel signal Vpix at this time is an N signal.

In the T302 period, the vertical scanning circuit 108 sets the transfer signal TX to the H level. As a result, the transfer transistor 205 is turned on, and the electric charge accumulated in the PD 201 is transferred to the floating diffusion layer 202. Then, the pixel signal Vpix obtained by adding the reset level held by the floating diffusion layer 202 to the electric charge accumulated in the PD 201 is output to the vertical signal line 107 via the pixel transistor 203 and the selection transistor 204. The pixel signal Vpix at this time is an S signal.

FIG. 4 is a diagram showing an example of the configuration of the column circuit shown in FIG.

The column circuit 109 includes a comparator 402, a counter 403, an AD conversion unit 404 including an OR circuit OG1, and an amplifier 401. Further, the column circuit 109 includes first to fifth switches SW1 to SW5, a clamp capacitance element Cclmp, and sample hold capacitance elements C_Vpix1 and C_Vpix2. The first to fifth switches SW1 to SW5 are on / off controlled by the first switch signals P_SW1 to P_SW5, respectively.

A pixel signal Vpix is input to the amplifier 401 from the pixel unit 101 via the vertical signal line 107. Then, the amplifier 401 amplifies the pixel signal Vpix and outputs the amplified signal Vpix_amp. In response to the on / off control of the first to fourth switches SW1 to SW4, the sample hold capacitance elements C_Vpix1 and C_Vpix2 sample-hold the amplification signal Vpix_amp and output it as the sample hold signal Vpix_sh.

The sample hold signal Vpix_sh is input to the comparator 402. Further, a lamp signal Vramp is input to the comparator 402 as a lamp signal Vcomp via the clamp capacitance element Cclmp according to the on / off control of the fifth switch SW5. As shown, the sample hold signal Vpix_sh is input to one input end of the comparator 402, and the lamp signal Vcomp is input to the other input end. Then, the comparator 402 outputs the comparison result as a comparison result signal CMP to the OR circuit OG1.

Further, a fifth switch signal P_SW5 is input to the OR circuit OG1, and the OR circuit OG1 outputs an OR signal that is the OR of the comparison result signal CMP and the fifth switch signal P_SW5 to the counter 403. The counter 403 counts based on the clock CLK during the period when the OR signal is at the L level, that is, during the period when the comparison result signal CMP and the fifth switch signal P_SW5 are at the L level. Then, the counter 403 outputs the count result as a count signal.

The counter 403 resets the count result in response to the count reset signal P_rst_count.

FIG. 5 is a diagram for explaining an operation in response to signal reading of OB pixels provided in the OB region in the column circuit shown in FIG.

In the illustrated example, since the signal level of the OB pixel 105 is small, AD conversion is performed a plurality of times. Further, when the first to fifth switch signals P_SW1 to P_SW5 are at H level, the first to fifth switches SW1 to SW5 are turned on, and when the first to fifth switch signals P_SW1 to P_SW5 are at L level. The first to fifth switches SW1 to SW5 are turned off. Although omitted in FIG. 5, the lamp signal Vramp monotonically increases during the periods T506 to T528.

In the period T500, the column circuit control unit 110 resets the counter 403 with the counter reset signal P_rst_count as the H level. Further, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the H level and turns on the fifth switch SW5. As a result, the lamp signal Vcomp is clamped to the reference voltage Vref. Further, when the fifth switch signal P_SW5 reaches the H level, the output of the OR circuit OG1 becomes the H level, and the counter 403 stops the counting operation.

Subsequently, in the period T501, the N signal is output from the pixel row selected by the vertical scanning circuit 108. As a result, the amplified signal Vpix_amp changes. Further, the column circuit control unit 110 turns on the switch SW1 with the first switch signal P_SW1 as the H level. As a result, the amplified signal Vpix_amp is sample-held by the sample hold capacitance element C_Vpix1. Hereinafter, the amplified signal Vpix_amp will be referred to as an AMP_N signal.

In the period T502, the column circuit control unit 110 turns on the switch SW2 with the second switch signal P_SW2 as the H level. As a result, the AMP_N signal sample-held by the sample-hold capacitive element C_Vpix1 is input to the comparator 402. Then, the comparator 402 compares the lamp signal Vcomp with the AMP_N signal and outputs the comparison result signal CMP.

In the period T502, the potential (voltage) of the lamp signal Vcomp is lower than the potential of the AMP_N signal, so that the comparison result signal CMP becomes the L level.

Further, the column circuit control unit 110 sets the fifth switch signal P_SW5 to the L level. As a result, the OR circuit OG1 outputs an L-level OR signal in response to the comparison result signal CMP and the fifth switch signal P_SW5. As a result, in the period T502, the counter 403 starts the counting operation at the timing when the fifth switch signal P_SW5 reaches the L level.

In the period T503, the potential of the lamp signal Vcomp becomes higher than the potential of the AMP_N signal, so that the comparison result signal CMP, which is the output of the comparator 402, becomes the H level. Therefore, since the OR circuit OG1 outputs an H level OR signal, the counter 403 stops the counting operation.

At this time, as will be described later, the counter 403 adds and outputs the result of AD conversion a plurality of times, and therefore holds the count value.

During the period T504, the column circuit control unit 110 sets the fifth switch signal P_SW5 to L level and turns on the fifth switch SW5. As a result, the lamp signal Vlamp is reset to the reference potential Vref and clamped to the reference voltage Vref. Further, since the fifth switch signal P_SW5 is at H level, the OR circuit OG1 maintains the OR signal at H level. As a result, the counter 403 maintains the stopped operation state.

In the period T505, the vertical scanning circuit 108 turns on the transfer transistor 205 with the transfer signal TX as the H level. As a result, the S signal is output to the amplifier 401 via the vertical signal line 107. Further, the column circuit control unit 110 turns on the third switch SW3 with the third switch signal P_SW3 as the H level. As a result, the S signal is sample-held by the sample hold capacitance element C_Vpix2, and the amplified signal Vpix_amp is output as an AMP_S signal.

In the periods T506 to T507, the same operation as the above-mentioned periods T502 to T503 is performed. Here, since the counter 403 starts and stops counting from the count value held in the period T503, the AD conversion result is added as a result.

During the period T508, the column circuit control unit 110 turns on the switch SW5 with the fifth switch signal P_SW5 as the H level. As a result, as described above, the lamp signal Vcomp is clamped to the reference voltage Vref.

In the period T509 to T516, the same operation as in the periods T506 to T508 is repeated. The count value held by the counter 403 in the period T516 is the sum of the results of AD conversion of the AMP_N signal a plurality of times, and the addition result is divided by the number of AD conversions by the arithmetic circuit (not shown). Average.

In the period T517, the column circuit control unit 110 resets the count value of the counter 403 to the initial value with the counter reset signal P_rst_count as the H level. Further, the column circuit control unit 110 turns on the switch SW4 with the fourth switch signal P_SW4 as the H level. As a result, the AMP_S signal sample-held by the sample-hold capacitance element C_Vpix2 is input to the comparator 402.

In the periods T518 to T528, the same operation as in the periods T506 to T516 is performed on the AMP_S signal. The count value held by the counter 403 in the period T528 is the sum of the results of AD conversion of the AMP_S signal a plurality of times, and the addition result is divided by the number of AD conversions by the arithmetic circuit and averaged.

In the period T529, the column circuit control unit 110 resets the count value of the counter 403 to the initial value with the counter reset signal P_rst_count as the H level. Then, in the period T529, the operation of reading the selected row is completed, the next row is selected by the vertical scanning circuit 108, and the same operation is performed.

FIG. 6 is a diagram for explaining an operation in response to signal reading of an aperture pixel provided in an aperture pixel region in the column circuit shown in FIG. Although omitted in FIG. 6, the lamp signal Vramp monotonically increases during the periods T606 to T607.

In the periods T600 to 603, the same operation as in the periods T500 to T503 described with reference to FIG. 5 is performed. In the period T603, the count value held by the counter 403 is a digital signal corresponding to the AMP_N signal.

In the period T604, the column circuit control unit 110 turns on the fifth switch SW5 with the fifth switch signal P_SW5 as the H level. As a result, the lamp signal Vlamp is reset and clamped to the reference voltage Vref. Further, since the fifth switch signal P_SW5 is at H level, the OR signal, which is the output of the OR circuit OG1, is maintained at H level, and the counter 403 is in a state of being stopped.

In the period T605, the same operation as in the period T505 described with reference to FIG. 5 is performed. Further, in the period T606, the operation performed on the AMP_N signal in the period T602 is performed on the AMP_S signal. In the period T607, the same operation as in the period T603 is performed. At this time, the count value held by the counter 403 becomes a digital signal corresponding to the AMP_S signal.

In the period T610, the column circuit control unit 110 resets the count value of the counter 403 to the initial value with the counter reset signal P_rst_count as the H level. In the period T610, the operation of reading the selected row is completed, the next row is selected by the vertical scanning circuit 108, and the same operation is performed. In FIG. 6, the periods T500 to T529 are the same periods as the periods T500 to T529 shown in FIG.

As is clear from the above description, at the timing of starting the AD conversion for the S signal in the aperture pixel region 103, the AD conversion is performed a plurality of times for the N signal in the OB region 102.

Here, the noise reduction effect and the determination of the AD conversion number in the above-mentioned camera will be described.

In the correlated double sampling used in the illustrated camera, the noise reduction effect of multiple samplings is given by the following equation (1) by error propagation.

In the equation (1), σmulti indicates the noise level when sampling is performed multiple times, and σsingle indicates the noise level when sampling is not performed multiple times. Further, l and m indicate the number of sampling times of the AMP_N signal and the AMP_S signal, respectively.

From the equation (1), under the condition that the total number of samplings of the AMP_N signal and the AMP_S signal is constant, the effect of reducing random noise by multiple samplings is maximized when the sampling times l and m are equal.

On the other hand, under the same conditions, when either one of the sampling times l and m is 1, the effect of reducing random noise by multiple samplings is minimized.

For example, the total number of sampling times of the AMP_N signal and the AMP_S signal in the OB region 102 is 9 times. In this case, the number of samplings of the AMP_N signal is set to 5 and the number of samplings of the AMP_S signal is set to 4 so that the noise reduction effect when sampling is performed a plurality of times in the correlated double sampling is maximized. The number of samplings is an example, and is not limited to this example.

Further, due to changes in imaging conditions (for example, high sensitivity, long exposure, or high temperature environment), the signal level of the S signal in the OB region 102 may increase even though the light is shielded. In such a case, the dynamic range in the AD conversion may be changed to change the total number of AD conversions of the AMP_N signal and the AMP_S signal.

In this way, in the first embodiment of the present invention, while the AD conversion is performed once for the first pixel signal obtained from the aperture pixel region, AD is performed for the second pixel signal obtained from the OB region. Have the conversion performed multiple times. Then, the AD conversion results obtained by the plurality of AD conversions are added and averaged. As a result, the random noise in the OB region is reduced while preventing an increase in the time required for reading the image signal, and as a result, the generation of pattern noise due to the random noise can be reduced.

[Second Embodiment]
Subsequently, an example of the camera according to the second embodiment of the present invention will be described. The configuration of the camera according to the second embodiment is the same as that of the camera shown in FIG.

FIG. 7 is a diagram showing an example of the configuration of pixels in the image sensor used in the camera according to the second embodiment of the present invention.

The pixel 104 shown in FIG. 7 has a plurality of PD701 and 702 according to the pupil division, unlike the pixel 104 described in FIG. The transfer transistors 706 and 707 transfer the charges of PD 701 and 702 to the floating diffusion layer 703, respectively. The pixel transistor 704 outputs a voltage signal corresponding to the voltage of the floating diffusion layer 703 as a pixel signal. The selection transistor 705 selectively connects the pixel transistor 704 to the vertical signal line 107. The reset transistor 708 is a transistor for resetting the electric charge of the floating diffusion layer 703.

The selection signal SEL, the transfer signals TX_A and TX_B, and the reset signal RES are sent from the vertical scanning circuit 108 to the selection transistor 705, the transfer transistors 706 and 707, and the reset transistor 708, respectively.

FIG. 8 is a timing diagram for explaining the pixel reading operation shown in FIG. 7.

In the period T800, the vertical scanning circuit 108 sets the transfer signals TX_A and TX_B and the reset signal RE as the H level, and turns on the transfer transistors 706 and 707 and the reset transistor 708. As a result, the PDs 701 and 702 and the floating diffusion layer 703 are reset to potentials corresponding to the power supply voltage VDD.

In the period T801, light is incident on the pixel portion 101, and charge accumulation in the PD 701 and 702 starts. The vertical scanning circuit 108 sets the selection signal SEL to the H level and turns on the selection transistor 705. As a result, the reset level is output to the vertical output line 107 as a pixel signal Vpix. The pixel signal Vpix at this time is an N signal.

In the period T802, the vertical scanning circuit 108 turns on the transfer transistor A706 with the transfer signal TX_A as the H level. As a result, the electric charge accumulated in the PD 701 is transferred to the floating diffusion layer 703. Then, the pixel signal Vpix obtained by adding the reset level held by the floating diffusion layer 703 to the electric charge accumulated in the PD 701 is output to the vertical signal line 107 via the pixel transistor 704 and the selection transistor 705. The pixel signal Vpix at this time is used as the S_A signal.

During period T803, the vertical scanning circuit 108 turns on the transfer transistors 706 and 707 with the transfer signals TX_A and TX_B as H levels. As a result, the charges accumulated in the PDs 701 and 702 are transferred to the floating diffusion layer 703. Then, the pixel signal Vpix obtained by adding the reset level held by the floating diffusion layer 703 to the charges accumulated in the PD 701 and 702 is output to the vertical signal line 107 via the pixel transistor 704 and the selection transistor 705. The pixel signal Vpix at this time is defined as an S_AB signal.

FIG. 9 is a diagram for explaining an operation in response to signal reading of OB pixels provided in an OB region in a column circuit used in a camera according to a second embodiment of the present invention. The configuration of the column circuit used in the camera according to the second embodiment is the same as that of the column circuit shown in FIG.

In the illustrated example, since the signal level of the OB pixel 105 is small, AD conversion is performed a plurality of times. Also, although omitted in FIG. 9, the ramp signal Vram monotonically increases during periods T906-T917 and periods T920-930.

In the period T900, the column circuit control unit 110 resets the counter 403 with the counter reset signal P_rst_count as the H level. Further, the column circuit control unit 110 turns on the switch SW5 with the fifth switch signal P_SW5 as the H level. As a result, the lamp signal Vcomp is clamped to the reference voltage Vref. Then, when the fifth switch signal P_SW5 reaches the H level, the OR signal, which is the output of the OR circuit OG1, becomes the H level, and the counter 403 stops the counting operation.

In the periods T901 to T904, the same operation as in the periods T501 to T504 described with reference to FIG. 5 is performed.

During the period T905, the vertical scanning circuit 108 turns on the transfer transistor 706 with the transfer signal TX_A as the H level. As a result, as described above, the S_A signal is output to the amplifier 401 via the vertical signal line 107. Further, the column circuit control unit 110 turns on the third switch SW3 with the third switch signal P_SW3 as the H level. As a result, the S_A signal is sample-held by the sample-hold capacitance element C_Vpix2. Here, the amplification signal Vpix_amp, which is the output of the amplifier 401, is used as the AMP_S_A signal.

In the periods T906 to T909, the same operation as in the periods T506 to T509 described with reference to FIG. 5 is performed. In the period T910, the same operation as in the period T907 is performed. At that time, the count value held by the counter 403 is the sum of the results of AD conversion of the AMP_N signal a plurality of times, and the addition result is divided by the number of AD conversions by the arithmetic circuit and averaged.

In the period T911, the column circuit control unit 110 turns on the fifth switch SW5 with the fifth switch signal P_SW5 as the H level. As a result, the lamp signal Vcomp is clamped at the reference voltage Vref. Then, the column circuit control unit 110 resets the count value of the counter 403 to the initial value by setting the counter reset signal P_rst_count to the H level.

In the period T912, the column circuit control unit 110 turns on the fourth switch SW4 with the fourth switch signal P_SW4 as the H level. As a result, the AMP_S_A signal sample-held by the sample-hold capacitance element C_Vpix2 is input to the comparator 402.

In the periods T913 to T916, the same operation as in the periods T906 to T909 is performed for the AMP_S_A signal. In the period T917, the same operation as in the period T910 is performed for the AMP_S_A signal. At this time, the count value held by the counter 403 is the sum of the results of AD conversion of the AMP_S_A signal a plurality of times, and the addition result is divided by the number of AD conversions by the arithmetic circuit and averaged. In the period T918, the same operation as in the period T911 is performed.

In the period T919, the column circuit control unit 110 turns on the transfer transistors 706 and 707 with the transfer signals TX_A and TX_B as H levels. As a result, the S_AB signal is output to the amplifier 401 via the vertical signal line 107. Further, the column circuit control unit 110 turns on the first switch SW1 and the third switch SW3, and sample-holds the S_AB signal by the sample hold capacitance element C_Vpix1. Here, the amplification signal Vpix_amp, which is the output of the amplifier 401, is used as the AMP_S_AB signal.

In the periods T920 to T931, the same operation as in the periods T518 to T529 described with reference to FIG. 5 is performed for the AMP_S_AB signal. Then, in the period T931, the operation of reading the selected row is completed, the next row is selected by the vertical scanning circuit 108, and the same operation is performed.

FIG. 10 is a diagram for explaining an operation in response to signal reading of an aperture pixel provided in an aperture pixel region in a column circuit used in a camera according to a second embodiment of the present invention. Although the odor is omitted in FIG. 10, the lamp signal Vlamp increases monotonically in the periods T1006 to T1017 and the periods T1020 to T1030.

In the periods T1001 to T1004, the same operation as in the periods T601 to T604 described with reference to FIG. 6 is performed.

In the period T1005, the column circuit control unit 110 turns on the transfer transistor 706 with the transfer signal TX_A as the H level. As a result, the S_A signal is output to the amplifier 401 via the vertical signal line 107. Further, the column circuit control unit 110 turns on the third switch SW3 with the third switch signal P_SW3 as the H level. As a result, the S_A signal is sample-held by the sample-hold capacitance element C_Vpix2. The amplified signal Vpix_amp, which is the output of the amplifier 401, is used as the AMP_S_A signal.

In the periods T1006 to T1007, the operation performed on the AMP_N signal in the period T1002 is performed on the AMP_S_A signal. In the periods T1008 to T1016, the same operation as the period T1003 is performed, and in the periods T1017 and T1018, the same operation as the period T1004 is performed. Further, in the period T1019, the same operation as the period T919 described with reference to FIG. 9 is performed.

In the periods T1020 to T1022, the same operation as in the periods T1006 to 1007 is performed for the AMP_S_AB signal. In the periods T1023 to T1030, the same operation as in the periods T1008 to T1015 is performed.

In the period T1031, the column circuit control unit 110 resets the count value of the counter 403 to the initial value with the counter reset signal P_rst_count as the H level. Then, in the period T1031, the operation of one line selected by the pixel unit is completed, the next line is selected by the vertical scanning circuit 108, and the same operation is performed.

As described above, in the second embodiment of the present invention, the AD conversion is performed on the N signal in the OB region 102 during the period T1006 when the AD conversion is started for the S_A signal in the opening region 103. Further, the S_AB signal in the OB region 102 is subjected to AD conversion in synchronization with the S_A signal in the opening region 103.

In the second embodiment, for example, the number of samplings of the AMP_N signal in the OB region is 3 times, the number of samplings of the AMP_S_A signal is 2 times, and the number of samplings of the AMP_S_AB signal is 4 times. The number of samplings is an example, and is not limited to this example.

Further, as in the first embodiment, the signal level of the S signal in the OB region 102 may be high even though the light is shielded due to changes in imaging conditions and the like. In such a case, the dynamic range in the AD conversion may be changed to change the total number of AD conversions of the AMP_N signal, the AMP_S_A signal, and the AMP_S_AB signal. Along with this, the AD conversion may be performed on the S_A signal in the OB area 102 during the period during which the AD conversion is performed on the S_AB signal in the opening region 103.

In this way, also in the second embodiment of the present invention, as a result of reducing the random noise in the OB region, it is possible to reduce the generation of pattern noise caused by the random noise.

Although not shown in FIG. 1, the camera includes a processing device such as an image pickup lens and an image processing unit that performs predetermined image processing on an image signal read from the image sensor.

Although the present invention has been described above based on the embodiments, the present invention is not limited to these embodiments, and various embodiments within the scope of the gist of the present invention are also included in the present invention. ..

For example, the function of the above-described embodiment may be used as a control method, and the image sensor control device may be made to execute this control method. Further, a program having the functions of the above-described embodiment may be used as a control program, and the control program may be executed by a computer included in the image sensor control device. The control program is recorded on a computer-readable recording medium, for example.

[Other Embodiments]
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

101 Pixel part 102 OB area 103 Aperture pixel area 108 Vertical scanning circuit 109 Row circuit 110 Row circuit control unit 111 Horizontal scanning circuit 112 Timing control unit 113 Output unit

Claims (7)

An image sensor control device in which a plurality of pixels are arranged in a two-dimensional matrix and read-out control of the pixels is performed on an image sensor having a first pixel region that receives light and a second pixel region that is shielded from light. hand,
The second pixel signal obtained by performing AD conversion on the first pixel signal obtained by performing read control on the pixels in the first pixel region and performing read control on the pixels in the second pixel region. And the reading means to perform AD conversion
A control means for controlling the reading means to perform AD conversion for the first pixel signal once, and a control means for performing AD conversion for the second pixel signal a plurality of times.
An arithmetic means for adding and averaging the AD conversion results obtained by the plurality of AD conversions,
An image sensor control device characterized by having. The claim is characterized in that the control means causes the first pixel signal to be AD-converted while the second pixel signal obtained when the pixel is reset by the reading means is AD-converted. The image pickup element control device according to 1. Each of the plurality of pixels has a plurality of pupil-divided photoelectric conversion units.
The control means receives the first pixel signal obtained by the plurality of photoelectric conversion units while the second pixel signal obtained when the pixel is reset is AD-converted to the reading means. The image pickup element control device according to claim 1, wherein the image sensor is subjected to AD conversion. A first photoelectric conversion unit and a second photoelectric conversion unit are provided as the plurality of photoelectric conversion units.
When the AD conversion is performed, the reading means samples and holds the second pixel signal, and then displays the first pixel signal obtained by the first photoelectric conversion unit and the second photoelectric conversion unit. The image pickup device control device according to claim 3, wherein the sample is held, and the second pixel signal obtained by the first photoelectric conversion unit is sample-held. An image sensor in which a plurality of pixels are arranged in a two-dimensional matrix and has a first pixel region that receives light and a second pixel region that is shielded from light.
The image sensor control device according to any one of claims 1 to 4.
An image processing means that performs predetermined image processing on the image signal obtained by AD conversion by the reading means, and
An imaging device characterized by having. Control of an image sensor control device that controls reading out the pixels of an image sensor having a first pixel region in which a plurality of pixels are arranged in a two-dimensional matrix and receives light and a second pixel region that is shielded from light. It's a method
The second pixel signal obtained by performing AD conversion on the first pixel signal obtained by performing read control on the pixels in the first pixel region and performing read control on the pixels in the second pixel region. And the read step to perform AD conversion
A control step in which the AD conversion is performed a plurality of times for the second pixel signal while the AD conversion is performed once for the first pixel signal by the read step.
The calculation step of adding and averaging the AD conversion results obtained by the plurality of AD conversions,
A control method characterized by having. Used in an image sensor control device that controls reading out the pixels of an image sensor having a first pixel region that receives light and a second pixel region that is shielded from light, in which a plurality of pixels are arranged in a two-dimensional matrix. It is a control program that can be
In the computer included in the image sensor control device
The second pixel signal obtained by performing AD conversion on the first pixel signal obtained by performing read control on the pixels in the first pixel region and performing read control on the pixels in the second pixel region. And the read step to perform AD conversion
A control step in which the AD conversion is performed a plurality of times for the second pixel signal while the AD conversion is performed once for the first pixel signal by the read step.
The calculation step of adding and averaging the AD conversion results obtained by the plurality of AD conversions,
A control program characterized by executing.

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