JP6766607B2

JP6766607B2 - Thin film device

Info

Publication number: JP6766607B2
Application number: JP2016220929A
Authority: JP
Inventors: 智進藤; 智行芦峰; 竹島　裕; 裕竹島
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2016-11-11
Filing date: 2016-11-11
Publication date: 2020-10-14
Anticipated expiration: 2036-11-11
Also published as: JP2018078259A

Description

本発明は、薄膜キャパシタ素子と薄膜抵抗素子を備える薄膜デバイスに関する。 The present invention relates to a thin film device including a thin film capacitor element and a thin film resistance element.

従来、薄膜キャパシタ素子と薄膜抵抗素子を備える種々の薄膜デバイスが提供されている（例えば特許文献１参照）。例えば、図６に示す従来の薄膜デバイス１００は、支持基板上に複数の薄膜キャパシタ素子Ｃ１〜Ｃ５と複数の薄膜抵抗素子Ｒ１〜Ｒ４とにより高周波回路が形成されている。薄膜キャパシタ素子Ｃ１〜Ｃ５は、それぞれ可変容量素子であり、第１の可変容量素子Ｃ１の入力端子と、第２の可変容量素子Ｃ２−第３の可変容量素子Ｃ３の直列接続点および第４の可変容量素子Ｃ４−第５の可変容量素子Ｃ５の直列接続点との間に、薄膜抵抗素子Ｒ１，Ｒ２を有するバイアスラインＢ１，Ｂ２がそれぞれ設けられる。また、第５の薄膜キャパシタ素子Ｃ５の出力側端子部と、第３の可変容量素子Ｃ３−第４の可変容量素子Ｃ４の直列接続点および第１の可変容量素子Ｃ１−第２の可変容量素子Ｃ２の直列接続点との間に、薄膜抵抗素子Ｒ３，Ｒ４を有するバイアスラインＢ３，Ｂ４がそれぞれ設けられる。 Conventionally, various thin film devices including a thin film capacitor element and a thin film resistance element have been provided (see, for example, Patent Document 1). For example, in the conventional thin film device 100 shown in FIG. 6, a high frequency circuit is formed by a plurality of thin film capacitor elements C1 to C5 and a plurality of thin film resistance elements R1 to R4 on a support substrate. The thin film capacitor elements C1 to C5 are variable capacitance elements, respectively, and are a series connection point of the input terminal of the first variable capacitance element C1, the second variable capacitance element C2-third variable capacitance element C3, and the fourth variable capacitance element C3. Bias lines B1 and B2 having thin film resistance elements R1 and R2 are provided between the variable capacitance element C4- and the series connection point of the fifth variable capacitance element C5, respectively. Further, the output side terminal portion of the fifth thin film capacitor element C5, the series connection point of the third variable capacitance element C3-fourth variable capacitance element C4, and the first variable capacitance element C1-second variable capacitance element. Bias lines B3 and B4 having thin film resistance elements R3 and R4 are provided between the series connection point of C2, respectively.

ここで、バイアスラインＢ１〜Ｂ４の薄膜抵抗素子Ｒ１〜Ｒ４は、直列接続された可変容量素子Ｃ１〜Ｃ５の高周波信号の周波数領域でのインピーダンスよりも大きな抵抗成分となっており、高周波信号を遮蔽するため、高周波信号は直列に接続された可変容量素子Ｃ１〜Ｃ５を通り、直流バイアス電圧は各可変容量素子Ｃ１〜Ｃ５に独立に印加される。これにより、直流的には可変容量素子Ｃ１〜Ｃ５が並列に接続された可変コンデンサとなる。一方、高周波信号はバイアスラインＢ１〜Ｂ４により遮蔽されるため、高周波的には可変容量素子Ｃ１〜Ｃ５が直列に接続された可変コンデンサとなる。したがって、高周波電圧は、各可変容量素子Ｃ１〜Ｃ５に分圧されるため、容量変化を小さくでき、波形歪みや相互変調歪み等を抑制することができる。 Here, the thin film resistance elements R1 to R4 of the bias lines B1 to B4 have a resistance component larger than the impedance in the frequency region of the high frequency signal of the variable capacitance elements C1 to C5 connected in series, and shield the high frequency signal. Therefore, the high frequency signal passes through the variable capacitance elements C1 to C5 connected in series, and the DC bias voltage is independently applied to the variable capacitance elements C1 to C5. As a result, in terms of direct current, the variable capacitance elements C1 to C5 become a variable capacitor connected in parallel. On the other hand, since the high frequency signal is shielded by the bias lines B1 to B4, the variable capacitor elements C1 to C5 are connected in series at high frequencies. Therefore, since the high frequency voltage is divided into the variable capacitance elements C1 to C5, the capacitance change can be reduced and waveform distortion, intermodulation distortion, and the like can be suppressed.

このような構成の場合、薄膜抵抗素子Ｒ１〜Ｒ４の抵抗値が小さすぎると、高周波信号がバイアスラインＢ１〜Ｂ４に流れてＱ値が低下する。一方、薄膜抵抗素子Ｒ１〜Ｒ４の抵抗値が大きすぎると、可変容量素子Ｃ１〜Ｃ５に印加される直流バイアス電圧が減少するため、所望の容量変化量が得られない。そこで、特許文献１の薄膜デバイスでは、薄膜抵抗素子Ｒ１〜Ｒ４の抵抗値が各可変容量素子Ｃ１〜Ｃ５の絶縁抵抗Ｒｃ１〜Ｒｃ５の１／１００以下としている。 In the case of such a configuration, if the resistance values of the thin film resistance elements R1 to R4 are too small, a high frequency signal flows to the bias lines B1 to B4 and the Q value decreases. On the other hand, if the resistance values of the thin film resistance elements R1 to R4 are too large, the DC bias voltage applied to the variable capacitance elements C1 to C5 decreases, so that a desired capacitance change amount cannot be obtained. Therefore, in the thin film device of Patent Document 1, the resistance value of the thin film resistance elements R1 to R4 is set to 1/100 or less of the insulation resistances Rc1 to Rc5 of the variable capacitance elements C1 to C5.

また、可変容量素子Ｃ１〜Ｃ５はセラミックで形成されており、この場合は、温度が上がると絶縁抵抗が減少するという負の抵抗温度係数（例えば、−１５４００ｐｐｍ／℃）を有することが知られている。したがって、特許文献１では、所望の容量変化量が得るためには、薄膜抵抗素子Ｒ１〜Ｒ４の抵抗温度係数も負の値を持つ方が好ましいとしている。 Further, the variable capacitance elements C1 to C5 are made of ceramic, and in this case, it is known to have a negative temperature coefficient of resistance (for example, -15400 ppm / ° C.) that the insulation resistance decreases as the temperature rises. There is. Therefore, Patent Document 1 states that it is preferable that the resistance temperature coefficients of the thin film resistance elements R1 to R4 also have a negative value in order to obtain a desired capacitance change amount.

特開２００６−６６６４７号公報（段落００２６〜００３７、図１など）Japanese Unexamined Patent Publication No. 2006-66647 (paragraphs 0026 to 0037, FIG. 1 and the like)

ところで、薄膜デバイスの小型化のためには、薄膜抵抗素子を形成する材料の電気抵抗率（比抵抗）を高くして、薄膜抵抗素子の形成領域を小さくしたいという要請がある。引用文献１では、薄膜抵抗素子Ｒ１〜Ｒ４の比抵抗が１Ωｃｍ以上であることが望ましいとされている。このような高い比抵抗を有する抵抗材料の一例としては、ＴａＳｉＮ、ＴａＳｉＯ系などがあるが、比抵抗を上げるにはＳｉの含有量を増やすのが一般的である。薄膜抵抗素子にＳｉの含有量が増加すると、抵抗温度係数の負の値が大きくなるため、薄膜抵抗素子の抵抗温度係数の値が負であり、かつ、可変容量素子の抵抗温度係数の値が負である場合に、薄膜抵抗素子の抵抗温度係数の大きさ（絶対値）が可変容量素子の抵抗温度係数の大きさ（絶対値）よりも大きくなる場合がある。この場合、使用温度範囲の低温側において、可変容量素子の絶縁抵抗値に対する薄膜抵抗素子の抵抗値の比率が高くなって、可変容量素子において所望の容量変化量が得られないという問題が生じる場合がある。特に、可変容量素子をセラミックで形成して、バイアス電圧を印加して容量変化を利用する用途においては、セラミックの誘電体の膜厚を薄くして、バイアス電圧の電界強度を高くする方が優れた容量変化特性を得られる。しかしながら、膜厚を薄くすると可変容量素子の絶縁抵抗が減少するため、このような場合は上述の問題が顕著化する。 By the way, in order to reduce the size of a thin film device, there is a demand to increase the electrical resistivity (specific resistance) of the material forming the thin film resistance element and reduce the formation region of the thin film resistance element. In Reference 1, it is desirable that the specific resistances of the thin film resistance elements R1 to R4 are 1 Ωcm or more. Examples of resistance materials having such a high specific resistance include TaSiN and TaSiO-based materials, but in order to increase the specific resistance, it is common to increase the Si content. As the Si content in the thin film resistance element increases, the negative value of the temperature coefficient of resistance increases. Therefore, the value of the temperature coefficient of resistance of the thin film resistance element is negative and the value of the temperature coefficient of resistance of the variable capacitance element increases. When it is negative, the magnitude (absolute value) of the temperature coefficient of resistance of the thin film resistance element may be larger than the magnitude (absolute value) of the temperature coefficient of resistance of the variable capacitance element. In this case, on the low temperature side of the operating temperature range, the ratio of the resistance value of the thin film resistance element to the insulation resistance value of the variable capacitance element becomes high, and there arises a problem that the desired capacitance change amount cannot be obtained in the variable capacitance element. There is. In particular, in an application in which a variable capacitance element is formed of ceramic and a bias voltage is applied to utilize the capacitance change, it is better to reduce the film thickness of the ceramic dielectric and increase the electric field strength of the bias voltage. The capacitance change characteristic can be obtained. However, when the film thickness is reduced, the insulation resistance of the variable capacitance element decreases, and in such a case, the above-mentioned problem becomes remarkable.

この発明は、上記した課題に鑑みてなされたものであり、セラミックで形成された薄膜キャパシタ素子に直流バイアス電圧を印加して、容量変化特性を利用する薄膜デバイスにおいて、薄膜キャパシタ素子の絶縁抵抗が低い場合であっても、薄膜キャパシタ素子に十分に直流バイアス電圧を印加することができ、所望の容量変化特性を得ることができる技術を提供することを目的とする。 The present invention has been made in view of the above-mentioned problems, and in a thin film device in which a DC bias voltage is applied to a thin film capacitor element made of ceramic to utilize the capacitance change characteristic, the insulation resistance of the thin film capacitor element is increased. It is an object of the present invention to provide a technique capable of sufficiently applying a DC bias voltage to a thin film capacitor element even when the value is low and obtaining desired capacitance change characteristics.

上記した目的を達成するために、本発明の薄膜デバイスは、高周波信号ラインと、前記高周波信号ラインに挿入された、直流バイアス電圧により容量が変化する薄膜キャパシタ素子と、該薄膜キャパシタ素子に対して直流バイアス電圧を印加するバイアス電圧印加ラインと、該バイアス電圧印加ラインに挿入されて、前記薄膜キャパシタ素子と直列に接続される薄膜抵抗素子とを有する回路が形成された薄膜デバイスであって、前記薄膜キャパシタ素子と、前記薄膜抵抗素子とは、同一の積層体内部に形成されており、前記薄膜キャパシタ素子は、負の抵抗温度係数を有するセラミック誘電体薄膜と、一対の電極膜とを有するとともに、使用温度範囲において絶縁抵抗値が５０ＭΩ以下であり、前記薄膜抵抗素子を形成する材料は、電気抵抗率が１００００μΩｃｍ以上であって、抵抗温度係数が前記誘電体薄膜の抵抗温度係数の絶対値よりも小さく、前記積層体は、基板と、該基板の一方主面上に積層された複数の樹脂層とを有し、前記薄膜抵抗素子は、前記複数の樹脂層のうちの一つに形成されるとともに、前記薄膜抵抗素子が形成された前記樹脂層とは異なる前記樹脂層には配線電極が形成され、前記薄膜抵抗素子上には補強用薄膜が形成され、前記補強用薄膜は、前記基板の前記一方主面に対して垂直な方向から見たときに、前記配線電極の端縁と重なるように配置されていることを特徴としている。 In order to achieve the above object, the thin film device of the present invention relates to a high frequency signal line, a thin film capacitor element whose capacitance is changed by a DC bias voltage inserted in the high frequency signal line, and the thin film capacitor element. A thin film device in which a circuit having a bias voltage application line for applying a DC bias voltage and a thin film resistance element inserted into the bias voltage application line and connected in series with the thin film capacitor element is formed. The thin film capacitor element and the thin film resistance element are formed inside the same laminate, and the thin film capacitor element has a ceramic dielectric thin film having a negative resistance temperature coefficient and a pair of electrode films. In the operating temperature range, the insulation resistance value is 50 MΩ or less, the material forming the thin film resistance element has an electric resistance of 10,000 μΩcm or more, and the resistance temperature coefficient is based on the absolute value of the resistance temperature coefficient of the dielectric thin film. even rather small, the laminate comprises a substrate and a plurality of resin layers laminated on one main surface of the substrate, the thin film resistive element is formed in one of the plurality of resin layers At the same time, a wiring electrode is formed in the resin layer different from the resin layer in which the thin film resistance element is formed, a reinforcing thin film is formed on the thin film resistance element, and the reinforcing thin film is formed of the reinforcing thin film. It is characterized in that it is arranged so as to overlap with the end edge of the wiring electrode when viewed from a direction perpendicular to the one main surface of the substrate .

この構成によれば、薄膜抵抗素子の電気抵抗率が１００００μΩｃｍ以上という高い値であって、セラミック誘電体薄膜の絶縁抵抗値が５０ＭΩ以下という低い値であっても、使用範囲内の全てにおいて、印加した直流バイアス電圧の９５％以上を薄膜キャパシタ素子に印加でき、所望の容量変化特性を得ることができる。また、同じ積層体内部に薄膜キャパシタ素子と薄膜抵抗素子の両方が形成されるため、薄膜デバイスの小型化を図ることができる。また、基板の一方主面に対して垂直な方向から見たときに、薄膜抵抗素子における、配線電極の端縁と重なる部分には応力が集中しやすいため、薄膜抵抗素子上の補強用薄膜が配線電極の端縁と重なるように配置されることで、薄膜抵抗素子に加わる曲げ応力等を好適に緩和できる。 According to this configuration, even if the electric resistance of the thin film resistance element is as high as 10000 μΩcm or more and the insulation resistance value of the ceramic dielectric thin film is as low as 50 MΩ or less, it is applied in all of the range of use. 95% or more of the DC bias voltage can be applied to the thin film capacitor element, and a desired capacitance change characteristic can be obtained. Further, since both the thin film capacitor element and the thin film resistance element are formed inside the same laminate, the thin film device can be miniaturized. Further, when viewed from a direction perpendicular to one main surface of the substrate, stress tends to concentrate on the portion of the thin film resistance element that overlaps with the edge of the wiring electrode, so that the reinforcing thin film on the thin film resistance element is formed. By arranging so as to overlap the edge of the wiring electrode, bending stress and the like applied to the thin film resistance element can be suitably relaxed.

また、前記薄膜抵抗素子を形成する材料が、ＳｉとＮｉとＣｒとを含有していてもよい。 Further, the material forming the thin film resistance element may contain Si, Ni and Cr.

この構成によれば、電気抵抗率が１００００μΩｃｍ以上であって、抵抗温度係数が前記誘電体薄膜の抵抗温度係数の絶対値よりも小さい薄膜抵抗素子を容易に形成することができる。 According to this configuration, it is possible to easily form a thin film resistance element having an electrical resistivity of 10,000 μΩcm or more and a resistance temperature coefficient smaller than the absolute value of the resistance temperature coefficient of the dielectric thin film.

本発明によれば、薄膜抵抗素子の電気抵抗率が１００００μΩｃｍ以上という高い値であって、セラミック誘電体薄膜の絶縁抵抗値が５０ＭΩ以下という低い値であっても、使用範囲内の全てにおいて、印加した直流バイアス電圧の９５％以上を薄膜キャパシタ素子に印加でき、所望の容量変化特性を得ることができる。 According to the present invention, even if the electric resistance of the thin film resistance element is as high as 10000 μΩcm or more and the insulation resistance value of the ceramic dielectric thin film is as low as 50 MΩ or less, it is applied in all of the range of use. 95% or more of the DC bias voltage can be applied to the thin film capacitor element, and a desired capacitance change characteristic can be obtained.

本発明の一実施形態にかかる薄膜デバイスの断面図である。It is sectional drawing of the thin film device which concerns on one Embodiment of this invention. 図１の薄膜デバイスの回路の概略構成図である。It is a schematic block diagram of the circuit of the thin film device of FIG. 図１の薄膜デバイスと従来との特性比較を示す図である。It is a figure which shows the characteristic comparison between the thin film device of FIG. 1 and the conventional type. 薄膜キャパシタ素子に印加されるバイアス電圧の割合を従来と比較した図である。It is a figure which compared the ratio of the bias voltage applied to the thin film capacitor element with the conventional. 使用温度範囲内の薄膜キャパシタ素子の絶縁抵抗と薄膜抵抗素子の抵抗との関係を従来の薄膜抵抗素子と比較した図である。It is a figure which compared the relationship between the insulation resistance of a thin film capacitor element within the operating temperature range, and the resistance of a thin film resistance element with a conventional thin film resistance element. 従来の薄膜デバイスの回路構成図である。It is a circuit block diagram of the conventional thin film device.

＜実施形態＞
本発明の一実施形態について図１および図２を参照して説明する。なお、図１および図２では、説明を簡易なものとするために本発明にかかる主要な構成のみが図示されている。 <Embodiment>
An embodiment of the present invention will be described with reference to FIGS. 1 and 2. Note that, in FIGS. 1 and 2, only the main configuration according to the present invention is shown for the sake of simplicity.

（構成）
薄膜デバイス１００の概略構成について説明する。 (Constitution)
The schematic configuration of the thin film device 100 will be described.

薄膜デバイス１００は、ガラス基板やセラミック基板、樹脂基板、Ｓｉ基板、ＧａＡｓ基板などの基板１と、基板１の一方主面１ａ側に積層された複数の樹脂層２，３，４と、基板１の一方主面１ａ上に設けられた可変容量型の薄膜キャパシタ素子Ｃと、薄膜抵抗素子Ｒ１，Ｒ２とを備え、基板１上に複数の樹脂層２，３，４が積層されてなる１つの積層体内に、薄膜キャパシタ素子Ｃと薄膜抵抗素子Ｒ１，Ｒ２とが形成されている。 The thin film device 100 includes a substrate 1 such as a glass substrate, a ceramic substrate, a resin substrate, a Si substrate, and a GaAs substrate, a plurality of resin layers 2, 3 and 4 laminated on one main surface 1a side of the substrate 1, and a substrate 1. One variable-capacity thin-film capacitor element C provided on one main surface 1a and thin-film resistance elements R1 and R2, and a plurality of resin layers 2, 3 and 4 are laminated on the substrate 1. The thin film capacitor element C and the thin film resistance elements R1 and R2 are formed in the laminate.

薄膜キャパシタ素子Ｃは、基板１の一方主面１ａ上の所定領域にＰｔ薄膜により形成されたキャパシタ電極層５（本発明の「電極膜」に相当）と、（Ｂａ，Ｓｒ）ＴｉＯ３（以下「ＢＳＴ」と称する）誘電体層６（本発明の「誘電体薄膜」に相当）と、ＢＳＴ誘電体層６上にＰｔ薄膜により形成されたキャパシタ電極層７（本発明の「電極膜」に相当）とにより形成される。なお、この実施形態では、薄膜キャパシタ素子Ｃ（誘電体層６）がＢＳＴのセラミックで形成されており、抵抗温度係数が−１５４００ｐｐｍ／℃を有する。また、ＢＳＴで形成された誘電体層６は、直流バイアス電圧により容量が変化する特性を有することから、可変コンデンサとして機能する。 The thin film capacitor element C includes a capacitor electrode layer 5 (corresponding to the "electrode film" of the present invention) formed of a Pt thin film in a predetermined region on one main surface 1a of the substrate 1, and (Ba, Sr) TiO3 (hereinafter, "" A dielectric layer 6 (corresponding to the "dielectric thin film" of the present invention) (referred to as "BST") and a capacitor electrode layer 7 (corresponding to the "electrode film" of the present invention) formed of a Pt thin film on the BST dielectric layer 6 ) And. In this embodiment, the thin film capacitor element C (dielectric layer 6) is made of BST ceramic and has a temperature coefficient of resistance of -15400 ppm / ° C. Further, since the dielectric layer 6 formed by BST has a characteristic that the capacitance changes depending on the DC bias voltage, it functions as a variable capacitor.

また、薄膜キャパシタ素子Ｃは、ＳｉＯ２耐湿保護膜により形成された保護層８により被覆され、保護層８上に樹脂層２が積層されている。樹脂層２の一方主面２ａには、保護層８および樹脂層２に形成された透孔を介して薄膜キャパシタ素子Ｃの上側のキャパシタ電極層７に接続されたＣｕ／Ｔｉ引出電極９と、薄膜キャパシタ素子Ｃの下側のキャパシタ電極層５に接続されたＣｕ／Ｔｉ引出電極１０と、第２の金属薄膜１１ａ，１１ｂとが形成されている。 Further, the thin film capacitor element C is covered with a protective layer 8 formed of a SiO2 moisture-resistant protective film, and a resin layer 2 is laminated on the protective layer 8. On one main surface 2a of the resin layer 2, a Cu / Ti extraction electrode 9 connected to the upper capacitor electrode layer 7 of the thin film capacitor element C via a through hole formed in the protective layer 8 and the resin layer 2 and The Cu / Ti extraction electrode 10 connected to the capacitor electrode layer 5 on the lower side of the thin film capacitor element C and the second metal thin films 11a and 11b are formed.

第２の金属薄膜１１ａ，１１ｂは、それぞれ、同一の薄膜形成プロセスにより同一の材料を用いて引出電極９，１０と同時に形成されている。また、樹脂層２の一方主面２ａには、引出電極９，１０および第２の金属薄膜１１ａ，１１ｂを被覆する樹脂層３が積層されている。なお、この実施形態では、第２の金属薄膜１１ａ，１１ｂと引出電極９，１０とが一体形成されているが、第２の金属薄膜１１ａ，１１ｂと引出電極９，１０とが分離して形成されていてもよいし、第２の金属薄膜１１ａ，１１ｂが樹脂層２の一方主面２ａに形成された他の引出電極と一体形成されていてもよい。 The second metal thin films 11a and 11b are formed at the same time as the extraction electrodes 9 and 10, respectively, by the same thin film forming process using the same material. Further, a resin layer 3 covering the extraction electrodes 9 and 10 and the second metal thin films 11a and 11b is laminated on one main surface 2a of the resin layer 2. In this embodiment, the second metal thin films 11a and 11b and the extraction electrodes 9 and 10 are integrally formed, but the second metal thin films 11a and 11b and the extraction electrodes 9 and 10 are formed separately. The second metal thin films 11a and 11b may be integrally formed with the other extraction electrode formed on one main surface 2a of the resin layer 2.

各薄膜抵抗素子Ｒ１，Ｒ２は、それぞれ、樹脂層３の一方主面３ａの所定領域に薄膜形成プロセスにより形成されたＮｉ、Ｃｒ、Ｓｉを主成分とする抵抗薄膜１２と、それぞれ抵抗薄膜１２上に形成された第１、第２の補強用薄膜１２ａ，１２ｂおよび接続電極１２ｃ，１２ｄとを備えている。第１、第２の補強用薄膜１２ａ，１２ｂおよび接続電極１２ｃ，１２ｄは、それぞれ、Ｎｉを主成分としてＣｒを含む同一の材料を用いて同一の薄膜形成プロセスにより、分離配置された状態で形成されている。 Each of the thin film resistance elements R1 and R2 is formed on a resistance thin film 12 containing Ni, Cr, and Si as main components formed in a predetermined region of one main surface 3a of the resin layer 3 by a thin film formation process, and on the resistance thin film 12, respectively. The first and second reinforcing thin films 12a and 12b and the connection electrodes 12c and 12d formed in the above are provided. The first and second reinforcing thin films 12a and 12b and the connection electrodes 12c and 12d are respectively formed in a separated state by the same thin film forming process using the same material containing Cr as the main component of Ni. Has been done.

ここで、抵抗薄膜１２を形成する材料は、Ｎｉ、Ｃｒ、Ｓｉを含有する。なお、この実施形態では、抵抗薄膜１２は、Ｎｉが１０ｗｔ％、Ｃｒが２０ｗｔ％、Ｓｉが７０ｗｔ％で形成されており、電気抵抗率（比抵抗）が１５０００μΩｃｍ、抵抗温度係数が−３８５０ｐｐｍ／℃である。この構成によれば、各薄膜抵抗素子Ｒ１，Ｒ２を共に１００ｋΩの抵抗で作製するのに、それぞれ配線長が０．４ｍｍあればよく、基板１の一方主面１ａが０．２５ｍｍ２以下であっても、ミアンダ形状にすることにより同一面上に配置することができる。なお、基板１の一方主面１ａが０．２５ｍｍ２以下の場合に、例えば、特許文献１のように９個以上の薄膜抵抗素子を同一面上に設けようとすると、１個の薄膜抵抗素子の長さは０．４ｍｍ以下が望ましく、各薄膜抵抗素子の膜厚を０．１μｍ、ライン幅を４μｍ、隣接するパターン間のギャップを４μｍ確保した場合、各薄膜抵抗素子を共に１００ｋΩにするには、比抵抗が１００００μΩｃｍ以上であることが望ましい。また、この実施形態では、抵抗薄膜１２の抵抗温度係数（−３８５０ｐｐｍ／℃）の絶対値は、誘電体層６の抵抗温度係数（−１５４００ｐｐｍ／℃）の絶対値よりも小さい材料で形成される。なお、薄膜抵抗素子Ｒ１，Ｒ２を形成する材料は、上記したものに限らず、比抵抗が１００００μΩｃｍ以上であって、抵抗温度係数の絶対値が、薄膜キャパシタ素子Ｃの抵抗温度係数の絶対値よりも小さいものであれば、Ｎｉ−Ｃｒ−Ｓｉ系の重量比率を変えてもよいし、他の材料で形成してもよい。なお、Ｎｉ−Ｃｒ−Ｓｉ系の重量比率は、Siが５０ｗｔ％以上９０ｗｔ％以下の範囲で、比抵抗とキャパシタに対する抵抗温度特性の関係を満足するよう決定され、本実施形態で示した重量比率以外にも、種々の重量比率とすることができる。 Here, the material forming the resistance thin film 12 contains Ni, Cr, and Si. In this embodiment, the resistance thin film 12 is formed of 10 wt% Ni, 20 wt% Cr, and 70 wt% Si, has an electrical resistivity (specific resistance) of 15,000 μΩcm, and a temperature coefficient of resistance of −3850 ppm / ° C. Is. According to this configuration, in order to manufacture each of the thin film resistance elements R1 and R2 with a resistance of 100 kΩ, the wiring length may be 0.4 mm, and one main surface 1a of the substrate 1 is 0.25 mm2 or less. Can be arranged on the same surface by forming a mianda shape. When one main surface 1a of the substrate 1 is 0.25 mm2 or less, for example, if nine or more thin film resistance elements are provided on the same surface as in Patent Document 1, one thin film resistance element can be provided. The length is preferably 0.4 mm or less, and when the film thickness of each thin film resistance element is 0.1 μm, the line width is 4 μm, and the gap between adjacent patterns is 4 μm, it is necessary to make each thin film resistance element 100 kΩ. It is desirable that the specific resistance is 10,000 μΩcm or more. Further, in this embodiment, the absolute value of the temperature coefficient of resistance (-3850 ppm / ° C.) of the resistance thin film 12 is formed of a material smaller than the absolute value of the temperature coefficient of resistance (-15400 ppm / ° C.) of the dielectric layer 6. .. The materials forming the thin film resistance elements R1 and R2 are not limited to those described above, and the specific resistance is 10,000 μΩcm or more, and the absolute value of the temperature coefficient of resistance is higher than the absolute value of the temperature coefficient of resistance of the thin film capacitor element C. As long as it is small, the weight ratio of the Ni—Cr—Si system may be changed, or it may be formed of another material. The weight ratio of the Ni—Cr—Si system was determined so as to satisfy the relationship between the specific resistance and the resistance temperature characteristic with respect to the capacitor in the range of 50 wt% or more and 90 wt% or less of Si, and the weight ratio shown in the present embodiment. In addition, various weight ratios can be used.

また、各薄膜抵抗素子Ｒ１，Ｒ２（抵抗薄膜１２）は、樹脂層３の一方主面３ａ上に積層された樹脂層４により被覆されている。樹脂層４の一方主面４ａには、樹脂層３，４に形成された透孔を介して引出電極９，１０や薄膜抵抗素子Ｒ１，Ｒ２の接続電極１２ｃ，１２ｄに電気的に接続されたＣｕ／Ｔｉ引出電極１３，１４と、第１の金属薄膜１５ａ，１５ｂ，１５ｃとが形成されている。第１の金属薄膜１５ａ〜１５ｃそれぞれは、同一の薄膜形成プロセスにより同一の材料を用いて引出電極１３，１４と同時に形成されている。なお、第１の金属薄膜１５ｃが、それぞれ引出電極１３，１４と一体形成された第１の金属薄膜１５ａ，１５ｂと分離した状態で形成されているが、第１の金属薄膜１５ｃが、第１の金属薄膜１５ａ，１５ｂや他の引出電極と一体形成されていてもよい。 Further, each thin film resistance element R1 and R2 (resistance thin film 12) is covered with a resin layer 4 laminated on one main surface 3a of the resin layer 3. One main surface 4a of the resin layer 4 was electrically connected to the extraction electrodes 9 and 10 and the connection electrodes 12c and 12d of the thin film resistance elements R1 and R2 via the through holes formed in the resin layers 3 and 4. The Cu / Ti extraction electrodes 13 and 14 and the first metal thin films 15a, 15b and 15c are formed. Each of the first metal thin films 15a to 15c is formed at the same time as the extraction electrodes 13 and 14 by the same thin film forming process using the same material. The first metal thin film 15c is formed in a state of being separated from the first metal thin films 15a and 15b integrally formed with the extraction electrodes 13 and 14, respectively, but the first metal thin film 15c is the first. The metal thin films 15a and 15b of the above and other extraction electrodes may be integrally formed.

また、図１に示すように、抵抗薄膜１２のうち、樹脂層３の基板１と反対側に配置された樹脂層４の第１の金属薄膜１５ａ〜１５ｃと平面視で重ならない部分に、第１の補強用薄膜１２ａが配置され、抵抗薄膜１２のうち、樹脂層３の基板１側に配置された樹脂層２の第２の金属薄膜１１ａ，１１ｂと平面視で重ならない部分に、第２の補強用薄膜１２ｂが配置されている。なお、第１、第２の金属薄膜１１ａ，１１ｂ，１５ａ〜１５ｃと抵抗薄膜１２との平面視における境界部分に重なるように、第１、第２の補強用薄膜１２ａ，１２ｂが配置されるようにするとよい。さらに、境界部分には応力が集中しやすいため、補強用薄膜１２ａ，１２ｂが境界部分に重なるように配置されることで、薄膜抵抗素子に加わる曲げ応力等を好適に緩和できる。 Further, as shown in FIG. 1, a portion of the resistance thin film 12 that does not overlap with the first metal thin films 15a to 15c of the resin layer 4 arranged on the opposite side of the resin layer 3 from the substrate 1 in a plan view is formed. The reinforcing thin film 12a of 1 is arranged, and the second metal thin film 12a of the resistance thin film 12 does not overlap with the second metal thin films 11a and 11b of the resin layer 2 arranged on the substrate 1 side of the resin layer 3 in a plan view. The reinforcing thin film 12b of the above is arranged. The first and second reinforcing thin films 12a and 12b are arranged so as to overlap the boundary portion between the first and second metal thin films 11a, 11b, 15a to 15c and the resistance thin film 12 in a plan view. It is good to set it to. Further, since stress tends to be concentrated on the boundary portion, the bending stress applied to the thin film resistance element can be suitably relaxed by arranging the reinforcing thin films 12a and 12b so as to overlap the boundary portion.

また、引出電極１３，１４に接続された第１の金属薄膜１５ａ，１５ｂ上に複数のＡｕ／Ｎｉ外部電極１６が形成され、引出電極１３，１４および第１の金属薄膜１５ａ，１５ｂと、各外部電極１６それぞれの端縁部分とを被覆するように樹脂により形成された保護層１７が樹脂層４の一方主面４ａ上に積層されている。 Further, a plurality of Au / Ni external electrodes 16 are formed on the first metal thin films 15a and 15b connected to the extraction electrodes 13 and 14, and the extraction electrodes 13 and 14 and the first metal thin films 15a and 15b, respectively. A protective layer 17 formed of resin so as to cover the edge portions of each of the external electrodes 16 is laminated on one main surface 4a of the resin layer 4.

以上のように構成された薄膜デバイス１００は、図２に示すように、それぞれ外部電極１６により形成された第１〜第４外部電極Ｐ１〜Ｐ４を有し、第１、第２外部電極Ｐ１，Ｐ２間に薄膜キャパシタ素子Ｃが直列接続されている。また、一端が第３外部電極Ｐ３に接続された第１の薄膜抵抗素子Ｒ１の他端と、一端が第４外部電極Ｐ４に接続された第２の薄膜抵抗素子Ｒ２の他端との間に薄膜キャパシタ素子Ｃが挿入されるように、各第１の薄膜抵抗素子Ｒ１それぞれの他端および各第２の薄膜抵抗素子Ｒ２それぞれの他端が各薄膜キャパシタ素子Ｃそれぞれの両端に接続されている。また、第１外部電極Ｐ１と第２外部電極Ｐ２とを結ぶラインは、高周波信号が伝送される高周波信号ラインＳＬ（図２の一点鎖線）が形成される。一方、第３外部電極Ｐ３と、第４外部電極Ｐ４との間には、直流バイアス電圧が印加される、バイアス電圧印加ラインＢＬ（図２の二点鎖線）が形成される。この場合、バイアス電圧印加ラインＢＬ上に、第１の薄膜抵抗素子Ｒ１、薄膜キャパシタ素子Ｃ、第２の薄膜抵抗素子Ｒ２が直列に接続されることになる。 As shown in FIG. 2, the thin film device 100 configured as described above has the first to fourth external electrodes P1 to P4 formed by the external electrodes 16, respectively, and the first and second external electrodes P1 and A thin film capacitor element C is connected in series between P2. Further, between the other end of the first thin film resistance element R1 whose one end is connected to the third external electrode P3 and the other end of the second thin film resistance element R2 whose one end is connected to the fourth external electrode P4. The other ends of each of the first thin film resistance elements R1 and the other ends of each of the second thin film resistance elements R2 are connected to both ends of each of the thin film capacitor elements C so that the thin film capacitor element C is inserted. .. Further, in the line connecting the first external electrode P1 and the second external electrode P2, a high frequency signal line SL (one-dot chain line in FIG. 2) through which a high frequency signal is transmitted is formed. On the other hand, a bias voltage application line BL (two-dot chain line in FIG. 2) to which a DC bias voltage is applied is formed between the third external electrode P3 and the fourth external electrode P4. In this case, the first thin film resistance element R1, the thin film capacitor element C, and the second thin film resistance element R2 are connected in series on the bias voltage application line BL.

次に、図３〜図５を参照して、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２の抵抗温度係数と、従来の薄膜抵抗素子の抵抗温度係数の比較と、薄膜抵抗素子Ｒ１，Ｒ２を用いた場合において、印加する直流バイアス電圧に対して薄膜キャパシタ素子Ｃに印加される電圧の比率と、従来の薄膜抵抗素子を用いた場合において、印加する直流バイアス電圧に対して薄膜キャパシタ素子Ｃに印加される電圧の比率を比較する。 Next, with reference to FIGS. 3 to 5, the resistance temperature coefficient of the thin film resistance elements R1 and R2 of the present embodiment is compared with the resistance temperature coefficient of the conventional thin film resistance element, and the thin film resistance elements R1 and R2 are used. If so, the ratio of the voltage applied to the thin film capacitor element C to the applied DC bias voltage and the applied DC bias voltage to the thin film capacitor element C when the conventional thin film resistance element is used. Compare the ratio of voltages to be made.

図３に示すように、本実施形態の薄膜キャパシタ素子Ｃ（ＢＳＴ誘電体層６）の抵抗温度係数は、−１５４００ｐｐｍ／℃であり、比抵抗が１００００μΩｃｍ以上の従来の薄膜抵抗素子の一例として、Ｓｉを主成分とする材料を用いた場合の抵抗温度係数は、−１６０００ｐｐｍ／℃である。つまり、比抵抗が高い従来の薄膜抵抗素子の抵抗温度係数は、薄膜キャパシタ素子Ｃの抵抗温度係数と同じ負の値を示すが、その絶対値は従来の薄膜抵抗素子の方が大きい。これに対して、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２の抵抗温度係数は、それぞれ−３８５０ｐｐｍ／℃であり、薄膜キャパシタ素子Ｃの抵抗温度係数と同じ負の値を示すとともに、その絶対値は薄膜抵抗素子Ｒ１，Ｒ２の方が小さい。 As shown in FIG. 3, the temperature coefficient of resistance of the thin film capacitor element C (BST dielectric layer 6) of the present embodiment is -15400 ppm / ° C., and as an example of a conventional thin film resistance element having a specific resistance of 10000 μΩcm or more, The temperature coefficient of resistance when a material containing Si as a main component is used is -16000 ppm / ° C. That is, the resistance temperature coefficient of the conventional thin film resistance element having a high specific resistance shows the same negative value as the resistance temperature coefficient of the thin film capacitor element C, but the absolute value is larger in the conventional thin film resistance element. On the other hand, the temperature coefficient of resistance of the thin film resistance elements R1 and R2 of the present embodiment is −3850 ppm / ° C., which is the same negative value as the temperature coefficient of resistance of the thin film capacitor element C, and its absolute value is The thin film resistance elements R1 and R2 are smaller.

ここで、直流バイアス電圧の印加による薄膜キャパシタ素子Ｃの容量変化特性を向上するためには、薄膜キャパシタ素子Ｃ（ＢＳＴ誘電体層６）の厚みを薄くして直流バイアス電圧の電界強度を高くするのが好ましいが、ＢＳＴ誘電体層６の厚みを薄くすると、薄膜キャパシタ素子Ｃの絶縁抵抗が低下する。そこで、薄膜抵抗素子Ｒ１，Ｒ２よりも十分高い絶縁抵抗を確保できる膜厚で形成した、高抵抗側の薄膜キャパシタ素子Ｃ（ＢＳＴ誘電体層６）と、優れた容量変化特性を得るために膜厚を薄くした低抵抗側の薄膜キャパシタ素子Ｃ（ＢＳＴ誘電体層６）とを準備して、それぞれ従来の薄膜抵抗素子を用いた場合に薄膜キャパシタ素子Ｃに印加される直流バイアス電圧の比率と、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２を用いた場合に薄膜キャパシタ素子Ｃに印加される直流バイアス電圧の比率とを図３に示す。 Here, in order to improve the capacitance change characteristic of the thin film capacitor element C by applying the DC bias voltage, the thickness of the thin film capacitor element C (BST dielectric layer 6) is reduced to increase the electric field strength of the DC bias voltage. However, if the thickness of the BST dielectric layer 6 is reduced, the insulation resistance of the thin film capacitor element C is lowered. Therefore, a thin film capacitor element C (BST dielectric layer 6) on the high resistance side, which is formed with a film thickness capable of ensuring a sufficiently higher insulation resistance than the thin film resistance elements R1 and R2, and a film for obtaining excellent capacitance change characteristics. The ratio of the DC bias voltage applied to the thin film capacitor element C when the thin film capacitor element C (BST dielectric layer 6) on the low resistance side with a reduced thickness is prepared and the conventional thin film capacitor element is used, respectively. FIG. 3 shows the ratio of the DC bias voltage applied to the thin film capacitor element C when the thin film resistance elements R1 and R2 of the present embodiment are used.

なお、薄膜デバイス１００の使用温度範囲は、−２５℃〜８５℃であり、好適には２５℃〜８５℃である。ここで、好適な使用温度範囲において、高抵抗側の薄膜キャパシタ素子Ｃは、２５℃で３００ＭΩ、８５℃で３０ＭΩであり、低抵抗側の薄膜キャパシタ素子Ｃは、２５℃で３０ＭΩ、８５℃で３ＭΩである。また、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２の２５℃での合成抵抗値は２００ｋΩ、８５℃での合成抵抗値は１５３ｋΩである。なお、この実施形態では、薄膜抵抗素子Ｒ１，Ｒ２の２５℃での合成抵抗値が、使用上限温度８５℃で抵抗素子の機能として必要な抵抗値１５０ｋΩ程度となるように設計している。 The operating temperature range of the thin film device 100 is −25 ° C. to 85 ° C., preferably 25 ° C. to 85 ° C. Here, in a suitable operating temperature range, the thin film capacitor element C on the high resistance side is 300 MΩ at 25 ° C. and 30 MΩ at 85 ° C., and the thin film capacitor element C on the low resistance side is 30 MΩ at 25 ° C. and 85 ° C. It is 3 MΩ. Further, the combined resistance values of the thin film resistance elements R1 and R2 of the present embodiment at 25 ° C. are 200 kΩ, and the combined resistance values at 85 ° C. are 153 kΩ. In this embodiment, the combined resistance values of the thin film resistance elements R1 and R2 at 25 ° C. are designed to be about 150 kΩ, which is a resistance value required for the function of the resistance element at the upper limit temperature of 85 ° C.

ここで、バイアス電圧印加ラインＢＬに印加する直流バイアス電圧に対して薄膜キャパシタＣに印加される直流バイアス電圧の割合（バイアス電圧比率）が９５％以上である場合は、所望の容量変化特性を十分に満たすとし、少なくとも９０％以上であることが好ましい。まず、高抵抗側の薄膜キャパシタ素子Ｃの場合について説明する。この場合、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２および従来のＳｉ系の薄膜抵抗素子のいずれを用いた場合であっても、使用温度範囲の全てで９５％を超える値を示しており、十分な容量変化特性が得られている。これは、従来の薄膜抵抗素子の抵抗温度係数（−１６０００ｐｐｍ／℃）の絶対値が、薄膜キャパシタ素子Ｃの抵抗温度係数（−１５４００ｐｐｍ／℃）の絶対値よりも大きい値であっても、薄膜キャパシタ素子Ｃの絶縁抵抗値が、薄膜抵抗素子の抵抗値に対して十分に大きいためである。すなわち、薄膜キャパシタ素子Ｃと薄膜抵抗素子Ｒ１，Ｒ２とが直列に接続されているときに、両端に直流バイアス電圧を印加した場合は、薄膜抵抗素子にかかる電圧（抵抗側分圧）と、薄膜キャパシタ素子にかかる電圧（キャパシタ側分圧）の比は、それぞれの抵抗値の比と同じとなる。したがって、薄膜キャパシタ素子の絶縁抵抗をＲｘとし、薄膜抵抗素子の合成抵抗をＲｙとした場合、バイアス電圧比率＝Ｒｘ／（Ｒｘ＋Ｒｙ）×１００[％]となる。ここで、薄膜キャパシタ素子Ｃと従来の薄膜抵抗素子は、共に負の抵抗温度係数を有するが、絶対値が従来の薄膜抵抗素子の方が大きいため、低温になるにつれて薄膜キャパシタ素子の絶縁抵抗値と従来の薄膜抵抗素子の抵抗値の差が小さくなる（図５参照）。したがって、バイアス電圧比率は、低温になるにつれて低くなるものの、薄膜キャパシタ素子の絶縁抵抗Ｒｘが、薄膜抵抗素子の合成抵抗Ｒｙよりも十分大きいため、使用温度範囲の全てで９５％を超える値を示す。一方、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２は、負の抵抗温度係数を有し、かつ、絶対値が薄膜キャパシタ素子Ｃの抵抗温度係数の絶対値よりも小さいため、低温になるにつれて、薄膜キャパシタ素子の絶縁抵抗値と、薄膜抵抗素子Ｒ１，Ｒ２の合成抵抗値の差が大きくなる。したがって、バイアス電圧比率は、低温になるにつれて高くなるものの、薄膜キャパシタ素子Ｃの絶縁抵抗Ｒｘが、薄膜抵抗素子Ｒ１，Ｒ２の合成抵抗Ｒｙよりも十分大きいため、使用温度範囲の全てで９５％を超える値を示す。 Here, when the ratio of the DC bias voltage applied to the thin film capacitor C (bias voltage ratio) to the DC bias voltage applied to the bias voltage application line BL is 95% or more, the desired capacitance change characteristic is sufficiently obtained. It is preferable that the content is at least 90% or more. First, the case of the thin film capacitor element C on the high resistance side will be described. In this case, regardless of which of the thin film resistance elements R1 and R2 of the present embodiment and the conventional Si-based thin film resistance element is used, the value exceeds 95% in the entire operating temperature range, which is sufficient. Excellent capacitance change characteristics have been obtained. This is because even if the absolute value of the temperature coefficient of resistance (-16000 ppm / ° C.) of the conventional thin film resistance element is larger than the absolute value of the temperature coefficient of resistance (-15400 ppm / ° C.) of the thin film capacitor element C, the thin film is formed. This is because the insulation resistance value of the capacitor element C is sufficiently larger than the resistance value of the thin film resistance element. That is, when the thin film capacitor element C and the thin film resistance elements R1 and R2 are connected in series and a DC bias voltage is applied to both ends, the voltage applied to the thin film resistance element (voltage division on the resistance side) and the thin film The ratio of the voltage applied to the capacitor element (voltage division on the capacitor side) is the same as the ratio of each resistance value. Therefore, when the insulation resistance of the thin film capacitor element is Rx and the combined resistance of the thin film resistance element is Ry, the bias voltage ratio = Rx / (Rx + Ry) × 100 [%]. Here, both the thin film capacitor element C and the conventional thin film resistance element have a negative temperature coefficient of resistance, but since the absolute value of the conventional thin film resistance element is larger, the insulation resistance value of the thin film capacitor element increases as the temperature becomes lower. The difference between the resistance value of the conventional thin film resistance element and the resistance value of the conventional thin film resistance element becomes small (see FIG. 5). Therefore, although the bias voltage ratio decreases as the temperature decreases, the insulation resistance Rx of the thin film capacitor element is sufficiently larger than the combined resistance Ry of the thin film resistance element, so that the value exceeds 95% in the entire operating temperature range. .. On the other hand, since the thin film resistance elements R1 and R2 of the present embodiment have a negative temperature coefficient of resistance and the absolute value is smaller than the absolute value of the temperature coefficient of resistance of the thin film capacitor element C, the film becomes thinner as the temperature becomes lower. The difference between the insulation resistance value of the capacitor element and the combined resistance value of the thin film resistance elements R1 and R2 becomes large. Therefore, although the bias voltage ratio increases as the temperature decreases, the insulation resistance Rx of the thin film capacitor element C is sufficiently larger than the combined resistance Ry of the thin film resistance elements R1 and R2, so that 95% is set in the entire operating temperature range. Indicates a value that exceeds.

次に、低抵抗側の薄膜キャパシタ素子Ｃの場合について説明する。この場合、従来のＳｉ系の薄膜抵抗素子を用いた場合において、使用温度範囲内で低温側になるにつれてバイアス電圧比率が低くなるのは同じである。しかしながら、使用温度の上限（８５℃）ではバイアス電圧比率が９５％を超える値を確保することができるものの、使用温度の下限（２５℃）ではバイアス電圧比率が８８．７％となり、所望の容量変化特性が得られないことが分かる。これは、従来の薄膜抵抗素子の抵抗温度係数の絶対値が、薄膜キャパシタ素子Ｃの抵抗温度係数の絶対値よりも大きいことに加え、薄膜キャパシタ素子Ｃの絶縁抵抗値が従来の薄膜抵抗素子の抵抗値に対して十分に大きくないことから、使用温度の低温側の薄膜抵抗素子の抵抗値の高まりが、バイアス電圧比率に影響したためである。一方、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２の場合、使用温度範囲の全てで９５％を超える値を示す。これは、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２の抵抗温度係数の絶対値が、薄膜キャパシタ素子Ｃの抵抗温度係数の絶対値よりも小さいことにより、従来の薄膜抵抗素子（Ｓｉ系）の場合に問題となる使用温度範囲の低温側において、９５％以上のバイアス電圧比率を確保できたためと考えられる。 Next, the case of the thin film capacitor element C on the low resistance side will be described. In this case, when a conventional Si-based thin film resistance element is used, the bias voltage ratio becomes lower as the temperature becomes lower within the operating temperature range. However, although the bias voltage ratio can be secured to exceed 95% at the upper limit of the operating temperature (85 ° C.), the bias voltage ratio becomes 88.7% at the lower limit of the operating temperature (25 ° C.), which is a desired capacity. It can be seen that the change characteristics cannot be obtained. This is because the absolute value of the resistance temperature coefficient of the conventional thin film resistance element is larger than the absolute value of the resistance temperature coefficient of the thin film capacitor element C, and the insulation resistance value of the thin film capacitor element C is that of the conventional thin film resistance element. This is because the increase in the resistance value of the thin film resistance element on the low temperature side of the operating temperature affected the bias voltage ratio because it was not sufficiently large with respect to the resistance value. On the other hand, in the case of the thin film resistance elements R1 and R2 of the present embodiment, the values exceed 95% in the entire operating temperature range. This is because the absolute value of the temperature coefficient of resistance of the thin film resistance elements R1 and R2 of the present embodiment is smaller than the absolute value of the temperature coefficient of resistance of the thin film capacitor element C, which is the case of the conventional thin film resistance element (Si system). It is considered that the bias voltage ratio of 95% or more could be secured on the low temperature side of the operating temperature range, which is a problem.

なお、このような構成の場合、使用温度の下限（２５℃）でバイアス電圧比率が９５％を超えていれば、全ての使用温度範囲でバイアス電圧比率が９５％以上を確保できると考えられることから、２５℃の環境下において、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２を用いた場合の薄膜キャパシタ素子Ｃの絶縁抵抗とバイアス電圧比率との関係、並びに、２５℃の環境下において、従来の薄膜抵抗素子を用いた場合の薄膜キャパシタ素子Ｃの絶縁抵抗とバイアス電圧比率との関係を図４に示す。 In the case of such a configuration, if the bias voltage ratio exceeds 95% at the lower limit of the operating temperature (25 ° C.), it is considered that the bias voltage ratio can be secured at 95% or more in the entire operating temperature range. Therefore, the relationship between the insulation resistance of the thin film capacitor element C and the bias voltage ratio when the thin film resistance elements R1 and R2 of the present embodiment are used in an environment of 25 ° C., and the conventional relationship in an environment of 25 ° C. FIG. 4 shows the relationship between the insulation resistance of the thin film capacitor element C and the bias voltage ratio when the thin film resistance element is used.

この場合、薄膜キャパシタ素子Ｃの絶縁抵抗値が５０ＭΩを超える場合は、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２および従来の薄膜抵抗素子の両方で、９０％以上のバイアス電圧比率を確保することができるが、薄膜キャパシタ素子Ｃの絶縁抵抗値が５０ＭΩ以下の場合は、従来の薄膜抵抗素子の場合はバイアス電圧比率が９０％を下回って所望の容量変化特性を得ることができないが、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２の場合は、バイアス電圧比率が９５％以上を確保することができているのが分かる。以上のように、本実施形態の薄膜抵抗素子Ｒ１，Ｒ２を用いた場合は、薄膜キャパシタ素子Ｃの厚みを薄くして絶縁抵抗値が５０ＭΩよりも低くなった場合でも、直流バイアス電圧を十分に薄膜キャパシタＣに印加することができ、優れた容量変化特性が得られる。 In this case, when the insulation resistance value of the thin film capacitor element C exceeds 50 MΩ, it is possible to secure a bias voltage ratio of 90% or more in both the thin film resistance elements R1 and R2 of the present embodiment and the conventional thin film resistance element. However, when the insulation resistance value of the thin film capacitor element C is 50 MΩ or less, the bias voltage ratio is less than 90% in the case of the conventional thin film resistance element, and the desired capacitance change characteristic cannot be obtained. In the case of the thin film resistance elements R1 and R2, it can be seen that the bias voltage ratio can be secured at 95% or more. As described above, when the thin film resistance elements R1 and R2 of the present embodiment are used, the DC bias voltage is sufficiently set even when the thickness of the thin film capacitor element C is reduced and the insulation resistance value becomes lower than 50 MΩ. It can be applied to the thin film capacitor C, and excellent capacitance change characteristics can be obtained.

（製造方法）
薄膜デバイス１００の製造方法の一例について説明する。なお、この実施形態では、大面積の基板１が用いられて複数の薄膜デバイス１００の集合体が形成された後に個片化されることにより、複数の薄膜デバイス１００が同時に形成される。 (Production method)
An example of a method for manufacturing the thin film device 100 will be described. In this embodiment, the plurality of thin film devices 100 are formed at the same time by using the large-area substrate 1 to form an aggregate of the plurality of thin film devices 100 and then disassembling them.

まず、例えばＳｉにより形成された基板１上の所定領域にスパッタにより下側のＰｔキャパシタ電極層５を形成し、溶液塗布法によりＢＳＴ誘電体層６を形成する。なお、ＢＳＴ誘電体層６の成膜方法の他の例としては、スパッタ法やＣＶＤ法を用いることができる。ＢＳＴ誘電体層６の成膜後は、スパッタにより上側のＰｔキャパシタ電極層７を形成し、ドライエッチングにより、所望の容量にするためのＢＳＴ誘電体層６および上側のＰｔキャパシタ電極層７のパターンニングおよび下側のＰｔキャパシタ電極層５と導通用のビアホールを形成する。その際、エッチングしない部分はレジスト膜で保護する。 First, for example, a lower Pt capacitor electrode layer 5 is formed by sputtering in a predetermined region on a substrate 1 formed of Si, and a BST dielectric layer 6 is formed by a solution coating method. As another example of the film forming method of the BST dielectric layer 6, a sputtering method or a CVD method can be used. After the formation of the BST dielectric layer 6, the upper Pt capacitor electrode layer 7 is formed by sputtering, and the pattern of the BST dielectric layer 6 and the upper Pt capacitor electrode layer 7 for achieving a desired capacity by dry etching. A via hole for conduction is formed with the ning and the lower Pt capacitor electrode layer 5. At that time, the non-etched portion is protected by a resist film.

エッチング終了後はレジスト膜を剥離して、スパッタにより薄膜キャパシタ素子Ｃを被覆するＳｉＯ２保護層８を成膜する。ＳｉＯ２保護層８の他の成膜方法としては、ＣＶＤ法等を用いることができる。また、保護層８は、ＳｉＯ２に限らず、ＳｉＮ等の他の無機材料であってもよいし、有機絶縁材料を用いてもよい。次に、フォトリソグラフィによって透孔が形成されたフェノール系感光性樹脂絶縁膜から成る樹脂層２を形成し、樹脂層硬化のための熱処理を行う。なお、保護層８を設けずに、薄膜キャパシタ素子Ｃを被覆するように樹脂層２を形成してもよい。 After the etching is completed, the resist film is peeled off to form a SiO2 protective layer 8 that covers the thin film capacitor element C by sputtering. As another film forming method of the SiO2 protective layer 8, a CVD method or the like can be used. Further, the protective layer 8 is not limited to SiO2, and may be another inorganic material such as SiN, or an organic insulating material may be used. Next, a resin layer 2 made of a phenolic photosensitive resin insulating film having through holes formed by photolithography is formed, and a heat treatment for curing the resin layer is performed. The resin layer 2 may be formed so as to cover the thin film capacitor element C without providing the protective layer 8.

続いて、樹脂層２の透孔内のＳｉＯ２耐湿保護膜をドライエッチングにより除去し、スパッタにより、引出電極９，１０および第２の金属薄膜１１ａ，１１ｂを形成するＴｉ膜を成膜し、さらにＣｕ膜を成膜する。そして、フォトリソグラフィによるエッチングによりパターン形成し、引出電極９，１０および第２の金属薄膜１１ａ，１１ｂを形成する。次に、フォトリソグラフィによって透孔が形成されたフェノール系感光性樹脂絶縁膜から成る樹脂層３を形成し、樹脂層硬化のための熱処理を行う。 Subsequently, the SiO2 moisture-resistant protective film in the through hole of the resin layer 2 is removed by dry etching, and a Ti film forming the extraction electrodes 9 and 10 and the second metal thin films 11a and 11b is formed by sputtering, and further. A Cu film is formed. Then, a pattern is formed by etching by photolithography to form the extraction electrodes 9 and 10 and the second metal thin films 11a and 11b. Next, a resin layer 3 made of a phenolic photosensitive resin insulating film having through holes formed by photolithography is formed, and a heat treatment for curing the resin layer is performed.

次に、リフトオフレジストを形成し、Ｎｉ、Ｃｒ、Ｓｉを主成分とする混合物から成る蒸着材料を用いて、リフトオフ法により抵抗薄膜１２を蒸着形成する。このとき、抵抗薄膜１２が、Ｎｉ：１０ｗｔ％、Ｃｒ：２０ｗｔ％、Ｓｉ：７０ｗｔ％となるように調整する。続いて、リフトオフレジストを形成し、Ｎｉ、Ｃｒを主成分とする混合物から成る蒸着材料を用いて、リフトオフ法により第１、第２の補強用薄膜１２ａ，１２ｂおよび接続電極１２ｃ，１２ｄを抵抗薄膜１２上に蒸着形成する。このとき、第１、第２の補強用薄膜１２ａ，１２ｂは、それぞれ、平面視したときに、樹脂層２上の第２の金属薄膜１１ａ，１１ｂおよび後述する樹脂層４上の第１の金属薄膜１５ａ〜１５ｃの両方を形成することができない部分、または形成しない部分に重なるように配置する。 Next, a lift-off resist is formed, and the resistance thin film 12 is vapor-deposited by a lift-off method using a vapor deposition material composed of a mixture containing Ni, Cr, and Si as main components. At this time, the resistance thin film 12 is adjusted to have Ni: 10 wt%, Cr: 20 wt%, and Si: 70 wt%. Subsequently, a lift-off resist is formed, and the first and second reinforcing thin films 12a and 12b and the connection electrodes 12c and 12d are made into resistance thin films by the lift-off method using a vapor deposition material composed of a mixture containing Ni and Cr as main components. It is vapor-deposited on 12. At this time, the first and second reinforcing thin films 12a and 12b are the second metal thin films 11a and 11b on the resin layer 2 and the first metal on the resin layer 4 described later, respectively, when viewed in a plan view. Both the thin films 15a to 15c are arranged so as to overlap the portion that cannot be formed or the portion that is not formed.

続いて、フォトリソグラフィによって透孔が形成されたフェノール系感光性樹脂絶縁膜から成る樹脂層４を形成し、樹脂層硬化のための熱処理を行う。そして、スパッタにより、引出電極１３，１４および第１の金属薄膜１５ａ〜１５ｃを形成するＴｉ膜を成膜したあと、Ｃｕ膜を成膜する。 Subsequently, a resin layer 4 made of a phenolic photosensitive resin insulating film having through holes formed by photolithography is formed, and a heat treatment for curing the resin layer is performed. Then, the Ti film forming the extraction electrodes 13 and 14 and the first metal thin films 15a to 15c is formed by sputtering, and then the Cu film is formed.

次に、形成したＣｕ／Ｔｉ膜上に所定位置に開口が設けられたレジストをパターン形成して、めっき法により第１〜第４外部電極Ｐ１〜Ｐ４を成す外部電極１６をＣｕ／Ｔｉ膜上の所定位置に形成する。そして、レジストを除去した後に、フォトリソグラフィによるエッチングによりＣｕ／Ｔｉ膜をパターン形成して、引出電極１３，１４および第１の金属薄膜１５ａ〜１５ｃを形成する。 Next, a resist having openings at predetermined positions is formed on the formed Cu / Ti film, and the external electrodes 16 forming the first to fourth external electrodes P1 to P4 are formed on the Cu / Ti film by a plating method. Is formed at a predetermined position. Then, after removing the resist, a Cu / Ti film is formed by etching by photolithography to form the extraction electrodes 13 and 14 and the first metal thin films 15a to 15c.

そして、フォトリソグラフィによって外部電極露出部が形成されたフェノール系感光性樹脂絶縁膜からなる保護層１７を形成し、樹脂層硬化のための熱処理を行った後に、ダイシングにより個々の薄膜デバイス１００に個片化することによって、薄膜デバイス１００が完成する。 Then, a protective layer 17 made of a phenolic photosensitive resin insulating film on which an external electrode exposed portion is formed by photolithography is formed, heat treatment is performed for curing the resin layer, and then dicing is performed on each thin film device 100. By disintegrating, the thin film device 100 is completed.

したがって、上記した実施形態によれば、薄膜抵抗素子Ｒ１，Ｒ２の比抵抗が１００００μΩｃｍ以上という高い値であっても、抵抗温度係数の絶対値を薄膜キャパシタ素子Ｃの抵抗温度係数の絶対値よりも小さくすることにより、薄膜キャパシタ素子Ｃ（ＢＳＴ誘電体層６）の絶縁抵抗値が５０ＭΩ以下という低い値であっても、２５℃〜８５℃の使用範囲内の全てにおいて、バイアス電圧比率が９５％以上を確保することができ、所望の容量変化特性を得られることが分かった。 Therefore, according to the above-described embodiment, even if the specific resistances of the thin film resistance elements R1 and R2 are as high as 10000 μΩcm or more, the absolute value of the temperature coefficient of resistance is larger than the absolute value of the temperature coefficient of resistance of the thin film capacitor element C. By making it smaller, even if the insulation resistance value of the thin film capacitor element C (BST dielectric layer 6) is as low as 50 MΩ or less, the bias voltage ratio is 95% in all of the usage ranges of 25 ° C to 85 ° C. It was found that the above can be ensured and the desired capacitance change characteristic can be obtained.

また、薄膜抵抗素子Ｒ１，Ｒ２を形成する材料を、Ｎｉが１０ｗｔ％、Ｃｒが２０ｗｔ％、Ｓｉが７０ｗｔ％とすれば、１００００μΩｃｍ以上の比抵抗を有し、かつ、薄膜抵抗素子Ｒ１，Ｒ２の抵抗温度係数が負であって、その絶対値が薄膜キャパシタ素子Ｃの抵抗温度係数の絶対値よりも小さくする上で好適であることが分かった。 Further, if the material forming the thin film resistance elements R1 and R2 is 10 wt% for Ni, 20 wt% for Cr, and 70 wt% for Si, the film resistivity elements R1 and R2 have a specific resistance of 10,000 μΩcm or more. It was found that the resistivity temperature coefficient is negative, which is suitable for making the absolute value smaller than the absolute value of the resistivity temperature coefficient of the thin film capacitor element C.

また、薄膜キャパシタ素子Ｃと、薄膜抵抗素子Ｒ１，Ｒ２とが、同じ積層体内部に形成されるため、薄膜デバイスの小型化を図ることができる。 Further, since the thin film capacitor element C and the thin film resistance elements R1 and R2 are formed inside the same laminate, the thin film device can be miniaturized.

なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて、上記したもの以外に種々の変更を行なうことが可能であり、例えば、上記した実施形態では、薄膜キャパシタ素子Ｃが可変容量素子である場合について説明したが、直流バイアス電圧で容量が変化することを利用したものであれば、本発明を適用することができる。 The present invention is not limited to the above-described embodiment, and various modifications can be made other than the above-mentioned ones as long as the gist of the present invention is not deviated. Although the case where the capacitor element C is a variable capacitance element has been described, the present invention can be applied as long as it utilizes the fact that the capacitance changes with a DC bias voltage.

また、高周波信号ラインＳＬに複数の薄膜キャパシタ素子Ｃを直列に接続するとともに、薄膜キャパシタ素子Ｃごとに、直流バイアス電圧を印加するバイアス印加ラインＢＬを設け、各バイアス印加ラインＢＬに薄膜抵抗素子Ｒ１，Ｒ２を設ける回路構成であってもよい。 Further, a plurality of thin film capacitor elements C are connected in series to the high frequency signal line SL, and a bias application line BL for applying a DC bias voltage is provided for each thin film capacitor element C, and the thin film resistance element R1 is provided for each bias application line BL. , R2 may be provided in the circuit configuration.

また、誘電体層を形成する誘電体材料は上記した例に限定されるものではない。たとえば、ＢａＴｉＯ３、ＳｒＴｉＯ３、ＰｂＴｉＯ３などの誘電体材料により誘電体層が形成されていてもよい。 Further, the dielectric material forming the dielectric layer is not limited to the above example. For example, the dielectric layer may be formed of a dielectric material such as BaTiO3, SrTiO3, or PbTiO3.

本発明は、薄膜抵抗素子と薄膜キャパシタ素子とを備える種々の薄膜デバイスに広く適用することができる。 The present invention can be widely applied to various thin film devices including a thin film resistance element and a thin film capacitor element.

５キャパシタ電極層（電極膜）
６誘電体層６（誘電体薄膜）
７キャパシタ電極層（電極膜）
１００薄膜デバイス
Ｃ薄膜キャパシタ素子
Ｒ１，Ｒ２薄膜抵抗素子
ＳＬ高周波信号ライン
ＢＬバイアス電圧印加ライン
5 Capacitor electrode layer (electrode film)
6 Dielectric layer 6 (dielectric thin film)
7 Capacitor electrode layer (electrode film)
100 Thin film device C Thin film capacitor element R1, R2 Thin film resistance element SL High frequency signal line BL Bias voltage application line

Claims

High frequency signal line and
A thin-film capacitor element whose capacitance changes depending on the DC bias voltage inserted in the high-frequency signal line,
A bias voltage application line that applies a DC bias voltage to the thin film capacitor element,
A thin film resistance element inserted into the bias voltage application line and connected in series with the thin film capacitor element.
It is a thin film device in which a circuit having
The thin film capacitor element and the thin film resistance element are formed inside the same laminate.
The thin film capacitor element has a ceramic dielectric thin film having a negative temperature coefficient of resistance and a pair of electrode films, and has an insulation resistance value of 50 MΩ or less in the operating temperature range.
The material forming the thin film resistance elements, the electrical resistivity is not more than 10000Myuomegacm, temperature coefficient of resistance rather smaller than the absolute value of the resistance temperature coefficient of the dielectric film,
The laminate has a substrate and a plurality of resin layers laminated on one main surface of the substrate.
The thin film resistance element is formed in one of the plurality of resin layers, and a wiring electrode is formed in the resin layer different from the resin layer in which the thin film resistance element is formed.
A reinforcing thin film is formed on the thin film resistance element.
A thin film device characterized in that the reinforcing thin film is arranged so as to overlap the edge of the wiring electrode when viewed from a direction perpendicular to the one main surface of the substrate .

The thin film device according to claim 1, wherein the material forming the thin film resistance element contains Si, Ni, and Cr.