JP6773335B2 - Anomaly detector, non-volatile memory device, anomaly detection method, and anomaly detection program - Google Patents

Description

The present invention relates to an anomaly detector, a non-volatile memory device, an anomaly detection method, and an anomaly detection program.

A non-volatile memory element (NVRAM, etc.) including a volatile storage unit (SRAM, etc.) and a non-volatile storage unit (EEPROM, etc.) has high-speed processing performance by the volatile storage unit and data retention performance by the non-volatile storage unit when the power is turned off. It has both. The non-volatile memory element realizes high-speed processing performance by using a volatile storage unit in a normal state (when the power is turned on). Further, the non-volatile memory element stores data from the volatile storage unit to the non-volatile storage unit when the power is turned off, and recalls the stored data from the non-volatile storage unit to the volatile storage unit when the power is turned on. The data retention performance when the power is turned off is realized by operating in.

For example, Patent Document 1 is known as a related technique for detecting an abnormality in the operation of this non-volatile memory element. Patent Document 1 discloses a technique for detecting an abnormality in the operation of a non-volatile memory element based on the high or low potential of a capacitor connected to the non-volatile memory element.

Japanese Unexamined Patent Publication No. 2001-43146

However, the related technology has the following problems.
That is, in the above-mentioned related technique, the abnormality is detected through the capacitor connected to the non-volatile memory element without directly detecting the abnormality in the operation of the non-volatile memory element. Therefore, in the above-mentioned related technology, for example, when the abnormality of the operation of the non-volatile memory element is not reflected in the state of the capacitor, the abnormality of the operation of the non-volatile memory element cannot be detected. That is, in the above-mentioned related technology, there is a problem that an abnormality in the operation of the non-volatile memory element cannot be reliably detected.

An object of the present invention is to provide an abnormality detector, a non-volatile memory device, an abnormality detection method, and an abnormality detection program that solve the problem that an abnormality in the operation of a non-volatile memory element cannot be reliably detected in view of the above-mentioned problems. There is.

In order to solve the above problems, the first configuration of the present invention relates to an abnormality detector and is a first error detection code for data before being stored in the non-volatile storage unit from the volatile storage unit of the non-volatile memory element. And, when the second error detection code of the data after recalling the stored data from the non-volatile storage unit to the volatile storage unit does not match, the operation of the non-volatile memory element is abnormal. It is characterized by including an abnormality determination unit for determining that.

The second configuration of the present invention relates to an abnormality detection method, and comprises a first error detection code of data before being stored in the non-volatile storage unit from the volatile storage unit of the non-volatile memory element, and the data after being stored. When the second error detection code of the data after recalling the data from the non-volatile storage unit to the volatile storage unit does not match, it is determined that the operation of the non-volatile memory element is abnormal. It is supposed to be.

The third configuration of the present invention relates to the anomaly detection program and comprises the first error detection code of the data before storing the computer of the anomaly detector from the volatile storage unit of the non-volatile memory element to the non-volatile storage unit. When the second error detection code of the data after recalling the stored data from the non-volatile storage unit to the volatile storage unit does not match, the operation of the non-volatile memory element is abnormal. It is characterized in that it functions as a determination means for determining the existence.

According to the present invention, in view of the above-mentioned problems, it is possible to reliably detect an abnormality in the operation of the non-volatile memory element.

It is a block diagram which shows the structure of the non-volatile memory apparatus which comprises the abnormality detector which concerns on 1st Embodiment. It is a figure which shows the processing flow of the abnormality detector which concerns on 1st Embodiment. It is a block diagram which shows the structure of the non-volatile memory apparatus which comprises the abnormality detector which concerns on the 2nd modification of the 1st Embodiment. It is a block diagram which shows the structure of the non-volatile memory apparatus which comprises the abnormality detector which concerns on 3rd modification of 1st Embodiment. It is a block diagram which shows the structure of the non-volatile memory apparatus which comprises the abnormality detector which concerns on 2nd Embodiment. It is a figure which shows the processing flow of the abnormality detector which concerns on 2nd Embodiment. It is a figure which shows the minimum structure of the determination apparatus by one Embodiment.

<First Embodiment>
Hereinafter, the non-volatile memory device 1 and the abnormality detector 10 according to the first embodiment will be described with reference to FIGS. 1 and 2.
FIG. 1 is a configuration diagram showing a configuration of a non-volatile memory device 1 including the abnormality detector 10 according to the first embodiment. As shown in FIG. 1, the non-volatile memory device 1 includes an abnormality detector 10 and a non-volatile memory element 20. The non-volatile memory device 1 stores data from the outside in the non-volatile memory element 20 or returns the data of the non-volatile memory element 20 to the outside in response to a request from the outside.

The non-volatile memory element 20 includes a volatile storage unit 21, a non-volatile storage unit 22, and a controller 23. As a result, as will be described later, the non-volatile memory element 20 has both high-speed processing performance by the volatile storage unit 21 and data retention performance by the non-volatile storage unit 22 when the power is turned off. In the first embodiment, the case where the non-volatile memory element 20 is NVRAM (Non-Volatile Random Access Memory) will be described, but the non-volatile memory element 20 may be other than NVRAM.

The volatile storage unit 21 is a volatile storage unit in which data is not retained when the power is turned off, and high-speed processing such as data storage is possible. The volatile storage unit 21 may be, for example, an SRAM (Static Random Access Memory). The non-volatile storage unit 22 is a non-volatile storage unit that can hold data even when the power is turned off. The non-volatile storage unit 22 may be, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory).

The controller 23 stores data from the volatile storage unit 21 to the non-volatile storage unit 22 when the power supply is turned off when the supply of electric power to the non-volatile memory element 20 is cut off. Further, the controller 23 recalls the data stored when the power is turned on when the power supply to the non-volatile memory element 20 is started from the non-volatile storage unit 22 to the volatile storage unit 21. As a result, the non-volatile memory element 20 can perform processing such as data storage using the volatile storage unit 21 capable of high-speed processing when the power is turned on. Further, when the power is turned off, data can be held by using the non-volatile storage unit 22. That is, the non-volatile memory element 20 has both high-speed processing performance by the volatile storage unit 21 and data retention performance by the non-volatile storage unit 22 when the power is turned off.

The abnormality detector 10 includes a CPU (Central Processing Unit) 11 and a main memory 30.
The CPU 11 is a processor (arithmetic unit) that controls the entire operation of the abnormality detector 10. The CPU 11 realizes each function described later by reading the programs and data stored in the non-volatile memory element 20 into the main memory 30 and executing the processing.

The main memory 30 is a volatile memory used as a work area or the like of the CPU 11. As the main memory 30, for example, a RAM (Random Access Memory) is used. In the first embodiment, as shown in FIG. 1, a case where the CPU 11, the main memory 30, and the non-volatile memory element 20 are connected to the same bus will be described, but the CPU 11, the main memory 30, and the non-volatile memory will be described. The element 20 does not necessarily have to be connected to the same bus. For example, the CPU 11 and the main memory 30 may be connected to the first bus, and the CPU 11 and the non-volatile memory element 20 may be connected to a second bus different from the first bus.

In the first embodiment, the case where the programs and data required for the processing of the CPU 11 are stored in the non-volatile memory element 20 will be described, but these programs and data are acquired from other than the non-volatile memory element 20. May be good. For example, the abnormality detector 10 may include a recording medium for storing programs and data necessary for processing by the CPU 11. In this case, the CPU 11 reads the program and data stored in the recording medium into the main memory 30 and executes the process. As the recording medium, for example, an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a Flash ROM is used.

Further, for example, the abnormality detector 10 may include an application program required for processing by the CPU 11 and an interface for acquiring various data from an external device. In this case, the CPU 11 communicates with the external device via the interface, acquires the program and data, and stores them in the main memory 30.

Next, various functions of the CPU 11 according to the first embodiment will be described.
The store / recall processing unit 110 issues an instruction to the controller 23 of the non-volatile memory element 20 to store data from the volatile storage unit 21 to the non-volatile storage unit 22 at the timing when the power of the non-volatile memory element 20 is turned off. .. The timing for turning off the power of the non-volatile memory element 20 may be, for example, the timing before turning off the power of the non-volatile memory device 1.

Further, the store / recall processing unit 110 instructs the controller 23 of the non-volatile memory element 20 to recall data from the non-volatile storage unit 22 to the volatile storage unit 21 at the timing when the power of the non-volatile memory element 20 is turned on. Is issued. The timing for turning on the power of the non-volatile memory element 20 may be, for example, the timing after turning on the power of the non-volatile memory device 1.

The error detection code processing unit 120 calculates an error detection code to be used as determination information for determining whether or not the operation of the non-volatile memory element 20 is abnormal. In the first embodiment, the error detection code processing unit 120 calculates the error detection code for the data in the entire area of the volatile storage unit 21. Further, in the first embodiment, the error detection code processing unit 120 calculates the checksum value as the error detection code. Specifically, the error detection code processing unit 120 divides the data to be processed into 1 byte units, generates a plurality of 1 byte data, and calculates the lower 1 byte of the total sum of the generated 1 byte data groups as a checksum value. The error detection code processing unit 120 may calculate the checksum value by using another algorithm. Further, the error detection code processing unit 120 may calculate an error detection code other than the checksum value such as the parity value and the CRC value (cyclic redundancy code), for example.

The error detection code processing unit 120 stores in the main memory 30 the first error detection code calculated for the data before being stored in the non-volatile storage unit 22 from the volatile storage unit 21 of the non-volatile memory element 20. Further, the error detection code processing unit 120 transfers the second error detection code calculated for the data after recalling from the non-volatile storage unit 22 of the non-volatile memory element 20 to the volatile storage unit 21 to the abnormality determination unit 130 described later. input.

As will be described later with reference to FIG. 2, the abnormality determination unit 130 determines whether or not the operation of the non-volatile memory element 20 is abnormal based on the error detection code calculated by the error detection code processing unit 120. Specifically, the abnormality determination unit 130 determines whether at least one of the store and recall operations of the non-volatile memory element 20 is abnormal.

(Processing flow of anomaly detector)
FIG. 2 is a diagram showing a processing flow of the abnormality detector 10 according to the first embodiment.
Hereinafter, the processing flow of the abnormality detector 10 will be described in detail with reference to FIG.

The processing flow shown in FIG. 2 is started at a timing when the store or recall processing of the non-volatile memory element 20 is required. The timing at which the store of the non-volatile memory element 20 needs to be processed is, for example, the timing at which the power of the non-volatile memory device 1 is turned off, the timing at which the data of the volatile storage unit 21 of the non-volatile memory element 20 is updated, or the like. It may be there. The timing at which the recall process of the non-volatile memory element 20 is required is, for example, the timing at which the power supply of the non-volatile memory device 1 is supplied, or the timing at which the data in the volatile storage unit 21 of the non-volatile memory element 20 is updated. And so on.

As shown in FIG. 2, the store / recall processing unit 110 determines whether or not the store processing of the non-volatile memory element 20 is necessary (step S101). When it is necessary to process the store of the non-volatile memory element 20 (YES in step S101), the store / recall processing unit 110 instructs the error detection code processing unit 120 to calculate the first error detection code. Is issued. On the other hand, when the processing of the store of the non-volatile memory element 20 is not necessary (NO in step S101), steps S102 to S104 shown in FIG. 2 are skipped, and the processing proceeds to step S105.

Upon receiving an instruction from the store / recall processing unit 110, the error detection code processing unit 120 receives a first error detection code for the data before being stored in the non-volatile storage unit 22 from the volatile storage unit 21 of the non-volatile memory element 20. Is calculated (step S102). Next, the error detection code processing unit 120 saves the calculated first error detection code in the main memory 30 (step S103). The error detection code processing unit 120 notifies the store / recall processing unit 110 that the saving of the first error detection code is completed.

Upon receiving the notification from the error detection code processing unit 120, the store / recall processing unit 110 issues an instruction to the non-volatile memory element 20 and stores the data of the non-volatile memory element 20 (step S104). Specifically, the store / recall processing unit 110 issues an instruction to store data in the controller 23 of the non-volatile memory element 20. As a result, the controller 23 of the non-volatile memory element 20 performs a process of storing data from the volatile storage unit 21 to the non-volatile storage unit 22.

Next, as shown in FIG. 2, the store / recall processing unit 110 determines whether or not the recall processing of the non-volatile memory element 20 is necessary (step S105). When the recall processing of the non-volatile memory element 20 is required (YES in step S105), the store / recall processing unit 110 issues an instruction to the non-volatile memory element 20 to recall the data of the non-volatile memory element 20. (Step S107). Specifically, the store / recall processing unit 110 issues an instruction to the controller 23 of the non-volatile memory element 20 to recall the data. As a result, the controller 23 of the non-volatile memory element 20 performs a process of recalling data from the non-volatile storage unit 22 to the volatile storage unit 21.

On the other hand, when the recall process of the non-volatile memory element 20 is not necessary (NO in step S105), steps S107 to S111 shown in FIG. 2 are skipped, and the process proceeds to step S106. In this case, the store / recall processing unit 110 notifies the abnormality determination unit 130 that the recall processing of the non-volatile memory element 20 is not necessary. Based on this notification, the abnormality determination unit 130 determines that the operation of the non-volatile memory element 20 is normal (S106), and the processing flow ends.

After the recall process of the non-volatile memory element 20 (step S107) is completed, the controller 23 of the non-volatile memory element 20 notifies the store / recall processing unit 110 of the completion of the recall process. As a result, the store / recall processing unit 110 instructs the error detection code processing unit 120 to calculate the second error detection code. Upon receiving an instruction from the store / recall processing unit 110, the error detection code processing unit 120 receives a second error detection code for the data after recalling from the non-volatile storage unit 22 of the non-volatile memory element 20 to the volatile storage unit 21. Is calculated (step S108). The range of data for which the second error detection code is calculated in step S108 is the same as the range of data for which the first error detection code is calculated in step S102.

Next, the error detection code processing unit 120 reads out the first error detection code stored in the main memory 30 in the process of step S103 (step S109). The error detection code processing unit 120 inputs the first error detection code and the second error detection code to the abnormality determination unit 130.

The abnormality determination unit 130 receives the first error detection code of the data before being stored in the non-volatile storage unit 22 from the volatile storage unit 21 of the non-volatile memory element 20 and the data after the storage from the non-volatile storage unit 22. It is determined whether or not the second error detection code of the data after recalling to the volatile storage unit 21 does not match (step S110). When the first error detection code and the second error detection code do not match (YES in step S110), it is considered that the data before the store and the data after the recall are not the same, so that the abnormality determination unit 130 Determines that the operation of the non-volatile memory element 20 is abnormal (step S111). On the other hand, when the first error detection code and the second error detection code do not match (NO in step S110), it is considered that the data before storing and the data after recalling are the same, so that an abnormality determination is made. The unit 130 determines that the operation of the non-volatile memory element 20 is normal (step S106). As a result, the processing flow shown in FIG. 2 is completed.

(Action, effect)
As described above, the abnormality detector 10 according to the first embodiment includes the first error detection code of the data before being stored in the non-volatile storage unit 22 from the volatile storage unit 21 of the non-volatile memory element 20 and the store. When the second error detection code of the data after recalling the data after recalling from the non-volatile storage unit 22 to the volatile storage unit 21 does not match, it is determined that the operation of the non-volatile memory element 20 is abnormal. The abnormality determination unit 130 is provided.

According to the above configuration, the abnormality determination unit 130 uses the error detection code to store the data from the volatile storage unit 21 of the non-volatile memory element 20 to the non-volatile storage unit 22 and after the data is stored. Since it is directly determined whether or not the data after recalling the data from the non-volatile storage unit 22 to the volatile storage unit 21 is the same, it is certain that the operation of the non-volatile memory element 20 is abnormal. Can be detected.
As a result, for example, when an abnormality in the operation of the non-volatile memory element 20 is indirectly detected via a capacitor or the like, the abnormality in the operation of the non-volatile memory element 20 is not reflected in the capacitor, and the non-volatile memory element is not reflected. It is possible to avoid the detection omission that the abnormality of the operation of 20 cannot be detected.

Further, in the abnormality detector 10 according to the first embodiment described above, the data before storage, which is the target for calculating the error detection code, is the data of the entire area of the volatile storage unit 21.
According to the above configuration, the error detection code is used for the data in the entire area of the volatile storage unit 21 of the non-volatile memory element 20, and the abnormality in the operation of the non-volatile memory element 20 is detected. Abnormalities that have occurred in unused areas of unit 21 can be reliably detected.

<Modified Example of First Embodiment>
Although the abnormality detector 10 according to the first embodiment has been described in detail above, the specific embodiment of the abnormality detector 10 is not limited to the above, and varies within a range that does not deviate from the gist. It is possible to make design changes to the above.
(First Modified Example of First Embodiment)
For example, in the abnormality detector 10 according to the first embodiment, it has been described that the data before storage, which is the target for calculating the first error detection code, is the data of the entire area of the volatile storage unit 21. The data before storing, which is the target for calculating the first error detection code, may be the data in the used area of the volatile storage unit 21.

By doing so, the processing load of the abnormality detector 10 can be reduced by making only the data in the used area excluding the unused area of the volatile storage unit 21 the target for calculating the first error detection code. Abnormal operation of the non-volatile memory element 20 can be efficiently detected.

Further, for example, a first error detection code is calculated for each of a plurality of specific range data of the volatile storage unit 21, and the calculated first error detection code is stored in the main memory 30. May be good. The plurality of specific ranges may be defined, for example, by dividing the range of the volatile storage unit 21 for each sector size.

By doing so, it is possible not only to detect an abnormality in the operation of the non-volatile memory element 20, but also to obtain detailed information on which part of the data of the volatile storage unit 21 the inconsistency has occurred. This makes it possible to effectively investigate the cause of the abnormality in the operation of the non-volatile memory element 20. Further, among the plurality of first error detection codes calculated for each of the plurality of specific range data of the volatile storage unit 21, only the first error detection code for the data in the used area of the volatile storage unit 21 is used. It may be saved in the main memory 30. As a result, the processing load of the abnormality detector 10 can be reduced, and abnormalities in the operation of the non-volatile memory element 20 can be efficiently detected.

(Second Modified Example of First Embodiment)
Next, the abnormality detector 10 according to the second modified embodiment of the first embodiment will be described with reference to FIG.

FIG. 3 is a diagram showing a configuration of an abnormality detector 10 according to a second modification of the first embodiment.
As shown in FIG. 3, the abnormality detector 10 according to the second modification of the first embodiment has a configuration in which the main memory 30 is removed from the components of the first embodiment. Further, as shown in FIG. 3, in the abnormality detector 10 according to the second modification of the first embodiment, in addition to the components of the first embodiment, the power supply to the abnormality detector 10 is cut off. An error detection code holding unit 60 capable of holding the first error detection code in the state of being used is further provided. Therefore, each component other than the error detection code holding unit 60 included in the abnormality detector 10 according to the second modification of the first embodiment has an abnormality according to the first embodiment unless otherwise specified. It is configured and functions in the same manner as each component of the detector 10.

The error detection code holding unit 60 includes a SRAM (Static Random Access Memory) 61 as a storage device for storing the first error detection code, and a battery 62 connected to the SRAM 61. In the second modification of the first embodiment, the SRAM 61 has the function of the main memory 30 according to the first embodiment. As a result, the SRAM 61 performs the operation of the main memory 30 according to the first embodiment. For example, in the second modification of the first embodiment, in step S103 of the processing flow shown in FIG. 2, the first error detection code is stored in SRAM 61 instead of the main memory 30. Further, in step S109 of the processing flow shown in FIG. 2, the first error detection code is read from the SRAM 61 instead of the main memory 30. The battery 62 connected to the SRAM 61 functions as a backup power source. The battery 62 can supply power to the SRAM 61 in a state where the power supply to the abnormality detector 10 is cut off. As a result, for example, the error detection code holding unit 60 is stored in the SRAM 61 even when the power supply to the non-volatile memory device 1 is unintentionally cut off due to a failure or the like and the power supply to the abnormality detector 10 is cut off. It is possible to hold the first error detection code.

As described above, the abnormality detector 10 according to the second modification of the first embodiment is an error detection capable of holding the first error detection code in a state where the power supply to the abnormality detector 10 is cut off. A code holding unit 60 is further provided.

According to the above configuration, for example, even if the power supply to the non-volatile memory device 1 is unintentionally cut off due to a failure or the like and the power supply to the abnormality detector 10 is cut off, the power supply is cut off. The error detection code holding unit 60 holds the first error detection code, and can prevent the loss of the first error detection code. As a result, the abnormality determination unit 130 of the abnormality detector 10 has an error detection code after the power supply to the abnormality detector 10 is restarted even if the power supply to the abnormality detector 10 is cut off. An abnormality in the operation of the non-volatile memory element 20 can be reliably detected by using the first error detection code held by the holding unit 60.
The SRAM 61 constituting the error detection code holding unit 60 according to the second modification of the first embodiment may have a minimum capacity capable of storing only the first error detection code. Further, the storage device included in the error detection code holding unit 60 may be other than the SRAM 61. Further, the main memory 30 according to the first embodiment may be used without separately providing the storage device included in the error detection code holding unit 60.

Further, in the abnormality detector 10 according to the second modification of the first embodiment, the error detection code holding unit 60 includes a battery 62 that functions as a backup power source.
According to the above configuration, the backup power supply can be miniaturized by using the battery 62, so that the error detection code holding unit 60 can be easily mounted on the abnormality detector 10. Further, the abnormality detector 10 provided with the error detection code holding unit 60 can be miniaturized. Therefore, the non-volatile memory device 1 provided with the abnormality detector 10 can be miniaturized and simplified.

(Third modified embodiment of the first embodiment)
Next, the abnormality detector 10 according to the third modified embodiment of the first embodiment will be described with reference to FIG.

FIG. 4 is a diagram showing a configuration of an abnormality detector 10 according to a third modified embodiment of the first embodiment.
As shown in FIG. 4, the abnormality detector 10 according to the third modified embodiment of the first embodiment has a configuration in which the main memory 30 is removed from the components of the first embodiment. Therefore, each component of the abnormality detector 10 according to the third modification of the first embodiment is the same as each component of the abnormality detector 10 according to the first embodiment, unless otherwise specified. It is configured and works.

In the third modification of the first embodiment, the CPU 11 has the function of the main memory 30 according to the first embodiment. As a result, the CPU 11 performs the operation of the main memory 30 according to the first embodiment.

The abnormality detector 10 according to the third modification of the first embodiment is configured to store the first error detection code in the general-purpose register R of the CPU 11. Specifically, in step S103 of the processing flow shown in FIG. 2, the first error detection code is stored in the general-purpose register R instead of the main memory 30. Further, in step S109 of the processing flow shown in FIG. 2, the first error detection code is read from the general-purpose register R instead of the main memory 30.

As described above, the abnormality detector 10 according to the third modification of the first embodiment stores the first error detection code in the general-purpose register R of the CPU 11 included in the abnormality detector 10.

According to the above configuration, it is not necessary to provide the main memory 30 in the abnormality detector 10, so that the abnormality detector 10 can be miniaturized. Moreover, the configuration of the abnormality detector 10 can be simplified. Therefore, the non-volatile memory device 1 provided with the abnormality detector 10 can be miniaturized and simplified.

<Second embodiment>
Next, the non-volatile memory device 1 and the abnormality detector 10 according to the second embodiment will be described with reference to FIGS. 5 and 6.

(Configuration of anomaly detector)
FIG. 5 is a diagram showing a configuration of a non-volatile memory device 1 including the abnormality detector 10 according to the second embodiment.
As shown in FIG. 5, the abnormality detector 10 according to the second embodiment further includes a power supply controller 70 connected to the non-volatile memory element 20 in addition to the components of the first embodiment. Therefore, each component other than the power supply controller 70 included in the abnormality detector 10 according to the second embodiment is the same as each component of the abnormality detector 10 according to the first embodiment, unless otherwise specified. It is configured and works.

The power controller 70 controls the power supply of the non-volatile memory element 20. The power controller 70 may be, for example, a power control switch connected to the power supply terminal of the non-volatile memory element 20. The power controller 70 can stop the power supply to the non-volatile memory element 20 and turn off the power of the non-volatile memory element 20 according to the instruction from the store / recall processing unit 110. Further, the power supply controller 70 can start supplying power to the non-volatile memory element 20 and turn on the power of the non-volatile memory element 20 according to an instruction from the store / recall processing unit 110.

(Processing flow of anomaly detector)
FIG. 6 is a diagram showing a processing flow of the abnormality detector 10 according to the second embodiment.
Hereinafter, the processing of the abnormality detector 10 according to the second embodiment will be described with reference to FIG.

The processing flow shown in FIG. 6 is different from the processing flow according to the first embodiment shown in FIG. 2, in which step S101 is changed to step 201 and steps S104, S105, and S107 are changed to steps S202 to 203. Only the point is different. Since the process flow is the same as that of the first embodiment shown in FIG. 2, except for these different steps, the description thereof will be omitted.

As shown in FIG. 6, when the processing flow is started, the store / recall processing unit 110 determines whether or not the store processing or the recall processing of the non-volatile memory element 20 is required (step S201). .. When at least one of the store processing and the recall processing of the non-volatile memory element 20 is required (YES in step S201), the store / recall processing unit 110 causes the error detection code processing unit 120 to make a first error. An instruction is given to calculate the detection code, and the process proceeds to step S102.

On the other hand, when both the store processing and the recall processing of the non-volatile memory element 20 are not required (NO in step S201), steps S102 to S103, S202 to S203, and S108 to S111 shown in FIG. 6 are skipped. , The process proceeds to step S106. In this case, the store / recall processing unit 110 notifies the abnormality determination unit 130 that neither the store nor the recall processing of the non-volatile memory element 20 is required. Based on this notification, the abnormality determination unit 130 determines that the operation of the non-volatile memory element 20 is normal (S106), and the processing flow ends.

The error detection code processing unit 120 calculates the first error detection code for the data before being stored in the non-volatile storage unit 22 from the volatile storage unit 21 of the non-volatile memory element 20 (step S102), and the calculated first error detection code is calculated. The error detection code of is stored in the main memory 30 (step S103). Next, the error detection code processing unit 120 notifies the store / recall processing unit 110 that the saving of the first error detection code is completed, and the process proceeds to step S202.

Upon receiving the notification from the error detection code processing unit 120, the store / recall processing unit 110 stops the power supply to the non-volatile memory element 20 (step S202). Specifically, the store / recall processing unit 110 instructs the power supply controller 70 to stop the power supply to the non-volatile memory element 20. As a result, the power controller 70 stops supplying power to the non-volatile memory element 20. The controller 23 of the non-volatile memory element 20 performs a process (auto store process) of storing data from the volatile storage unit 21 to the non-volatile storage unit 22 triggered by the stop of the power supply.

Next, the store / recall processing unit 110 starts supplying power to the non-volatile memory element 20 (step S203). Specifically, the store / recall processing unit 110 instructs the power supply controller 70 to start supplying power to the non-volatile memory element 20. As a result, the power controller 70 starts supplying power to the non-volatile memory element 20. The controller 23 of the non-volatile memory element 20 performs a process (auto recall process) of recalling data from the non-volatile storage unit 22 to the volatile storage unit 21 triggered by the supply of power supply.

The store / recall processing unit 110 instructs the power supply controller 70 to start supplying power to the non-volatile memory element 20 after the above-mentioned store processing (auto store processing) is completed. In other words, the time from the stop to the start of the power supply to the non-volatile memory element 20 is set to be longer than the time required for the store processing (auto store processing) described above.

Next, the store / recall processing unit 110 instructs the error detection code processing unit 120 to calculate the second error detection code. Upon receiving an instruction from the store / recall processing unit 110, the error detection code processing unit 120 receives a second error detection code for the data after recalling from the non-volatile storage unit 22 of the non-volatile memory element 20 to the volatile storage unit 21. Is calculated (step S108).

The store / recall processing unit 110 instructs the error detection code processing unit 120 to calculate the second error detection code after the above-mentioned recall process (auto recall process) is completed. In other words, the time from the start of power supply to the non-volatile memory element 20 to the start of the calculation process of the second error detection code is set to be longer than the time required for the above-mentioned recall process (auto recall process). Has been done.

The processing after step S109 is performed in the same manner as the processing flow shown in FIG. Finally, the abnormality determination unit 130 determines that the operation of the non-volatile memory element 20 is normal (step S106), or determines that the operation of the non-volatile memory element 20 is abnormal (step S111), and FIG. The processing flow shown in is completed.

(Action, effect)
As described above, the abnormality detector 10 according to the second embodiment further includes a power supply controller 70 that controls the power supply of the non-volatile memory element 20.

According to the above configuration, the abnormality detector 10 utilizes the auto-store and auto-recall functions of the non-volatile memory element 20 and is very easily non-volatile through the control of the power supply of the non-volatile memory element 20. The store processing and recall processing of the volatile memory element 20 can be performed. As a result, it is possible to omit the process of directly instructing the controller 23 of the non-volatile memory element 20 from the store / recall processing unit 110 of the abnormality detector 10, so that the process performed by the CPU can be simplified. Further, the mounting on the non-volatile memory device 1 is facilitated.

FIG. 7 is a diagram showing the minimum configuration of the abnormality detector 10.
The abnormality detector 10 may include at least the above-mentioned abnormality determination unit 130.

The above-mentioned abnormality detector 10 may have a computer system inside. The process of each process described above is stored in a computer-readable recording medium in the form of a program, and the process may be performed by the computer reading and executing this program. Here, the computer-readable recording medium refers to a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Further, this computer program may be distributed to a computer via a communication line, and the computer receiving the distribution may execute the program.

The above program may be for realizing a part of the above-mentioned functions. Further, a so-called difference file (difference program) may be used, which can realize the above-mentioned functions in combination with a program already recorded in the computer system.

Some or all of the above embodiments may also be described, but not limited to:

(Appendix 1) The first error detection code of the data before being stored in the non-volatile storage unit from the volatile storage unit of the non-volatile memory element and the data after being stored are stored in the volatile storage unit from the non-volatile storage unit. An abnormality detector including an abnormality determination unit that determines that the operation of the non-volatile memory element is abnormal when the second error detection code of the data after recalling to the unit does not match.

(Appendix 2) The abnormality detector according to Appendix 1, wherein the data before storage is data for the entire area of the volatile storage unit.

(Appendix 3) The anomaly detector according to Appendix 1 or Appendix 2, wherein the data before storage is data of a used area of the volatile storage unit.

(Supplementary note 4) The abnormality detector according to any one of Supplementary note 1 to Supplementary note 3, which calculates the first error detection code for each of a plurality of specific ranges of data before storing.

(Supplementary note 5) The item according to any one of Supplementary note 1 to Supplementary note 4, further comprising an error detection code holding unit capable of holding the first error detection code in a state where the power supply to the abnormality detector is cut off. Anomaly detector.

(Appendix 6) The abnormality detector according to Appendix 5, wherein the error detection code holding unit includes a battery that functions as a backup power source.

(Supplementary note 7) The abnormality detector according to any one of Supplementary note 1 to Supplementary note 4, wherein the first error detection code is stored in a general-purpose register of a CPU included in the abnormality detector.

(Supplementary note 8) The abnormality detector according to any one of Supplementary note 1 to Supplementary note 7, further comprising a power supply controller for controlling the power supply of the non-volatile memory element.

(Appendix 9) The abnormality detector according to any one of Appendix 1 to Appendix 8 and
With the non-volatile memory element
A non-volatile memory device comprising.

(Appendix 10) The first error detection code of the data before being stored in the non-volatile storage unit from the volatile storage unit of the non-volatile memory element and the data after being stored are stored in the volatile storage unit from the non-volatile storage unit. An abnormality detection method for determining that the operation of the non-volatile memory element is abnormal when the second error detection code of the data after recalling to the unit does not match.

(Appendix 11) Computer of anomaly detector
The first error detection code of the data before being stored from the volatile storage unit of the non-volatile memory element to the non-volatile storage unit and the data after being stored were recalled from the non-volatile storage unit to the volatile storage unit. A determination means for determining that the operation of the non-volatile memory element is abnormal when the second error detection code of the later data does not match.
Anomaly detection program that functions as.

1 Non-volatile memory device 10 Abnormality detector 11 CPU (processor)
20 Non-volatile memory element 21 Volatile storage unit 22 Non-volatile storage unit 23 Controller 30 Main memory 60 Error detection code holding unit 61 SRAM
62 Battery 70 Power controller 110 Store / recall processing unit 120 Error detection code processing unit 130 Abnormality judgment unit R General-purpose register

Claims (9)

The first error detection code of the data before being stored from the volatile storage unit of the non-volatile memory element to the non-volatile storage unit and the data after being stored were recalled from the non-volatile storage unit to the volatile storage unit. When the second error detection code of the later data does not match, the abnormality determination unit that determines that the operation of the non-volatile memory element is abnormal, and
At the timing when the power of the non-volatile memory element is turned off, the volatile storage unit issues an instruction to the controller of the non-volatile memory element to store the data before storing in the non-volatile storage unit, and the non-volatile memory element is stored. A store / recall processing unit that instructs the controller to recall the data after being stored in the volatile storage unit from the non-volatile storage unit at the timing when the power of the memory element is turned on.
CPU general-purpose registers and
Equipped with a,
Anomaly detector you save the first error detection code to the general purpose register. The abnormality detector according to claim 1, wherein the data before being stored is data in the entire area of the volatile storage unit. The abnormality detector according to claim 1 or 2, wherein the data before storing is data in a used area of the volatile storage unit. The abnormality detection according to any one of claims 1 to 3, further comprising an error detection code holding unit capable of holding the first error detection code in a state where the power supply to the abnormality detector is cut off. vessel. The abnormality detector according to claim 4, wherein the error detection code holding unit includes a battery that functions as a backup power source. According to the instruction from the store / recall processing unit, the power supply of the non-volatile memory element is stopped, the power of the non-volatile memory element is turned off, and the power supply of the non-volatile memory element is followed by the instruction from the store / recall processing unit. The abnormality detector according to any one of claims 1 to 5 , further comprising a power controller that starts power supply and turns on the non-volatile memory element. The abnormality detector according to any one of claims 1 to 6 ,
With the non-volatile memory element
A non-volatile memory device comprising. By the abnormality detector, the first error detection code of the data before being stored in the non-volatile storage unit from the volatile storage unit of the non-volatile memory element and the data after being stored are stored in the non-volatile storage unit. When the second error detection code of the data after recalling to the storage unit does not match, it is determined that the operation of the non-volatile memory element is abnormal.
The abnormality detector instructs the controller of the non-volatile memory element to store the data before being stored in the non-volatile storage unit from the volatile storage unit at the timing when the power of the non-volatile memory element is turned off. the out, and given instructions said non-volatile memory device from said nonvolatile storage unit at the timing of the power supply oN to the controller so as to recall the data after storing in the volatile storage unit,
An abnormality detection method in which the first error detection code is stored in a general-purpose register of a CPU included in the abnormality detector. Anomaly detector computer,
The first error detection code of the data before being stored from the volatile storage unit of the non-volatile memory element to the non-volatile storage unit and the data after being stored were recalled from the non-volatile storage unit to the volatile storage unit. When the second error detection code of the later data does not match, the determination means for determining that the operation of the non-volatile memory element is abnormal, and the volatilization at the timing when the power of the non-volatile memory element is turned off. The non-volatile storage unit issues an instruction to the controller of the non-volatile memory element to store the data before being stored in the non-volatile storage unit from the sexual storage unit, and turns on the power of the non-volatile memory element. A store / recall processing means that instructs the controller to recall the data after being stored in the volatile storage unit.
To function as
The first error detection code, the abnormality detection program that will be stored in the general-purpose register of the CPU where the anomaly detector is provided.

Images