JP6774512B2 - FEC error addition device, test signal generator using it, and FEC error addition method - Google Patents

Description

The present invention relates to an FEC error addition device, a test signal generator using the FEC error addition device, and an FEC error addition method, and in particular, generates a test signal for measuring an error rate of a communication device based on a communication standard using forward error correction. The present invention relates to an FEC error addition device for this purpose, a test signal generator using the FEC error addition device, and an FEC error addition method.

In recent years, the speed of communication systems has been steadily increasing, and the performance of various communication devices constituting the communication systems has been improved. Then, as one of the indexes for evaluating the quality of signals in these communication devices, a bit error rate defined as a comparison between the number of received data in which bit errors occur and the total number of received data is known.

In standards such as 100G and 400G defined by IEEE, transmission by PAM4 signal is specified instead of transmission by PAM2 (NRZ) signal so far in order to respond to ultra-high speed of bit rate. The PAM4 signal is composed of four PAM4 symbols consisting of "00", "01", "10", and "11".

In the transmission by the PAM4 signal, a technique of forward error correction coding (hereinafter, also referred to as “FEC coding”) is used. For example, as shown in FIG. 5, in the FEC coding by RS-FEC (544,514) defined in IEEE802.3, a parity part consisting of 30 FEC symbols and a message part consisting of 514 FEC symbols An FEC code word consisting of 544 FEC symbols is generated.

Since the FEC codeword includes the parity portion of the 30 FEC symbol, the FEC decoder of the communication device on the receiving side can correct errors of up to 15 FEC symbols per 1 FEC codeword. The 1FEC symbol consists of 10 bits, but if the number of error bits included in the 1FEC symbol is in the range of 1 to 10, the FEC symbol is an FEC symbol containing an error (hereinafter, also referred to as "error FEC symbol"). It becomes.

The FEC codeword is converted into a PAM4 signal through processing such as gray coding, interleaving, programming, and PAM4 encoding.

FIG. 6 is a schematic diagram for explaining interleaving of FEC codewords. In the 200G or 400G standard defined in IEEE802.3bs, two Reed-Solomon encoders A and B convert two messages A and B into two FEC codewords A and B, respectively.

Further, FIG. 6 shows a situation in which a burst error for 18 FEC symbols is added to the two interleaved FEC code words A and B. The FEC symbols extracted from the two FEC codewords A and B by interleaving are rearranged so as to be adjacent to the FEC symbols from different FEC codewords, and are distributed to, for example, 16 lanes. Will be done. As a result, the burst error for 18 FEC symbols is distributed to the two FEC codewords A and B by 9 FEC symbols, so that the error is corrected by the FEC decoder.

Therefore, in order to ensure that the FEC codeword A cannot be corrected by the FEC decoder, it is necessary to add a burst FEC symbol error to the data for 32 FEC symbols transmitted in one lane, for example. Since the burst bit error is removed by PAM4 recording, it is difficult to make the error uncorrectable by the FEC decoder. Therefore, in order to make the FEC codeword uncorrectable by the FEC decoder, it is necessary to add a burst FEC symbol error. Here, the burst bit error is a plurality of consecutive error bits. On the other hand, a burst FEC symbol error is a plurality of consecutive error FEC symbols in one FEC codeword, and can be generated by providing only one error bit in each of the consecutive FEC symbols. Burst FEC symbol errors generated in this way are not eliminated by PAM4 recording.

Conventionally, an error adding device that adds an error to a data signal has been used in order to generate a test signal for measuring an error rate for a communication device having an FEC function (see, for example, Patent Document 1).

Japanese Patent No. 52158881

In the error rate measurement, in order to evaluate the FEC function of the communication device, it is necessary to add an FEC symbol error that cannot be corrected by the FEC decoder of the communication device. For a PAM4 signal in which two differently guarded FEC code words by two Reed-Solomon encoders are interleaved, one or both of the MSB (most significant bit) and LSB (least significant bit) of the PAM4 symbol. The two guards cannot be error-correctable at the same time unless an error is added to to generate a burst FEC symbol error.

However, since the error adding device disclosed in Patent Document 1 does not have a means for separating the PAM4 signal into the MSB and the LSB, it is not possible to add a bit error to one or both of the MSB and the LSB. Therefore, the above-mentioned conventional error adding device cannot add a burst FEC symbol error to a PAM4 signal in which two guarded FEC codewords by two Reed-Solomon encoders are interleaved. There was a problem.

The present invention has been made to solve such a conventional problem, and is an FEC error adding device capable of generating a test signal for testing the FEC function of a communication device that receives a PAM4 signal. It is an object of the present invention to provide a test signal generator using the same and a FEC error addition method.

In order to solve the above problem, the FEC error adding device according to the present invention is an FEC error adding device that adds an error to a PAM4 signal including a plurality of FEC code words composed of a plurality of FEC symbols, and the PAM4 signal is used as an MSB. A dividing unit that divides the MSB and the LSB, an error signal generating unit that generates an error signal for continuously adding the error to one or both of the MSB and the LSB at predetermined bit intervals, and the MSB and the LSB. An exclusive logical sum operation with the error signal is performed on a bit-by-bit basis, and an error addition section that outputs a bit string obtained as a result of the calculation is combined with a bit string of the MSB and the LSB output from the error addition section. A compositing unit that generates a PAM4 signal to which the error is added and outputs the PAM4 signal to which the error is added as a test signal, a bit error rate input unit to which the bit error rate of the test signal is input, and the test. Of the plurality of FEC code words included in the signal, the number of the error FEC symbols included in the FEC code word having the error FEC symbol which is the FEC symbol to which the error is added is input. A unit, an error bit number input unit in which the number of error bits included in the error FEC symbol is input, a CW size input unit in which the number of bits constituting the FEC code word is input, and the bit error rate input unit. The bit error rate input to the unit, the number of the error FEC symbols input to the error FEC symbol number input unit, the number of error bits input to the error bit number input unit, and the CW size input. Based on the number of the bits input to the unit, it has the minimum number of the FEC code words required to realize the bit error rate and the error FEC symbol included in the minimum number of the FEC code words. The CW number calculation unit for calculating the number of FEC code words is provided, and the error signal generation unit is such that the minimum number of consecutive FEC code words calculated by the CW number calculation unit calculates the CW number. The configuration is such that the error signal for generating the test signal including the FEC code word having the number of the error FEC symbols calculated by the unit is output.

With this configuration, the FEC error addition device according to the present invention can generate a test signal for testing the FEC function of the communication device that receives the PAM4 signal. The FEC error addition device according to the present invention can easily generate a test signal that can be error-corrected or cannot be corrected by the FEC decoder of the communication device to be tested by changing parameters such as the bit error rate. Can be done.

Further, in the FEC error adding device according to the present invention, the error signal generating unit generates one error FEC symbol for every n FEC codewords in the minimum number of consecutive FEC codewords in the test signal. The error signal is repeated m times so that the pattern including the FEC codeword having the FEC codeword is repeated m times and the pattern including the FEC codeword having one error FEC symbol is repeated p times for every n + 1 FEC codewords. It may be configured to generate.

With this configuration, the FEC error addition device according to the present invention continuously adds errors to the MSB and LSB of the PAM4 signal at predetermined bit intervals, so that FEC codewords including burst errors are approximately evenly spaced in time. Can be generated with. As a result, the FEC error adding apparatus according to the present invention can generate a test signal that enables efficient error rate measurement in a short time.

Further, the test signal generator according to the present invention outputs a PAM4 signal including the above FEC error addition device and a plurality of FEC code words composed of a plurality of FEC symbols to the division portion of the FEC error addition device. It is a configuration including a unit.

With this configuration, the test signal generator according to the present invention can generate a test signal for testing the FEC function of the communication device that receives the PAM4 signal.

Further, the FEC error addition method according to the present invention is a FEC error addition method in which an error is added to a PAM4 signal including a plurality of FEC code words composed of a plurality of FEC symbols, and the PAM4 signal is divided into MSB and LSB. The step, the error signal generation step of generating an error signal for continuously adding the error to one or both of the MSB and the LSB at a predetermined bit interval, and the exclusion of the MSB, the LSB, and the error signal. The error was added by synthesizing the error addition step that performs a forward error addition operation in bit units and outputs the bit string obtained as the result of the operation, and the bit strings of the MSB and the LSB output from the error addition step. A synthesis step that generates a PAM4 signal and outputs the PAM4 signal to which the error is added as a test signal, a bit error rate input step in which the bit error rate of the test signal is input, and a plurality of steps included in the test signal. Among the FEC code words, the error FEC symbol number input step in which the number of the error FEC symbols included in the FEC code word having the error FEC symbol which is the FEC symbol to which the error is added is input, and the error FEC. The error bit number input step in which the number of error bits included in the symbol is input, the CW size input step in which the number of bits constituting the FEC code word is input, and the bit error rate input step input. The bit error rate, the number of the error FEC symbols input in the error FEC symbol number input step, the number of error bits input in the error bit number input step, and the error input in the CW size input step. Based on the number of bits, the minimum number of the FEC code words required to realize the bit error rate and the number of FEC code words having the error FEC symbol included in the minimum number of the FEC code words. In the error signal generation step, the minimum number of consecutive FEC code words calculated by the CW number calculation step is calculated by the CW number calculation step. The configuration is such that the error signal for generating the test signal including the FEC code word having the number of the error FEC symbols is output.

With this configuration, the FEC error addition method according to the present invention can generate a test signal for testing the FEC function of the communication device that receives the PAM4 signal. The FEC error addition method according to the present invention easily generates a test signal in which an error can be corrected or cannot be corrected by the FEC decoder of the communication device to be tested by changing parameters such as a bit error rate. Can be done.

Further, in the FEC error addition method according to the present invention, in the error signal generation step, in the minimum number of consecutive FEC codewords in the test signal, one error FEC symbol is used for every n FEC codewords. The error signal is repeated m times so that the pattern including the FEC codeword having the FEC codeword is repeated m times and the pattern including the FEC codeword having one error FEC symbol is repeated p times for every n + 1 FEC codewords. It may be configured to generate.

With this configuration, the FEC error addition method according to the present invention continuously adds errors to the MSB and LSB of the PAM4 signal at predetermined bit intervals, so that FEC codewords including burst errors are approximately evenly spaced in time. Can be generated with. As a result, the FEC error adding apparatus according to the present invention can generate a test signal that enables efficient error rate measurement in a short time.

The present invention provides an FEC error addition device capable of generating a test signal for testing the FEC function of a communication device that receives a PAM4 signal, a test signal generator using the FEC error addition device, and an FEC error addition method. Is.

It is a block diagram which shows the structure of the test signal generator which concerns on embodiment of this invention. It is a figure for demonstrating the appearance timing of the error FEC codeword controlled by the control part of the FEC error addition apparatus which concerns on embodiment of this invention. It is a figure for demonstrating the error addition timing with respect to the PAM4 signal controlled by the control part of the FEC error addition apparatus which concerns on embodiment of this invention. It is a sequence diagram for demonstrating the process of the FEC error addition method using the FEC error addition apparatus which concerns on embodiment of this invention. It is a figure which shows the structure of the FEC code word of RS-FEC (544,514). It is a schematic diagram for demonstrating interleaving.

Hereinafter, an FEC error addition device according to the present invention, a test signal generator using the FEC error addition device, and an embodiment of the FEC error addition method will be described with reference to the drawings.

As shown in FIG. 1, the test signal generator 100 according to the embodiment of the present invention adds an error to the PAM4 signal output unit 10 and the PAM4 signal including a plurality of FEC code words composed of a plurality of FEC symbols. A device 20 is provided, and a test signal is output to a device under test (DUT) 200.

The PAM4 signal output unit 10 includes a MAC frame data output unit 11, an FEC encoder 12, and a PAM4 processing unit 13. The MAC frame data output unit 11 outputs the MAC frame data for testing the DUT 200 to be tested to the FEC encoder 12 as test signal data.

The FEC encoder 12 performs FEC coding on the MAC frame data output from the MAC frame data output unit 11 to sequentially generate FEC codewords composed of a plurality of FEC symbols. In the present embodiment, it is assumed that the FEC coding by the FEC encoder 12 corresponds to RS-FEC (544,514) defined in IEEE802.3.

The FEC codeword of RS-FEC (544,514) generated by the FEC encoder 12 has 544 FEC symbols consisting of a parity part consisting of 30 FEC symbols and a message part consisting of 514 FEC symbols. Have. Since the FEC codeword includes the parity portion of the 30FEC symbol, the FEC decoder on the DUT200 side can correct errors of up to 15 FEC symbols per FEC codeword. The 1FEC symbol consists of 10 bits, but if the number of error bits included in the 1FEC symbol is in the range of 1 to 10, the FEC symbol becomes an error FEC symbol including an error.

The PAM4 processing unit 13 has come to generate a PAM4 signal including a plurality of FEC codewords output from the FEC encoder 12 by performing processing such as gray coding and PAM4 encoding specified in IEEE802.3. ing. The PAM4 signal is composed of four PAM4 symbols consisting of "00", "01", "10", and "11".

The FEC error addition device 20 includes a division unit 21, an error signal generation unit 22, an error addition unit 23, a synthesis unit 24, a control unit 25, a display unit 26, and an operation unit 27.

The dividing unit 21 divides the PAM4 signal output from the PAM4 processing unit 13 of the PAM4 signal output unit 10 into the MSB (most significant bit) and the LSB (least significant bit) of the PAM4 symbol.

The error signal generation unit 22 is adapted to generate an error signal for continuously adding an error to the MSB and LSB of the PAM4 signal output from the division unit 21 at predetermined bit intervals, respectively.

It is assumed that the error signal output from the error signal generation unit 22 is time-adjusted so as to be synchronized with the signals of the MSB and LSB bit strings output from the division unit 21 under the control of the control unit 25.

The error addition unit 23 performs an exclusive OR (XOR) operation of the MSB and LSB of the PAM4 signal output from the division unit 21 and the error signal output from the error signal generation unit 22 in bit units, and performs the operation. The resulting bit string is output.

The synthesis unit 24 synthesizes the MSB and LSB bit strings output from the error addition unit 23 to generate a PAM4 signal to which an error is added, and outputs the PAM4 signal to which this error is added to the DUT 200 as a test signal. It has become.

The DUT 200 performs the reverse processing of the PAM4 processing unit 13 on the test signal output from the test signal generator 100 to restore the FEC codeword to which an error is added, and uses the FEC decoder to restore the restored FEC codeword. It is designed to decode.

The control unit 25 is composed of, for example, a microcomputer including a CPU, ROM, RAM, HDD, or the like, a personal computer, or the like, and controls the operation of each of the above units constituting the test signal generator 100. Further, the control unit 25 transfers a predetermined program stored in the ROM or the like to the RAM and executes the program to execute the bit error rate input unit 25a, the error FEC symbol number input unit 25b, and the error bit number input unit 25c, which will be described later. The CW size input unit 25d, the CW number calculation unit 25e, and the CW timing control unit 25f can be configured by software.

The bit error rate input unit 25a, the error FEC symbol number input unit 25b, the error bit number input unit 25c, the CW size input unit 25d, the CW number calculation unit 25e, and the CW timing control unit 25f are FPGA (Field Programmable Gate Array). ) And ASIC (Application Specific Integrated Circuit) and other digital circuits can also be used. Alternatively, the bit error rate input unit 25a, the error FEC symbol number input unit 25b, the error bit number input unit 25c, the CW size input unit 25d, the CW number calculation unit 25e, and the CW timing control unit 25f are subjected to hardware processing by a digital circuit. It is also possible to configure by appropriately combining and software processing by a predetermined program.

The bit error rate input unit 25a is adapted to input a desired bit error rate ER of the test signal output from the synthesis unit 24 in response to an operation on the operation unit 27 by the user.

The error FEC symbol number input unit 25b is a FEC codeword having an error FEC symbol among a plurality of FEC codewords included in the test signal in response to an operation on the operation unit 27 by the user (hereinafter, “error FEC codeword”). The desired number of erroneous FEC symbols included in (also referred to as) sE is input.

The error bit number input unit 25c is adapted to input a desired number bE of error bits included in the error FEC symbol in response to an operation on the operation unit 27 by the user.

In the CW size input unit 25d, the number of bits (hereinafter, also referred to as “CW size”) CW _size that constitutes the FEC codeword is input in response to the operation of the operation unit 27 by the user. For example, in the case of RS-FEC (544,514), the CW size is 5440 bits.

The CW number calculation unit 25e was input to the bit error rate ER input to the bit error rate input unit 25a, the number sE of the error FEC symbols input to the error FEC symbol number input unit 25b, and the error bit number input unit 25c. the number of error bits bE, and, based on the CW size _{CW size} input to the CW size input unit 25d, and the minimum number of FEC codewords required in order to achieve a desired bit error rate, FEC of the minimum number The number of error FEC code words included in the code word is calculated.

The CW timing control unit 25f causes the minimum number of consecutive FEC codewords calculated by the CW number calculation unit 25e to generate a test signal including the number of error FEC codewords calculated by the CW number calculation unit 25e. , Generates a timing signal that controls the timing of the error signal output from the error signal generation unit 22.

The error signal generation unit 22 generates an error signal according to the timing signal output from the CW timing control unit 25f. For example, this error signal causes the pattern including one error FEC codeword for every n FEC codewords to be repeated m times in the above-mentioned minimum number of consecutive FEC codewords in the test signal, and n + 1 FECs. A pattern containing one error FEC codeword for each codeword is repeated p times.

The display unit 26 is composed of a display device such as an LCD or a CRT, and displays various display contents according to a control signal from the control unit 25. Further, the display unit 26 displays an operation target such as a soft key for setting various conditions, a pull-down menu, and a text box.

The operation unit 27 is for receiving an operation input by the user, and is composed of, for example, a touch panel provided on the surface of the display screen of the display unit 26. Alternatively, the operating unit 27 may be configured to include an input device such as a keyboard or mouse. Further, the operation unit 27 may be configured by an external control device that performs remote control by a remote command or the like.

The operation input to the operation unit 27 is detected by the control unit 25. For example, the operation unit 27 can select the MAC frame data to be output from the MAC frame data output unit 11, and the user can arbitrarily specify various parameters such as ER, sE, bE, and CW _size , which will be described later. is there.

Hereinafter, an example of the processing executed by the bit error rate input unit 25a, the error FEC symbol number input unit 25b, the error bit number input unit 25c, the CW size input unit 25d, the CW number calculation unit 25e, and the CW timing control unit 25f will be described. To do.

First, by the operation of the operation unit 27 by the user, the bit error rate ER, the number of error FEC symbols per 1FEC code word sE, the number of error bits bE per error FEC symbol, and the CW size CW _size are each set to the bit error rate. Input is performed to the input unit 25a, the error FEC symbol number input unit 25b, the error bit number input unit 25c, and the CW size input unit 25d.

The bit error rate ER (= α × 10 ^−N ) is the bit error rate ER, the number of error FEC symbols per 1 FEC code word sE, the number of error bits per 1 error FEC symbol bE, CW size CW _size , and the FEC code of interest. using equation _{E CW} of error FEC codeword contained several _{T CW,} and _{T CW} number of FEC codewords of the word, is expressed by the following equation (1).

ここで、式（１）の分母は注目する全ビット数であり、分子は注目する全ビット数に含まれる誤りビット数を表している。

Here, the denominator of the equation (1) is the total number of bits of interest, and the numerator represents the number of erroneous bits included in the total number of bits of interest.

Equation (1) can be transformed as in equation (2). As described above, since the error FEC symbol can be generated by including one error bit in the FEC symbol, the number of error bits bE per one error FEC symbol is set to 1 in the equation (2).

When the formula (2) is reduced, the numerator and denominator are shown in the formulas (3) and (4), respectively.

ここで、式（３）及び式（４）の分母は、式（２）の分子と分母の最大公約数である。式（３）で与えられるＴ_ＣＷの値は、所望のビット誤り率ＥＲを実現するために必要なＦＥＣコードワードの最小数である。また、式（４）で与えられるＥ_ＣＷの値は、Ｔ_ＣＷ個のＦＥＣコードワードに含まれる誤りＦＥＣコードワードの数である。

Here, the denominator of the formula (3) and the formula (4) is the greatest common divisor of the numerator and the denominator of the formula (2). The value of _TCW given by the equation (3) is the minimum number of FEC codewords required to realize the desired bit error rate ER. The value of _{E CW} given by equation (4) _is the number of errors FEC codeword contained in _{T CW} number of FEC codewords.

That, CW number calculating unit 25e calculates the _{T CW} and _{E CW} in accordance with equation (3) and (4). For example, the bit error rate ER 3 × ^{10 -4} (i.e., alpha = 3 and N = 4), When the 5, CW size _{CW size} error FEC symbol number sE _{5440, T CW} 625 _{becomes, E CW} is It becomes 204.

Further, the CW timing control unit 25f calculates n, m, and p already described according to the following equations (5) to (7).

ここで、ｍｏｄ（Ｔ_ＣＷ／Ｅ_ＣＷ）は、Ｔ_ＣＷをＥ_ＣＷで割ったときの余りである。このようにして、ｎ、ｍ、及びｐを算出することにより、Ｔ_ＣＷ個のＦＥＣコードワードの中に、ほぼ均等にＥ_ＣＷ個の誤りＦＥＣコードワードを配置することができる。

_{Here, mod (T CW / E CW} ) _is the remainder when divided by the _{T CW} in _{E CW.} In this manner, n, m, and by calculating the _p, in the _{T CW} number of FEC codewords can be arranged _{E CW} number of error FEC codeword substantially uniformly.

In the above example, where the bit error rate ER is 3 × 10 ^-4 , the number of error FEC symbols sE is 5, the CW size CW _size is 5440, the _TCW is 625, and the _ECW is 204, the equations (5) to (7). ), N = 3, m = 191 and p = 13. That is, as shown in FIG. 2, for 573 (= n × m) of the 625 FEC codewords, one error FEC codeword (indicated in black) is generated for every three FEC codewords. The included pattern is repeated 191 times. Further, for 52 (= (n + 1) × p) of the 625 FEC codewords, a pattern including one error FEC codeword for every four FEC codewords is repeated 13 times. Within each error FEC codeword, there are five consecutive error FEC symbols (ie, burst FEC symbol errors). The same applies to the 626th and subsequent FEC codewords.

In the example shown in FIG. 2, in 625 consecutive FEC codewords, after all the patterns for each of the three FEC codewords are repeated, the patterns for each of the four FEC codewords are repeated. However, the present invention is not limited to this. For example, the pattern for each of the three FEC codewords and the pattern for each of the four FEC codewords may be arranged in a random order.

The CW timing control unit 25f causes an error in one or both of the MSB and LSB of the PAM4 signal output from the PAM4 processing unit 13 at predetermined bit intervals according to the appearance timing of the error FEC codeword obtained as described above. Generate a timing signal for addition. For example, paying attention to one error FEC codeword, when the number of error FEC symbols sE is 2, as shown in black in FIG. 3, for example, for every 10 PAM4 symbols, one bit of error is continuously generated in the MSB. It is added times. The place where the error is added may be the LSB or both the MSB and the LSB.

Hereinafter, an example of the processing of the FEC error addition method using the FEC error addition device 20 will be described with reference to the sequence diagram of FIG.

First, various parameters are input by the user's operation on the operation unit 27 (input step S1). These parameters include the bit error rate ER of the test signal, the number sE of the error FEC symbols included in the error FEC codeword, the number bE of the error bits included in the error FEC symbol, the CW size CW _{size, and the} like. Is done.

Next, the CW number calculation unit 25e determines the FEC code word required to realize a desired bit error rate based on parameters such as the bit error rate input in the input step S1 and the number of error FEC symbols. The minimum number and the number of error FEC code words included in the minimum number of FEC code words are calculated (CW number calculation step S2).

Next, the CW timing control unit 25f starts outputting a timing signal that controls the timing of the error signal output from the error signal generation unit 22 (step S3).

Next, the error signal generation unit 22 starts outputting an error signal for continuously adding an error to one or both of the MSB and the LSB of the PAM4 signal output from the division unit 21 at predetermined bit intervals (error). Signal generation step S4). This error signal is for generating a test signal in which the minimum number of consecutive FEC codewords calculated in the CW number calculation step S2 includes the number of error FEC codewords calculated in the CW number calculation step S2. is there.

On the other hand, the division unit 21 starts a process of dividing the PAM4 signal output from the PAM4 signal output unit 10 into the MSB and the LSB (division step S5).

Next, the error addition unit 23 performs an XOR operation on the MSB and LSB of the PAM4 signal output from the division step S5 and the error signal output from the error signal generation step S4 in bit units, and obtains the result of the calculation. The output of the bit string to be generated is started (error addition step S6).

Next, the synthesis unit 24 synthesizes the MSB and LSB bit strings output from the error addition step S6 to generate a PAM4 signal to which an error is added, and outputs the PAM4 signal to which this error is added as a test signal. The process is started (synthesis step S7).

As described above, in the FEC error adding device 20 according to the present embodiment, the FEC of the DUT 200 that receives the PAM4 signal when parameters such as the bit error rate of the test signal and the number of error FEC symbols are specified by the user. A test signal for testing the function can be generated. By changing these parameters, the FEC error addition device 20 according to the present embodiment can easily generate a test signal that can be error-corrected or cannot be error-corrected by the FEC decoder of the DUT 200.

By the way, conventionally, in the error rate measurement, a test signal in which the error has a Poisson distribution may be used. However, when a test signal having a Poisson distribution error is used, there is a problem that the test time becomes long. Furthermore, when the bit rate exceeds 100 Gbit / s, if a test signal whose error is a Poisson distribution is to be generated by a logic circuit such as FPGA, the mounting scale of the circuit becomes enormous, and as a result, it becomes impossible to realize. There is a problem that it becomes.

On the other hand, the FEC error adding device 20 according to the present embodiment continuously adds an error to the MSB and LSB of the PAM4 signal at predetermined bit intervals, so that the FEC codeword including the burst error is substantially temporally. It can be generated at even intervals. As a result, the FEC error addition device 20 according to the present embodiment can generate a test signal that enables efficient error rate measurement in a short time.

10 PAM4 signal output unit 11 MAC frame data output unit 12 FEC encoder 13 PAM4 processing unit 20 FEC error addition device 21 Division unit 22 Error signal generation unit 23 Error addition unit 24 Synthesis unit 25 Control unit 25a Bit error rate input unit 25b Error FEC Number of symbols input unit 25c Number of error bits Input unit 25d CW size input unit 25e CW number calculation unit 25f CW timing control unit 26 Display unit 27 Operation unit 100 Test signal generator 200 DUT

Claims (5)

An FEC error adding device (20) that adds an error to a PAM4 signal including a plurality of FEC codewords composed of a plurality of FEC symbols.
A dividing unit (21) that divides the PAM4 signal into MSB and LSB, and
An error signal generation unit (22) that generates an error signal for continuously adding the error to one or both of the MSB and the LSB at predetermined bit intervals.
An error addition unit (23) that performs an exclusive OR operation of the MSB, the LSB, and the error signal in bit units and outputs a bit string obtained as a result of the operation.
The synthesis unit (24) that synthesizes the bit strings of the MSB and the LSB output from the error addition unit to generate a PAM4 signal to which the error is added, and outputs the PAM4 signal to which the error is added as a test signal. When,
The bit error rate input unit (25a) into which the bit error rate of the test signal is input, and
Among the plurality of FEC code words included in the test signal, the error FEC symbol in which the number of the error FEC symbols included in the FEC code word having the error FEC symbol which is the FEC symbol to which the error is added is input. Number input section (25b) and
An error bit number input unit (25c) into which the number of error bits included in the error FEC symbol is input, and
A CW size input unit (25d) into which the number of bits constituting the FEC codeword is input, and
The bit error rate input to the bit error rate input unit, the number of error FEC symbols input to the error FEC symbol number input unit, the number of error bits input to the error bit number input unit, and , The minimum number of the FEC code words required to realize the bit error rate based on the number of the bits input to the CW size input unit, and the said minimum number included in the FEC code word. A CW number calculation unit (25e) for calculating the number of FEC code words having an erroneous FEC symbol is provided.
In the error signal generation unit, the minimum number of consecutive FEC code words calculated by the CW number calculation unit is a FEC code word having the number of the error FEC symbols calculated by the CW number calculation unit. An FEC error adding device for outputting the error signal for generating the test signal including the test signal. In the error signal generation unit, in the minimum number of consecutive FEC codewords in the test signal, a pattern including one FEC codeword having one error FEC symbol for every n FEC codewords is repeated m times. The first aspect of claim 1, wherein the error signal is generated so that the pattern including the FEC codeword having one error FEC symbol for every n + 1 FEC codewords is repeated p times. FEC error addition device. The FEC error adding device (20) according to claim 1 or 2,
A test signal generator including a PAM4 signal output unit (10) that outputs a PAM4 signal including a plurality of FEC codewords composed of a plurality of FEC symbols to the division unit of the FEC error adding device. This is an FEC error addition method for adding an error to a PAM4 signal containing a plurality of FEC codewords composed of a plurality of FEC symbols.
A division step (S5) for dividing the PAM4 signal into MSB and LSB, and
An error signal generation step (S4) for generating an error signal for continuously adding the error to one or both of the MSB and the LSB at predetermined bit intervals, and
An error addition step (S6) in which an exclusive OR operation of the MSB, the LSB, and the error signal is performed in bit units, and a bit string obtained as a result of the operation is output.
A synthesis step (S7) in which the bit strings of the MSB and the LSB output from the error addition step are combined to generate a PAM4 signal to which the error is added, and the PAM4 signal to which the error is added is output as a test signal. When,
The bit error rate input step (S1) in which the bit error rate of the test signal is input, and
Among the plurality of FEC code words included in the test signal, the error FEC symbol in which the number of the error FEC symbols included in the FEC code word having the error FEC symbol which is the FEC symbol to which the error is added is input. Number input step (S1) and
In the error bit number input step (S1) in which the number of error bits included in the error FEC symbol is input,
A CW size input step (S1) in which the number of bits constituting the FEC codeword is input, and
The bit error rate input to the bit error rate input step, the number of error FEC symbols input to the error FEC symbol number input step, the number of error bits input to the error bit number input step, and the number of error bits input to the error bit number input step. , The minimum number of the FEC code words required to realize the bit error rate based on the number of the bits input to the CW size input step, and the said FEC code words included in the minimum number. Including a CW number calculation step (S2) for calculating the number of FEC code words having an erroneous FEC symbol.
In the error signal generation step, the minimum number of consecutive FEC code words calculated by the CW number calculation step is a FEC code word having the number of the error FEC symbols calculated by the CW number calculation step. A FEC error addition method, characterized in that the error signal for generating the test signal including the test signal is output. In the error signal generation step, in the minimum number of consecutive FEC codewords in the test signal, a pattern including one FEC codeword having the error FEC symbol for every n FEC codewords is repeated m times. The fourth aspect of the present invention is characterized in that the error signal is generated so that the pattern including the FEC codeword having one error FEC symbol for every n + 1 FEC codewords is repeated p times. FEC error addition method.

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