JP6776367B2 - 金属配線層形成方法、金属配線層形成装置および記憶媒体 - Google Patents
金属配線層形成方法、金属配線層形成装置および記憶媒体 Download PDFInfo
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Description
2a 表面
3 凹部
3a 底面
3b 側面
4 タングステンまたはタングステン合金
5 触媒
7 第1めっき層
7a 異物めっき層
8 第2めっき層
10 金属配線層形成装置
11 触媒付与部
12 触媒洗浄部
13 第1めっき層形成部
14 UV処理部または加熱処理部
16 第2めっき層形成部
20 制御装置
21 記憶媒体
Claims (8)
- 基板に対して金属配線層を形成する金属配線層形成方法において、
底面に下部電極が形成された凹部を有する基板を準備する工程と、
前記基板に対して第1めっき処理を施すことにより、少なくとも前記凹部の下部電極上に保護層としての第1めっき層を形成するとともに、基板表面に前記第1めっき層と同一材料からなるめっき層が異物めっき層として付着する工程と、
前記基板を洗浄して前記第1めっき層と同時に形成された前記基板表面に付着する前記異物めっき層を除去する工程と、
前記基板に対して第2めっき処理を施すことにより、前記凹部内の前記第1めっき層上に第2めっき層を形成する工程と、を備えたことを特徴とする金属配線層形成方法。 - 前記異物めっき層を除去する工程の前に、前記基板に対して触媒を付与する工程と、
前記基板を予備洗浄して前記下部電極に形成された触媒以外の触媒を除去する工程とを更に備えたことを特徴とする請求項1記載の金属配線層形成方法。 - 前記第1めっき層を形成する工程と、前記異物めっき層を除去する工程との間に、前記基板に対してUV処理または加熱処理を施して前記異物めっき層の除去を容易とすることを特徴とする請求項1または2記載の金属配線層形成方法。
- 前記下部電極はタングステンまたはタングステン合金を含み、前記第1めっき層および前記第2めっき層はコバルトまたはコバルト合金を含むことを特徴とする請求項1乃至3のいずれか記載の金属配線層形成方法。
- 基板に対して金属配線層を形成する金属配線層形成装置において、
底面に下部電極が形成された凹部を有する基板に対して第1めっき処理を施すことにより、少なくとも前記凹部の下部電極上に保護層としての第1めっき層を形成するとともに、基板表面に前記第1めっき層と同一材料からなるめっき層が異物めっき層として付着する第1めっき層形成部と、
前記基板を洗浄して前記第1めっき層と同時に形成された前記基板表面に付着する前記異物めっき層を除去する異物めっき層洗浄部と、
前記基板に対して第2めっき処理を施すことにより、前記凹部内の前記第1めっき層上に第2めっき層を形成する第2めっき層形成部と、を備えたことを特徴とする金属配線層形成装置。 - 前記基板に対して触媒を付与する触媒付与部と、
前記基板を予備洗浄して前記下部電極に形成された触媒以外の触媒を除去する触媒洗浄部を更に備えたことを特徴とする請求項5記載の金属配線層形成装置。 - 前記基板に対してUV処理または加熱処理を施して前記異物めっき層の除去を容易とするUV処理部または加熱処理部を設けたことを特徴とする請求項5または6記載の金属配線層形成装置。
- コンピュータに金属配線形成方法を実行させるためのコンピュータプログラムを格納した記憶媒体において、
金属配線層形成方法は、
基板に対して金属配線層を形成する金属配線層形成方法において、
底面に下部電極が形成された凹部を有する基板を準備する工程と、
前記基板に対して第1めっき処理を施すことにより、少なくとも前記凹部の下部電極上に保護層としての第1めっき層を形成するとともに、基板表面に前記第1めっき層と同一材料からなるめっき層が異物めっき層として付着する工程と、
前記基板を洗浄して前記第1めっき層と同時に形成された前記基板表面に付着する前記異物めっき層を除去する工程と、
前記基板に対して第2めっき処理を施すことにより、前記凹部内の前記第1めっき層上に第2めっき層を形成する工程と、を備えたことを特徴とする記憶媒体。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016203758 | 2016-10-17 | ||
| JP2016203758 | 2016-10-17 | ||
| PCT/JP2017/030991 WO2018074072A1 (ja) | 2016-10-17 | 2017-08-29 | 金属配線層形成方法、金属配線層形成装置および記憶媒体 |
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| Publication Number | Publication Date |
|---|---|
| JPWO2018074072A1 JPWO2018074072A1 (ja) | 2019-08-08 |
| JP6776367B2 true JP6776367B2 (ja) | 2020-10-28 |
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| JPH05166939A (ja) * | 1991-12-19 | 1993-07-02 | Nissan Motor Co Ltd | 多層配線層の形成方法 |
| KR100434946B1 (ko) * | 2001-09-28 | 2004-06-10 | 학교법인 성균관대학 | 무전해도금방식을 이용한 반도체 소자의 구리배선형성방법 |
| US20050067295A1 (en) * | 2003-09-25 | 2005-03-31 | Dory Thomas S. | Deep via seed repair using electroless plating chemistry |
| US7998857B2 (en) * | 2007-10-24 | 2011-08-16 | Intel Corporation | Integrated circuit and process for fabricating thereof |
| JP5486821B2 (ja) | 2009-02-12 | 2014-05-07 | 学校法人 関西大学 | 無電解銅めっき方法、及び埋め込み配線の形成方法 |
| US8895441B2 (en) * | 2012-02-24 | 2014-11-25 | Lam Research Corporation | Methods and materials for anchoring gapfill metals |
| SG11201509673SA (en) * | 2013-06-17 | 2016-01-28 | Applied Materials Inc | Method for copper plating through silicon vias using wet wafer back contact |
| JP6054279B2 (ja) * | 2013-10-17 | 2016-12-27 | 東京エレクトロン株式会社 | 金属配線層形成方法、金属配線層形成装置および記憶媒体 |
| JP6121348B2 (ja) * | 2014-02-28 | 2017-04-26 | 東京エレクトロン株式会社 | めっきの前処理方法、記憶媒体およびめっき処理システム |
| JP6527030B2 (ja) * | 2015-06-19 | 2019-06-05 | 東京エレクトロン株式会社 | めっき処理方法及びめっき処理部品並びにめっき処理システム |
| US9935004B2 (en) * | 2016-01-21 | 2018-04-03 | Applied Materials, Inc. | Process and chemistry of plating of through silicon vias |
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| CN109715852A (zh) | 2019-05-03 |
| TWI745443B (zh) | 2021-11-11 |
| US20190229016A1 (en) | 2019-07-25 |
| KR102424817B1 (ko) | 2022-07-25 |
| KR20190064569A (ko) | 2019-06-10 |
| WO2018074072A1 (ja) | 2018-04-26 |
| JPWO2018074072A1 (ja) | 2019-08-08 |
| US10755973B2 (en) | 2020-08-25 |
| TW201830486A (zh) | 2018-08-16 |
| CN109715852B (zh) | 2021-09-21 |
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