JP6788738B2 - Solid-state image sensor and manufacturing method of solid-state image sensor - Google Patents

Description

The present invention relates to a solid-state image sensor and a method for manufacturing the solid-state image sensor.

Conventionally, the signal charge from the photodiode section is completely transferred to the charge holding section, and then the charge is completely transferred to the charge detection section in sequence line by line to realize global shutter operation and further suppress noise and afterimages. There is known a solid-state image sensor capable of obtaining an electric charge (see, for example, Patent Document 1).

Japanese Patent Publication "Japanese Patent Laid-Open No. 2004-111590 (published April 08, 2004)"

However, in the conventional technique as described above, the noise charge generated at the silicon / silicon oxide film interface state is accumulated in the charge holding portion during the charge holding period, and the difference in image noise due to the difference in the read timing for each row is caused. There is a problem that causes it.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique capable of suppressing noise charges.

In order to solve the above problems, the solid-state imaging device according to the present invention is a solid-state imaging device provided with a plurality of unit pixels provided on a semiconductor substrate, and each of the unit pixels converts light into a signal charge. A photodiode section that generates electric charge by photoelectric conversion, a first charge transfer section adjacent to the photodiode section and covered with a first gate electrode, and a first gate electrode covered with the first gate electrode. A charge holding portion including a first conductive semiconductor region that holds the charge transferred from the photodiode section by the charge transfer section 1, and a second gate electrode section adjacent to the charge holding section and covered with a second gate electrode section. A charge transfer unit and a charge discharge unit which is adjacent to the photodiode unit at a portion different from the first gate electrode and is covered with a third gate electrode, and the photodiode unit and the first charge transfer unit are provided. The semiconductor surfaces of the charge holding portion, the second charge transfer portion, and the charge discharging portion are all covered with the second conductive semiconductor region.

According to one aspect of the present invention, noise charge is suppressed.

It is a figure which shows the schematic structure of the solid-state image sensor which concerns on embodiment of this invention. It is an equivalent circuit diagram which shows the structure of the unit pixel in the image pickup part of a solid-state image sensor. It is sectional drawing of a unit pixel. It is a figure which shows the 1st step of the manufacturing process of a unit pixel. It is a figure which shows the 2nd step of the manufacturing process of a unit pixel. It is a figure which shows the 3rd step of the manufacturing process of a unit pixel. It is a figure which shows the 4th step of the manufacturing process of a unit pixel. It is a figure which shows the 5th step of the manufacturing process of a unit pixel. It is a figure which shows the 6th step of the manufacturing process of a unit pixel.

[Structure of solid-state image sensor 1]
Hereinafter, embodiments of the present invention will be described in detail. In the present embodiment, a CMOS image sensor, which is an example of a solid-state image sensor in which two different field-effect transistors, a P-type layer MOS and an N-type layer MOS, are connected so as to complement each other's characteristics is used. explain.

FIG. 1 is a diagram showing a schematic configuration of a solid-state image sensor 1 according to an embodiment of the present invention. The solid-state image sensor 1 includes a plurality of unit pixels 10 arranged in a plurality of rows and a plurality of columns.

Further, the solid-state imaging device 1 includes a vertical scanning circuit 3 that vertically transfers the signal charge from each unit pixel 10, and a horizontal scanning circuit 4 that transfers the signal charge from each unit pixel in the horizontal direction. There is.

Although only a part of the rows and columns of the solid-state image sensor 1 is shown in FIG. 1, dozens to thousands of unit pixels 10 are arranged in each row and each example of the solid-state image sensor 1.

The vertical scanning circuit 3 and the horizontal scanning circuit 4 are composed of, for example, shift registers, and perform scanning in response to a pulse signal emitted by a control circuit (not shown). A pulse signal for driving each unit pixel is sent to each unit pixel 10 via the vertical control line 5. In each unit pixel 10, the wiring through which the pulse signal flows may be arranged in either the row direction or the column direction.

The output signal from each unit pixel 10 is transmitted from the vertical signal line 6 to the horizontal signal line 7, then driven by the horizontal selection signal from the horizontal scanning circuit 4 and supplied to the output buffer 8. A circuit for removing noise, an amplifier circuit, an analog-digital conversion circuit, and the like are appropriately arranged between the vertical signal line 6 and the horizontal signal line 7 for the output signal from each unit pixel 10. May be good.

FIG. 2 is an equivalent circuit diagram showing the configuration of the unit pixel 10 in the image pickup unit 2 of the solid-state image pickup device 1. As shown in FIG. 2, the unit pixel 10 includes a photodiode unit 130 that photoelectrically converts light into signal charges and stores the charges generated by the photoelectric conversion in the first conductive type (n type) semiconductor region. ..

The photodiode unit 130 includes a first conductive type (n type) semiconductor region and a second conductive type (p type) semiconductor region. The photodiode unit 130 converts the incident light into electrons and holes in the depletion layer of the first conductive semiconductor region and the second conductive semiconductor region. In the photodiode section 130, the generated electrons and holes flow and accumulate in the first conductive semiconductor region and the holes flow into the second conductive semiconductor region, respectively.

In the following description, n-type and N represent the first conductive type, and p-type and P represent the second conductive type.

Further, the unit pixel 10 has a transfer gate unit (first charge transfer unit) 103A adjacent to the photodiode unit 130 and a charge holding unit 131 that holds the signal charge transferred from the photodiode unit 130 by the transfer gate unit 103A. And have. Further, the unit pixel 10 includes a read selection transistor (second charge transfer unit) 103B adjacent to the charge holding unit 131, and a reset transistor 135.

Further, the unit pixel 10 is a vertical selection transistor 140 having a gate connected to the vertical selection line 142, a floating diffusion 150 which is an example of a charge injection unit having a function of a charge storage unit, and a potential of the floating diffusion 150. It includes an amplification transistor 160 having a source follower configuration, which is an example of a detection element that detects a change.

Further, the unit pixel 10 includes a pixel signal generation unit 170 having an FDA (Floating Diffusion Amplifier) configuration including a floating diffusion 150, which is an example of a charge injection unit having a function of a charge storage unit, and a charge discharge unit 180. I have.

Further, as shown in FIG. 2, the unit pixel 10 of the solid-state image sensor 1 includes a signal processing circuit 201 to which the output signal line 200 is connected for each column.

The source of the transfer gate unit 103A is connected to the cathode of the photodiode unit 130. The read selection transistor 103B is connected to a floating diffusion 150 whose drain is a storage unit.

The source unit of the charge discharge unit 180 is connected to the photodiode unit 130, and when the transistor is ON, all the charges accumulated in the photodiode unit 130 are discharged to the drain unit. Further, the charge discharge unit 180 is set to the potential of the channel unit so as to discharge the excess charge that does not contribute to image formation among the signal charges generated by the photodiode unit 130 in the transistor OFF state.

In the reset transistor 135, the source is connected to the floating diffusion 150, the drain is connected to the power supply VDD, and the reset pulse is input to the gate. When electrically conducted, the reset transistor 135 is configured so that the electric charge held in the floating diffusion 150 flows out to the power supply VDD via the reset transistor 135 to return the potential state of the floating diffusion 150 to the initial level. ing.

In the amplification transistor 160, the gate is connected to the floating diffusion 150, the drain is connected to the power supply VDD, and the source is connected to the drain of the vertical selection transistor 140.

In the vertical selection transistor 140, the drain is connected to the amplification transistor 160, the source is connected to the output signal line 200, and the gate is connected to the vertical selection line 142 to which the vertical selection signal is input.

When the vertical selection transistor 140 of the unit pixel 10 is turned on, the signal charge read by the floating diffusion 150 is amplified by the amplification transistor 160 and output to the output signal line 200.

Subsequently, the cross-sectional structure of the unit pixel 10 will be described with reference to FIG. FIG. 3 is a cross-sectional view of the unit pixel 10. As shown in FIG. 3, in the unit pixel 10, a p-type well (embedded semiconductor layer) which is a p-type layer forming a substrate-side potential barrier in a semiconductor substrate 100 (n ^- type Si substrate) made of silicon. 101 is formed.

An n ^- type well 132, which is an n-type layer, and a first semiconductor well region 102 (p-type layer) adjacent to the n ^- type well 132 are formed on the p-type well 101.

On the other hand, as shown in FIG. 3, the substrate surface of the unit pixel 10 is entirely covered with the gate oxide film 119. Further, on the gate oxide film 119, the gate electrode (third gate electrode) 111 of the charge discharging portion 180, the gate electrode (first gate electrode) 109 common to the transfer gate portion 103A and the charge holding portion 131. , The gate electrode (second gate electrode) 110 of the read selection transistor 103B and the gate electrode 112 of the reset transistor 135 are formed.

The gate electrode (third gate electrode) 111 of the charge discharging unit 180, the gate electrode (first gate electrode) 109 common to the transfer gate unit 103A and the charge holding unit 131, and the gate electrode (third) of the read selection transistor 103B. The gate electrode (2) 110 and the gate electrode 112 of the reset transistor 135 are formed in a single-layer or two-layer structure by, for example, polysilicon. A read pulse is input to the gate electrode (second gate electrode) 110 of the read selection transistor 103B. A reset pulse is input to the gate electrode 112 of the reset transistor 135.

Further, a storage pulse is input to the gate electrode (first gate electrode) 109 common to the transfer gate unit 103A and the charge holding unit 131.

Further, a global reset pulse is input to the gate electrode (third gate electrode) 111 of the charge discharging unit 180.

Further, signal lines OFG, TRX, TRG, and RST are connected to the gate electrode 111, the gate electrode 109, the gate electrode 110, and the gate electrode 112, respectively.

As shown in the cross-sectional view of FIG. 3, the unit pixel 10 includes a photodiode unit 130, a transfer gate unit (first charge transfer unit) 103A, a charge holding unit 131, and a read / selection transistor (second charge transfer unit). A charge transfer unit) 103B, an amplification transistor (not shown), a floating diffusion N ⁺ region 114, and a charge discharge unit 180 are provided.

The photodiode portion 130 is formed to include a photodiode surface P ⁺ layer 113 and a photodiode N region 104. Further, a gate overlap portion surface P ^- layer 105 is formed on the surface side of the photodiode N region 104, which is a region adjacent to the photodiode surface P ⁺ layer 113. The photodiode unit 130 converts the incident light into electrons and holes in the depletion layer. In the photodiode section 130, electrons and holes generated in the depletion layer flow and accumulate in the photodiode N region 104 for electrons and in the photodiode surface P ⁺ layer 113.

A transfer gate unit (first charge transfer unit) 103A and a charge holding unit 131 are formed horizontally side by side between the photodiode unit 130 and the read / selection transistor 103B.

The transfer gate portion (first charge transfer portion) 103A is adjacent to the photodiode portion 130, and the gate electrode 109 described above is arranged on the substrate surface by, for example, polysilicon.

Further, as shown in FIG. 3, a surface P ^- layer 103 under the gate is formed in a region adjacent to the charge holding portion 131.

Further, as shown in FIG. 3, a floating diffusion N ⁺ region 114 is formed on the surface side adjacent to the surface P ⁻ layer 103 under the gate. Further, as shown in FIG. 3, a drain portion N ⁺ region 115 is also formed at a position adjacent to the n region of the reset transistor 135.

As shown in FIG. 3, the floating diffusion 150 is formed to include a floating diffusion N ⁺ region 114.

Further, as shown in FIG. 3, the unit pixel 10 is separated from other pixel units by the element separation region 120.

The charge holding unit 131 has a function of holding the electric charge transferred from the photodiode unit 130 via the transfer gate unit (first charge transfer unit) 103A in the first conductive semiconductor region. The above-mentioned gate electrode 109 is arranged on the substrate surface of the charge holding portion 131, for example, by polysilicon.

From the surface side of the substrate, the charge holding portion 131 includes a charge holding portion surface P layer 108 which is a second conductive semiconductor region, a charge holding portion N region 107 which is a first conductive semiconductor region, and a second conductive semiconductor region. It has a three-layer structure with the P layer 106 under the charge holding portion. In other words, the charge holding portion 131 is formed by the charge holding portion surface P layer 108 from the substrate front surface side (gate oxide film 119 side) and by the charge holding portion lower P layer 106 from the substrate back surface side (in other words, the semiconductor substrate 100 side). It is formed to include a sandwiched charge holding portion N region 107.

In this way, by surrounding the upper and lower sides of the charge holding portion N region 107 that holds the charge with the charge holding portion surface P layer 108 and the charge holding portion lower P layer 106, the depletion is a neutral region between the P layer and the N layer. Layer elongation is suppressed. As a result, the junction capacitance between the P layer and the N layer is increased, and the amount of charge that can be held by the charge holding unit 131 can be efficiently increased.

Further, the unit pixel 10 inputs a global reset pulse to the gate electrode 111 of the charge discharge unit 180 to simultaneously discharge all the charges of the photodiode units 130 of all the pixels (global reset operation), and then causes the photodiode unit 130 to operate for a certain period of time. After the exposure, the signal charge accumulated in the photodiode unit 130 is input to the gate electrode (first gate electrode, first transfer gate electrode) 109 as a storage pulse to be transferred to the charge holding unit 131 at the same time for all pixels. Therefore, it is possible to realize a global shutter function which is an electronic shutter function that does not cause a difference in storage time.

As described above, the substrate surface of the unit pixel 10 is covered with the second conductive type (p-type) semiconductor regions 103, 105, 113, and 108 except for the drain portion N ⁺ region 115 floating diffusion N ⁺ region 114. As described above, the unit pixel 10 includes a gate electrode (third gate electrode) 111, a photodiode portion 130, a gate electrode (first gate electrode, first transfer gate electrode) 109, a charge holding portion 131, and the like. , A gate oxide film 119 connected to the gate electrode (second gate electrode) 110 is formed.

According to these configurations, noise electrons generated inside the unit pixel 10 are trapped in holes existing in the second conductive type (p-type) semiconductor regions 103, 105, 113, and 108. Therefore, it is possible to prevent noise electrons generated inside the unit pixel 10 from being mixed in the pixel output.

Further, the impurity concentration of the photodiode surface P ⁺ layer 113, which is the second conductive semiconductor surface region of the photodiode portion 130, is the concentration C1, and the charge holding portion surface P layer, which is the second conductive semiconductor surface region of the charge holding portion 131. The impurity concentration of 108 is the concentration C2, and the impurity concentration of the read-selection transistor 103B directly under the gate electrode (second gate electrode) 110 is the concentration C3 (more generally, the semiconductor surface other than the photodiode portion 130 and the charge holding portion 131). The relationship between the respective concentrations C1, C2, and C3 when the density C3) of the second conductive semiconductor surface region is set to C1>C2> C3. According to this configuration, the hole concentration distribution required for each part is determined according to the difference in the structure of each part such as the presence or absence of the gate electrode and whether or not there is an N-type semiconductor region directly under the gate oxide film 119 on the semiconductor surface. It is formed. By the above action, it is possible to suppress the noise change for each line due to the deviation of the reading timing from the charge holding unit.

[Manufacturing method of unit pixel 10]
Next, a method of manufacturing the unit pixel 10 will be described with reference to FIGS. 4 to 9. The method for manufacturing the unit pixel 10 described below is executed by, for example, the semiconductor manufacturing apparatus according to the present embodiment, which includes an ion implantation unit for implanting ions and a photomask setting unit for setting a photomask.

The unit pixel 10 has a p-type well 101 formed on the semiconductor substrate 100, an n ^- type well 132 on the p-type well 101, and a first semiconductor well region 102 adjacent to the n ^- type well 132. , Is formed and the photoresist 190 is arranged as a photomask on the surface of the semiconductor whose entire surface is covered with the gate oxide film 119, and ions are implanted into the n ^- type well 132 and the first semiconductor well region 102. It is formed by doing.

(1st step)
FIG. 4 is a diagram showing a first step in the manufacturing process of the unit pixel 10. In this first step, first, the surface of the semiconductor outside the region forming the photodiode portion 130 is covered with the photoresist 190A. Then, n ^- ions are implanted into the mold well 132, the photodiode N region 104, and the gate overlap portion surface P ^- layer 105 is formed of the same photomask.

(Second step)
Next, in the second step of the manufacturing process of the unit pixel 10 shown in FIG. 5, an ion implantation step of forming the charge holding portion 131 is performed. First, the surface of the semiconductor outside the region forming the charge holding portion 131 is covered with the photoresist 190B. Then, ions are implanted into the first semiconductor well region 102.

This ion injection step includes a first step of forming the charge holding portion lower P layer 106 by ion injection, and a second step of forming the charge holding portion N region 107 by ion injection after the first step. After the second step, a third step of forming the charge holding portion surface P layer 108 by ion injection is included, and the first step, the second step, and the third step are described. Performed using the same photomask.

(Third step)
After forming the charge holding portion 131, in the third step of the manufacturing process of the unit pixel 10 shown in FIG. 6, the gate electrode 112 portion of the reset transistor 135 is covered with the photoresist 190C to form the gate electrode 112 of the reset transistor 135. Ion implantation is performed outside the region. As a result, the surface P ^- layer 103 under the gate is formed. The lower surface P ^- layer 103 of the gate is configured as the transfer gate portion 103A, the read / selection transistor 103B, and the charge discharge portion 180 described above.

(4th step)
After the surface P ^- layer 103 under the gate is formed, in the fourth step of the manufacturing process of the unit pixel 10 shown in FIG. 7, the outside of the region where the reset transistor 135 is formed is covered with the photoresist 190D, and ion implantation is performed to reset. The transistor N region 116 is formed.

Further, in the unit pixel 10, a gate electrode 111, a gate electrode 109, a gate electrode 110, and a gate electrode 112 are formed by gate oxidation, polysilicon depot, gate electrode photolithography, and dry etching steps (not shown).

(Fifth step)
Subsequently, in the fifth step of the manufacturing process of the unit pixel 10 shown in FIG. 8, the photoresist 190E and the gate electrode 111, the gate electrode 109, the gate electrode 110, and the gate electrode 112 are used as photomasks to form ions. Implantation is performed to form the photodiode surface P ⁺ layer 113 of the photodiode portion 130.

(6th step)
After the photodiode portion 130 is formed in this way, in the sixth step of the manufacturing process of the unit pixel 10 shown in FIG. 9, the photoresist 190F, the gate electrode 111, the gate electrode 109, and the gate electrode 110 are photomasked. Ion implantation is performed to form a floating diffusion N ⁺ region 114 and an element separation region (rain portion N ⁺ region) 120.

[Additional notes]
By the way, when the positional relationship between the charge holding portion N region 107, the charge holding portion lower P layer 106, and the charge holding portion surface P layer 108 is deviated, the transfer to the read selection transistor (second charge transfer unit) 103B is performed. The characteristics deteriorate sharply. According to the manufacturing method described above, the charge holding portion lower P layer 106, the charge holding portion N region 107, and the charge holding portion surface P layer 108 are formed by ion implantation using the same photoresist as a photomask. As a result, the formed regions of the charge holding portion lower P layer 106, the charge holding portion N region 107, and the charge holding portion surface P layer 108 do not shift from each other, and deterioration of transfer characteristics due to manufacturing variations can be avoided. ..

[Summary]
The solid-state imaging device 1 according to the first aspect of the present invention is a solid-state imaging device 1 provided with a plurality of unit pixels 10 provided on the semiconductor substrate 100, and each of the unit pixels 10 photoelectrically converts light into a signal charge. A photodiode section 130 that generates an electric charge by conversion, a transfer gate section (first charge transfer section) 103A adjacent to the photodiode section and covered with a first gate electrode 109, and the first gate. Charges including the charge holding portion N region (first conductive semiconductor region) 107 which is covered with the electrode 109 and holds the charge transferred from the photodiode section 130 by the transfer gate section (first charge transfer section) 103A. The holding portion 131, the read-selection transistor 103B adjacent to the charge holding portion 131 and covered with the second gate electrode 110, and the photodiode portion 130 adjacent to the third gate electrode at a portion different from the first gate electrode. A charge discharging part 180 covered with a gate electrode 111 is provided, and the semiconductor surface of the photodiode part 130, the transfer gate part 103A, the charge holding part 131, the read selection transistor 103B, and the charge discharging part 180 are all second. It is covered with conductive semiconductor regions 103, 105, 113, 108.

According to the above configuration, after all the charges of the photodiode units 130 of all pixels are simultaneously discharged (global reset operation) through the charge discharge unit 180, the signal charges accumulated in the photodiode unit 130 for a certain period of time are used as the first gate. By simultaneously transferring all the pixels to the charge holding unit 131 by the electrode 109, it is possible to realize the global shutter function, which is an electronic shutter function that does not cause a difference in storage time.

Further, according to this configuration, noise electrons generated inside the unit pixel 10 are trapped in holes existing in the second conductive type (p type) semiconductor regions 103, 105, 113, and 108. Therefore, it is possible to prevent noise electrons generated inside the unit pixel 10 from being mixed in the pixel output.

Further, the charge holding portion N region (first conductive semiconductor region) 107 is formed by the second conductive semiconductor region (charge holding portion surface P layer, charge holding portion lower P layer) 108, 106 from the substrate front surface side and the substrate back surface side. May be sandwiched between. According to this configuration, in the charge holding portion 131, since the N layer holding the charge is sandwiched between the P layers, the elongation of the depletion layer, which is the neutral region of the P layer and the N layer, is suppressed. As a result, the junction capacitance between the P layer and the N layer is increased, and the amount of charge that can be held by the charge holding unit 131 can be efficiently increased.

In the solid imaging apparatus 1 according to the second aspect of the present invention, in the above aspect 1, the density C1 of the photodiode surface P ⁺ layer 113 of the photodiode section 130 and the charge holding portion surface P layer 108 of the charge holding section 131 The relationship between the concentration C2 of the P layer 106 under the charge holding portion and the concentration C3 of the P layer on the other semiconductor surface may be C1>C2> C3.

According to the above configuration, the structure of each part differs depending on the presence or absence of the gate electrode and whether or not there is an N-type semiconductor region directly under the second conductive type (p-type) semiconductor regions 103, 105, 113, 108. Therefore, the required hole concentration distribution is formed in each part. As a result, it is possible to suppress a noise change for each row due to a deviation in the reading timing from the charge holding unit 131.

The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Is also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

1 Solid-state imaging device 2 Imaging unit 3 Vertical scanning circuit 4 Horizontal scanning circuit 5 Vertical control line 6 Vertical signal line 7 Horizontal signal line 8 Output buffer 10 Unit pixel 135 Reset transistor 140 Vertical selection transistor 100 Semiconductor substrate 101 p-type well 102 Semiconductor well region 103 Gate lower surface P ^- layer 103A Transfer gate unit (first charge transfer unit)
103B Read selection transistor (second charge transfer unit)
104 Photodiode N region 105 Gate overlap surface P ^- layer 106 Charge holding part lower P layer 107 Charge holding part N region 108 Charge holding part surface P layer 109 Gate electrode (first gate electrode)
110 Gate electrode (second gate electrode)
111 Gate electrode (third gate electrode)
112 Gate electrode 113 Photodiode surface P ⁺ layer 114 Floating diffusion N ⁺ area 115 Drain part N ⁺ area 116 Reset transistor N area 119 Gate oxide film 120 Element separation area 130 Photodiode part 131 Charge holding part 132 n ^- type well 135 Reset Transistor 140 Vertical selection transistor 142 Vertical selection line 150 Floating diffusion 160 Amplification transistor 170 Pixel signal generator 180 Charge discharge unit 190, 190A, 190B, 190C, 190D, 190E, 190F photodiode 200 Output signal line 201 Signal processing circuit Vdd Power supply

Claims (2)

A solid-state image sensor equipped with a plurality of unit pixels provided on a semiconductor substrate.
Each of the above unit pixels
A photodiode section that generates an electric charge by photoelectrically converting light into an electric charge,
A first charge transfer section adjacent to the photodiode section and covered with a first gate electrode,
A charge holding portion that is covered with the first gate electrode and includes a first conductive semiconductor region that holds the charge transferred from the photodiode section by the first charge transfer section.
A second charge transfer unit adjacent to the charge holding unit and covered with a second gate electrode,
A charge discharging part adjacent to the photodiode part at a portion different from the first gate electrode and covered with the third gate electrode,
With
The semiconductor surfaces of the photodiode section, the first charge transfer section, the charge holding section, the second charge transfer section, and the charge discharging section are all covered with the second conductive semiconductor region.
The density C1 of the second conductive semiconductor surface region of the photodiode section, the concentration C2 of the second conductive semiconductor surface region of the charge holding section, the first charge transfer section, and the second charge transfer. A solid-state imaging device characterized in that the relationship between the portion and the concentration C3 of the second conductive semiconductor surface region of the charge discharging portion is C1>C2> C3. The solid-state image sensor according to claim 1, wherein the semiconductor surface is further covered with a gate oxide film.

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