JP6789709B2 - Imaging device - Google Patents

Description

The present invention relates to an image pickup device including an image pickup device, and more particularly to an image pickup device having an AD circuit in the image pickup device.

In recent years, an image sensor mounted on an image pickup device has been required to support a high pixel count and a high frame rate.

Higher pixel count and higher frame rate indicate an increase in the number of pixels per frame to be recorded and an increase in the number of frames acquired per second. In order to cope with these, the read speed is increased. I had to go.

Patent Document 1 discloses a technique for performing high-speed reading by performing an analog signal reading operation and an AD conversion operation in parallel in an image sensor equipped with an AD circuit.

Japanese Patent Application No. 2008-283966

Although the technique described in Patent Document 1 performs analog signal reading and AD conversion in parallel, there is a concern that the AD conversion operation affects the analog signals read in parallel and causes noise. On the contrary, the reading operation of the analog signal affects the AD conversion operation in parallel, and there is a concern that it also causes noise.

In view of the above problems, an object of the present invention is to provide an imaging device capable of performing AD conversion operation and analog signal reading operation at appropriate timings and enabling high-speed reading.

In order to achieve the above object, the image pickup device according to the present invention is an image pickup device having a plurality of pixels in a matrix, and is a mode setting means for setting a drive mode for reading out the plurality of pixels, and the plurality of pixels. A plurality of output lines provided for each column for outputting the signal of the above, a plurality of holding means provided for each of the plurality of output lines and for holding the signal output to the output line, and the plurality of holding means. A plurality of AD conversion means for AD conversion of the signal held by the holding means, and a plurality of first signals and a plurality of second signals output from the plurality of pixels to the plurality of output lines, respectively. The first signal includes an adding means for adding and a switching means for switching a holding means for holding the first signal and the second signal added by the adding means, respectively. The first signal includes a reset signal, the second signal includes a signal based on the charge generated in the pixel, and the switch means is added by the addition means as a drive mode set by the mode setting means. The signal and the second signal are switched to be held in different holding means, and the plurality of AD conversion means are held in the different holding means, respectively, and the added first signal and the second signal are held. It is characterized by including a drive mode in which the signals of are AD-converted in parallel .

It is possible to provide an image pickup apparatus capable of high-speed reading by performing an AD conversion operation and an analog signal reading operation at appropriate timings.

It is a block diagram of the image pickup apparatus which concerns on this invention. It is an equivalent circuit diagram of the image pickup device which concerns on 1st Embodiment. It is an equivalent circuit diagram of the unit pixel which concerns on 1st Embodiment. It is a timing chart of still image drive which concerns on 1st Embodiment. It is a moving image drive timing chart which concerns on 1st Embodiment. It is a simple timing chart of the conventional drive and the drive of the present invention which concerns on 1st Embodiment. It is an equivalent circuit diagram of the image pickup device which concerns on 2nd Embodiment. It is an equivalent circuit diagram of the unit pixel which concerns on 2nd Embodiment. It is a moving image drive timing chart which concerns on 2nd Embodiment. It is a simple timing chart of the conventional drive and the drive of the present invention concerning the second embodiment. It is an equivalent circuit diagram of the image pickup device which concerns on 3rd Embodiment. It is a moving image drive timing chart which concerns on 3rd Embodiment. It is an equivalent circuit diagram of the image pickup device which concerns on 3rd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The imaging device of the present embodiment can be applied to, for example, an electronic still camera with a moving image function or a mobile phone with a camera function. Further, the content is not limited to the content of the present embodiment, and various modifications may be performed.

(First Embodiment)
FIG. 1 is a block diagram showing an example of an imaging device according to the present embodiment. In FIG. 1, 101 is a lens unit that forms an optical image of a subject on an image sensor 105. The lens unit 101 includes a zoom mechanism for changing a focal length (not shown), a focus mechanism for changing the focal position, an aperture mechanism for adjusting the amount of incident light, and the like. Further, in each mechanism, zoom control, focus control, aperture control and the like are performed by the lens driving device 102.

The 103 is a mechanical shutter and is controlled by the shutter drive device 104. Instead of providing the mechanical shutter 103 as in the present embodiment, the electronic shutter provided in the image sensor 105 described later may be used.

Reference numeral 105 denotes an image sensor for capturing the subject imaged by the lens unit 101 as an image signal, and 106 performs various corrections to the image signal output from the image sensor 105 and compresses image data generated from the image signal. It is an image sensor processing circuit. In the present embodiment, the image sensor 105 may be a solid-state image sensor such as a CMOS sensor including an AD conversion unit and various correction circuits, or a photoelectric conversion film type image sensor using a conductive organic thin film. You may. Further, the image pickup signal processing circuit 106 includes not only a defect correction processing circuit for correcting defects and non-uniformity of the image signal output from the image pickup element 105, but also white balance processing for adjusting the color balance of the image signal. An image processing circuit such as a development process may be included.

Reference numeral 107 denotes a timing generation circuit which is a driving means for outputting various timing signals to the image sensor 105 and the image signal processing circuit 106. The timing generation circuit 107 transmits a periodic synchronization signal and a control signal for driving various circuits to the image sensor 105 and the image signal processing circuit 106. Further, the timing generation circuit 107 may transmit a setting parameter or the like indicating an operation mode or the like by using serial communication or the like as a control signal, or may receive each operation state as operation information. Further, the timing generation circuit 107 may be included in the image sensor 105 or the control circuit 109 described later.

Reference numeral 108 denotes a memory for temporarily storing various data, and can temporarily store image data output from the image pickup signal processing circuit 106, intermediate data in a predetermined process, and the like.

Reference numeral 109 denotes a control circuit that controls various operations and the entire image pickup apparatus 100. For example, it is a microcontroller composed of a CPU, a ROM, a RAM, and the like, and by executing a program stored in the ROM and the like, each part of the image pickup apparatus 100 is collectively controlled. Further, the ROM may be, for example, a recording medium such as a non-volatile memory or a memory card for recording image data or the like processed by the CPU. The CPU executes various instructions included in the program stored in the program and outputs the processing result. The ROM and RAM are used as a program storage area executed by the CPU, a work area during program execution, a data storage area, and the like.

Reference numeral 110 denotes an interface (I / F) for recording or reading on the recording medium, and reference numeral 111 is a removable recording medium such as a semiconductor memory for recording or reading image data.

Reference numeral 112 denotes a display unit for displaying various information and captured images. Further, the operation instruction from the user may be received including the touch panel and the like.

Reference numeral 113 denotes a photometric device for measuring the brightness of the subject in the direction of the optical axis of the lens unit 101. The photometric result of the photometric device 113 is input to the control circuit 109 and used for controlling the lens drive device 102 and the shutter drive device 104.

Reference numeral 114 denotes a distance measuring device for measuring the distance of the lens unit 101 to the subject in the optical axis direction. The distance measurement result by the distance measuring device 114 is input to the control circuit 109 and used for focus control in the lens driving device 102.

In the imaging device 100 of the present embodiment, an example in which the photometric device 113 and the distance measuring device 114 are individually provided has been shown, but the present invention is not limited to this. For example, each function may be provided in the image sensor 105, and photometry and distance measurement may be performed based on the image signal output from the image sensor 105.

Further, the image pickup apparatus 100 in the present embodiment may have a circuit configuration other than the above configuration. For example, a communication device that communicates with an external device such as a PC for controlling the image pickup device 100 may be provided. By using this communication device, the image pickup device 100 can transmit various acquired data to the outside and receive control commands for control.

Next, the configuration of the image pickup device 105 in the first embodiment will be described in detail with reference to FIG. FIG. 2 shows an equivalent circuit diagram of the image sensor 105. Here, it is assumed that an image sensor capable of horizontal addition is provided by providing a circuit that horizontally adds 3 pixels for each color in front of the column AD conversion unit when the number of pixels is reduced according to the video format when driving a moving image. There is. However, the addition circuit 207 is not always necessary, and may be omitted when a horizontal thinning mode is provided in which horizontal pixels are thinned out and read in the horizontal direction. More specifically, the same effect can be obtained by using the column memory 211 and the AD conversion unit in the rows thinned out in the horizontal direction.

Reference numeral 201 denotes a unit pixel, which is composed of a microlens (hereinafter, ML), a photodiode (hereinafter, PD), a floating diffusion (hereinafter, FD), and the like. The detailed configuration of the unit pixel will be described later.

R, G, and B described in the unit pixel 201 represent the color filters of Red, Green, and Blue, respectively, and are arranged two-dimensionally in a matrix in a Bayer array as shown in FIG.

The vertical scanning circuit 202 supplies drive signals (PRES, PTX, PSEL, etc.) to each pixel in common for each row. The number at the end of each signal and n (integer of 3 or more) indicate the line number, for example, n indicates the signal to be supplied to each pixel on the nth line. If it is not necessary to specify the number of lines, the character indicating the number of lines at the end is omitted. The drive signal will be described later together with the configuration of the unit pixel.

The signal of each pixel is transmitted to the subsequent circuit via the vertical signal line 203 commonly arranged in the column unit, and the constant current circuit 204 is connected to each vertical signal line 203 as shown in FIG. ..

Addition selector switches 205 and 206 are further connected to the vertical signal line 203. The signal PHADD is a signal supplied from a mode setting circuit (not shown) included in the image sensor 105, and the signal is output based on the mode setting set from the outside. A column memory 211 arranged corresponding to the pixel row to be read is connected to the other end of the addition changeover switch 205, and it is possible to hold a signal output from the unit pixel 201 for each row. In this embodiment, the column memory 211 corresponds to a holding unit for holding each signal. On the other hand, the addition circuit 207 is connected to the other end of the addition changeover switch 206. As described above, the addition circuit 207 is a circuit that performs horizontal addition for each pixel (3 pixels in the present embodiment) in which a color filter of the same color is arranged, and one addition circuit 207 is provided in the addition cycle. The adder circuit 207 of the present embodiment includes one or more capacitive elements, and it is possible to add and average a plurality of input signals. Further, it is also possible to make the addition ratio different by providing a capacitance element for each terminal connected from each vertical signal property 203 and making the capacitance of the capacitance element different. The mode setting circuit corresponds to a mode setting unit that sets a drive mode for reading a signal from each unit pixel 201. The mode setting circuit is provided with a register that can be set by communication from the outside of the image sensor 105, and by setting a predetermined parameter in the register, the image sensor 105 can be operated in a desired drive mode. The control circuit 109 may set the register via the timing generation circuit 107, or the control circuit 109 may directly set the register. Further, a control circuit may be provided in the image sensor 105, and the register may be adaptively rewritten according to the subject or the like to autonomously control the drive mode.

The addition changeover switches 205 and 206 are driven by the signal PHADD, and any of the addition changeover switches 205 and 206 is in a conductive state according to the polarity of the signal PHADD. More specifically, the addition changeover switch 205 is composed of a pMOS switch, and 206 is composed of an nMOS switch. Then, when the signal PHADD is “L”, the addition changeover switch 205 is turned on, the addition changeover switch 206 is turned off, and the pixel signal is written to the column memory 211 corresponding to the vertical signal line 203. When the signal PHADD is “H”, the addition changeover switch 205 is turned off, the addition changeover switch 206 is turned on, and the signal of the vertical signal line 203 is input to the addition circuit 207.

Each addition circuit 207 in the present embodiment has a configuration capable of outputting the added pixel signal to a plurality of vertical signal lines 203. More specifically, assuming that the column located at the center of the column to be horizontally added is the mth column (column number is m), the output of the addition circuit 207 is m-2, respectively via the column changeover switches 209 and 210. Connect to the column memory 211 corresponding to the m-th column. Here, the output of the adder circuit does not need to be limited to the m-2 and m columns, and two of the column circuits to add such as m-2 and m + 2 columns and m and m + 2 columns can be selected. If possible. Further, the switches may be prepared for three rows. The column changeover switches 209 and 210 are driven by the signals PMOV_N and PMOV_S supplied from the mode setting circuit, respectively. The adder circuit 207 corresponds to an adder that adds each signal. Further, the column changeover switches 209 and 210 correspond to switch units for selecting the column memory 211 for holding each signal.

Reference numeral 212 denotes a comparator provided corresponding to each row, and the signal held in the row memory 211 and the lamp signal VRAMP supplied from the DAC circuit 213 are input, and the two signals are compared. In the comparator 212, the output signal is inverted at the timing when the two input signals match. The DAC circuit 213 in this embodiment corresponds to a signal generation unit for generating a lamp signal.

Reference numeral 214 denotes a counter, and the reference clock CLK and the output of the comparator 212 are input. The counter 214 counts based on the reference clock CLK during the comparison period from the start of the two-input comparison until the output of the comparator 212 is inverted, and holds the count value. A signal PH is further input to the counter 214 from the horizontal scanning circuit 215, and the held count value is output to the output line 216 in synchronization with the signal PH. The output line 216 is connected to the image pickup signal processing circuit 106 shown in FIG. Here, the comparator 212, the DAC circuit 213, and the counter 214 correspond to the single slope type column AD conversion unit included in the image pickup device 105 in the present embodiment. Here, the illustrated AD conversion unit is an example, and a column AD conversion unit of a different method may be used.

Next, the unit pixel 201 in the first embodiment will be described in detail with reference to FIG. The unit pixel 201 is composed of one ML (not shown), one PD, one FD, and four transistors. In addition to the above configuration, a memory for temporarily holding the signal generated by the PD before being transferred to the FD may be provided.

Reference numeral 301 denotes PD, which performs photoelectric conversion that converts the light received by the image sensor 105 into electric charges. The PD 301 is connected to the gate of the transistor 304 forming the source follower amplifier together with the constant current source connected to the vertical signal line 203 via the transfer switch 302 and the FD 303. The transfer switch 302 is driven by the signal PTX. The FD 303 plays a role of converting the electric charge accumulated in the PD into a voltage. Further, the FD 303 is connected to the potential VDD via a transistor 306 driven by the signal PRESS, and when the PRESS becomes “H”, the FD is reset to the potential VDD. The transistor 305 is driven by the signal PSEL and acts as a switch that transmits the output of the transistor 304 to the vertical signal line. The signal PRESS, the signal PTX, and the signal PSEL are commonly supplied from the vertical scanning circuit 202 for each line.

Next, the drive mode of the image pickup device 105 of the present embodiment will be described. First, a drive mode for reading the signals in each row without reducing the number of pixels (without horizontally adding the signals in each row) will be described. This drive mode is used, for example, when capturing a still image having a higher resolution and a lower frame rate. This drive is a drive in which an analog signal read and an AD conversion operation are sequentially performed and read. More specifically, it is a drive mode in which signals to be sequentially output are held in the column memory 211, and the sequentially held signals are AD-converted.

FIG. 4 shows a timing chart when reading signals from each unit pixel 201 without addition (first drive mode). Further, a graph showing the potential VC of the column memory 211 and the potential VRAMP output from the DAC circuit 213 and a graph showing the count value of the counter are shown on the same time axis, respectively. In the first drive mode, the signals PHADD, PMOV_N, and PMOV_S are always controlled to "L". Note that FIG. 4 typically shows the read operation in the first line. In the subsequent lines, control is sequentially performed at the same timing.

First, all the pixels are reset at the same time, and the pixels are accumulated for a predetermined period. After that, at time t401, PSEL1 corresponding to the first line is set to "H", and the signal of the first line is output. Further, by setting PRESS1 to "H" at time t401, the FD is reset by the potential VDD. Since the PHADD of the signal reset by the potential VDD (hereinafter referred to as the reset signal) is “L”, the signal is transmitted to the column memory 211 arranged in the column corresponding to the pixel to be read. The reset signal is transmitted to the column memory 211, and at a stable time t402, the DAC circuit 213 outputs a RAMP signal and starts AD conversion of the reset signal. The counter 214 counts from the timing when the AD conversion is started until the VC and the VRAMP match and the inverted signal output from the comparator is received, and holds the count value. At the time t403 when the AD conversion period ends, PRESS1 becomes “L”, and the counter receives the signal PH output from the horizontal scanning circuit 215 and outputs the held count value to the output line 217 in sequence. In addition, the counter is reset to the initial value after outputting the reset signal to the output line.

Then, at time t404, the signal PTX1 becomes “H”, and the accumulated charge of the PD is transferred in addition to the FD in which the reset signal is held. A signal corresponding to the amount of received light (hereinafter referred to as an optical signal) is transmitted to the column memory 211 arranged in the column corresponding to the pixel to be read in the same manner as the reset signal. The optical signal is transmitted to the column memory 211, and at a stable time t405, the DAC circuit 213 outputs a RAMP signal and starts AD conversion of the optical signal. The counter 214 counts from the timing when the AD conversion is started until the VC and the VRAMP match and the inverted signal output from the comparator is received, and holds the count value. At the time t406 when the AD conversion period ends, PSEL1 becomes “L”. Further, the counter receives the signal PH output from the horizontal scanning circuit 215 and outputs the held count value to the output line 216 in sequence. After outputting the optical signal to the output line, the counter 214 is reset to the initial value.

The above operation is performed in sequence up to the nth line, and the read operation is completed. The reset signal and optical signal output from the image pickup element 105 are arithmetically processed by the image pickup signal processing circuit 106 in the subsequent stage to obtain an optical signal from which reset noise has been removed. The process of subtracting the reset signal from the optical signal may be performed in the image sensor 105 such as the counter 214 or the horizontal scanning circuit 215. By performing the processing in the image sensor 105 in this way, it is possible to reduce the amount of data to be transferred to the image sensor processing circuit 106.

Next, a drive mode for reading by reducing the number of pixels by horizontal addition will be described. This drive mode is used, for example, at the time of moving image imaging in which the number of pixels may be reduced (the signals of each column are horizontally added) instead of requiring a high frame rate. As described above, the image sensor 105 of the present embodiment is provided with an addition circuit 207 that adds three rows of the same color in front of the row AD conversion unit. The present invention is characterized in that the surplus AD conversion unit is utilized.

FIG. 5 shows a timing chart when reading signals from each unit pixel 201 by addition (second drive mode). Further, similarly to FIG. 4, a graph showing the potential VC of the column memory 211 and the potential VRAMP output from the DAC circuit 213 and a graph showing the count value of the counter are shown on the time axis, respectively. Further, the letters m-2 and m added to the end of the potential VC indicate the columns when the column number located at the center of the columns to be horizontally added is m, as in the case described above. In the second drive mode, the signal PHADD is always controlled to "H". Note that FIG. 5 also typically shows the read operation in the first line. In the subsequent lines, control is sequentially performed at the same timing.

First, all the pixels are reset at the same time, and the pixels are accumulated for a predetermined period. After that, at time t501, PSEL1 corresponding to the first line is set to "H", and the signal of the first line is output. Further, by setting PRESS1 to "H" at time t501, the FD is reset by the potential VDD. Since the PHADD is "H", the reset signal is transmitted to the addition circuit 207 corresponding to the column to be read. Further, at time t501, the signal PMOV_N becomes “H”, and the signal to which the reset signals of the three rows of the same color are added by the addition circuit 207 is transmitted to the row memory 211 of the m-2nd row.

After the added reset signal has been written to the column memory 211 in the m-2nd column, the signals PRES1 and PMOV_N become “L” at time t502.

Then, at time t503, the signal PTX1 becomes “H”, and the accumulated charge of PD is transferred in addition to the FD in which the reset signal is held. Like the reset signal, the optical signal is transmitted to the addition circuit 207 corresponding to the row to be read, and the optical signals of three rows of the same color are added. Further, when the signal PMOV_S becomes “H” at time t503, the added optical signal is transmitted to the column memory 211 in the m-th column.

After the added optical signal has been written to the column memory 211 in the m-th column, the signals PTX1 and PMOV_S become “L” at time t504.

Here, at time t504, the reset signal and the optical signal are held in the m-2nd row and the mth row row memory 211, respectively. Then, these two signals are subjected to AD conversion in parallel. Specifically, at time t504, the DAC circuit 213 outputs a RAMP signal and starts AD conversion of the above two signals. The counter 214 counts from the timing when the AD conversion is started until the respective VCs and VRAMPs match and receives the inverted signal output from the comparator, and holds the count value. At the time t505 when the AD conversion period ends, the counter 214 receives the signal PH output from the horizontal scanning circuit 215 and outputs the held count values to the output line 216 in sequence. After outputting the signal to the output line, the counter is reset to the initial value.

The above operation is performed in sequence up to the nth line, and the read operation is completed. The reset signal and optical signal output from the image sensor 105 are arithmetically processed by the image pickup signal processing circuit 106 in the subsequent stage to obtain an image pickup signal from which reset noise has been removed.

FIG. 6 is a diagram simply showing the timing of the conventional drive and the drive of the present invention in which the analog signal reading and AD conversion of the reset signal and the analog signal reading and AD conversion of the optical signal are sequentially performed. As shown in FIG. 6, in the present invention, the reset signal and the optical signal are held by using the surplus column memory, and then the two signals are subjected to AD conversion in parallel, so that the reading speed can be increased.

Further, in the above description, an example in which three rows of the same color are added in the horizontal direction is shown, and a signal is read out using a row circuit for two rows. Therefore, there is a surplus of one row, but this surplus row circuit may save power by saving power.

Further, the configuration is not limited to the configuration in which three rows of the same color are added in the horizontal direction, and two rows of the same color in the horizontal direction may be added, four or more rows of the same color may be added in the horizontal direction, and different color rows may be added.

Further, since the signals of the same pixel are read out using different column circuits, there is a concern that the correct signal cannot be obtained due to the variation of the column circuits. However, the variation of the column circuit occurs as fixed noise. In order to remove this, for example, an OB (optical black) pixel in which the upper part of the PD is shielded from aluminum or the like is provided in a part of the image sensor 105, and the signal of the corresponding OB pixel is subtracted from the aperture pixel. As a result, a mechanism or function for correcting the fixed noise component of the column circuit may be separately provided, such as driving for removing the variation in the column circuit.

(Second Embodiment)
Here, an application example of the present invention will be described in a configuration having pixels capable of receiving light passing through different pupil regions of an image pickup lens and capable of performing focus detection using a signal output from the image pickup element 105. To do.

The configuration of the image pickup device 105 in the second embodiment will be described in detail with reference to FIG. 7. FIG. 7 shows an equivalent circuit diagram of the image sensor 105. Those having the same configuration as that of the first embodiment shown in FIG. 2 are indicated by the same number, and those having changes or additions are given new numbers. Here, only the difference from the first embodiment will be described.

Reference numeral 701 is a unit pixel in the second embodiment, which will be described in detail later. With the change in the configuration of the unit pixel 701, the signal PTX supplied from the vertical scanning circuit has two types, PTX_A and PTX_B.

Further, in addition to the row changeover switches 209 and 210, a row changeover switch 702 is added. The signal for driving the column changeover switch 210 is changed from PMOV_S to PMOV_A, the row changeover switch 702 is driven by the added signal PMOV_AB, and the output of the adder circuit 207 is connected to the m + 2nd row.

Next, the unit pixel 701 in the second embodiment will be described in detail with reference to FIG. The unit pixel 701 is composed of one ML (not shown), two PDs, one FD, and five transistors. The two PDs of the present embodiment are arranged so as to divide the photoelectric conversion region of the unit pixel 701. The exit pupil of the image pickup lens is configured to be capable of receiving light that has passed through different regions. In addition to the above configuration, a memory for temporarily holding the signal generated in each PD before being transferred to the FD may be provided.

Reference numerals 801 and 802 indicate PD, and photoelectric conversion is performed. The PD801 and PD802 are connected to the gate of the transistor 806 forming the source follower amplifier together with the constant current source connected to the vertical signal line 203 via the FD805 common to the corresponding transfer switches 803 and 804, respectively. The transfer switches 803 and 804 are driven by the signals PTX_A and PTX_B, respectively. The FD805 plays a role of converting the electric charge stored in the PD into a voltage. Further, the FD 805 is connected to the potential VDD via a transistor 808 driven by the signal PRESS, and when the PRESS becomes “H”, the FD is reset to the potential VDD. The transistor 807 is driven by the signal PSEL and acts as a switch that transmits the output of the transistor 806 to the vertical signal line 203. The signal PRESS, the signal PTX_A, the signal PTX_B, and the signal PSEL are commonly supplied from the vertical scanning circuit 202 for each line.

Next, the drive mode of the image pickup device 105 of the present embodiment will be described. First, a first drive mode when reading out the signals in each row without reducing the number of pixels (without horizontally adding the signals in each row) will be described.

Specifically, by driving PTX_A1 and PTX_B1 with the same drive as PTX1 in the timing chart described with reference to FIG. 4, and simultaneously transferring the charges accumulated in the two PDs to the FD sharing the charges, the two PDs can be transferred. Read the added signal. Further, the signal PMOV_A and the signal PMOV_AB are always set to "L". Since other operations are the same as those in the first embodiment, they are omitted here.

Here, the drive mode in which the image pickup signals due to the charges generated by the PD801 and PD802 are not read independently, but the two transfer switches 803 and 804 are simultaneously driven and the image pickup signals added by the FD805 are read out has been described. .. However, the present invention is not limited to the above example, and each may be read independently.

Next, a second drive mode for reading by reducing the number of pixels by horizontal addition will be described. In this drive mode, the signals due to the charges generated by the PD801 and PD802 are independently read out. Therefore, it is possible to perform focus control even during imaging by using the phase difference type focus detection by the image sensor 105 using pupil division. The present invention is characterized in that the surplus AD conversion unit is utilized.

FIG. 9 shows a timing chart when reading the signal added from each unit pixel 701 (second drive mode). Further, similarly to FIG. 4, the graph shown at the lower part of the figure shows the potential VC of the column memory 211 and the potential VRAMP output from the DAC circuit 213 on the time axis, and the lower graph shows the count value of the counter. Further, the letters m-2, m, and m + 2 added to the end of the potential VC indicate the columns when the column number located at the center of the columns to be horizontally added is m, as in the case described above. .. In the second drive mode, the signal PHADD is always controlled to "H". Note that FIG. 8 also typically shows the read operation in the first line. In the subsequent lines, control is sequentially performed at the same timing.

First, all the pixels are reset at the same time, and the pixels are accumulated for a predetermined period. After that, at time t901, PSEL1 corresponding to the first line is set to "H", and the signal of the first line is output. Further, by setting PRESS1 to "H" at time t901, the FD is reset by the potential VDD, and since PHADD is "H", the reset signal is transmitted to the addition circuit 207 corresponding to the column to be read. .. Further, at time t901, the signal PMOV_N becomes “H”, and the signal to which the reset signals of the three rows of the same color are added by the addition circuit 207 is transmitted to the row memory 211 of the m-2nd row.

After the added reset signal has been written to the column memory 211 in the m-2nd column, the signals PRES1 and PMOV_N become “L” at time t902.

Then, at time t903, the signal PTX_A1 becomes “H”, and the accumulated charge of one of the pupil-divided PD801s is read out to the FD. The signal at this time is referred to as an optical signal A, and the other optical signal is referred to as an optical signal B. Like the reset signal, the optical signal A is transmitted to the addition circuit 207 corresponding to the row to be read, and the optical signals A in three rows of the same color are added. Further, when the signal PMOV_A becomes “H” at time t903, the added optical signal A is transmitted to the column memory 211 in the m-th column.

After the added optical signal A has been written to the column memory 211 in the m-th column, the signals PTX_A1 and PMOV_A become "L" at time t904.

Then, at time t905, the signals PTX_A1 and PTX_B1 become "H", and the accumulated charges of both the corresponding pupil-divided PD801 and PD802 are simultaneously read out to the FD. The signals of both PDs are added by FD. The signal at this time is referred to as an optical signal AB. The optical signal AB is transmitted to the addition circuit 207 corresponding to the row to be read, and the optical signals AB of three rows of the same color are added, as in the case of the two signals described above. Further, when the signal PMOV_AB becomes “H” at time t905, the added optical signal AB is transmitted to the column memory 211 in the m + 2nd row.

After the optical signal AB finishes writing to the column memory 211 of the m + 2nd row, the signals PSEL1, PTX_A1, PTX_B1, and PMOV_AB become “L” at time t906.

Here, at time t906, the reset signal, the optical signal A, and the optical signal AB are held in the column memory 211 of the m-2nd row, the mth row, and the m + 2nd row, respectively. Then, these three signals are subjected to AD conversion in parallel. Specifically, at time t906, the DAC circuit 213 outputs a RAMP signal and starts AD conversion of the above three signals. The counter 214 counts from the timing when the AD conversion is started until the respective VCs and VRAMPs match and receives the inverted signal output from the comparator, and holds the count value. At the time t907 when the AD conversion period ends, the counter 214 receives the signal PH output from the horizontal scanning circuit 215 and outputs the held count values to the output line 216 in sequence. After outputting the signal to the output line, the counter is reset to the initial value.

The above operation is performed in sequence up to the nth line, and the read operation is completed. The reset signal, optical signal A, and optical signal AB output from the image pickup element 105 are arithmetically processed by the image pickup signal processing circuit 106 in the subsequent stage to obtain a focus detection signal and an image pickup signal from which reset noise has been removed.

FIG. 10 is a diagram simply showing the timing of the conventional drive and the drive of the present invention in which the analog signal reading and AD conversion of the reset signal and the analog signal reading and AD conversion of the optical signal A and the optical signal AB are sequentially performed. As shown in FIG. 10, in the present invention, the reset signal and the optical signal are held by using the surplus column memory, and then the two signals are subjected to AD conversion in parallel, so that the reading speed can be increased. In the present embodiment, an example in which a unit pixel is provided with two photoelectric conversion units has been shown, but the present invention is not limited to this. Even when two or more photoelectric conversion units are provided, the same effect can be obtained by using the signals from a single photoelectric conversion unit and the signals from all the photoelectric conversion units.

As described above, the present invention can be applied even in a configuration capable of phase difference type focus detection by an image sensor.

(Third Embodiment)
In the first embodiment and the second embodiment, the drive for performing AD conversion of the reset signal and the optical signal (optical signal A, optical signal AB) in parallel has been described. This drive mode is a technology that can increase the speed without increasing the circuit scale by utilizing the surplus column circuit, but on the other hand, redundant operation occurs. For example, since the optical signal A is a signal including a reset signal, some of the same signals are AD-converted at the same time. In the present embodiment, the operation capable of performing the minimum AD conversion operation by changing the operation of the counter 214 of the column AD conversion unit will be described. The description of the third embodiment will be based on the configuration of the second embodiment.

FIG. 11 is a circuit diagram of the image sensor 105 in the third embodiment after the column memory 211. For the sake of simplification of the explanation, only the circuits of the m-2nd column, the mth column, and the m + 2nd column, which are horizontal addition units, are shown. The omitted circuit is the same as in FIG. 7.

Here, in FIG. 11, in addition to FIG. 7, the signal line 1101 capable of inputting the output signal of the comparer 212 in the m-2nd row to the counter in the mth row and the output signal of the comparator 212 in the mth row are displayed. A signal line 1102 that can be input to the counter in the m + 2nd column is added. In this embodiment, the output signal of the comparator corresponds to the operation signal of the AD conversion unit. Although the output signal of the comparator is used as the operation signal in this embodiment, the count value of the counter or the like may be used.

In the second embodiment, the count is started at the timing when the AD conversion is started, and the count is stopped by receiving the inverting signal of the comparator. However, in addition to this, the counter 214 of the third embodiment starts counting by receiving the inverted signal of the signal lines 1101 and 1102, and stops counting by receiving the inverted signal of the comparator corresponding to the counter. Further has. Here, the counter operation used in the second embodiment is referred to as a first counter mode, and the mode added in the third embodiment is referred to as a second counter mode. Since the counter in the m-2nd row is not used when the second counter mode is performed, power saving may be performed.

The same as in the second embodiment in the first drive mode in which the signals in each row are read out without horizontally adding the signals in each row without reducing the number of pixels, and the counter 214 operates in the first counter mode. To do.

On the other hand, the counter 214 in the second drive mode in which the pixels are reduced and read out by horizontal addition in the third embodiment operates in the second counter mode. The operation at that time will be described with reference to the timing chart of FIG.

Since the driving in the second embodiment is the same as the operation described with reference to FIG. 9 in the second embodiment except for the operation of the counter, the description thereof will be omitted.

As a feature of this embodiment, the DAC circuit 213 outputs a RAMP signal at time t1201 and starts AD conversion. At this time, the counter in the m-th column and the counter in the m + 2nd column do not operate.

Next, at time t1202, the comparator in the m-2nd row outputs an inverted signal at the timing when VC_m-2 held in the row memory 211 in the m-2nd row, which is a reset signal, coincides with VRAMP. This inverted signal is input to the counter in the m-th column via the signal line 1101, and the counter in the m-th column starts counting.

Next, at the timing when VC_m held in the m-th row memory 211, which is the optical signal A, coincides with VRAMP at time t1203, the m-th row comparator outputs an inverted signal, and at the same time, the m-th row counter counts. Make a stop. Further, this inverted signal is input to the counter in the m + 2nd column via the signal line 1102, and the counter in the m + 2nd column starts counting.

Next, at time t1204, at the timing when VC_m + 2 held in the column memory 211 of the m + 2nd column, which is the optical signal AB, coincides with VRAMP, the comparator in the m + 2nd column outputs an inverted signal, and at the same time, the counter in the m + 2nd column counts. Make a stop.

At this time, the count value of the counter in the m-th column holds the value of the optical signal A that does not include the reset noise, which is the value obtained by subtracting the reset signal from the optical signal A. The count value of the counter in the m + 2nd column holds the value of the optical signal B obtained by subtracting the optical signal A including the reset signal from the optical signal AB. That is, the AD conversion unit operates only for the signals of the optical signal A and the optical signal B that do not include the reset noise, and the minimum operation is possible. When performing focus detection, the obtained optical signal A and optical signal B may be used as they are, and when using as an imaging signal, the obtained optical signal A and optical signal B need only be added.

By operating the counter in the second counter mode in this way, the period during which the counter operates is shortened, so that a power saving effect can be expected.

This operation does not necessarily require the focus detection of the phase difference method, and may be applied to, for example, a normal pixel configuration as shown in the first embodiment.

Further, for example, when considering the case of acquiring a light-shielded image, since there is no optical signal in the light-shielded image, ideally, the reset signal, the optical signal A, and the optical signal AB all have the same level. At this time, if delay variation of the inverting signal of the comparator occurs, for example, the inverting signal of the comparator in the m-th column is input to the counter in the m-th column before the inverting signal of the comparator in the m-2nd column. Therefore, there is a concern that the counter in the m-th column may not operate.

As shown in FIG. 13, each of the lamp signals input to the comparators in the m-2nd row, the mth row, and the m + 2nd row from the DAC circuit 213 is provided so that the second counter mode can be operated correctly even in the above case. Then, a predetermined level may be offset between the lamp signals in consideration of delay variation of the comparator and other noise. Specifically, the lamp signals input to the comparators in the m-2nd column, the mth column, and the m + 2nd column are VRAMPN, VRAMPA, and VRAMPB, respectively. Then, the potential relationship when the offset level is σ is set to be VRAMPN + 2σ = VRAMPA + σ = VRAMPB.

By setting the lamp signal in this way, even in the above case, the output of the comparator in the m-2nd row is inverted first, so that a correct signal can be obtained. Further, since the obtained count value is a value deviated by a predetermined offset, it is subtracted by the image pickup signal processing circuit 106 in the subsequent stage.

203 Vertical signal line 205, 206 Addition selector switch 207 Addition circuit 209, 210 Row selector switch 211 Row memory

Claims (8)

An image sensor having a plurality of pixels in a matrix.
A mode setting means for setting a drive mode for reading a plurality of pixels, and
A plurality of output lines provided for each column for outputting signals of the plurality of pixels , and
A plurality of holding means provided for each of the plurality of output lines and for holding the signal output to the output line, and
The signals held in said plurality of holding means and a plurality of AD conversion means for AD conversion,
And adding means for adding the plurality of the plurality of first output from said plurality of pixels to the output line of the signal and a plurality of second signals, respectively,
And switching means for switching the retaining means for retaining said summed by adding means and the first signal and the second signal respectively,
With
The first signal includes a reset signal, and the second signal includes a signal based on the charge generated in the pixel.
As a drive mode set by said mode setting means switches to said switching means for holding each of the hold means that different to the first signal and the second signal added by said adding means, and imaging device, which comprises a driving mode of the AD conversion of the plurality of the AD conversion unit are added being held to each of the different holding means first signal and the second signal in parallel. As a drive mode set by said mode setting means, wherein each of the plurality of holding means sequentially holds the first signal and the second signal, the AD conversion unit sequentially to each of said plurality of holding means The image pickup device according to claim 1, further comprising a drive mode in which the held first signal and the second signal are AD-converted in the order in which they are held. Imaging device according to claim 1 or 2, wherein the pixel is characterized in that it comprises a plurality of photoelectric conversion means. Wherein the plurality of AD conversion means, the image pickup device according to any one of claims 1 to 3, that the characteristics, including an input means capable of inputting an operation signal outputted from another AD conversion means. Wherein the plurality of AD conversion means includes signal generating means for generating a ramp signal, comparison means for comparing said ramp signal and said first and second signals, counting means for counting a comparison time of the comparator means Including and
The image pickup device according to claim 4 , wherein the operation signal is an output signal of the comparison means. It further includes a register for designating a drive mode set by the mode setting means.
The image pickup device according to any one of claims 1 to 5 , wherein the mode setting means sets the drive mode based on a parameter set in the register. The image pickup device according to any one of claims 1 to 6 , wherein the adding means is provided at a cycle corresponding to the number of columns to be added. An image pickup apparatus including the image pickup device according to any one of claims 1 to 7 .

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