JP6793626B2 - Game machine - Google Patents

Description

The present invention relates to a gaming machine capable of playing a game.

As a game machine, a slot machine in which a predetermined number of bets is set and a plurality of types of identification information are variably displayed based on a start operation, or a game medium such as a game ball is launched into a game area by a launching device. There is a pachinko gaming machine or the like in which a plurality of types of identification information are variably displayed when a game medium wins a prize in a starting area such as a winning opening provided in the game area.

As a game machine of this type, a device that specifies an address of a storage area and executes a specific instruction to read data by accessing the storage area of the specified address has been proposed (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2014-83327

In the gaming machine described in Patent Document 1, if a specific command is issued due to a malfunction when the specific storage area should be protected, there is a risk that the specific storage area may be unintentionally accessed. It was.

The present invention has been made by paying attention to such a problem, and an object of the present invention is to provide a gaming machine capable of reducing the possibility of unintended access to a specific storage area.

(A) A gaming machine capable of playing games
An instruction execution means capable of specifying the address of the storage area using the data stored in the predetermined storage area and executing a specific instruction for reading data from the storage area of the specified address based on a program.
Execution of processing to restore the control state based on the data stored in the specific storage area when the power supply to the game machine is detected, when the stop of the power supply is detected. With means,
Predetermined value data used for specifying the address of the specific storage area is stored in the predetermined storage area until the stop of power supply to the game machine is detected.
Specific value data used to identify an address in an area different from the specific storage area when the stop of power supply to the game machine is detected is stored in the predetermined storage area.
The program includes a first program that executes a process related to the progress of the game and a second program that executes a process not related to the progress of the game.
The first program is stored in the first program storage area.
The second program is stored in the second program storage area.
The address of the first program storage area includes the first information and the second information.
The instruction executing means can execute a special instruction for reading the first program from the first program storage area.
By executing the special instruction, the address of the first program storage area is specified from the first information and the second information specified by the special instruction, and the first program is obtained from the specified address. Can be read and
While the special instruction can be executed based on the first program, the special instruction is not executed based on the second program.
The gaming machine may have the following configuration.
(1) A gaming machine capable of playing games
The address of the storage area is specified using the data stored in the predetermined storage area (for example, Q register), and a specific instruction (for example, LDQ instruction) for reading data from the storage area of the specified address is given based on the program. Instruction execution means to be executed (for example, main control unit 41) and
To restore the control state based on the data stored in the specific storage area (for example, the game RAM area) when the power supply to the game machine is detected (for example, the processing of Sa16 to Sa26 in FIG. 5). (For example, the process of supplying backup power to the game RAM area, the process of saving the register shown in Sk1 to the game RAM area, the process of saving the stack pointer to the game RAM area of Sk2, etc.), the power supply is stopped. Is provided with a processing execution means (for example, the main control unit 41) to be executed when is detected (in the power failure processing of FIG. 6).
In the predetermined storage area (for example, Q register),
Predetermined value data used to specify the address of the specific storage area until the stop of power supply to the game machine is detected (for example, a predetermined value capable of specifying the upper address "F0" of the game RAM area). Is stored (for example, as shown in FIG. 7, a predetermined value is stored in the Q register until the timing T0 when the power failure processing is executed).
When the stop of power supply to the game machine is detected, the specific value data used to specify the address of the area different from the specific storage area (for example, the internal function register which is the area different from the game RAM area). A specific value that can identify the upper address "F5") is stored.

According to such a configuration, when the stop of the power supply is detected, it is an unstable state from the viewpoint of the power supply, and when a specific instruction is mistakenly executed in such an unstable state. Even so, it is possible to reduce the possibility that an unintended access is executed to an important specific storage area in which data for returning to the control state when the power supply is stopped is stored.

Further, the address of the storage area (including the specific storage area and the area different from the specific storage area) includes the first information (for example, the upper address of the address) and the second information (for example, the lower address of the address). For example, it is preferable to store the first information in a predetermined storage area (for example, a Q register). Then, in the specific instruction, the address is specified from the first information and the second information, and the data is read from the storage area of the specified address. At the time of this reading, the address is specified from the first information stored in the predetermined storage area and the second information specified by the specific instruction. According to such a configuration, the program capacity of the specific instruction can be reduced as compared with the configuration in which both the first information and the second information are specified in the specific instruction to specify the address.

(2) In the game machine of (1)
The specific value data is data used to specify the address of the area that is initialized when the power supply to the game machine is started (for example, the specific value is executed before the start-up process). It is a value that can specify the upper address of the internal function register that is initialized in the startup setting process).

According to such a configuration, even if a specific instruction is mistakenly executed in an unstable state, the area initialized when the power supply is started is accessed, but such an area is used. Even if it is accessed, it is possible to reduce the occurrence of special problems.

(3) In the game machine of (1) or (2)
Generates confirmation data for confirming whether the data stored in the storage area is normal (for example, fixed data for RAM destruction diagnosis shown in Sk4 in FIG. 6 and RAM parity adjustment data shown in Sk7). The confirmation data generation process (for example, the processes of Sk4 and Sk7 in FIG. 6) to be stored in the specific storage area is executed when the power supply stop is detected (for example, in the power failure process). Further equipped with data generation processing execution means
After the confirmation data generation process is executed, the specific value data is stored in the predetermined storage area (for example, the Q register) (for example, as shown in FIG. 6, the Sk4 and Sk7 processes are executed. After that, a specific value is set in the Q register in Sk8).

According to such a configuration, even if a specific instruction is erroneously executed after the confirmation data is stored in the specific storage area, the confirmation data is stored in the specific storage area. The possibility of access can be reduced.

(4) In any of the game machines (1) to (3)
When the stoppage of power supply to the game machine is detected (for example, in the power interruption process of FIG. 6), after the specific value data is stored in the predetermined storage area (for example, after the process of Sk8). , Special value data corresponding to the stop of the power supply (for example, RAM access prohibition flag shown in Sk9 and Sk10, and set value at the time of power failure such as interrupt prohibition flag) are stored in the special area (for example, internal function register). Further equipped with special value storage means to make
The specific instruction is an instruction that identifies the address of the storage area using the data stored in the predetermined storage area and stores the data in the storage area of the specified address based on the program (for example, LDQ). Instructions are also used to perform the process of setting data in an area),
The specific value data is data used for specifying a part of the addresses of the special storage area (for example, a value capable of specifying the upper address "F5" of the internal function register), and is the value of the special storage area. Data that can specify an address other than the part of the addresses is specified by the specific instruction (the lower address of the internal function register is specified by the LDQ instruction).

According to such a configuration, when the stop of the power supply is detected, the program capacity of the instruction for storing the special value in the special area can be reduced.

(5) In any of the game machines (1) to (4)
The program includes a specific program (eg, a gaming program) and a non-specific program (eg, a non-gaming program).
The specific storage area (for example, a game RAM area) is an area in which data used in the specific program is stored.
The address of the specific storage area includes first information (for example, a higher address of the address) and second information (for example, a lower address of the address).
The first information is stored in the predetermined storage area (for example, Q register).
The specific instruction is an instruction for specifying an address from the first information and the second information designated by the specific instruction and reading data from the specific storage area of the specified address.
The instruction executing means executes the specific instruction based on the specific program, but does not execute the specific instruction based on the non-specific instruction (for example, an LDQ instruction is used in a game program, but an LDQ instruction is used in a non-game program. Is not used).

According to such a configuration, since the specific instruction is not executed based on the non-specific program, the storage area in which the data used in the specific program is stored is accessed by executing the specific instruction in the non-game program. Can be reduced. Therefore, it is possible to reduce the possibility that an unintended access is executed to the storage area in which the data used in the specific program is stored.

(6) In any of the game machines (1) to (5)
The program includes a specific program (eg, a gaming program) and a non-specific program (eg, a non-gaming program).
The addresses of the program storage area (for example, the game program area) in which the program used in the specific program is stored are the first information (for example, the upper address of the address) and the second information (for example, the lower address of the address). ) And
The first information is stored in a special storage area (for example, a vector table area).
The special instruction (for example, the RST instruction and the CALLV instruction) specifies an address from the first information and the second information specified by the special instruction, and reads a program from the program storage area of the specified address. Is an instruction
The instruction executing means executes the special instruction based on the specific program, but does not execute the special instruction based on the non-specific program (for example, the RST instruction and the CALLV instruction are used in the game program, but the non-game program). The RST and CALLV instructions are not used).

According to such a configuration, since the special instruction is not executed based on the non-specific program, the storage area in which the program used in the specific program is stored is accessed by executing the special instruction in the non-game program. Can be reduced. Therefore, it is possible to reduce the possibility that an unintended access is executed to the storage area in which the program used in the specific program is stored.

It is a schematic diagram of the slot machine of the Example to which this invention was applied. It is a figure which shows the memory map of ROM and RAM mounted on the main control part. It is a figure which shows the detail of the memory map of ROM and RAM mounted on the main control part. It is a flow chart which shows the control content of the start processing performed by the main control part (the 1). It is a flow chart which shows the control content of the start processing performed by the main control part (the 2). It is a flow chart which shows the control content of the power failure process performed by the main control unit. It is a figure which shows the timing such as prohibition of RAM access.

[overall structure]
FIG. 1 is a schematic view showing an example of the overall configuration of the game machine. FIG. 1A is a schematic view showing an example of a main appearance configuration of the game machine 1. FIG. 1B is a schematic view showing an example of a main internal configuration of the game machine 1.

As shown in FIG. 1A, the gaming machine 1 according to the present embodiment includes a liquid crystal display 51 and one or more speakers 53 capable of outputting various sounds as effect means for executing the effect. , One or more lamps 63 capable of emitting light in various modes. The liquid crystal display 51 functions as a display means for displaying an image. The speaker 53 functions as a sound output means for outputting sound. The lamp 63 functions as a light emitting means for emitting light.

As shown in FIG. 1B, inside the game machine 1, a game control board 40 that controls the progress of the game and outputs various commands according to the progress of the game, and a predetermined effect according to the command. The effect control board 90 and the like for controlling the above are provided. The game control board 40 includes a main control unit 41 that performs processing related to the progress of the game and controls a configuration mounted or connected to the game control board 40. The effect control board 90 includes a sub control unit 91 that receives a command transmitted from the game control board 40 to perform an effect, and controls a configuration mounted on or connected to the effect control board 90.

Further, the main control unit 41 includes a CPU (Central Processing Unit) 41a, a ROM (Read only memory) 41b, and a RAM (Random access memory) 41c. Further, the sub control unit 91 has a CPU 91a, a ROM 91b, and a RAM 91c.

Further, the main control unit 41 includes a plurality of input ports and a plurality of output ports. Each of the plurality of output ports outputs various signals (control signals for controlling various motors, lights, display units, etc.). Various signals (such as an operation detection signal from the writing operation unit and a power failure detection signal described later) are input to each of the plurality of input ports. Further, although the game machine 1 will be described below as a slot machine, the following idea can be applied to other game machines (for example, pachinko game machines).

When playing a game on a slot machine, first, a predetermined number of bets are set by inserting medals into the medal insertion section or operating the MAXBET switch. As a result, the winning line becomes valid, the operation to the start switch becomes valid, and the game can be started. If a medal is inserted with the number of bets set, the amount will be increased to credit.

If the start switch is operated while the number of bets that can start one game is set (the state where the game can be started), the symbols will change due to the rotation of multiple (for example, three) reels. Then, the rotation of the corresponding reel is stopped by operating the stop switch corresponding to each of the reels. Then, three symbols are derived and displayed as display results in the upper, middle, and lower rows of the perspective window. When a prize is generated by stopping the combination of the winning symbols on the winning line LN, a predetermined number of medals are given to the player according to the winning.

In addition, the target role drawn by the internal lottery is referred to as a lottery target combination or a winning combination. In order for a role to win, the role must have been won by an internal lottery.

[About the memory area and program of the main control unit]
FIG. 2 is an address map of the memory area used by the main control unit 41. As shown in FIG. 2, the memory area used by the main control unit 41 includes a memory area (0000H to 7FFFH) allocated to the ROM 41b and a memory area (F000H to FFFFH) allocated to the RAM 41c.

The memory area of the ROM 41b includes a program / data area (0000H to 26FFH) in which a program and fixed data are stored, a ROM comment area (2700H to 277FH) in which arbitrary data such as a program title and version can be set, and a later description. Vector table area (2780H to 27A7H) where the upper address of the subroutine of the CALLV instruction and the start address of the timer interrupt processing (main) are set, and parameters for setting the internal functions of the main control unit 41 in terms of hardware. The HW parameter area (27A8H to 27FFH) in which is set and the unused area (2800H to 7FFFH) in which access is prohibited are included.

The parameters set in the HW parameter area in the ROM 41b include the final address (HPRGEND) of the ROM area used in the program / data area, the start address (HRAMSTAT) and the final address (HRAMEND) of the RAM area for which access is prohibited.

The memory area of the RAM 41c is an internal function register area (F500H to F500H) in which a usable area (F000H to F400H) that can be used as a work and a register group for controlling each function mounted on the main control unit 41 are stored. F6FFH) and unused areas (F401H to F4FFH, F700H to FFFFH) whose access is prohibited. Further, although not particularly shown in FIG. 2, the memory area of the RAM 41c includes a signal area described later. It is assumed that the upper address of the signal region is "F5" as in the internal function register.

FIG. 3 is an address map of the program / data area in the ROM 41b of the main control unit 41 and the usable area in the RAM 41c.

As shown in FIG. 3A, the program / data area in the ROM 41b includes a game program area in which a game program related to the progress of the game is stored, a game data area in which the game data used by the game program is stored, and a game data area. It includes a used area 1, a non-game program area in which a non-game program not related to the progress of a game is stored, a non-game data area in which non-game data used by the non-game program is stored, and an unused area 2. ..

Note that the progress of the game is to proceed with a series of processes constituting the game, and in the case of a slot machine, at the stage where the number of bets can be set and the game can be started, the game is started and the reels are rotated. The stage of causing the reel to be stopped, the stage of deriving the display result, and the stage of giving the value of a medal or the like according to the display result are advanced.

The game program area related to the progress of the game and the non-game program not related to the progress of the game are separately allocated, and are allocated rearward in the storage area of ROM 41b among the game program area and the non-program area. Since an unused area 1 of at least 16 bytes or more is allocated to the area in front of the non-programmed area, a game program area related to the progress of the game and a non-game program not related to the progress of the game are stored in the storage area. It can be easily identified according to the difference between the two.

Further, the game program area and the game data area, and the non-game program area and the non-game data area are allotted to continuous areas, while the game program area and the game data area related to the progress of the game and the non-game area not related to the progress of the game. Since the game program and the non-game data area are allocated to areas that are not continuous with an unused area 1 of at least 16 bytes or more in between, the game program area and the game data area related to the progress of the game and the progress of the game The non-game program and the non-game data area, which are not involved, can be easily specified according to the difference in the storage area.

In the above, the front and back of the storage area are the magnitude relations of the address values assigned to the storage area, and the smaller address is the front and the larger address is the rear. Therefore, the storage area allocated after the one storage area corresponds to the storage area having an address value larger than that of the one storage area, and the storage area allocated before the one storage area. , A storage area whose address value is smaller than that of one storage area is applicable.

Further, the game program may be allocated behind the non-game program area, and the unused area may be allocated in front of the game program allocated behind the non-game program area. A game program area related to the progress of the game and a non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

Further, the game program area and the non-game program area may be allocated to adjacent areas with the unused area 1 in between, and even with such a configuration, the game program area related to the progress of the game , A non-game program that is not related to the progress of the game can be easily identified according to the difference in the storage area.

Further, since 0 values are stored in all the unused areas 1 and 2 of the program / data area of the ROM 41b, the game program area and the game data area, the non-game program area and the non-game data, The unused areas 1 and 2 can be easily distinguished, and even when invalid data is stored in the unused areas 1 and 2, it can be easily found.

Note that 1 may be stored in all the unused areas 1 and 2 of the program / data area of the ROM 41b, and even in such a configuration, the game program area, the game data area, and the non-game The program area and non-game data can be easily distinguished from the unused areas 1 and 2, and even when invalid data is stored in the unused areas 1 and 2, it can be easily found. ..

Further, as long as the game program area and the non-game program area are allocated to separate areas, the game program area and the non-game program area may be applied to adjacent areas. Even with such a configuration, the game program area related to the progress of the game and the non-game program not related to the progress of the game can be easily specified according to the difference in the storage area.

Further, both the game program area and the non-game program area start from an address (0H) in which the lower four digits have the same value when the address is expressed in binary, and the program / data area of ROM 41b. Of these, the game program area related to the progress of the game and the non-game program area not related to the progress of the game can be easily distinguished from other areas.

In addition, both the game program area and the non-game program area not only start from an address having the same 0 in the lower 4 digits when the address is expressed in binary, but also in the lower 1 digit when the address is expressed in hexadecimal. Starts from the same 0 address (0H), so the game program area and the non-game program area can be easily distinguished from other areas not only when the address is expressed in binary not only but also when it is expressed in hexadecimal. can do.

In both the game program area and the non-game program area, regardless of whether the address is expressed in binary or hexadecimal, the lower N (N is a natural number of 1 or more) starts from the address having the same value. The game program area and the non-game program area can be easily distinguished from other areas. For example, the value of the lower N (N is a natural number of 1 or more) digits is the same 1. The same effect can be obtained with a configuration starting from the address of.

As shown in FIG. 3B, the usable area of the RAM 41c includes a game RAM area used as a work by the game program, a non-game RAM area used by the non-game program as a work, and an unused area 4. The game RAM area includes a special work, an important work, a general work, an unused area 3, and a game stack area in which the game program saves data, and the non-game RAM area includes a game. An area that can be referred to by the program, an area that cannot be referred to by the game program, and a non-game stack area in which the non-game program saves data are included. In the present embodiment, the game stack area and the non-game stack area are individually provided in different areas, but a single stack area shared by the game program and the non-game program may be provided.

The special work is a work in which data for transmitting a command to the sub-control unit 91, various software random numbers, and other data that are initialized only before the start of setting are stored.

The important work is a work in which various indicators, LED display data, I / O port input / output data, game time timing counters, and the like are stored.

The general work is a work in which a stop control table, a stop symbol, the number of medals to be paid out, and the like are stored.

The game stack area (in use) is an area in which data saved from the register of the CPU 41a is stored. Further, the unused stack area (unused) will be initialized in the startup process, but the game stack area (in use) will not be initialized because the program continues.

Further, the start address of the game RAM area is "F000H". Further, in this embodiment, the upper address of each of the start address of the special work, the start address of the important work, and the start address of a part of the general work is assumed to be "F0".

The unused area 3 is an area in which neither the game program nor the non-game program is used, and is an area that is surplus with respect to the game RAM area having a predetermined capacity.

Further, the unused area 4 is an area of 16 bytes or more in which neither the game program nor the non-game program is used. Since the game RAM area and the non-game RAM area are allocated to areas that are not continuous with the unused area 4 in between, the game RAM area used by the game program related to the progress of the game and the non-game RAM area not related to the progress of the game The non-game RAM area used by the game program and the non-game RAM area can be easily specified according to the difference in the storage area.

In the following, the game program area, the game data area, and the game RAM area may be collectively referred to as a game area, and the non-game program area, the non-game data area, and the non-game RAM area may be collectively referred to as a non-game area. .. Further, the unused area 1, the unused area 2, the unused area 3 and the unused area 4 may be collectively referred to as an unused area.

Based on the parameters set in the HW parameter area, the main control unit 41 permits access to the available area of the RAM 41c when the access is prohibited in the program / data area of the ROM 41b. When there is an access to an area other than the program / data area of the ROM 41b, or when there is an access to an area other than the usable area of the RAM 41c. That is, the unused area of the ROM 41b is executed because the invalidation process for disabling the progress of the game is executed by generating the illegal access reset when there is an access to the memory area which is not accessed in the normal operation. Even when an illegal program is stored in an area unrelated to the operation, an unused area of the RAM 41c, or the like, it is possible to prevent the illegal program from being executed.

In the present embodiment, when RAM access is prohibited (see, for example, Sk9 in FIG. 6), when the game RAM area is accessed, the disabling process is executed. On the other hand, when RAM access is prohibited, the invalidation process is not executed even if the internal function register is accessed. As a modification, when RAM access is prohibited, disabling processing may be executed when the internal function register is accessed.

In particular, in the present embodiment, the game program area and the non-game program area are allocated to the program / data area of the ROM 41b that is permitted to be accessed by the program, and the game program area is located in front of the non-game program area behind the game program area. An unused area 1 is allocated to the area, and a group of programs / data areas including an area from the start address of the game program area to the final address of the non-game program based on the parameters set in the HW parameter area. While the access to the area (the area from the game program area to the non-game data area) is collectively set to allow, the other areas, that is, the game program, the game data, and the non-game program among the program / data areas, Since access to the area after the non-game data in which the non-game data is not stored is prohibited, it is possible to prevent unintended control by a malicious program or illegal data.

Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and access to a group of areas including the area from the start address of the non-game program area to the final address of the game program in the program / data area is collectively based on the parameters set in the HW parameter area. Even if access to other areas is prohibited while setting the permission, it is possible to prevent unintended control by malicious programs and malicious data.

A game program area and a non-game program area are allocated to the program / data area, and an unused area 1 is allocated to an area behind the game program area and before the non-game program area, and the program / data. Of the areas, to a group of areas including the game program area (area from the game program area to the game data area) and to a group of areas including the non-game program (area from the non-game program area to the non-game data area). Access may be set to allow each and access to other areas may be prohibited. Even with such a configuration, the program / data area to the area where the game program or non-game program is not stored Since access to the data is prohibited, it is possible to prevent unintended control by malicious programs and malicious data. Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and a group of areas including the game program area (the area from the game program area to the game data area) and a group of areas including the non-game program (from the non-game program area to the non-game area) in the program / data area. Access to each of the areas up to the data area) may be set to allow and access to other areas may be prohibited. Even with such a configuration, game programs and non-games in the program / data area may be set. Since access to the area where the program is not stored is prohibited, it is possible to prevent unintended control by malicious programs and malicious data.

Further, in the above, the configuration is such that the area itself for which access is permitted in the program / data area is set, but by setting the area for which access is prohibited in the program / data area, the area for indirectly permitting access is set. It may be configured to be performed.

The main control unit 41 determines that the user program is executed when the user program is executed in an area other than the designated area where the program running is permitted, that is, in normal operation, based on the parameters set in the HW parameter area. When the user program is executed in an area that does not exist, the IAT circuit (Illegal Address Trap: not shown in particular) outputs an IAT generation signal to disable the progress of the game, so that the unused area and operation of the ROM 41b Even when an illegal program is stored in an area unrelated to the above, an unused area of the RAM 41c, or the like, it is possible to prevent the illegal program from being executed.

In particular, in the present embodiment, the game program area and the non-game program area are allocated to the program / data area of the ROM 41b that is permitted to be accessed by the program, and the game program area is assigned to the front of the non-game program area behind the game program area. The unused area 1 is assigned to the area, and the IAT circuit permits the program running for each of the game program area and the non-game program area in the program / data area based on the parameters set in the HW parameter area. While it is set as an area, program running is prohibited in other areas, that is, in the program / data area where game programs and non-game programs are not stored, so unintended control by malicious programs and data is prohibited. Can be prevented from being done.

Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and based on the parameters set in the HW parameter area, each of the game program area and the non-game program area of the program / data area is set as a designated area in which the IAT circuit permits program running. Even if the program running in other areas is prohibited, it is possible to prevent unintended control due to an illegal program or illegal data.

A game program area and a non-game program area are allocated to the program / data area, and an unused area 1 is allocated to an area behind the game program area and before the non-game program area, and an HW parameter area. A group of areas including the area from the start address of the game program area to the final address of the non-game program in the program / data area based on the parameters set in (the area from the game program area to the non-game data area). The IAT circuit may be collectively set as a designated area that allows program running, and program running in other areas may be prohibited. Even in such a configuration, the program / data area may be used. Since the program running in the area where the game program or the non-game program is not stored is prohibited, it is possible to prevent unintended control by the malicious program or the illegal data. Further, in the program / data area of the ROM 41b that is permitted to be accessed by the program, the game area is allocated behind the non-game program area, and the unused area is in front of the game program area behind the non-game program area. Is assigned, and based on the parameters set in the HW parameter area, a group of areas (from the game program area) including the area from the start address of the non-game program area to the final address of the game program in the program / data area. The area up to the non-gaming data area) is collectively set as a designated area where the IAT circuit allows program running, and even if program running in other areas is prohibited, the intention due to malicious programs and illegal data It is possible to prevent control that is not performed.

Further, in the above, the configuration is such that the area itself that allows the program running is set in the program / data area, but the program running is indirectly permitted by setting the area that prohibits the program running in the program / data area. The configuration may be such that an area is set.

[Instructions used by the program]
The program executed by the main control unit 41 includes a main routine that manages the progress of the entire program and a subroutine that is called during the execution of another program.

Further, a CALL instruction is included as an instruction for causing the main control unit 41 to execute the program stored in the program / data area.

The CALL instruction is an instruction that calls and executes a subroutine stored at an address specified in the main routine or the subroutine. When calling a subroutine by a CALL instruction, the main control unit 41 stores the address of the caller in the stack area, and calls and executes the subroutine stored in the designated address. Then, after the subroutine is completed, the address of the caller stored in the stack area, that is, the program of the main routine or the subroutine of the caller who executed the CALL instruction is returned.

Further, the CALL instruction includes a normal CALL instruction and a CALLV instruction which is a special CALL instruction. The normal CALL instruction is an instruction that calls a subroutine by specifying both the upper address and the lower address and specifying the address by the specified upper address and lower address, whereas the CALLV instruction only uses the lower address. By designating, it is an instruction to specify an address by a preset upper address and a designated lower address in the vector table area of ROM 41b and call a subroutine. A program (subroutine) used in the game program is stored in the storage area of the specified address. Therefore, the CALLV instruction makes it possible to call the program (subroutine) used in the game program with a smaller amount of data than the normal CALL instruction.

The RST instruction calls and executes a subroutine stored in a specific address corresponding to a specified value by specifying a value corresponding to a plurality of predetermined specific addresses (a value whose capacity is smaller than the specific address). It is an instruction to make. A program (subroutine) used in the game program is stored in the storage area of the specific address. Therefore, the RST instruction makes it possible to call the program (subroutine) used in the game program with a smaller amount of data as compared with the above-mentioned ordinary CALL instruction and CALLV instruction. When the subroutine is called by the RST instruction, the main control unit 41 stores the address of the caller in the stack area, and calls and executes the subroutine stored in the specific address corresponding to the specified value. Then, after the subroutine is completed, the address of the caller stored in the stack area, that is, the main routine or subroutine of the caller who executed the RST instruction is returned.

The main control unit 41 identifies an address by the upper address set in the vector table area by the CALLV instruction and the lower address specified by the CALLV instruction, and is used in the game program stored in the specified address. Call and execute a program (subroutine). Therefore, the upper addresses that form a part of the addresses used when calling the subroutines that are used particularly frequently in the game program are set in advance in the vector table, and the addresses are set based on the upper addresses set in the vector table. Since it is specified, it is possible to call a subroutine with a smaller amount of data than a normal CALL instruction that calls a program by specifying both the upper address and the lower address, and the address is specified when calling these subroutines. It is possible to reduce the waste of the program for doing so.

Further, since the capacity of the value specified by the RST instruction (value corresponding to a plurality of predetermined addresses) is smaller than the capacity of the address, the RST instruction has a smaller amount of data than the normal CALL instruction. Since it is possible to call the program (subtractor) used in the game program in the game program, the data capacity of the game program can be reduced by using the RST instruction in the game program.

The main control unit 41 includes an LD instruction as an instruction to read data stored in the program / data area. The LD instruction is an instruction to read the data stored at the address specified in the main routine or the subroutine into the specified register. The main control unit 41 reads the data stored at the address specified by the LD instruction, and stores the read data in a register (for example, an internal function register) specified by the LD instruction.

Further, the LD instruction includes a normal LD instruction and an LDQ instruction which is a special LD instruction. A normal LD instruction is an instruction to read data stored in an area of ROM 41b or RAM 41c by a designated upper address and lower address by designating both an upper address and a lower address. By specifying only the lower address, the LDQ instruction specifies the address by the upper address preset in the special register (Q register) in the internal function register area of the RAM 41c and the specified lower address, and the ROM 41b or It is an instruction to read the data stored in the area of the RAM 41c and store the read data in the specified register, and to store the predetermined data in the predetermined register with a smaller amount of data as compared with the normal LD instruction. Is possible.

When reading the data stored in the areas of ROM 41b and RAM 41c in the main routine or subroutine, all the addresses (upper part and lower part) indicating the area are specified by using the LDQ instruction which is a special LD instruction. It is possible to read the data in the area by specifying only the lower part of the address instead of. By using the LDQ instruction, it is possible to read data with a smaller amount of data than the normal LD instruction that reads data by specifying both the upper address and the lower address, and the address is specified when reading the data. It is possible to reduce the waste of the program for doing so.

The LD instruction (ordinary LD instruction, LDQ instruction, etc.) is also used for other processing using the storage area. The other processes include a process of referencing data stored in the storage area (for example, the process of Sa1 in FIG. 4 described later), a process of setting data in the storage area, and the storage process. It includes a process of erasing (clearing) the set data (for example, a process of Sa16 in FIG. 5 described later) and the like.

Further, the game program is a program related to the progress of the game, and is a program for executing a process that hinders the progress of the game unless the process based on the program is executed. On the other hand, the non-game program is a program that is not related to the progress of the game, and even if it is called from the game program and returns to the game program without executing the process based on the program, the game can be progressed. It is a program for executing processing.

In other words, the non-game program is a program that executes a process different from the process related to the progress of the game. The "process different from the process related to the progress of the game" is, for example, in the process of initializing the non-game RAM area in the non-game RAM area initialization process, the medal sensor check process in the medal sensor process, and the data processing for the combination monitor. Includes each state count processing, sensor monitoring processing in non-game related processing, test signal output processing, medal passing time timer update processing, combination ratio monitor display data selection processing, and the like. Further, as shown in FIG. 3A, the game program area and the non-game program area are separately configured. Therefore, for example, even if the capacity of the game program area is defined, it is not necessary to consider the capacity of the non-game program area. Therefore, the degree of freedom regarding the design of the game program area can be improved.

In the game program, with respect to the above-mentioned CALL instruction and LD instruction, any instruction including a CALLV instruction which is a special CALL instruction, an RST instruction, and an LDQ instruction which is a special LD instruction may be used, and a special CALL instruction may be used. It is possible to specify the address by using the above and call the subroutine, or to read the specific game data and non-game data in the ROM 41b and the RAM 41c by using the special LD instruction.

In the non-game program, the normal CALL instruction is used for the above-mentioned CALL instruction, while the CALLV instruction, which is a special CALL instruction, is not used. Therefore, while a normal CALL instruction may be used to specify an address and a subroutine may be called, a special CALL instruction may not be used to call a subroutine. Therefore, it is possible to prevent the non-game program from inadvertently accessing the game program area in the ROM 41b.

Further, in the non-game program, a normal LD instruction can be used for the above-mentioned LD instruction. As a result, in the non-game program, it is possible to specify the address and read the predetermined data by using the normal LD instruction. On the other hand, the LDQ instruction is not used in the non-game program. Therefore, it is possible to prevent the process of reading data by the LDQ instruction from being inadvertently executed.

The control contents of various processes performed by the main control unit 41 by executing the game program and the non-game program will be described with reference to FIGS. 4 to 6. Further, FIGS. 4 to 6 show control contents when the gaming machine is a slot machine.

[Processing at startup and startup processing of main control unit 41]
The activation process performed by the main control unit 41 will be described with reference to FIGS. 4 and 5. The activation process is a subroutine included in the game program.

When a predetermined start condition is satisfied, the main control unit 41 starts with the timer interrupt set to be disabled due to the occurrence of a reset, and performs various processes according to the program stored in the ROM 41b. After starting, first, the startup setting process included in the game program is performed to initialize all the output ports, and the internal registers (including the internal function registers) included in the main control unit 41 are set in advance in the predetermined area of the ROM 41b. Performs the initial setting process included in the game program, which is initialized based on the set built-in register initialization table. As described above, in the present embodiment, the initialization of the internal function register and the like are executed when the power supply is started. Further, the predetermined start conditions are the condition that is satisfied when the power supply to the game machine 1 is started (the power supply to the game machine 1 is detected), and the system is reset for the game machine 1. Including the conditions that are satisfied by. The execution condition of the system reset includes, for example, when a reset operation is executed by the user, when a timeout signal is generated from the watchdog timer, and when an IAT signal is generated from the IAT circuit.

As a modification, the initialization processing of the internal registers (including the internal function registers) included in the main control unit 41 is not executed by the program, but is hardware (for example, an initialization circuit (not shown in particular)). May be configured to be executed by.

As shown in FIG. 4, first, in Sa1A, the main control unit 41 sets specific value data in the Q register. In the following, "specific value data" is simply referred to as "specific value". Here, a specific value will be described. In the present embodiment, when the power is restored from the power failure (when the power supply is started, that is, when the startup process is executed), when the power failure occurs (power supply) based on the data such as the game RAM area. Return to the control state (when the supply is stopped). Therefore, the game RAM area is an important area from the viewpoint of returning to the control state.

As shown in FIG. 2, the upper address of the game RAM area is "F0". Here, the specific value is an area in which a higher address of an area different from the game RAM area can be specified. In the present embodiment, the different regions are the "internal function register" and the "signal region". That is, the specific value is a value that can specify "F5", which is the upper address of the internal function register. In other words, the specific value is a value used to specify "F5", which is the upper address of the internal function register. Further, the specific value is also a value capable of specifying the upper address "F5" of the signal region.

Sa1 When the processing of A is completed, to perform various types of setting process. In these various setting processes, a plurality of setting processes (N being N; N is an integer of 2 or more) are executed. The N setting processes include, for example, a random number start setting, a serial communication circuit setting, a reset / interrupt controller setting, and the like. By the N setting processing, N setting values (hereinafter, also referred to as "start-up setting values") corresponding to each of the N settings are stored in each of the N areas in the internal function register. Register.

Here, the storage of N start-up set values in the internal function register is also executed by the LDQ instruction. Specifically, the N settings are set based on the specific values (upper address is F5) stored in the Q register in Sa1A and the values (lower addresses) specified for each of the N in the LDQ instruction. The value is stored in each of the N areas in the internal function register.

After the processing of Sa1B is completed, the process proceeds to Sa1. In Sa1, a process of referencing the signal area of the input port is executed. When the power supply to the game machine 1 is stopped (when a power failure occurs), the power failure detection circuit (not shown) transmits a power failure detection signal to the main control unit 41. The power failure detection signal is a signal indicating that a power failure has occurred (voltage drop). In addition, information related to the power failure detection signal (for example, a power failure detection signal flag) is stored in the signal area. When the power failure detection signal is output from the power failure detection circuit, the power failure detection signal flag is stored in the signal area (ON state), and when the power failure detection signal is not output from the power failure detection circuit, the power failure detection signal flag is in the signal area. It will not be stored in (OFF state).

In the present embodiment, the address of this signal region is "F560". As a modification, the signal region may be any address as long as the upper address is "F5".

That is, in Sa1, the lower address (60) of the signal region is specified by the LDQ instruction, and is based on the lower address and the specific value stored in the Q register (F5, which is the upper address of the signal region). To specify the address of the signal area. In Sa1, the signal region (signal region of the input port) which is the region of the specified address is referred to.

In Sa2, it is determined whether or not the power failure detection signal output from the power failure detection circuit (not shown) is in the ON state (whether or not the power failure detection signal flag is stored in the signal area) (Sa2). .. Then, when the power failure detection signal is in the ON state, it waits until the power failure detection signal is in the OFF state (YES in Sa1). After that, the power supply voltage of the slot machine 1 becomes normal, and after the power failure detection signal is turned off (NO of Sa1), the process proceeds to Sa3A.

In Sa3A, the permission process for permitting access to the usable area of the RAM 41c is executed by the LDQ instruction. Specifically, the permission process is executed by setting a permission flag in the RAM access area in the internal function register. In the present embodiment, the address of the RAM access area is set to "F550".

That is, in Sa3A, the lower address (50) of the RAM access area is specified by the LDQ instruction, and the lower address and the specific value stored in the Q register (F5 which is the upper address of the RAM access area) are used. The address of the RAM access area is specified based on. In Sa3A, the permission flag is set by the LDQ instruction for the RAM access area which is the area of the specified address.

Next, in Sa3B, the specific value (specific value data) is erased in the Q register in which the specific value is set, and the predetermined value data is set. In the following, "predetermined value data" is simply referred to as "predetermined value". Here, the predetermined value is data that can specify the upper address "F0" of the game RAM area. In other words, the predetermined value is data used to specify the upper address "F0" of the game RAM area. That is, by executing the processing of Sa3B, the specific value (F5 can be specified) is changed to a predetermined value (F0 can be specified).
In this way, during the period in which the specific value is set in the Q register (the period from Sa1A to Sa3B, the period from Sk8 in the power interruption process of FIG. 6 described later to the end of the power interruption process), the function setting register When the process using the function setting register is executed, the LDQ instruction executes the process using the function setting register). Therefore, during the period in which a specific value is set in the Q register, the program capacity can be reduced as compared with the configuration in which the function setting register is used by the LD instruction.
Further, in the period in which the predetermined value is set in the Q register (for example, the period from the time when the processing of Sa3B is executed to the time when the processing of Sk8 (see FIG. 6 described later) of the power interruption processing is executed). When the process using the game RAM area is executed, the process using the game RAM area is executed by the LDQ instruction. Therefore, during the period in which the Q register is set to the predetermined value, the program capacity can be reduced as compared with the configuration in which the game RAM area is used by the LD instruction.

Next, the parity of the predetermined area of the RAM 41c is calculated (Sa3), and a predetermined initial address is set in the stack pointer (Sa4). Then, it is determined whether or not the parity calculated in the step of Sa3 is normal (Sa5). This determination is performed using the RAM parity adjustment data calculated by Sk6, which will be described later. When the parity is normal, the fixed data for RAM destruction diagnosis set in the predetermined area of the RAM 41c is acquired in Sk7 of the power interruption processing described later (Sa6), and the RAM 41c is based on the fixed data for the RAM destruction diagnosis. Diagnose whether or not the stored contents have been destroyed (Sa7).

When it is determined that the parity is normal in the step of Sa5, and when the stored content of the RAM 41c is diagnosed in the step of Sa7, the RAM 41c is set to the RAM 41c based on the parity of the RAM calculated in the step of Sa3 and the diagnosis result in Sa7. It is determined whether or not there is an abnormality (Sa8). The case where the RAM 41c has an abnormality is a case where the parity is not normal, or a case where it is diagnosed that the parity is normal but the storage content is abnormal.

Then, when there is an abnormality in the RAM 41c, the values of the flag registers in which the calculation results are stored among the registers provided in the main control unit 41 are saved in the game stack area of the game RAM area by storing them in a predetermined order. After that (Sa9), the non-game RAM area initialization process included in the non-game program is called and performed (Sa10). Then, in the non-game RAM area initialization process, after initializing the non-game RAM area of the RAM 41c, the process returns to the start-up process. Then, when returning to the activation process, the value of the flag register saved in the game stack area in the step of Sa9 is sequentially read from the game stack area in the reverse order of saving and set in the flag register. , The flag register is restored to the state before the RAM area initialization process is performed (Sa11).

In the non-game RAM area initialization process, first, the value of the current address of the game stack area indicated by the stack pointer SP used by the calling game program is stored in a predetermined area of the non-game RAM area and saved. Let me. After that, a predetermined value of the non-game stack area (a value stored in a predetermined area of the non-game RAM area as an address indicated by the stack pointer SP at the end of the previous non-game program) is set as the value of the stack pointer SP. By doing so, the stack pointer SP is set for the non-game program. Then, the values of all the registers included in the main control unit 41 including the above-mentioned flag register are stored in the non-game stack area of the non-game RAM area specified by the stack pointer SP in a predetermined order to save the values. After that, the start address (the first address of the unused area 4) and the end address (the last address of the non-game RAM area) of the initialization target RAM are specified, and the data of the specified address is set with the start address as the initial value of the specified address. By repeatedly executing the process of updating the specified address to the next address after clearing the above until the specified address becomes the end address, the area from the start address to the end address of the initialization target RAM (in this embodiment, The area from the beginning of the unused area 4 to the end of the non-game RAM area) is initialized. Then, the values of the registers stored and saved in the non-game stack area when the non-game RAM area initialization process is started are sequentially read from the non-game stack area in the reverse order of saving, and the order is as follows. By setting the register corresponding to, all the registers are restored to the state when the non-game RAM area initialization process is started. After that, when the non-game RAM area initialization process is started, the value of the stack pointer SP saved in the predetermined area of the non-game RAM area is set in the stack pointer SP to start the non-game RAM area initialization process. The stack pointer SP is returned to the state at that time, and the non-game RAM area initialization process is terminated.

In the non-game RAM area initialization process, the capacity of the initialization target RAM is calculated by designating the start address and end address of the initialization target RAM, and the RAM area corresponding to the capacity is used as the initialization target RAM. By clearing sequentially from the start address, the area from the start address to the end address of the initialization target RAM may be initialized.

When it is determined that there is no abnormality in the RAM 41c in the step of Sa8, or when the register is restored in the step of Sa11, the fixed data for RAM destruction diagnosis set in the RAM 41c is cleared (Sa12), and the RAM 41c is abnormal. If there is, the initialization start address at the time of RAM destruction for designating the address of the game RAM area to be initialized is set (Sa13). After that, it is determined whether or not the setting key switch is in the ON state by referring to the input port (Sa14).

If it is determined in the step of Sa14 that the setting key switch is in the ON state, the setting change process is performed. In the setting change process, the setting value is controlled to a setting change state in which the setting value can be changed by a clerk of a game store or the like. This set value is a value indicating the degree of advantage for the player.

When it is determined that the setting key switch is not in the ON state in the step of Sa14, it is determined whether or not there is an abnormality in the RAM 41c based on the parity of the RAM calculated in the step of Sa3 and the diagnosis result in Sa7 (Sa15). When it is determined that there is no abnormality in the RAM 41c, the output buffer for outputting the external output signal is cleared (Sa16). This output buffer is provided in a predetermined area of the game RAM area of the RAM 41c. Further, the reel error counter is set in a predetermined area of the RAM 41c and is used to count the number of times a reel rotation error is detected (Sa17). This reel error counter is provided in a predetermined area of the game RAM area of the RAM 41c. After that, by setting the address at the time of power failure in the stack pointer SP based on the stored contents of the RAM 41c, the stack pointer is returned to the state at the time of power failure (Sa18), and the port input process is performed twice in succession (Sa19). , Sa20).

In the port input process, the input status data related to the input status of the detection signals of various switches input to the parallel input port 511 (input data indicating the current input status of various switches, the previous input data and the current input data are the same. This is a process of updating the confirmed data indicating that the confirmation data is, and the edge data indicating that the confirmed data has changed from the previous time. Port input buffers 0 to 2 for storing input state data of various switches are provided in a predetermined area of the game RAM area of the RAM 41c, and the input state data of the various switches updated by the port input process is the input state data of the various switches. It is stored in a predetermined bit of a port input buffer defined in advance for each type. In the port input process, the detection states (ON state or OFF state) of various switches set to the input ports 0 to 2 of the parallel input port 511 are stored as input data in a predetermined bit of the port input buffer. Also, compare the detection status (ON state or OFF state) in the previous and current port input processing, and if the current and previous input data are in the same state, indicate the detection status of the current input data. On the other hand, if the input data of this time and the previous time are different, the confirmed data of the previous time is maintained. Further, comparing the confirmed data of this time and the previous time, when the confirmed data changes from the OFF state to the ON state, the ON edge data indicating that the confirmed data has changed from the OFF state to the ON state is input to the port input buffer 0. When the confirmed data changes from the ON state to the OFF state, the OFF edge data indicating that the confirmed data has changed from the ON state to the OFF state is stored in the predetermined bits of ~ 2 and is specified in the port input buffers 0 to 2. Store in bits. The input data, confirmed data, and edge data of various switches stored in the port input buffer can be referred to from the gaming program and the non-gaming program.

Further, in the start-up process, the port input process is performed twice in succession, and when the port input process is subsequently performed, the input state of various switches after the start-up process is performed, that is, the power to the game machine. Since the input status data related to the input status of the detection signals of the various switches is created based on the input status of the various switches after the supply is restarted, it is possible to prevent the unintended input status from being specified. It has become like. Further, in the port input process, the finalized data may be created based on the input data acquired by the port input process three or more times (for example, the input data of this time, the previous time and the time before the previous time). In such a configuration, the port input process is continuously performed in the start process one less than the number of port input processes required to create the finalized data, so that after the start process is performed. When the port input process is performed, it is possible to create input state data based on the input state of various switches after the start process is performed.

After performing the port input processing in the steps of Sa19 and Sa20, referring to the predetermined input port (Sa21), it is determined whether or not the reset / setting switch is in the ON state (Sa22), and the reset / setting switch is used. Is in the ON state, status data indicating that the reset / setting switch is in the ON state is set in a predetermined area of the RAM 41c (Sa23).

The reset / setting switch functions as a reset switch for canceling the error state or the stop state when the state is different from the setting change state, and changes the set value in the setting change state. Functions as a switch.

When it is determined that the reset / setting switch is not in the ON state in the step of Sa22, and after the status data is set in the step of Sa23, a return command indicating that the control state before the power failure has been restored is sent to the sub-control unit 91. After transmission (Sa24), in the command transmission process of the timer interrupt process (main), a door command transmission flag indicating that a door command indicating the detection state of the door open detection switch 25 is transmitted is set in a predetermined area of the RAM 41c (Sa24). Sa25). In the command transmission process, normally, the door command is transmitted when the detection state of the door open detection switch 25 changes, but when the door command transmission flag is set in the predetermined area of the RAM 41c, the door open detection switch 25 is transmitted. A door command indicating the detection state of the door open detection switch 25 is transmitted regardless of whether or not the detection state of the door has changed.

Then, after setting the door command transmission flag in the step of Sa25, all the registers are returned to the state before the power failure stored in the RAM 41c (Sa26), and the timer interrupt is set to enable (Sa27). After terminating the start-up process and shifting to the timer interrupt process (main), the process returns to the process in the main process that was executed before the power supply to the slot machine 1 was stopped.

On the other hand, if it is determined in the step of Sa15 that there is an abnormality in the RAM 41c, the game RAM initialization process is performed (Sa28), and the game RAM area of the RAM 41c is performed from the RAM destruction initialization start address set in the step of Sa13. Initialize the area up to the end of. After that, similarly to the processing from the steps of Sa9 to Sa11, the value of the flag register in which the flag is set is saved in the game stack area of the game RAM area (Sa29), and then the non-game included in the non-game program. After calling the game RAM area initialization process (Sa30) to initialize all the non-game RAM areas of the RAM 41c, the player returns to the caller and restores the register saved in the step of Sa29 (Sa31).

After returning the register in the step of Sa31, the door command transmission flag is set (Sa32), the timer interrupt is set to enable (Sa33), and the RAM error code (E8) indicating that there is an abnormality in the RAM 41c is set. It prepares in a predetermined register (Sa34), ends the start-up process, and shifts to the error process.

In the error processing, the error state is controlled so that the progress of the game is disabled. Further, an error command capable of identifying the error code (E8) prepared in the predetermined register is transmitted to the sub-control unit 91, and the error code (E8) can be referred to the predetermined area of the RAM 41c in other processing. Set as an error flag. Further, the error code (E8) is controlled to be displayed on the game auxiliary display (not particularly shown). After that, the error state is controlled until it is specified that the error state release condition corresponding to the error code (E8) prepared in the predetermined register is satisfied. When the RAM error error code (E8) is prepared in a predetermined register and the error state is entered, the setting change state is entered by turning on the power of the game machine with the setting key switch turned on. By initializing all the game RAM areas, it is possible to surely eliminate the abnormality of the data in the RAM 41c and release the error state. On the other hand, when the power switch is turned on without turning on the setting key switch, the abnormality of the RAM 41c is detected again, and the error state occurs again.

In this way, the main control unit 41 first performs the start-up process after the power supply to the slot machine 1 is started, and in the start-up process, the power supply to the slot machine 1 is started. Depending on the state of the main control unit 41 at that time, the process shifts to one of timer interrupt processing (main), setting change processing, and error processing. Then, when shifting to these processes, a command capable of specifying the type of the process to be transferred is transmitted to the sub-control unit 91, and when shifting to the timer interrupt process (main), that is, a game. When returning to the control state before the power supply to the machine is stopped, a return command is sent to the sub-control unit 91, and when the setting change process is started to shift to the setting change state, When a setting command (start) is transmitted to the sub control unit 91 and error processing is started due to an abnormality in the RAM 41c to shift to an error state, an error command is transmitted to the sub control unit 91.

After shifting from the startup process to the setting change process, the main control unit 41 returns to a state in which the game can be progressed through the setting change state, and the game can be progressed. When returning to, the setting command (end) that can specify that the setting change state is terminated is transmitted to the sub-control unit 91, but the return command is not transmitted. Further, after shifting to error processing due to an abnormality in the RAM 41c, the error state is canceled by shifting to the setting change processing as described above, so that the game can be returned to a state in which it can proceed. Even when the error processing is completed and the game returns to a state in which the game can proceed, the return command is not transmitted to the sub-control unit 91.

As described above, the main control unit 41 of the present embodiment is activated when the power supply to the game machine is started, performs the startup setting process included in the game program, and all outputs are performed by the startup setting process. It is designed to initialize the port.

Further, the main control unit 41 calls the non-game RAM area initialization process included in the non-game program when it determines that there is an abnormality in the RAM 41c in the start-up process after performing the start-up setting process, and the RAM 41c. Initializes a predetermined area of the non-game RAM area of. Further, in the startup process, the RAM initialization process included in the game program is called to initialize a predetermined area of the game RAM area of the RAM 41c, and the game RAM area is initialized by the game program and the non-game RAM. The area is configured to be initialized by a non-game program.

Next, the control content of the power interruption process (main) performed by the main control unit 41 will be described with reference to FIG. The power interruption process (main) is a subroutine included in the game program.

The main control unit 41 executes a power cut process (main) when it is determined in the timer interrupt process (main) described above that the voltage drop state has continued for a predetermined time. That is, when the main control unit 41 detects that the power supply to the game machine has stopped, the power interruption process is executed.

As shown in FIG. 6, in the power interruption process (main), first, the values of all the registers included in the main control unit 41 are saved in the game stack area of the game RAM area in a predetermined order (Sk1). ), The current address of the game stack area indicated by the stack pointer SP is stored in a predetermined area of the game RAM area to save it (Sk2). The predetermined area of the game RAM area including the game stack area of the game RAM area in which the main control unit 41 stores the register value and the predetermined area of the game RAM area in which the value of the address indicated by the stack pointer SP is stored is backed up. It is backed up by the power supply, and even if the power supply to the slot machine 1 is stopped, the stored contents of the game RAM area are saved as long as the power is supplied by the backup power supply.

Next, all of the plurality of output ports are initialized (Sk3). As a result, the output of the signals output from the plurality of output ports is stopped.

Next, the main control unit 41 sets the destruction diagnosis data in a predetermined area of the RAM 41c (Sk4). In the present embodiment, it is assumed that the predetermined area of the RAM 41c in which the destruction diagnosis data is set is the game RAM area. As a modification, the predetermined area of the RAM 41c in which the destruction diagnosis data is set may be a different area from the game RAM area.

Next, the parity adjustment data set in the predetermined area of the RAM 41c is cleared (Sk5). Next, the main control unit 41 calculates the parity adjustment data based on all the storage areas (including the unused area and the unused stack area) of the RAM 41c. In the present embodiment, the main control unit 41 calculates the parity adjustment data of the new RAM 41c so that the exclusive OR of all the storage areas (including the unused area and the unused stack area) of the RAM 41c becomes 0. To do. Next, the main control unit 41 sets the parity adjustment data in a predetermined area of the RAM 41c (Sk7). In the present embodiment, it is assumed that the predetermined area of the RAM 41c in which the parity adjustment data is set is the game RAM area. As a modification, the predetermined area of the RAM 41c in which the parity adjustment data is set may be a different area from the game RAM area.

Next, the main control unit 41 sets a specific value in the Q register. As described above, the specific value is information that can specify the upper address (F5) of the "internal function register", which is an area different from the game RAM area.

A predetermined value is set in the Q register between the time when the power failure processing is executed and the time when the Sk8 processing is executed (see FIG. 7 described later). For example, the identification of the area A in which the destruction diagnosis data is set in Sk4, the identification of the area B in which the RAM parity adjustment data is set in Sk5, the identification of the area C in which the RAM parity adjustment data of Sk7 is set, and the like are performed. It is executed using the LDQ instruction. In Sk4, the address of the area A is specified based on the predetermined value set in the Q register and the value specified by the LDQ instruction. Further, in Sk5, the address of the area B is specified based on the predetermined value set in the Q register and the value specified by the LDQ instruction. Further, in Sk7, the address of the area C is specified based on the predetermined value set in the Q register and the value specified by the LDQ instruction.

Next, in Sk9, the prohibition of access to the RAM 41c is set. The prohibition process of Sk9 will be described. This prohibition process is executed by using a specific instruction. Specifically, the prohibition process is executed by setting an access prohibition flag in the RAM access area (the address is "F550" as described above) in the internal function register.

That is, in Sk9, the lower address (50) of the RAM access area is specified by the LDQ instruction, and the lower address and the specific value stored in the Q register (F5 which is the upper address of the RAM access area) are used. The address of the RAM access area is specified based on. In Sk9, the access prohibition flag is set by the LDQ instruction for the RAM access area which is the area of the specified address.

Next, in Sk10, the prohibition of timer interrupt is set. The prohibition process of Sk10 will be described. This prohibition process is executed by using the LDQ instruction. Specifically, the prohibition process is executed by setting the timer interrupt prohibition flag in the timer interrupt area (address is "F560") in the internal function register.

That is, in Sk10, the lower address (60) of the timer interrupt area is specified by the LDQ instruction, and the lower address and the specific value stored in the Q register (F5, which is the upper address of the timer interrupt area). ) And the address of the timer interrupt area is specified. In Sk10, the timer interrupt prohibition flag is set by the LDQ instruction for the timer interrupt area which is the area of the specified address. In the following, the RAM access prohibition flag and the interrupt prohibition flag described in Sk9 and Sk10 are also referred to as “set value at the time of power failure”. It can be said that the set value at the time of power failure is a "value corresponding to the stop of power supply".

After the processing of Sk10 is completed, the loop processing is started. In the loop process, the device waits while monitoring the output status of the voltage drop signal. In this state, when the voltage drop signal is no longer input, the voltage recovery is determined, and the program is started from the start processing (main). On the other hand, if the voltage drops while the voltage drop signal is being input, the operation is stopped internally.

When the power supply of AC100V from the outside is stopped by the above processing, the power interruption processing (main) is executed, and the register value before the power interruption is saved in the game stack area of the game RAM area. Since the contents of the predetermined area of the game RAM area of the RAM 41c including the game stack area are also held by supplying the backup power supply, the start-up process executed when the power supply to the slot machine 1 is restarted ( In the main), it is possible to return to the control state before the power failure.

[About the setting timing of specific values and the setting timing of predetermined values]
Next, with reference to FIG. 7, the timing of setting a specific value in the Q register and the timing of setting a predetermined value in the Q register will be described. Note that each timing shown in FIG. 7 is merely an example, and the period between each timing may be another period.

It is assumed that the power interruption process is started at the timing T0. It is assumed that a specific value is set in the Q register at the timing T1 during the power interruption process (see FIG. 6) (Sk8 in FIG. 6). A predetermined value is set in the Q register in the period up to this timing T1. Further, after the timing T1, a specific value is set in the Q register. Further, at the timing T2 after the timing T1, access to the RAM 41c is set to be prohibited (Sk9). Then, at the timing T3, it is assumed that the power interruption process is completed. In the example of FIG. 7, when a specific value is set in the Q register, access to the RAM 41c is prohibited. However, after the specific value is set in the Q register, other processing is performed. After executing the execution, access to the RAM 41c may be prohibited.

Further, it is assumed that the start-up process (FIGS. 4 and 5) is started at the timing T4. When this activation process is executed, a specific value is set in the Q register (see Sa1A in FIG. 4). As a result, a specific value is set in the Q register. After that, at timing T5, access to the RAM 41c is permitted (see Sa3A). A predetermined value is set in the Q register at the timing T6 after the timing T5 (see Sa3B). As a result, a predetermined value is set in the Q register without setting a specific value. After that, it is assumed that the start-up process is completed at the timing T7.

[About the effect of this embodiment]
Next, the effect of this embodiment will be described.

(1-1) As described above, the game including the game stack area of the game RAM area in which the main control unit 41 stores the register value and the predetermined area of the game RAM area in which the value of the address indicated by the stack pointer SP is stored. A predetermined area of the RAM area is backed up by a backup power supply, and in the power interruption process, a process of saving the register shown in Sk1 to the game RAM area, a process of saving the stack pointer of Sk2 to the game RAM area, and the like are executed. .. Further, in the start-up process, the control state (control state at the time of executing the power interruption process) is restored based on the data stored in the game RAM area. Therefore, the game RAM area is an important area.

Further, the power interruption process is executed when it is determined that the voltage drop state has continued for a predetermined time. Therefore, the case where the power interruption process is executed is an unstable state from the viewpoint of power supply. In such an unstable state, the LDQ instruction may be executed due to a malfunction or the like.

If a predetermined value (a value indicating the upper address "F0" of the game RAM area) is stored in the Q register in the power interruption process and the LDQ instruction is executed due to a malfunction or the like, the LDQ instruction is executed in an important area. Access to a certain game RAM area (access not intended by the designer of the game machine) will be executed.

Therefore, in the present embodiment, a specific value is stored in the Q register at a predetermined timing of the power interruption process (timing T1 in the example of FIG. 7). The specific value is a value capable of specifying the upper address "F5" of an area different from the game RAM area (internal function register in this embodiment). Therefore, even if the LDQ instruction is executed due to a malfunction or the like in the power interruption process executed when the power supply is unstable, the game RAM area is not accessed (access to the internal function register). Will be). Therefore, it is possible to reduce the possibility that the access that the designer does not intend is executed.

The start-up process is a process executed immediately after the power supply is started. Therefore, the case where the startup process is executed is an unstable state from the viewpoint of power supply. In such an unstable state, the LDQ instruction may be executed due to a malfunction or the like.

If a predetermined value (a value indicating the upper address "F0" of the game RAM area) is stored in the Q register in the start-up process and the LDQ instruction is executed due to a malfunction or the like, it is an important area. Access to the game RAM area (access not intended by the designer) will be executed.

Therefore, in the present embodiment, a specific value is stored in the Q register at a predetermined timing of the start processing (timing T4 in the example of FIG. 7). The specific value is a value capable of specifying the upper address "F5" of an area different from the game RAM area (internal function register in this embodiment). Therefore, even if the LDQ instruction is executed due to a malfunction in the startup process executed when the power supply is unstable, the game RAM area is not accessed (the internal function register is accessed). ). Therefore, it is possible to reduce the possibility that the access that the designer does not intend is executed.

Further, the address of the storage area (including the game RAM area and the internal function register) includes the first information (for example, the upper address of the address) and the second information (for example, the lower address of the address), for example. , The first information is preferably stored in a predetermined storage area (for example, Q register). Then, in the specific instruction (for example, LDQ instruction), the address is specified from the first information and the second information, and the data is read out from the storage area of the specified address. At the time of this reading, the address is specified from the first information stored in the predetermined storage area and the second information specified by the specific instruction. According to such a configuration, the program capacity of the specific instruction can be reduced as compared with the configuration in which both the first information and the second information are specified in the specific instruction to specify the address.

Further, in the power interruption processing and the start processing, when a predetermined value is set in the Q register, processing using the game RAM area (area in which the address can be specified from the predetermined value) (for example, data from the game RAM area). When executing the process of reading the data, the process of writing the data to the game RAM area, etc.), the LDQ instruction is used. Therefore, the program capacity of the LDQ instruction in the processing using the game RAM area can be reduced.

Further, in the power interruption processing and the start processing, when a specific value is set in the Q register, processing using the internal function register (area in which the address can be specified from the specific value) (for example, data is stored in the internal function register). When executing the writing process, etc.), it is executed by the LDQ instruction. Therefore, the program capacity of the LDQ instruction in the processing using the internal function register can be reduced.

(1-2) When the power supply to the slot machine 1 is started, the start-up setting process is executed prior to the power failure process. In this startup setting process, the internal function register is initialized. In this way, even if the LDQ instruction is executed due to a malfunction or the like in the power interruption process after the specific value is set in the power interruption process, the LDQ instruction is initially set in the startup setting process. The internal function register to be converted will be accessed. Therefore, the possibility of a particular problem can be reduced.

(1-3) Further, confirmation data for confirming whether or not the data stored in the storage area (for example, the game RAM area) is normal (for example, for RAM destruction diagnosis shown in Sk4 of FIG. 6). A stoppage of power supply was detected in the confirmation data generation process (for example, the process of Sk4 and Sk7 in FIG. 6) that generates fixed data and RAM parity adjustment data shown in Sk7 and stores them in the specific storage area. Occasionally (for example, in a power failure process). Further, a specific value is set in the Q register after the confirmation data generation process is executed (for example, as shown in FIG. 6, after the processes of Sk4 and Sk7 are executed, the Q register is set in Sk8. A specific value is entered in).

Therefore, even if a specific instruction is erroneously executed after the confirmation data is stored in the specific storage area, the possibility of accessing the specific storage area in which the confirmation data is stored is reduced. it can.

(1-4) Further, the storage of the set values at the time of power failure (Sk9 and Sk10 in FIG. 6) in the internal function register is also executed by the LDQ instruction. Specifically, fixed data for RAM destruction diagnosis is based on a specific value (upper address is F5) stored in the Q register in Sk8 and a value (lower address) specified by the LDQ instruction in each of Sk9 and Sk10. And the RAM parity adjustment data is stored in the internal function register. Therefore, according to such a configuration, the program capacity of the LDQ instruction can be reduced as compared with the configuration in which all the addresses of the internal function registers are specified and the addresses are specified in the LDQ instruction.

(1-5) Further, as shown in FIG. 3, the upper address of the game RAM area is "F0", and the data used in the game program is stored in the game RAM area. On the other hand, the upper address of the non-game RAM area in which the data used in the non-game program is stored is "F3". Further, as shown in FIG. 7 and the like, “F0” is set in the Q register during the period from the execution of the start-up process to the execution of the power interruption process. If the LDQ instruction is used in a non-game program, the non-game RAM area whose higher address is "F3" should actually be accessed, but the game RAM area whose higher address is "F0". Will be accessed. Then, access to the game RAM area, which is an important area (access not intended by the designer of the game machine), will be executed.
Therefore, while the LDQ instruction is used in the game program, the LDQ instruction is not used in the non-game program. Therefore, it is possible to reduce the possibility that the game machine designer unintentionally accesses the game RAM area whose higher address is "F0".

(1-6) Further, as shown in FIG. 3, the upper address of the game program area is "00", and the program (subroutine) used in the game program is stored in the game program area. On the other hand, the upper address of the non-game program area in which the program (subroutine) used in the non-game program is stored is "20". Further, in the vector table area, a value (for example, "00") that can specify the upper address of the game program area is stored. If a special instruction (CALLV instruction) is used in a non-game program, the non-game program area whose upper address is "20" should actually be accessed, but the upper address is "00". A certain game program area (a storage area in which a program (subroutine) used in the game program is stored) is accessed. Then, in the non-game program, access to the game program area (access not intended by the designer of the game machine) is executed.

Further, a program (subroutine) used in the game program is stored in the storage area of the specific address corresponding to the value specified by the RST instruction. If a special instruction (RST instruction) is used in a non-game program, the non-game program area should actually be accessed, but the game in which the program (subroutine) used in the game program is stored. The program area is accessed. Then, in the non-game program, access to the game program area (access not intended by the designer of the game machine) is executed.
Therefore, while special commands are used in game programs, special commands are not used in non-game programs. Therefore, it is possible to reduce the execution of unintended access to the game program area by the designer of the game machine.

(2-1) Further, the Q register is different from the game RAM area until the access to the game RAM area is permitted (for example, until the RAM access shown at the timing T5 in FIG. 7 is permitted). A specific value that can specify the address of the internal function register that is an area (for example, a specific value that can specify the upper address "F5" of the internal function register) is stored. Further, after the access to the game RAM area is permitted (for example, after the RAM access shown at the timing T6 in FIG. 7 is permitted), a predetermined value that can specify the address of the game RAM area (for example, the game RAM area). A predetermined value that can identify the upper address "F0") is stored.

Further, it can be said that the game RAM area is an important area in the period until the access to the game RAM area is permitted (that is, the period in which the access to the game RAM area is prohibited).

Temporarily, during the period until RAM access is permitted (that is, the period during which RAM access is prohibited, for example, the period from timings T4 to T5), a predetermined value (upper address "F0" of the game RAM area is set in the Q register). ”) Is stored, the LDQ instruction may be executed due to a malfunction or the like. In this case, access (access not intended by the designer) will be executed in the game RAM area (important area) where access is prohibited. In the present embodiment, when the game RAM area for which access is prohibited is accessed, an illegal access reset is generated, thereby disabling the progress of the game. Therefore, if the LDQ command is executed due to a malfunction or the like, the progress of the game is inadvertently disabled.

Therefore, in the present embodiment, a specific value (a value that can specify the upper address of the internal function register) is stored until RAM access is permitted. Therefore, even if the LDQ instruction is executed due to a malfunction or the like until the RAM access is permitted, the game RAM area is not accessed, so that the progress of the game may be inadvertently disabled. Can be reduced.

As a modification, when RAM access is prohibited, even if the game RAM area is accessed, the "disable processing that disables the progress of the game" is not executed (hereinafter, the "disable processing non-execution configuration"). ".) May be used. In the case of such a configuration, when the game RAM area is accessed by executing the LDQ instruction due to a malfunction or the like when the RAM access is prohibited, the data stored in the game RAM area is stored. It may be changed.

On the other hand, in the present embodiment, when RAM access is prohibited, a specific value is set in the Q register. Therefore, it is possible to reduce the possibility that the game RAM area will be accessed even if the LDQ instruction is executed due to a malfunction or the like in the gaming machine in which the disabling processing non-execution configuration is adopted.

(2-2) Further, information (for example, a power failure detection signal flag) related to a power failure detection signal output from a power failure detection circuit (not shown) is stored in the signal area. The main control unit 41 executes the activation process based on the power failure detection signal (see, for example, Sa1 and Sa2 in FIG. 4). Further, when referring to the signal area of the input port of Sa1, the specific value set in the Q register in Sa1A (upper address of the signal area) and the value specified by the LDQ instruction in Sa1A (lower part of the signal area). Address) and the address of the signal area is specified. In Sa1, the signal region (signal region of the input port) which is the region of the specified address is referred to. Therefore, the program capacity of the LDQ instruction in the processing of Sa1 can be reduced as compared with the configuration in which all the addresses of the signal region are specified in the LDQ instruction to specify the addresses.

(2-3) Further, in the activation process of FIG. 4, a determination process of determining whether or not the data is normal is executed using the data stored in the storage area. In the present embodiment, as shown in Sa5 and Sa7 of FIG. 4, this determination process is a process of diagnosing the RAM 41c using the fixed data for RAM destruction diagnosis and the data for RAM parity adjustment. Further, a specific value is stored in the Q register until this determination process is executed (for example, in the example of FIG. 4, a specific value is set by the time the process of Sa7 is executed). Therefore, even if the LDQ instruction is erroneously executed by the time the determination process is executed, the possibility of accessing the game RAM area can be reduced, for example.

Further, in the present embodiment, the determination data (fixed data for RAM destruction diagnosis and RAM parity adjustment data) used for the determination process is stored in the game RAM area. Therefore, until this determination process is executed, that is, when the determination data stored in the game RAM area is stored, the determination data is changed by unintentionally accessing the game RAM area. The possibility of being done can be reduced.

(2-4) Further, the storage of the startup set value (Sa1B in FIG. 4) in the internal function register is also executed by the LDQ instruction. Specifically, the N settings are set based on the specific values (upper address is F5) stored in the Q register in Sa1A and the values (lower addresses) specified for each of the N in the LDQ instruction. The value is stored in each of the N areas in the internal function register. Therefore, according to such a configuration, the program capacity of the LDQ instruction can be reduced as compared with the configuration in which all the addresses of the internal function registers are specified and the addresses are specified in the LDQ instruction.

(3-1) Further, the address of the game RAM area is stored in the Q register until the access to the game RAM area is prohibited (for example, until the RAM access shown at the timing T2 in FIG. 7 is prohibited). A identifiable predetermined value (for example, a predetermined value that can identify the upper address "F0" of the game RAM area) is stored. Further, after the access to the game RAM area is prohibited (for example, after the RAM access shown at the timing T2 in FIG. 7 is prohibited), the address of the internal function register, which is an area different from the game RAM area, can be specified. A specific value (for example, a value capable of specifying the upper address "F5" of the internal function register) is stored.

Further, after the access to the game RAM area is prohibited, it can be said that the game RAM area is an important area.

If a predetermined value (a value indicating the upper address "F0" of the game RAM area) is stored in the Q register during the period after the RAM access is prohibited (for example, the period from timings T2 to T3). In some cases, the LDQ instruction may be executed due to a malfunction or the like. In this case, access (access not intended by the designer) will be executed in the game RAM area (important area) where access is prohibited. In the present embodiment, when the game RAM area whose access is prohibited is accessed, the progress of the game is disabled. Therefore, if the LDQ command is executed due to a malfunction or the like, the progress of the game is inadvertently disabled.

Therefore, in the present embodiment, after the RAM access is prohibited, a specific value (a value that can specify the upper address of the internal function register) is stored. Therefore, even if the LDQ instruction is executed due to a malfunction or the like after the RAM access is prohibited, the game RAM area is not accessed, so that the progress of the game may be inadvertently disabled. Can be reduced.

When RAM access is prohibited, a configuration that does not execute the "disable processing that disables the progress of the game" even if the game RAM area is accessed (hereinafter, referred to as "disable processing non-execution configuration"). May be. In the case of such a configuration, when the game RAM area is accessed by executing the LDQ instruction due to a malfunction or the like when the RAM access is prohibited, the data stored in the game RAM area is stored. It may be changed.

On the other hand, in the present embodiment, when RAM access is prohibited, a specific value is set in the Q register. Therefore, it is possible to reduce the possibility that the game RAM area will be accessed even if the LDQ instruction is executed due to a malfunction or the like in the gaming machine in which the disabling processing non-execution configuration is adopted.

[Modification example]
Although the main embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

(1) In the present embodiment, as shown in the power failure process of FIG. 6, it has been described that the setting of the specific value of Sk8 in the Q register is executed before the setting of the RAM access prohibition flag of Sk9. However, the Sk8 process may be executed after the Sk9 process. Alternatively, the Sk8 process and the Sk9 process may be executed at the same time. That is, the Sk8 process is a process that is executed when access to the RAM 41c is prohibited (when access to the RAM 41c is prohibited). Even with such a configuration, the same effect as that of the present embodiment is obtained.

(2) In the present embodiment, a backup power supply is supplied to the game RAM area as a method of returning to the control state (at the time of power failure detection) in the power failure process (at the time of power failure recovery) in the startup process. At the same time, as shown in Sk1 and Sk2 of FIG. 6, it has been described that the register and the stack pointer are saved. However, another method may be adopted as the method for returning to the control state at the time of power failure detection.

For example, a configuration may be adopted in which at least a part of the data indicating the control state when the power failure is detected is saved in the backup area. When such a configuration is adopted, it can be said that the backup area is an important area. Therefore, for example, a configuration may be adopted in which a predetermined value is a value that can specify the upper address of the backup area and the specific value is a value that can specify the upper address of an area different from the backup area. Even with such a configuration, the same effect as that of the present embodiment is obtained.

(3) Further, in FIG. 4, a period from when a specific value is set in the Q register processed by Sa1A to when a predetermined value is set in the Q register processed by Sa3B (hereinafter referred to as the first period). ), As a process using the function setting register, a process different from the process described in FIG. 4 is executed in addition to the process described in FIG. 4, or the process described in FIG. 4 is executed based on the LDQ instruction. It may be executed instead of. In this case, as a process using the function setting register during the first period, M processes (M is an integer of 2 or more) are executed based on the LDQ instruction (instruction that specifies only the lower address of the function setting register). This configuration can reduce the capacity of the program as compared with the configuration that executes the M processes based on the instructions that specify both the upper address and the lower address of the function setting register.

Further, in FIG. 6, in the period from the time when the specific value is set in the Q register by Sk8 to the entry into the loop (hereinafter referred to as the second period), the process using the function setting register is based on the LDQ instruction. Therefore, a process different from the process described in FIG. 6 may be executed in addition to the process described in FIG. 6, or may be executed in place of the process described in FIG. In this case, as a process using the function setting register during the second period, L processes (L is an integer of 2 or more) are executed based on the LDQ instruction (instruction that specifies only the lower address of the function setting register). This configuration can reduce the capacity of the program as compared with the configuration in which the L processes are executed based on the instruction for specifying both the upper address and the lower address of the function setting register.

(4) In the example of the power interruption process of FIG. 7, it has been described that the RAM access is prohibited at the timing T2 in which the specific value of the Q register is set. However, RAM access may be prohibited after executing other processing at the timing when the specific value of the Q register is set. Further, in the example of the startup process of FIG. 7, it has been described that a predetermined value is set in the Q register at the timing T6 when RAM access is permitted. However, at the timing when RAM access is permitted, a predetermined value may be set in the Q register after executing other processing. According to these configurations, the same effect as that of the present embodiment can be obtained while other processing can be performed.

(5) In the present embodiment, the upper address of the game RAM area is set to "F0", and the upper address of the internal function register is set to "F5". However, as long as the upper address of the game RAM area and the upper address of the internal function register are different from each other, the upper address of at least one area of both areas may be different from that of the present embodiment. For example, the upper address of the game RAM area may be "F1", and the upper address of the internal function register may be "FE". Even with such a configuration, the same effect as that of the present embodiment is obtained.

(6) In the start-up process of the present embodiment, in Sa1 and Sa2 in the start-up process, a process using a power failure detection signal (a signal indicating that the power supply has been stopped) is executed (see Sa1 and Sa2 in FIG. 4). Explained as doing. However, the start-up process is executed by using a signal indicating that the power supply has been started (hereinafter referred to as "power supply signal") instead of the power failure detection signal indicating that the power supply has been stopped. May be good.

In the case of the configuration using this power supply signal, in Sa1 of FIG. 4, data (power supply) indicating that the power supply signal has been input to the signal area (area in the internal function register) of the input port. Supply signal flag) is set. Then, in Sa2, it is determined whether or not the power supply signal flag is stored in the signal region, and if YES in the Sa2, the process proceeds to Sa3A. Even with such a configuration, the same effect as that of the present embodiment is obtained.

(7) In the present embodiment, it has been described that the upper address of each of the start address of the special work, the start address of the important work, and the start address of a part of the general work is "F0". However, the area where the upper address is "F0" may be another area. For example, the other area may be an area (specific storage area) for reading or writing data according to the progress of the game. Further, the other area may be an area (specific storage area) for saving (backing up) at least a part of the control data at the time of power failure when the power is cut off. In this case, at the time of recovery from power failure, the control data at the time of power failure may be restored based on the saved data.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown not by the above description but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1 slot machine, 6 MAXBET switch, 7 start switch, 41 main control unit, 91 sub control unit.

Claims (1)

It is a game machine that can play games
Identifying the address of the storage area by using the data stored in a predetermined storage area, an instruction execution unit is executable on the basis of the program specific instruction to read data from the storage area of the specific address,
Execution of processing to restore the control state based on the data stored in the specific storage area when the power supply to the game machine is detected, when the stop of the power supply is detected. and means, the,
Previously stored Symbol predetermined value data used to stop the power supply to identify the address of or is detected in front Symbol particular storage area to the gaming machine in the predetermined storage area,
Specific value data used to identify the address of a region different from the previous SL particular storage area when the stop of power supply to the gaming machine has been detected is stored in the predetermined storage area,
The program includes a first program that executes a process related to the progress of the game and a second program that executes a process not related to the progress of the game.
The first program is stored in the first program storage area.
The second program is stored in the second program storage area.
The address of the first program storage area includes the first information and the second information.
The instruction executing means can execute a special instruction for reading the first program from the first program storage area.
By executing the special instruction, the address of the first program storage area is specified from the first information and the second information specified by the special instruction, and the first program is obtained from the specified address. Can be read and
A gaming machine in which the special instruction can be executed based on the first program, but the special instruction is not executed based on the second program .

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