JP6797041B2 - Low noise amplifier - Google Patents

Description

The present invention relates to a low noise amplifier used for amplifying a high frequency (Radio Frequency: RF) signal.

An example of a low noise amplifier used for amplifying an RF signal is shown in Patent Document 1 below. In the low noise amplifier shown in Patent Document 1, a PIN diode (P-Intrinsic-N Diode) having one end grounded and a length of 1/4 of the input RF signal wavelength are provided at the other end of the PIN diode. Two sets of series connection circuits consisting of connected lines are provided, and each of the two sets of series connection circuits is connected to one end and the other end of the main line forming an input matching circuit, and the one end and the other end are connected. A configuration is disclosed in which the interval is set to a length of 1/4 of the input RF signal wavelength.

Japanese Unexamined Patent Publication No. 8-340226

As described above, the conventional low noise amplifier represented by Patent Document 1 has two sets of short stubs loaded with switches for controlling the passage or interruption of input power, and these two sets of short stubs. It was necessary to separate the connection points on the main line of the above by a length of 1/4 of the input RF signal wavelength. For this reason, the conventional low noise amplifier has a problem that the circuit becomes large and the cost increases.

The present invention has been made in view of the above, and a function for controlling the passage or interruption of input power is configured without using a short stub, and the size of the circuit and the increase in cost are suppressed. The purpose is to obtain a low noise amplifier.

In order to solve the above-mentioned problems and achieve the object, the low noise amplifier according to the present invention includes an input matching circuit including a series capacitor that cuts off direct current, an amplification element connected to the input matching circuit, and an amplification element. It includes an output matching circuit to be connected. The input matching circuit of the low noise amplifier includes a switching element in which one terminal side is electrically connected to the gate of the amplification element and the other terminal side is grounded.

According to the present invention, a function for controlling the passage or interruption of input power can be configured without loading a 1/4 wavelength line and short stubs at both ends thereof, thereby suppressing an increase in circuit size and cost. It has the effect of being able to do it.

A circuit diagram showing a configuration example of a low noise amplifier according to this embodiment. Equivalent circuit diagram of the circuit of FIG. 1 when the FET 3 is turned off. Equivalent circuit diagram of the circuit of FIG. 1 when the FET 3 is turned on.

The low noise amplifier according to the embodiment of the present invention will be described in detail below with reference to the drawings. The present invention is not limited to the following embodiments. Further, the connection between the elements in the following description is an electrical connection, and other elements may be included between the connected elements.

Embodiment.
FIG. 1 is a circuit diagram showing a configuration example of the low noise amplifier 100 according to the present embodiment. As shown in FIG. 1, the low noise amplifier 100 according to the present embodiment has an FET 11 which is an amplification element. Although FIG. 1 illustrates a case where the FET 11 is a field effect transistor (FET), an amplification element other than the FET may be used. Hereinafter, assuming that the FET 11 is an FET, the three terminals of the FET 11 are referred to as a gate, a drain, and a source, respectively. The gate may be referred to as a control terminal, the drain may be referred to as a first terminal, and the source may be referred to as a second terminal.

The low noise amplifier 100 according to the present embodiment is a gate bias circuit composed of a FET 3, a resistor 4 and a parallel resistor 5 connected in parallel, a series capacitor 6 and a series inductor 7, and an inductor 8, a capacitor 9 and a resistor 10. A parallel circuit that also serves as the above, and an input matching circuit 30 composed of the above are provided. In the input matching circuit 30 configured in this way, one end side is connected to the input terminal 1 and the other end side is connected to the gate of the FET 11. Further, one end of the resistor 4 is connected to the gate of the FET 3, and the other end of the resistor 4 is connected to the gate bias terminal 21 to which the gate bias voltage to the FET 3 is applied. Further, one end of the resistor 10 is connected to the connection point between the inductor 8 and the capacitor 9, and the other end of the resistor 10 is connected to the gate bias terminal 20 to which the gate bias voltage to the FET 11 is applied.

Further, the low noise amplifier 100 according to the present embodiment includes a circuit 40 composed of an inductor 12, a resistor 13 and a capacitor 14 having one end connected to the source of the FET 11 and the other end grounded.

Further, the low noise amplifier 100 according to the present embodiment includes a parallel circuit that also serves as a drain bias circuit composed of a series inductor 15, an inductor 16 and a capacitor 17 connected between the drain of the FET 11 and the output terminal, and a series capacitor. The output matching circuit 50 composed of 18 and 18 is provided. In the output matching circuit 50 configured in this way, one end side is connected to the output terminal 2 and the other end side is connected to the drain of the FET 11. Further, the connection point between the inductor 16 and the capacitor 17 is drawn out and connected to the drain bias terminal 19 to which the drain bias voltage to the FET 11 is applied.

As described above, the low noise amplifier 100 according to the present embodiment includes a series capacitor 6 that cuts off direct current, one terminal side is electrically connected to the gate of the FET 11, and the other terminal side is grounded. The input matching circuit 30 including the FET 3, the FET 11 connected to the input matching circuit 30, and the output matching circuit 50 connected to the FET 11 are provided.

The FET 3 operates as a switching element. As will be described later, a switching element other than the FET may be used as long as it is a switching element that exhibits capacitance when it is turned off and low resistance when it is turned on.

Although FIG. 1 shows a one-stage circuit configuration, it may be configured in multiple stages by using a plurality of amplification elements. The series capacitor 18 may be omitted when it is configured in multiple stages or when the input circuit in the next stage has a capacitor for cutting off DC.

Next, the operation of the low noise amplifier 100 according to the present embodiment will be described with reference to the circuit diagrams of FIGS. 2 and 3. FIG. 2 is an equivalent circuit diagram of the circuit of FIG. 1 when the FET 3 is turned off. FIG. 3 is an equivalent circuit diagram of the circuit of FIG. 1 when the FET 3 is turned on.

By turning off the FET 3 by the gate bias terminal 21, the FET 3 operates as a parallel capacitance 22 as shown in FIG. 2, and becomes a parallel capacitance of the input matching circuit 30 and a signal passes therethrough, so that the FET 3 operates as a low noise amplifier.

On the other hand, when the FET 3 is turned on by the gate bias terminal 21, the FET 3 operates as a parallel resistor 23 and blocks the signal to the input matching circuit 30, so that the input matching circuit 30 is inconsistent when viewed from the FET 11. Therefore, it is possible to prevent the input signal from the input terminal 1 from being applied to the gate of the FET 11.

As described above, by switching the operating state of the FET 3, the operation and non-operation of the amplification function of the low noise amplifier 100 can be switched. As described above, by turning off the FET 3, the input power to the FET 11 can be passed. Further, by turning on the FET 3, the input power to the FET 11 can be cut off.

A conventional low-noise amplifier represented by Patent Document 1 has two sets of short stubs loaded with switches for controlling the passage or interruption of input power, and in the main line of these two sets of short stubs. It is necessary to separate the connection points by a length of 1/4 of the input RF signal wavelength, which increases the size of the circuit and the cost. On the other hand, in the low noise amplifier 100 according to the present embodiment, a function for controlling the passage or interruption of the input power to the FET 11 which is an amplification element is loaded on the 1/4 wavelength line and short stubs at both ends thereof. Since it can be configured without this, it is possible to obtain an effect that a low noise amplifier can be configured while suppressing an increase in circuit size and cost.

The low noise amplifier 100 according to this embodiment can be used for a microwave receiver. As a recent technological trend, low noise amplifiers are required to have high power withstand against input power as well as demand for miniaturization and cost reduction. When the low noise amplifier is made to have high power resistance, circuit components such as a high power resistance switch, a limiter, and a circulator are often provided in front of the low noise amplifier. Even in the amplification system of a low noise amplifier, the resistance to input power is improved by increasing the size of the FET in the first stage or making it a balanced configuration so that it can withstand the input power. In particular, in a low noise amplifier used in a radar device, it is necessary to attenuate the input power so that the FET in the first stage is not damaged by the wraparound of the output power of the transmission system. In response to such a request, in the low noise amplifier 100 according to the present embodiment, the input power from the input terminal 1 can be cut off by turning on the FET 3, so that the FET 11 which is the first stage FET is protected. Is possible.

Further, according to the low noise amplifier 100 according to the present embodiment, it is possible to suppress an increase in the size of the FET 11 which is an amplification element and a complicated circuit configuration of the amplification system including the FET 11, so that the noise is low. The size of the amplifier 100 can be reduced, the loss can be reduced, and the price can be reduced.

The configuration shown in the above-described embodiment shows an example of the content of the present invention, can be combined with another known technique, and is configured without departing from the gist of the present invention. It is also possible to omit or change a part of.

1 input terminal, 2 output terminals, 3,11 FET, 4,10,13 resistor, 5,23 parallel resistor, 6,18 series capacitor, 9,14,17 capacitor, 7,15 series inductor, 8,12,16 Inductors, 19 drain bias terminals, 20, 21 gate bias terminals, 22 parallel capacitances, 30 input matching circuits, 40 circuits, 50 output matching circuits, 100 low noise amplifiers.

Claims (1)

It includes an input matching circuit including a switching element whose one end is grounded, a series capacitor that cuts off direct current, an amplification element connected to the input matching circuit, and an output matching circuit connected to the amplification element. It is a low noise amplifier
In the series capacitor, one terminal side is electrically connected to the gate of the amplification element, and the other terminal side is connected to the other end of the switching element.
The other end of the switching element is connected to the input terminal of the low noise amplifier .
When the input power to the amplification element is passed, the switching element is controlled to the off state, and when the input power to the amplification element is cut off, the switching element is controlled to the on state.
The switching element operates as a parallel capacitance of the input matching circuit when controlled in the off state, and operates as a parallel resistor of the input matching circuit when controlled in the on state. ..

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