JP6798418B2 - Manufacturing method of semiconductor devices - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

After forming an integrated circuit including a semiconductor element on the surface of a semiconductor wafer, the semiconductor wafer may be thinned. Specifically, a support substrate is attached to the semiconductor wafer to reinforce the semiconductor wafer, and then the back surface of the semiconductor wafer is ground. Patent Document 1 discloses that a metal electrode film is formed on the back surface of a thinned wafer after backside grinding by a vapor deposition method. Patent Document 1 further protects the entire surface of a semiconductor wafer before grinding. It is disclosed that the cracks generated in the process after grinding are suppressed by attaching the tape.

Patent Document 2 discloses a technique for accurately peeling off the protective tape without significantly advancing chipping or cracking even if a defect is generated on the outer periphery of the semiconductor wafer. In Patent Documents 1 and 2, a semiconductor wafer to which a protective tape is attached is attached to a dicing tape, and then the protective tape is peeled off using this as a support base.

In Patent Document 3, a plurality of semiconductor elements are formed on the upper surface side of the substrate, grooves are formed from the upper surface side of the substrate at the boundary positions of the semiconductor elements, and at least both side surfaces in the grooves are covered with a thin film layer for protection. It is disclosed to do. Further, in Patent Document 3, the thin film layer is polyimide, a gap portion in which no thin film exists is formed in the central portion of the groove width, the lower surface side of the substrate is removed by polishing, and each semiconductor element is separated along the gap portion. It is disclosed to do.

Japanese Unexamined Patent Publication No. 2004-186522 JP-A-2010-141101 Japanese Unexamined Patent Publication No. 2006-156863

When electrodes are provided on both the upper surface and the lower surface of the semiconductor wafer, if the protective tape or dicing tape is attached to the semiconductor wafer, it is not possible to inspect the electrical characteristics of the semiconductor wafer. Further, it is desirable to minimize the decrease in yield by suppressing the progress of cracks or chips generated in the semiconductor wafer.

The present invention has been made to solve the above-mentioned problems, and manufactures a semiconductor device capable of performing necessary inspections and suppressing the progress of cracks or chips generated in a semiconductor wafer. The purpose is to provide a method.

The method for manufacturing a semiconductor device according to the present invention includes a grinding step of grinding the lower surface of a semiconductor wafer having a plurality of semiconductor elements formed on the upper surface side, an inspection step of inspecting the semiconductor element after the grinding step, and the above-mentioned. It is characterized by comprising a coating step of applying a resin composition to an end portion of a crack of the semiconductor wafer or an intersection portion of a plurality of cracks after the grinding step and before or after the inspection step.

The method for manufacturing another semiconductor device according to the present invention includes a grinding step of grinding the lower surface of a semiconductor wafer having a plurality of semiconductor elements formed on the upper surface side, and an inspection step of inspecting the semiconductor element after the grinding step. After the grinding step and before or after the inspection step, the semiconductor wafer is provided with a film sticking step of locally sticking a film material to an end portion of a crack or an intersection of a plurality of cracks. It is a feature.

Other features of the present invention will be clarified below.

According to the present invention, in the process of inspecting a semiconductor wafer after grinding the lower surface of the semiconductor wafer, the resin composition is applied or the film material is attached to cracks or chips of the semiconductor wafer. Therefore, the necessary inspection can be performed, and the progress of cracks or chips generated in the semiconductor wafer can be suppressed.

It is a flowchart which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1. It is a top view of the semiconductor wafer which has a crack. It is a top view of the semiconductor wafer coated with the resin composition. It is a top view of the semiconductor wafer which has a crack and a chip. It is a top view of the semiconductor wafer coated with the resin composition. It is a top view of the semiconductor wafer to which a film material is attached.

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

Embodiment 1.
FIG. 1 is a flowchart showing a method of manufacturing a semiconductor device according to the first embodiment. A method of manufacturing the semiconductor device according to the first embodiment will be described with reference to this flowchart.

Step S1 is a pre-process. In the previous process, a plurality of semiconductor elements are formed on the semiconductor wafer. Semiconductor devices include, for example, field effect transistors or heterobipolar transistors. An integrated circuit that constitutes a circuit may be formed as a semiconductor element. The material of the semiconductor wafer is a compound semiconductor such as GaAs. A plurality of semiconductor elements are formed on the semiconductor wafer. The semiconductor element is formed on the upper surface side of the semiconductor wafer. Further, a through hole called a via hole penetrating from the upper surface to the lower surface of the semiconductor wafer is formed, and a metal is formed in the through hole.

Then, the process proceeds to step S2. In step S2, the support substrate is attached to the upper surface of the semiconductor wafer. Alternatively, the upper surface of the semiconductor wafer is mounted on the support substrate. The support substrate and the semiconductor wafer are attached with, for example, an adhesive. The support substrate is, for example, a well-known glass substrate.

Then, the process proceeds to step S3. In step S3, the lower surface of the semiconductor wafer in which the semiconductor element is formed on the upper surface side is ground. It is preferable to use a well-known grinder for grinding. The entire bottom surface is ground to make the semiconductor wafer thinner. This process is called a grinding process.

Then, the process proceeds to step S4. In step S4, a lower surface electrode is formed on the lower surface of the semiconductor wafer. The bottom electrode comes into contact with the metal formed in the via hole described above. As a result, the lower surface of the semiconductor chip obtained by fragmenting the semiconductor wafer can be used as a ground electrode or a heat dissipation electrode.

Then, the process proceeds to step S5. In step S5, the support substrate attached to the semiconductor wafer is peeled off from the semiconductor wafer. Since the semiconductor wafer is thin, its mechanical strength is low and it is very fragile.

Then, the process proceeds to step S6. Step S6 is a step of applying the resin composition to a part of the semiconductor wafer. FIG. 2 is a plan view of the semiconductor wafer 10 separated from the support substrate through the grinding process. A linear crack 2 and a T-shaped crack 3 appear on the upper surface of the semiconductor wafer 10. There may be cracks of a different shape. The directions of the linear cracks 2 and the T-shaped cracks 3 in the semiconductor wafer 10 are not particularly limited, but FIG. 2 shows typical crack directions in a GaAs substrate having a crystal plane orientation of (100). There is. Further, when substrates having different crystal plane orientations are used, or when a large external force in the oblique direction acts on the semiconductor wafer, cracks may occur in a direction different from the cracks in FIG. Then, in step S6, the resin composition is applied to the end portion of the crack or the intersection portion of the plurality of cracks on the upper surface of the semiconductor wafer 10. It is preferable to apply the resin composition to the chipped semiconductor element in addition to the crack ends or intersections of the semiconductor wafer 10.

FIG. 3 is a plan view of the semiconductor wafer 10 coated with the resin composition. The resin composition 4 is applied to both ends of the linear crack 2, the end of the T-shaped crack 3, and the intersection of the two cracks of the T-shaped crack 3. The resin composition 4 is locally formed on the semiconductor wafer 10 according to the shape of the cracks, and is not formed on the entire semiconductor wafer 10. The resin composition 4 is applied to prevent the progress of cracks. The resin composition 4 is not particularly limited as long as it is a resin material, but is, for example, polyimide. By applying the resin composition 4, it is possible to prevent cracks from progressing on the upper surface side of the semiconductor element in which the circuit is formed. This process is called a coating process.

Then, the process proceeds to step S7. In step S7, the semiconductor element of the semiconductor wafer thinned by the grinding process is inspected. This process is called an inspection process. In the inspection step, the semiconductor wafer 10 is handled and the semiconductor wafer 10 is vacuum-adsorbed to the stage to inspect the electrical characteristics of the semiconductor element. The means for inspecting electrical characteristics is not particularly limited. For example, the electrical characteristics can be inspected by applying a probe needle to the upper surface of the semiconductor wafer 10 and passing an electric current through the probe needle.

It is preferable to avoid handling the thin semiconductor wafer 10 or vacuum-adsorbing it to the stage because it causes cracks or chips in the semiconductor wafer 10. However, in the present embodiment, the quality of the metal formed in the via hole can be determined only after the semiconductor wafer 10 is thinned in the grinding process. Therefore, the inspection process is carried out after the grinding process. Therefore, in the inspection process, the connection between the bottom electrode connected via the metal in the via hole and the circuit on the top surface of the wafer is confirmed. Of course, another inspection item may be added in the inspection process. Further, in the inspection step, it is preferable to perform an appearance inspection of the semiconductor wafer 10.

In various inspections performed in the inspection process, the semiconductor wafer 10 is handled and the semiconductor wafer 10 is vacuum-adsorbed to the stage, paying close attention so as not to damage the thinned semiconductor wafer 10. For example, tighten the standards for foreign matter management on the stage. However, it is unavoidable that cracks occur in the thinned semiconductor wafer 10 in the inspection process. In particular, compound semiconductors have open surfaces, and once cracks occur, cracks progress along the open surfaces through the process. Due to the progress of cracks, the semiconductor wafer may be finally divided. As a result, the semiconductor wafer is discarded, and the yield of non-defective semiconductor chips is greatly reduced.

Further, in the inspection process, not only cracks but also chipping of the semiconductor wafer may occur. This chipping also advances the semiconductor wafer as the process progresses. As described above, some cracks and chips occur in the inspection process. Even if only one of the electrical property inspection and the visual inspection is performed in the inspection process, some cracks and chips occur.

FIG. 4 is a plan view of the semiconductor wafer after the inspection process. The inspection process causes cracks 20 and chips 22 on the upper surface of the semiconductor wafer 10. Other types of cracks or chips may occur.

Then, the process proceeds to step S8. In step S8, the resin composition is applied to the cracks and chips introduced into the semiconductor wafer 10 in the inspection step. This step, like step S6, refers to a coating step. FIG. 5 is a plan view of the semiconductor wafer after the coating step of step S8. The resin composition 24 is applied to the end portion of the crack 20, and the resin composition 24 is applied to the chip 22. The chip 22 is a portion in contact with the region that is chipped due to the chip of the semiconductor wafer 10. If there is a T-shaped crack, the resin composition 24 is also applied to the end portion and the intersection portion. If there are cracks or chips of different shapes, the resin composition 24 is applied to them.

In the coating steps of steps S6 and S8, it is preferable to apply the resin compositions 4 and 24 by the potting method. The potting method is to drop a liquid resin. By adopting the potting method, the resin compositions 4 and 24 can be applied accurately and locally to the intended place.

Then, the process proceeds to step S9. Step S9 is a step of attaching the dicing tape to the lower surface of the semiconductor wafer 10 after the coating process. The dicing tape is attached to the entire lower surface of the semiconductor wafer 10. This process is called a pasting process.

Then, the process proceeds to step S10. In step S10, at least the resin compositions 4 and 24 on the dicing line of the semiconductor wafer 10 are removed. All of the resin compositions 4 and 24 may be removed. This step is called a removal step.

Then, the process proceeds to step S11. In step S11, the semiconductor wafer 10 is diced along the dicing line. Since the resin composition applied on the dicing line is removed in the removing step, it is possible to prevent the blade from hitting the resin composition and being damaged during dicing. By dicing, the semiconductor wafer 10 is fragmented into a plurality of semiconductor chips. That is, one semiconductor element becomes one semiconductor chip. A metal formed in a via hole is provided in one semiconductor chip. This process is called a dicing process. If there is no problem even if the resin composition is present in the dicing line in the dicing step, the removal step described above may be omitted.

Then, the process proceeds to step S12. In step S12, a process called pickup is performed to peel off the plurality of semiconductor chips attached to the dicing tape from the dicing tape. At the end of step S11, the shape of the semiconductor wafer is maintained by the dicing tape, so that the pickup device can be aligned with reference to the outer peripheral portion of the semiconductor wafer. Wafer map data describing defective chips and non-defective chips is created from the chip addresses coated with the resin compositions 4 and 24 before picking up, the above alignment is performed, and the quality of the semiconductor chip is determined based on the map data. It is desirable to do. It is desirable that the wafer map data be stored in a memory when, for example, the resin compositions 4 and 24 are applied, and used for determining the quality of the semiconductor chip as described above.

In the method for manufacturing a semiconductor device according to the first embodiment of the present invention, an inspection step is performed after the support substrate is peeled off from the semiconductor wafer 10. That is, the electrical characteristics or appearance of the semiconductor wafer 10 to which neither the protective tape nor the dicing tape is attached is inspected in the inspection process. Therefore, it is possible to perform necessary inspections such as determining the quality of the via hole.

There is a concern that cracks or chips existing in the semiconductor wafer 10 before the grinding process may develop in the inspection process, or cracks or chips introduced into the semiconductor wafer 10 in the inspection process may develop in the subsequent process. Therefore, in the first embodiment of the present invention, the resin composition 4 is applied to the cracks or chips in step S6 before the inspection step, and the resin is applied to the cracks or chips generated in the inspection step in step S8 after the inspection step. The composition 24 is applied. Therefore, the progress of cracks or chips generated in the semiconductor wafer 10 can be suppressed by the resin compositions 4 and 24.

In order to prevent the progress of cracks, it is sufficient to apply the resin composition to the ends of the cracks, and it is not necessary to apply the resin composition to the entire cracks. By locally applying the resin composition to the cracks and their surroundings, it is possible to carry out the inspection of the semiconductor chip, which is assumed to be a good chip without cracks, as usual.

The method for manufacturing a semiconductor device according to the first embodiment can be variously modified without losing its characteristics. For example, the material of the semiconductor wafer 10 is not limited to the compound semiconductor, and a well-known material such as Si can be used. In the first embodiment, an inspection step after the grinding step is required in order to form a metal in the via hole penetrating the semiconductor wafer and determine the quality of the electrical connection of the metal. However, since the invention according to the first embodiment performs an inspection step on a thinned semiconductor wafer while suppressing harmful effects, it is effective for configurations other than those adopting via holes.

Only one of the coating steps of step S6 and step S8 may be adopted. For example, if the cracks and chips newly introduced in the inspection step can be ignored, the coating step of step S8 can be omitted. On the other hand, if the cracks and chips before the inspection step can be ignored, the coating step of step S6 can be omitted. Therefore, the coating step can be carried out after the grinding step and before or after the inspection step.

In the coating steps S6 and S8, the resin composition was applied only to a part of the cracks, but the resin composition may be continuously applied to the entire cracks. However, even in this case, the resin composition is not applied to the semiconductor element which is considered to be a good product without cracks or chips. The modification described in the first embodiment can be applied to the method for manufacturing a semiconductor device according to the following embodiment. Since the method for manufacturing the semiconductor device according to the embodiment has much in common with the first embodiment, the differences from the first embodiment will be mainly described below.

Embodiment 2.
In the method for manufacturing a semiconductor device according to the second embodiment, a visual inspection and a pickup for peeling the semiconductor chip from the dicing tape are performed in a subsequent process. In the visual inspection, the semiconductor chip coated with the resin compositions 4 and 24 is detected. Specifically, the semiconductor chip coated with the resin compositions 4 and 24 is detected by determining the presence or absence of ink using an image binarization method or the like. In order to facilitate the detection of the semiconductor chip coated with the resin compositions 4 and 24, the resin compositions 4 and 24 are preferably black or dark. Then, the semiconductor chip coated with the resin compositions 4 and 24 is treated as a defective product. This makes it possible to mechanically sort out defective chips without modifying the map data that defines the chip addresses of defective chips on the wafer.

Embodiment 3.
In the method for manufacturing a semiconductor device according to the third embodiment, a film material is used instead of a resin composition in order to stop the progress of cracks or chips. Specifically, the film material is locally attached to the end of a crack in the semiconductor wafer or the intersection of a plurality of cracks after the grinding step and before and after the inspection step. It is preferable to attach the film material to the chip.

FIG. 6 is a plan view of the semiconductor wafer 10 to which the film material 30 is attached. In the coating process, the film material 30 is attached to both ends of the linear crack 2, the end of the T-shaped crack 3, and the intersection of the two cracks of the T-shaped crack 3. Further, the film material 32 is attached to the crack 20 and the chip 22 introduced into the semiconductor wafer 10 in the inspection process. The film materials 30 and 32 are cut out into a shape corresponding to the cracks or chips, and then attached to the cracked or chipped portion. That is, the film material is not attached to the entire upper surface of the semiconductor wafer 10, but is locally attached to the portion where cracks or chips are found. The step of sticking the film materials 30 and 32 is called a film sticking step. The film sticking step may be carried out only before or after the inspection step. Prior to the dicing step of dicing the semiconductor wafer 10, it is preferable to remove at least the film material on the dicing line of the semiconductor wafer 10.

The method for manufacturing a semiconductor device according to the third embodiment is the same as that of the first embodiment except that the resin composition of the first embodiment is replaced with a film material. The features of each embodiment described so far may be used in combination.

10 Semiconductor wafer, 2 Linear crack, 3 T-shaped crack, 4,24 Resin composition

Claims (13)

A grinding process for grinding the lower surface of a semiconductor wafer in which a plurality of semiconductor elements are formed on the upper surface side,
After the grinding step, an inspection step of inspecting the semiconductor element and
A semiconductor characterized by comprising a coating step of applying a resin composition to an end portion of a crack of the semiconductor wafer or an intersection portion of a plurality of cracks after the grinding step and before or after the inspection step. Manufacturing method of the device. A grinding process for grinding the lower surface of a semiconductor wafer in which a plurality of semiconductor elements are formed on the upper surface side,
After the grinding step, an inspection step of inspecting the semiconductor element and
It is characterized by comprising a film pasting step of locally sticking a film material to an end portion of a crack of the semiconductor wafer or an intersection of a plurality of cracks after the grinding step and before or after the inspection step. A method for manufacturing a semiconductor device. After the coating step, a sticking step of sticking a dicing tape on the lower surface of the semiconductor wafer, and
A removal step of removing at least the resin composition on the dicing line of the semiconductor wafer.
The method for manufacturing a semiconductor device according to claim 1, further comprising a dicing step of dicing the semiconductor wafer along the dicing line. After the film sticking step, a sticking step of sticking a dicing tape on the lower surface of the semiconductor wafer,
A removal step of removing at least the film material above the dicing line of the semiconductor wafer.
The method for manufacturing a semiconductor device according to claim 2, further comprising a dicing step of dicing the semiconductor wafer along the dicing line. The method according to any one of claims 1 to 4, wherein in the inspection step, the semiconductor wafer is handled and the semiconductor wafer is vacuum-adsorbed to the stage to inspect the electrical characteristics of the semiconductor element. The method for manufacturing a semiconductor device according to the description. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein in the inspection step, an appearance inspection of a semiconductor wafer is performed. The method for manufacturing a semiconductor device according to claim 1, wherein in the coating step, the resin composition is coated by a potting method. After the coating step, a sticking step of sticking a dicing tape on the lower surface of the semiconductor wafer, and
After the pasting step, a dicing step of dicing the semiconductor wafer along the dicing line and a dicing step.
The method for manufacturing a semiconductor device according to claim 1, further comprising, after the dicing step, a post-step of treating the semiconductor element coated with the resin composition as a defective product. After the film sticking step, a sticking step of sticking a dicing tape on the lower surface of the semiconductor wafer,
After the pasting step, a dicing step of dicing the semiconductor wafer along the dicing line and a dicing step.
The method for manufacturing a semiconductor device according to claim 2, further comprising a post-step of treating the semiconductor element to which the film material is attached as a defective product after the dicing step. The method for manufacturing a semiconductor device according to claim 1, wherein in the coating step, a resin composition is applied to the chipped semiconductor element in addition to the crack end portion or the intersection portion of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 2, wherein in the film sticking step, a film material is stuck to the chipped semiconductor element in addition to the crack end portion or the intersection portion of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 8, wherein the resin composition is black or dark. The semiconductor wafer is made of a compound semiconductor.
The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein in the inspection step, a metal formed in a via hole of the semiconductor wafer is inspected.

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