JP6799247B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

The characteristics of semiconductor devices such as large scale integrated circuits (LSIs) are affected by the threshold voltage of the transistors included in the semiconductor devices. The threshold voltage of the transistor containing the polysilicon gate containing a large amount of impurities can be adjusted by controlling the concentration of the dopant in the channel region.

However, polysilicon gates cannot sufficiently meet the recent demand for transistor miniaturization. For example, the finer the transistor, the more depleted the polysilicon gate and the higher the resistance. Therefore, in recent years, a metal gate may be used instead of the polysilicon gate.

However, in a fine transistor including a metal gate, variations in characteristics are likely to occur due to fluctuations in the concentration of the dopant in the channel region. By lowering the concentration of the dopant, it is possible to suppress the variation in the above characteristics. However, when the concentration of the dopant is low, the threshold voltage of the transistor depends mainly on the work function of the metal gate. Therefore, the threshold voltage cannot be adjusted flexibly. Further, when forming a plurality of transistors having different threshold voltages, it is necessary to make the material of the metal gate different between them. For example, the same material cannot be used for the metal gate of an n-channel transistor and the metal gate of a p-channel transistor. Further, the metal gate has concerns such as the formation of an interface state at the interface with the gate insulating film and the diffusion of metal atoms into the gate insulating film. Since these can affect the characteristics of the transistor, some materials cannot be used for metal gates even if a desired threshold voltage can be obtained.

Japanese Unexamined Patent Publication No. 2013-1592969 International Publication No. 2015/068651

An object of the present invention is to provide a semiconductor device capable of flexibly adjusting the threshold voltage of a transistor.

One aspect of the semiconductor device is to dope a channel region, a source region and a drain region sandwiching the channel region, a gate insulating film on the channel region, a graphene film on the gate insulating film, and the graphene film. It has a doping layer on the graphene film and a protective film covering the graphite layer, and an opening is formed in the doping layer, and the protective film is in contact with the graphene film through the opening. .. Here, the graphene film refers to a film composed of one or more unit layers of graphene.

According to the above-mentioned semiconductor device or the like, since an appropriate doping layer is included, the threshold voltage of the transistor can be flexibly adjusted.

It is a figure which shows the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the characteristic of graphene. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. Following FIG. 3A, it is sectional drawing which shows the manufacturing method of a semiconductor device in the order of a process. It is a top view which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is a figure which shows the relationship between the gate voltage and the drain current in the 1st Embodiment. It is a figure which shows the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the relationship between the gate voltage and the drain current in the 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. It is a schematic diagram which shows the method of preparing the doping layer including the self-assembled monolayer in the order of steps. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows the relationship between the gate voltage and the drain current in the 3rd Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 5th Embodiment.

Hereinafter, embodiments will be specifically described with reference to the accompanying drawings.

(First Embodiment)
First, the first embodiment will be described. The first embodiment relates to a semiconductor device including a field effect transistor. FIG. 1 is a diagram showing a semiconductor device according to the first embodiment. FIG. 1 (a) is a cross-sectional view, and FIG. 1 (b) is a plan view showing some elements in FIG. 1 (a). FIG. 1 (a) shows a cross section along the line I-I of FIG. 1 (b).

In the semiconductor device 100 according to the first embodiment, as shown in FIG. 1A, an element separation region 102 for partitioning an element region is formed on the first conductive type semiconductor substrate 101, and a second element region is formed in the element region. A conductive source region 103s and a drain region 103d are formed. The portion between the source region 103s and the drain region 103d of the semiconductor substrate 101 is the channel region 101a. For example, the conductive type of the semiconductor substrate 101 is p-type, and the conductive type of the source region 103s and the drain region 103d is n-type. The insulating film 104 is formed on the semiconductor substrate 101. The insulating film 104 is formed with an opening 104s on the source region 103s and an opening 104d on the drain region 103d. A graphene film 111 above the channel region 101a is formed on the insulating film 104. The graphene film 111 comprises one or more unit layers of graphene. The portion of the insulating film 104 sandwiched between the channel region 101a and the graphene film 111 is the gate insulating film 104a. The conductive type of the semiconductor substrate 101 may be n-type, and the conductive type of the source region 103s and the drain region 103d may be p-type.

A doping layer 112 that doping the graphene film 111 is formed on the graphene film 111. The doping layer 112 includes, for example, 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ), 3,6-difluoro-2,5,7,7. , 8,8-Hexacyanoquinodimethane (F2-HCNQ), Tetracyanoquinodimethane (TCNQ), 2,5-Difluoro-Tetracyanoquinodimethane (F2-TCNQ), Nitrogen Dioxide (NO ₂ ), Fluoride Includes pentacene, diazonium salts, benzylviologen or iron chloride or any combination thereof. As diazonium salts, 4- (N, N-dimethylamino) benzenediazonium Tetrafluoroborate and 4-Bromobenzenediazonium Tetrafluoroborate are available. Illustrated. The doping layer 112 may contain polyetherimide (PEI), ferrocene, cobaltene or tetrathiafulvalene (TTF) or any combination thereof.

As shown in FIGS. 1A and 1B, a metal film 105s in contact with the source region 103s through the opening 104s and a metal film 105d in contact with the drain region 103d through the opening 104d are formed on the insulating film 104. The upper surface of the graphene film 111 is exposed from the doping layer 112 above the device separation region 102. Then, 105 g of a metal film in contact with the graphene film 111 is formed on the graphene film 111 above the element separation region 102. The semiconductor device 100 includes a protective film 113 that covers the doping layer 112. The protective film 113 is, for example, an alumina film. At least a part of the metal film 105s, at least a part of the metal film 105d, and at least a part of the metal film 105g are exposed from the protective film 113. The metal film 105s, the metal film 105d, and the metal film 105g are used as a source contact electrode, a drain contact electrode, and a gate contact electrode, respectively.

Here, the characteristics of graphene will be described. While graphene exhibits metallic properties, the density of states of graphene is small near the Fermi level, as shown in FIG. Therefore, the value of the work function can be freely changed by doping graphene. The relationship between the density of states of graphene and the energy difference from the Dirac point is given by the following equation. Here, E is energy, v _F is Fermi velocity (1 × 10 ⁶ m / s), h is Planck's constant, and E _Dirac is the position of Dirac point.

For example, from this equation, it is calculated that when the Fermi level is exactly at the Dirac point, the work function changes by about 120 meV by doping graphene with 10 ¹² cm ^-2 electrons.

In the first embodiment, the doping layer 112 doping the graphene film 111 depending on the material and amount it contains. Therefore, the work function of the graphene film 111 can be freely changed, and the threshold voltage of the transistor can be flexibly adjusted. Further, since the graphene film 111 is in contact with the gate insulating film 104a, it is possible to avoid the formation of an interface state, which is a concern when a metal gate is used. Further, the graphene film 111 prevents the atoms contained in the doping layer 112 from diffusing into the gate insulating film 104a. Therefore, it is possible to avoid fluctuations in the characteristics of the gate insulating film 104a due to such diffusion.

Next, a method of manufacturing the semiconductor device 100 according to the first embodiment will be described. 3A to 3B are cross-sectional views showing the manufacturing method of the semiconductor device 100 according to the first embodiment in process order, and FIG. 4 shows the manufacturing method of the semiconductor device 100 according to the first embodiment in process order. It is a plan view.

First, as shown in FIG. 3A (a), p-type impurities are ion-implanted into the semiconductor substrate 101 to make the conductive type of the semiconductor substrate 101 p-type, an element separation region 102 is formed, and n-type impurities are formed in the element region. Is ion-implanted to form a source region 103s and a drain region 103d. Next, the insulating film 104 is formed on the surface of the semiconductor substrate 101. The insulating film 104 can be formed by, for example, thermal oxidation.

After that, as shown in FIG. 3A (b), the graphene film 111 is provided on the insulating film 104. The graphene film 111 can be provided, for example, by growing the graphene film on the growth substrate and transferring it onto the insulating film 104.

Subsequently, as shown in FIGS. 3A (c) and 4 (a), the graphene film 111 is patterned. The graphene film 111 can be patterned by, for example, a photolithography technique and an etching technique. Examples of the etching technique include reactive ion etching (RIE) using oxygen plasma.

Next, as shown in FIG. 3A (d), the insulating film 104 is patterned to form the opening 104s and the opening 104d. The insulating film 104 can be patterned by, for example, a photolithography technique and an etching technique.

After that, as shown in FIGS. 3B (e) and 4 (b), the metal film 105s in contact with the source region 103s through the opening 104s, the metal film 105d in contact with the drain region 103d through the opening 104d, and the element separation region 102 above. To form 105 g of a metal film in contact with the graphene film 111. In the formation of the metal film 105s, the metal film 105d and the metal film 105g, for example, a mask is formed to expose the region where they are to be formed, a metal film is formed by a vacuum vapor deposition method, and the mask is formed together with the metal film on the mask. Remove. That is, the metal film 105s, the metal film 105d, and the metal film 105g can be formed by the lift-off method. In the formation of the metal film, for example, a Ti film having a thickness is formed, and an Au film having a thickness of 200 nm is formed on the Ti film.

Subsequently, as shown in FIGS. 3B (f) and 4 (c), the doping layer 112 is formed on the graphene film 111. In the formation of the doping layer 112, for example, F4-TCNQ is vacuum-deposited. The doping layer 112 may be formed by spin-coating an F4-TCNQ solution in which F4-TCNQ is dissolved in a solvent such as toluene. The doping layer 112 may be formed by dropping the F4-TCNQ solution. The thickness of the doping layer 112 is adjusted according to the threshold voltage of the transistor.

Next, as shown in FIG. 3B (g), a protective film 113 covering the doping layer 112 is formed, and at least a part of the metal film 105s, at least a part of the metal film 105d, and at least a part of the metal film 105g are formed on the protective film 113. An opening is formed to expose a part. The protective film can be formed, for example, by an atomic layer deposition (ALD) method.

In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

Here, the experiment conducted by the inventor of the present application will be described. In this experiment, three types of semiconductor devices 100 having different thicknesses of the doping layer 112 were manufactured. In the formation of the doping layer 112, an F4-TCNQ solution having a concentration of 0.05 mM was prepared using toluene as a solvent, and the F4-TCNQ solution was added dropwise to an area having an area of about 1 cm ² to dry the F4-TCNQ solution. I let you. At this time, the thickness of the doping layer 112 was adjusted by the amount of the F4-TCNQ solution added dropwise (10 μl, 40 μl, 70 μl). For reference, a reference example semiconductor device that does not form the doping layer 112 was also manufactured. Then, the relationship between the gate voltage and the drain current of these semiconductor devices was obtained. The result is shown in FIG. As shown in FIG. 5, the threshold voltage of the semiconductor device 100 including the doping layer 112 changed by about 300 meV from the threshold voltage of the semiconductor device of the reference example. Further, the threshold voltage changed according to the amount of the F4-TCNQ solution dropped, that is, according to the thickness of the doping layer 112. In this experiment, F4-TCNQ was sufficiently deposited even with a dropping amount of 10 μl, so that the change according to the dropping amount of the threshold voltage was relatively small. However, transistors having various threshold values can be realized by changing the dropping amount in a smaller direction.

If the doping layer 112 contains F4-TCNQ, F2-HCNQ, TCNQ, F2-TCNQ, NO ₂ , pentacene fluoride, diazonium salt, benzyl viologen or iron chloride or any combination thereof, the threshold voltage of the semiconductor device 100. Shifts to the positive side from the threshold voltage of the reference example that does not include the doping layer 112. On the other hand, when the doping layer 112 contains PEI, ferrocene, cobaltene or TTF or any combination thereof, the threshold voltage of the semiconductor device 100 shifts to the negative side from the threshold voltage of the reference example which does not include the doping layer 112. ..

(Second Embodiment)
Next, the second embodiment will be described. The second embodiment relates to a semiconductor device including a field effect transistor. FIG. 6 is a diagram showing a semiconductor device according to the second embodiment. 6 (a) is a cross-sectional view, and FIG. 6 (b) is a schematic view showing a part of the elements in FIG. 6 (a).

As shown in FIG. 6A, the semiconductor device 200 according to the second embodiment has a base 220 and a self-assembled monolayer instead of the doping layer 112 in the first embodiment. : SAM) 230 includes a doping layer 212. As shown in FIG. 6B, the self-assembled monolayer 230 contains a skeleton portion 231 and a functional group 232, and the doping layer 212 is arranged so that the functional group 232 is in contact with the graphene film 111. ing. The functional group 232 is, for example, ₂ NH, ₂ NH (CH ₃ ), ₂ N (CH ₃ ), ₃ CF or COOH groups. The base 220 is made of, for example, alumina. The doping layer 212 is covered with the protective film 113. Other configurations are the same as in the first embodiment.

In the second embodiment, since the functional group 232 is in contact with the graphene film 111, an electric charge is generated in the graphene film 111. That is, the graphene film 111 is doped by the doping layer 212. Functional group 232 NH ₂ groups, NH (CH ₃₎ is a group or a N (CH _{3) 2} group, electrons are generated in the graphene film 111, when the functional group 232 is a CF ₃ group or a COOH group, Holes are generated in the graphene film 111. Therefore, as in the first embodiment, the work function of the graphene film 111 can be freely changed, and the threshold voltage of the transistor can be flexibly adjusted. Further, it is possible to avoid the formation of the interface state and the diffusion of foreign matter into the gate insulating film 104a.

FIG. 7 is a diagram showing the relationship between the gate voltage and the drain current in the second embodiment. When the functional group 232 is _two N (CH ₃ ) groups, electrons are generated in the graphene film 111, so that the threshold voltage shifts to the negative side as compared with the reference example not including the doping layer 212.

Next, a method of manufacturing the semiconductor device 200 according to the second embodiment will be described. FIG. 8 is a cross-sectional view showing the manufacturing method of the semiconductor device 200 according to the second embodiment in the order of processes.

First, as shown in FIG. 8A, the treatment up to the formation of the metal film 105s, the metal film 105d, and the metal film 105g is performed in the same manner as in the first embodiment. In addition, the doping layer 212 is prepared. FIG. 9 is a schematic view showing a method of preparing the doping layer 212 in the order of steps.

In the preparation of the doping layer 212, first, as shown in FIG. 9A, an alumina base 220 is formed on the support substrate 240. Examples of the support substrate 240 include a nickel foil, a copper foil, a nickel film, and a copper film. A silicon substrate having a silicon oxide film formed on its surface may be prepared, and an aluminum film having a thickness of about 200 nm formed on the silicon oxide film may be used as the support substrate 240. The alumina base 220 can be formed, for example, by the ALD method using trimethylaluminum (TMA) as a precursor and water. The thickness of the base 220 is, for example, about 20 nm.

After the formation of the base 220, a self-assembled monolayer 230 is formed on the base 220 as shown in FIG. 9B. In the formation of the self-assembled monolayer 230, an open container containing the precursor of the self-assembled monolayer 230 and a laminate of the support substrate 240 and the base 220 are placed in a closed container in a glove box under atmospheric pressure. Encapsulate. After encapsulation, the closed container is placed in an electric furnace to heat it. For example, the heating time is several hours, and the heating temperature is about 100 ° C. By this heating, the self-assembled monolayer 230 is formed. After heating, the closed container is opened and the laminate on which the self-assembled monolayer 230 is formed is washed. In this cleaning, cleaning with ethanol, cleaning with toluene, cleaning with potassium hydroxide, and cleaning with nitric acid are performed for about 10 minutes each, and then cleaning with pure water is performed. After cleaning, nitrogen (N ₂ ) blow treatment is performed. In this way, the doping layer 212 can be prepared.

After the formation of the metal film 105s, the metal film 105d and the metal film 105g and the preparation of the doping layer 212 are completed, as shown in FIG. 8B, the functional group 232 is brought into contact with the graphene film 111 so that the support substrate 240 and the support substrate 240 and A laminate of the doping layer 212 is provided on the graphene film 111.

Then, as shown in FIG. 8C, the support substrate 240 is removed. When nickel foil is used as the support substrate 240, the support substrate 240 can be removed with hydrochloric acid.

Then, in the same manner as in the first embodiment, the treatment after the formation of the protective film 113 is performed. In this way, the semiconductor device 200 according to the second embodiment can be manufactured.

Examples of the precursor of the self-assembled monolayer 230 include N-dimethyl-3-aminopropylmethoxysilane, 3-aminopropyltrimethoxy (ethoxy) silane, N-methyl-3-aminopropylmethoxysilane, and fluoride. Alkylsilane or alkylsilane carboxylate is used. As alkylsilane fluorides, trimethoxy (1H, 1H, 2H, 2H-heptadecafluorodecyl) silane (heptadecafluoro-1,1,2,2-tetrahydro-decyl-1-trimethoxysilane) and triethoxytridecafluorooctylsilane are available. Illustrated. When N-dimethyl-3-aminopropylmethoxysilane is used, the functional group 232 becomes _two N (CH ₃ ) groups, and when 3-aminopropyltrimethoxy (ethoxy) silane is used, the functional group 232 is NH. _{When there are two} groups and N-methyl-3-aminopropylmethoxysilane is used, the functional group 232 becomes an NH (CH ₃ ) group. When an alkylsilane fluoride is used, the functional group 232 becomes a CF ₃ group, and when an alkylsilane carboxylate is used, the functional group 232 becomes a COOH group. The method of forming the self-assembled monolayer is described in detail in, for example, "H. Sugimura et al., Surf. Interf. Anal. 34, 550 (2002)".

(Third Embodiment)
Next, a third embodiment will be described. A third embodiment relates to a semiconductor device including a field effect transistor. FIG. 10 is a cross-sectional view showing the semiconductor device according to the third embodiment.

As shown in FIG. 10, the semiconductor device 300 according to the third embodiment includes a doping layer 312 instead of the doping layer 112 in the first embodiment. The doping layer 312 includes, for example, platinum, gold, silver, copper, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zinc, aluminum, ittrium, zirconium, niobium, molybdenum, ruthenium, rhodium, palladium, hafnium. , Tantalu, tungsten, osnium, iridium and other metals. The doping layer 312 may contain one or more films of the metal alone, may contain one or more films of the alloy, or may contain both. Other configurations are the same as in the first embodiment.

In the third embodiment, since the graphene film 111 is in contact with the doping layer 312 containing a metal, charge transfer occurs according to the work function of the metal. That is, the graphene film 111 is doped by the doping layer 312. Therefore, as in the first embodiment, the work function of the graphene film 111 can be freely changed, and the threshold voltage of the transistor can be flexibly adjusted. Further, since the graphene film 111 is interposed between the gate insulating film 104a and the doping layer 312, the state of the interface state hardly changes, and diffusion of metal atoms from the doping layer 312 to the gate insulating film 104a is avoided. You can also do it.

FIG. 11 is a diagram showing the relationship between the gate voltage and the drain current in the third embodiment. When the doping layer 312 is a platinum film, holes are generated in the graphene film 111, so that the threshold voltage shifts to the positive side as compared with the reference example not including the doping layer 312.

In the third embodiment, 105 g of the metal film may be omitted and a part of the doping layer 312 may be used as the gate contact electrode. A bulk film may be used for 105 g of the metal film, or an aggregate of metal nanoparticles may be used.

(Fourth Embodiment)
Next, a fourth embodiment will be described. A fourth embodiment relates to a semiconductor device including a field effect transistor. FIG. 12 is a cross-sectional view showing the semiconductor device according to the fourth embodiment.

As shown in FIG. 12, the semiconductor device 400 according to the fourth embodiment includes a doping layer 412 having an opening 412a formed in place of the doping layer 112 in the first embodiment. A part of the protective film 113 is in contact with the graphene film 111 through the opening 412a. For the doping layer 412, for example, the same material as the doping layer 112, 212 or 312 is used. Other configurations are the same as in the first embodiment.

The fourth embodiment also has the same effect as the first, second, or third embodiment, depending on the material of the doping layer 412. In the fourth embodiment, since the opening 412a is formed in the doping layer 412, a threshold voltage different from the case where the opening 412a is not formed can be obtained. That is, even if the materials of the doping layer 412 are common, the threshold voltage can be adjusted by changing the surface density of the doping layer 412.

The opening 412a can be formed, for example, by etching. When the doping layer 412 contains a self-assembled monolayer such as the doping layer 212, the opening 412a can also be formed by controlling the growth site of the self-assembled monolayer. When metal nanoparticles are used for the doping layer 412, if the number density of the metal nanoparticles is low, the gap between the metal nanoparticles can correspond to the opening 412a.

(Fifth Embodiment)
Next, a fifth embodiment will be described. A fifth embodiment relates to a semiconductor device including a field effect transistor. FIG. 13 is a cross-sectional view showing the semiconductor device according to the fifth embodiment.

As shown in FIG. 13, the semiconductor device 500 according to the fifth embodiment includes a doping layer 512 instead of the doping layer 112 in the first embodiment, and the graphene film 111 is placed on the doping layer 512. And a set of doping layers 512 are provided. That is, the semiconductor device 500 includes two sets of the graphene film 111 and the doping layer 512. For the doping layer 512, for example, the same material as the doping layer 112, 212 or 312 is used. Other configurations are the same as in the first embodiment.

The fifth embodiment also has the same effect as the first, second, or third embodiment, depending on the material of the doping layer 512. In the fifth embodiment, since the doping layer 512 near the channel of the two doping layers 512 is sandwiched between the graphene films 111, even if the dopant is unstable, it is easy to suppress the transformation and detachment of the dopant. .. Further, since the two graphene films 111 are included, the gate resistance can be reduced as compared with the case where the number of graphene films 111 is one. Further, since two sets of the graphene film 111 and the doping layer 512 are included, a threshold voltage different from the case where only one set is included may be obtained. The number of pairs of the graphene film 111 and the doping layer 512 is not limited, and may be 3 or more. Even if the materials of the doping layer 512 are common, the threshold voltage may be adjusted by changing the number of pairs of the graphene film 111 and the doping layer 512.

The material of the channel region, the source region and the drain region does not have to be a bulk semiconductor. For example, two-dimensional semiconductor materials may be used for the channel region, source region and drain region. A channel region, a source region, and a drain region may be included in a thin film transistor (TFT).

In any of the embodiments, the number of unit layers contained in the graphene film is not limited.

Hereinafter, various aspects of the present invention will be collectively described as appendices.

(Appendix 1)
A channel region, a source region and a drain region sandwiching the channel region, and
With the gate insulating film on the channel region,
The graphene film on the gate insulating film and
A doping layer on the graphene film that doping the graphene film,
A semiconductor device characterized by having.

(Appendix 2)
The semiconductor device according to Appendix 1, wherein the semiconductor device has a protective film that covers the doping layer.

(Appendix 3)
The doping layer is 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane, 3,6-difluoro-2,5,7,7,8,8-hexacyanoquinodimethane. Dimethane, tetracyanoquinodimethane, 2,5-difluoro-tetracyanoquinodimethane, nitrogen dioxide, pentacene fluoride, diazonium salts, benzylviologen or iron chloride or any combination thereof, or polyetherimide, ferrocene, The semiconductor device according to Appendix 1 or 2, which comprises cobaltene, tetrathiafulvalene, or any combination thereof.

(Appendix 4)
The semiconductor device according to Appendix 1 or 2, wherein the doping layer includes a self-assembled monolayer having a functional group in contact with the graphene film.

(Appendix 5)
The functional group, NH ₂ group, NH (CH ₃₎ group, N (CH _{3) 2} group, a semiconductor device according to Appendix 4, which is a CF ₃ group or a COOH group.

(Appendix 6)
The semiconductor device according to Appendix 1 or 2, wherein the doping layer contains a metal.

(Appendix 7)
The doping layer includes platinum, gold, silver, copper, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zinc, aluminum, ittrium, zirconium, niobium, molybdenum, ruthenium, rhodium, palladium, hafnium, and tantalum. , Tungsten, osnium or iridium, or any combination thereof, according to Appendix 6.

(Appendix 8)
An opening is formed in the doping layer,
The semiconductor device according to any one of Supplementary note 2 to 7, wherein the protective film is in contact with the graphene film through the opening.

(Appendix 9)
The semiconductor device according to any one of Appendix 1 to 8, wherein the graphene film is composed of one unit layer of graphene.

(Appendix 10)
With the second graphene film on the doping layer,
With the second doping layer on the second graphene membrane,
The semiconductor device according to any one of Supplementary Provisions 1 to 9, wherein the semiconductor device has.

100, 200, 300, 400, 500: Semiconductor device 101a: Channel area 103s: Source area 103d: Drain area 104a: Gate insulating film 111: Graphene film 112, 212, 312, 412, 512: Graphene film

Claims (5)

A channel region, a source region and a drain region sandwiching the channel region, and
With the gate insulating film on the channel region,
The graphene film on the gate insulating film and
A doping layer on the graphene film that doping the graphene film,
A protective film covering the doping layer and
Have,
An opening is formed in the doping layer,
A semiconductor device characterized in that the protective film is in contact with the graphene film through the opening. The doping layer is 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane, 3,6-difluoro-2,5,7,7,8,8-hexacyanoquinodimethane. Dimethane, tetracyanoquinodimethane, 2,5-difluoro-tetracyanoquinodimethane, nitrogen dioxide, pentacene fluoride, diazonium salt, benzylviologen or iron chloride or any combination thereof, or polyetherimide, ferrocene, The semiconductor device according to claim 1, wherein the semiconductor apparatus comprises cobaltene, tetrathiafulvalene, or any combination thereof. The semiconductor device according to claim 1, wherein the doping layer includes a self-assembled monolayer having a functional group in contact with the graphene film. The semiconductor device according to claim 1, wherein the doping layer contains a metal. With other graphene membranes on the doping layer,
With other doping layers on the other graphene membranes that dope the other graphene membranes,
The semiconductor device according to any one of claims 1 to 4 , further comprising.

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