JP6800726B2 - Image forming equipment, methods and programs - Google Patents

Description

The present invention relates to an image forming apparatus, method and program for performing an image forming process.

In an image forming apparatus such as a multifunction device, image data is converted into image data having an appropriate number of gradations before printing is performed. At that time, a screen processing technique such as a dither method is generally used. In the dither method, a LUT (Look Up Table) such as a dither matrix is used. In the dither method, the pixel value of the input image is compared with the threshold value of the dither matrix, and a halftone-processed binarized image is generated. By using the dither method, the number of gradations of the image can be reduced, and the capacity of the storage area can be reduced.

In recent years, with the development of screen processing technology, a new method for creating a dither matrix threshold is also known. For example, a technique such as a Blue Noise dither matrix (hereinafter referred to as BN mask) is known.

The BN mask is the same as the conventional dither matrix usage, but the threshold pattern is aperiodic, isotropic, and has a power spectrum (blue noise characteristic) composed of noise components with few low frequency components. It is characterized by that. Therefore, it is considered that moire of the image after screen processing is difficult to see, and the image quality is improved as compared with the conventional dither method. However, in order to apply the BN mask, it is necessary to use a matrix having a large size, and generally, a BN mask having a size of 256 × 256 or more is required. When a function for performing screen processing is implemented by hardware such as ASIC using the dither method, it is necessary to store the dither matrix in a storage area such as SRAM. Therefore, a huge storage area for storing the BN mask is required.

Patent Document 1 describes a method of rotating a BN mask and combining and using different rotation patterns of the same BN mask.

Japanese Unexamined Patent Publication No. 8-163361

By using the method described in Patent Document 1, as shown briefly in FIG. 15, a configuration in which a 128 × 128 size BN mask and a 128 × 128 size rotated BN mask are used in combination is configured. Conceivable. It is considered that such a configuration makes it possible to reduce the size of the BN mask to be stored in the storage area from 256 × 256 to 128 × 128.

When the screen processing is performed at high speed, the comparison between the pixel value of the input image and the threshold value of the dither matrix is often performed in block units of M × N pixels (for example, 4 × 2 pixels). In such a configuration, M × N threshold values are acquired at the same time in one clock cycle (one rising edge of the clock signal), and comparison with M × N pixel values is performed. Generally, only one threshold value can be read from one SRAM in one clock cycle, so in the case of a block unit of 4 × 2 pixels, eight same SRAMs are required.

Even if the size of the BN mask to be stored in the SRAM can be reduced to 128 × 128 by using the method described in Patent Document 1, in the case of the above screen processing, each of the eight SRAMs can be used. A 128 x 128 size BN mask is stored. As a result, the total size of the SRAM becomes 128 × 128 × 8, and the usage efficiency of the SRAM is rather lowered, which also contributes to an increase in the production cost of the ASIC.

An object of the present invention is to solve such a conventional problem. In view of the above points, it is an object of the present invention to provide an image forming apparatus, method and program for improving the efficiency of using the storage area of the matrix used in the halftone processing.

In order to solve the above problems, the image forming apparatus according to the present invention is an image forming apparatus that executes halftone processing on image data, and stores a threshold value set in a matrix used for the halftone processing in a storage unit. Pixel values are acquired in block units of M × N pixels smaller than the size of the matrix from the storage means for storing and the image data, and the matrix mapped to the image data corresponds to the block of M × N pixels. The storage means includes an acquisition means for acquiring the threshold value to be performed from the storage unit, and an execution means for executing the halftone process based on the pixel value acquired by the acquisition means and the threshold value. A plurality of threshold values set in the matrix are distributed and stored in a plurality of storage elements constituting the storage unit, and M × N threshold values corresponding to the block of M × N pixels are M by the acquisition means. The plurality of threshold values are distributed and stored in the plurality of storage elements so as to be acquired from × N storage elements, and the storage means is among the plurality of threshold values set in the matrix. It is characterized in that a plurality of threshold values to be acquired by the acquisition means are stored in one storage element for each position of the block of M × N pixels .

According to the present invention, it is possible to improve the efficiency of using the storage area of the matrix used in the halftone processing.

It is a figure which shows the block structure of a multifunction device. It is a figure which shows the structure of the dither setting module and the dither processing module. It is a figure which shows the structure of the SRAM array. It is a flowchart which shows the process until the binarized data is output. It is a flowchart which shows the process of reading a threshold value. It is a figure for demonstrating the identification of SRAM. It is a figure which shows how the threshold value in a BN mask is stored in 16 SRAMs. It is a figure which shows the index value. It is a figure for demonstrating the operation of reading threshold data. It is a figure for demonstrating the operation of reading threshold data. It is a figure which shows the index value. It is a figure for demonstrating the operation of reading threshold data. It is the figure which simplified the BN mask. It is the figure which simplified the BN mask. It is a figure which shows the mode that the BN mask is combined and used.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the following embodiments do not limit the present invention according to the claims, and not all combinations of features described in the present embodiment are essential for the means for solving the present invention. .. The same components are given the same reference numbers, and the description thereof will be omitted.

[First Embodiment]
FIG. 1A is a diagram showing a block configuration of the image forming apparatus 100. The digital multifunction device 100 includes a controller unit 110, an operation unit 120, a scanner 130, and a printer 140. An operation unit 120 is connected to the controller unit 110, and a scanner 130 which is an image input device and a printer 140 which is an image output device are connected. The printer 140 records an image on a recording medium by an inkjet recording method, an electrophotographic method, or the like. In the present embodiment, the multifunction device will be described as the image forming apparatus 100, but if the halftone processing before the image forming processing on the recording medium is executed, the printing function is used instead of the multifunction device (MFP). It may be an SFP having.

The controller unit 110 is a controller board that controls the entire device in an integrated manner, and includes a CPU 112. The CPU 112 boots the OS by the boot program stored in the ROM 116. The controller unit 110 executes an application program stored in the HDD 115 on the OS to execute various processes. The RAM 113 is used as a work area of the CPU 112. The HDD 115 stores the above application program and various data. The operation of this embodiment is also realized, for example, by the CPU 112 reading a program stored in the ROM 116 or the HDD 115 onto the RAM 113 and executing the program.

For example, the HDD 115, the ROM 116, the RAM 113, the operation unit interface (I / F) 111, the device I / F 114, the network I / F 117, and the image processing unit 118 are connected to the CPU 112 via the system bus 119. The operation unit I / F 111 is an interface with the operation unit 120 having a display unit such as a touch panel. The operation unit I / F 111 sends information such as various setting data to be displayed on the operation unit 120 to the operation unit 120, or receives the information input by the user operation from the operation unit 120 and sends it to the CPU 112. For example, a scanner 130 and a printer 140 are connected to the device I / F 114, and data and control signals are input and output. The network I / F 117 is connected to the external network 150 and communicates with each device on the network 150 via the network 150. The image processing unit 118 may, for example, perform various processes on image data optically read by the scanner 130, image rotation, image compression, resolution conversion, color space conversion, and gradation for printing by the printer 140. Performs various processes on image data such as conversion.

When the image forming apparatus 100 receives the PDL data to be printed from an external PC or the like via the network 150, the image processing unit 118 generates multi-valued image data in which the rendering process is executed under the control of the CPU 112. Then, the image processing unit 118 executes screen processing and generates binary image data (halftone data) corresponding to each color material color of the printer 140 from the multi-valued image data. In the present embodiment, the image processing unit 118 includes a screen processing system using the dither method, and the screen processing is executed by the screen processing system. The printer 140 records an image on a recording medium based on the generated binary image data, and then prints out the image. In addition to the above, necessary processing is appropriately performed between the reception of PDL data from the outside and the print output. For example, processing such as image processing or conversion may be performed based on the attribute information added to the PDL data.

FIG. 1B is a diagram showing a configuration of a screen processing system of the image processing unit 118. The screen processing system 160 converts the input image data into binary image data in block units of M × N pixels by the dither method. At that time, the screen processing system 160 generates binarized data 165 by comparing the input data 164 with the threshold value using a blue noise mask (hereinafter, BN mask) having a size of 128 × 128. The input data 164 is a pixel value of the image data corresponding to a block of M × N pixels in the image data. In the present embodiment, the screen processing system 160 converts the binarized data 165 in block units of 4 × 2 pixels. FIG. 1B shows the pixel values (1, 3, 7, 12, 1, 5, 12, 32) of the 4 × 2 pixel block of the input data 164 and the threshold values of the BN mask (2, 3, 2, 2,). 4, 1, 5, 12, 21) are compared for each pixel, and the binarized data 165 is generated. Hereinafter, the block will be described as 4 × 2 pixels, but it may be configured with another number of pixels depending on the processing capacity of the processor, the configuration of the storage element, and the like.

The screen processing system 160 includes a dither setting module 161, an SRAM array 162, and a dither processing module 163. The dither setting module 161 writes a threshold value to the address of a specific SRAM among a plurality of storage elements configured in the SRAM array 162, or a plurality of SRAMs in the present embodiment. The dither processing module 163 compares the pixel value of the input data with the threshold value, generates binarized data 165, and outputs the data. Further, as shown in FIG. 1B, a clock signal is input to the dither processing module 163 and the SRAM array 162, and one threshold value is read out in one clock cycle for one SRAM. That is, it is possible to read each threshold value from a plurality of SRAMs in one clock cycle.

FIG. 2A is a diagram showing an example of the configuration of the dither setting module 161. The dither setting module 161 is composed of, for example, a semiconductor integrated circuit device, and includes a control unit 201, an information storage unit 202, and a threshold value setting transmission unit 203. The control unit 201 includes, for example, a CPU or a dedicated control module, and controls the information storage unit 202 and the threshold value setting transmission unit 203. The control unit 201 may operate under the control of the CPU 112 of FIG. The information storage unit 202 includes a storage unit such as a RAM or ROM (not shown) and stores the threshold value in the dither matrix. The threshold setting transmission unit 203 generates a request command for writing a threshold value to a specific address of a specific SRAM of the SRAM array 162, and transmits the request command to the SRAM array 162.

FIG. 2B is a diagram showing an example of the configuration of the dither processing module 163. The dither processing module 163 is composed of, for example, a semiconductor integrated circuit device, and includes an image input unit 211, an index acquisition unit 212, a threshold request transmission unit 213, a threshold data reception unit 214, an image processing unit 215, and an image output unit 216.

The image input unit 211 is a circuit that receives image data from a memory or another module, and receives 4 × 2 input data, that is, a pixel value in one clock cycle. Further, the image input unit 211 has a function of transmitting the received input data to the image processing unit 215 and a function of issuing an index acquisition command to the index acquisition unit 212 each time the input data is received.

The index acquisition unit 212 is a circuit that acquires an index value for acquiring a threshold value corresponding to input data according to the rotation pattern for the time being each time an index acquisition command is received from the image input unit 211. In this embodiment, 4 × 2 index values are acquired. The index value is information indicating the position of a pixel in the BN mask, and is used when searching for a corresponding threshold value from the BN mask. The acquired index value is transmitted to the threshold request transmission unit 213. The threshold request transmission unit 213 receives the index value acquired by the index acquisition unit 212, generates a threshold read request command, and transmits the index value together with the index value to the SRAM array 162.

The threshold data receiving unit 214 receives 4 × 2 threshold data in one clock cycle from the SRAM array 162 and transmits the 4 × 2 threshold data to the image processing unit 215. The image processing unit 215 receives the input data from the image input unit 211 and the threshold data from the threshold data receiving unit 214, compares the pixel value of the input data with the threshold of the threshold data, and binarizes the comparison result. This is a circuit that transmits the data to the image output unit 216. The image output unit 216 receives the binarized data from the image processing unit 215 and transmits it to the memory or another dither processing module. In the present embodiment, binarized data for 4 × 2 pixels is transmitted in one clock cycle.

FIG. 3 is a diagram showing an example of the configuration of the SRAM array 162. The SRAM array 162 is composed of, for example, a semiconductor integrated circuit device, and includes a request receiving unit 301, an SRAM selection unit 302, an address generation unit 303, a data storage unit 304, and an output control unit 305.

The request receiving unit 301 receives a read request command from the dither processing module 163, and transmits the read request command to the SRAM selection unit 302, the address generation unit 303, and the output control unit 305. The SRAM selection unit 302 extracts index information from the read request command received from the request reception unit 301, generates a selection signal for selecting an SRAM that stores a threshold value corresponding to the corresponding index information, and transmits the selection signal to the data storage unit 304. To do.

The address generation unit 303 extracts index information from the read request command received from the request reception unit 301, generates a position signal (address signal) in the SRAM that stores the threshold value corresponding to the corresponding index information, and generates a data storage unit. Send to 304. The data storage unit 304 is configured to include an array of Max (M, N) × Max (M, N), that is, a square of the maximum value, which has a relatively small capacity. For example, in this embodiment, since it is a block of 4 × 2 pixels, Max (4,2) × Max (4,2) = 4 × 4, that is, an array of 16 SRAMs is included. Further, the total size of the SRAM array included in the data storage unit 304 is the minimum size for storing the BN mask, and is 128 × 128 in the present embodiment. That is, the size of one SRAM is 128 × 128 ÷ 16 = 1024 addresses.

The data storage unit 304 receives the SRAM selection signal and the address signal from the SRAM selection unit 302 and the address generation unit 303, reads the threshold value from the predetermined address of the predetermined SRAM, and transmits the threshold value to the output control unit 305. The output control unit 305 receives the threshold value from the data storage unit 304, and extracts the index information from the read request command received from the request reception unit 301. Then, out of the outputs of the 16 SRAMs, the outputs of the specific 4 × 2 SRAMs are transmitted to the dither processing module 163.

FIG. 4 is a flowchart showing a process from setting the threshold value of the dither matrix to outputting the binarized data. In S401 to S405, the dither setting module 161 indicates a process of writing the threshold data to the SRAM array 162. The processing of S401 to S405 is realized, for example, by the CPU of the control unit 201 reading and executing the program stored in the ROM.

In S401, the control unit 201 determines whether or not the threshold value setting is completed based on the number of the threshold values already set and the size of the BN mask. When it is determined that the threshold value setting is not completed, the control unit 201 reads the predetermined threshold value data from the information storage unit 202 in S402. On the other hand, when it is determined that the threshold value setting is completed, the process proceeds to S406 described later.

In S403, the control unit 201 specifies the SRAM of the writing destination of the threshold value of interest, and in S404, specifies the position (address) in the SRAM of the writing destination of the threshold value. In S405, the control unit 201 issues a threshold value write request to the SRAM array 214 via the threshold value setting transmission unit 203. After that, the process from S401 is repeated.

FIG. 6A is a diagram for explaining the identification of the SRAM of S403. The BN mask 601 is a 128 × 128 size matrix. When writing the attention threshold value 602 to the SRAM array 162, the control unit 201 confirms the position of the attention threshold value (X_Cord, Y_Cord). Here, X_Cord is the distance between the attention threshold value 602 and the beginning of the line to which the attention threshold value 602 belongs, and in the present embodiment, it takes a value of 0 to 127. Further, Y_Cord is the distance between the attention threshold value 602 and the head of the column to which the attention threshold value 602 belongs, and in the present embodiment, it takes a value of 0 to 127. Then, based on the above-mentioned values of X_Cord and Y_Cord, the number of the SRAM to be written is specified according to the equation (1).

X_Cord% max (M, N) + Y_Cord% max (M, N) * max (M, N) ... (1)
Here, "%" represents a remainder. In the present embodiment, 5% 4 + 3% 4 * 4 = 1 + 12 = 13, and it is specified that the SRAM for writing the attention threshold value 602 is the SRAM 13 shown in FIG. 6A.

FIG. 6B is a diagram for explaining the identification of the address of S404. X_Cord and Y_Cord are as described above. MatrixWidth is the width of the BN mask, which is 128 in this embodiment. In the present embodiment, the address to be written is specified according to the equation (2) based on X_Cord, Y_Cord, and MatrixWidth.

X_Cord / max (M, N) + (Y_Cord / (max (M, N)) * (MatrixWids / max (M, N)) ... (2)
Here, "/" represents a quotient. In the present embodiment, 5/4 + (3/4) * (128/4) = 1 + 0 = 1, and it is specified that the address of the SRAM 13 for writing the attention threshold value 602 is 1.

In the present embodiment, the threshold values in the BN mask 601 are distributed and stored in 16 SRAMs by the methods of FIGS. 6 (a) and 6 (b). FIG. 7 shows that 16 SRAMs are represented by A to P for convenience of display, and the threshold value in the BN mask 701 is stored in the corresponding SRAM. For example, the four thresholds A indicated by the arrows are stored at addresses 0, 1, 32, 33 of SRAM-A.

FIG. 7 shows a case where the BN mask is 128 × 128. 13 and 14 are diagrams for easily explaining the concept of the present application.

FIG. 13A is a diagram showing a case where the BN mask is tentatively 8 × 8. The block unit is 4 × 2 pixels as described above. Here, as shown in FIG. 13A, each block is designated as blocks A to H. Then, the positions in each block are defined as 1, 2, 3, 4 from the upper left to the upper right, and 5, 6, 7, 8 from the lower left to the lower right. That is, the block A has eight thresholds A1, A2, A3, A4, A5, A6, A7, and A8. The same applies to the other blocks B to H. FIG. 13B is a diagram showing how the equations (1) and (2) are stored in SRAMs 0 to 15 when the equations (1) and (2) are applied to FIG. 13 (a). The arrangement of SRAMs 0 to 15 in FIG. 13B is the same as the arrangement shown in FIGS. 3 and 6A. That is, since it is a block of 4 × 2 pixels, a maximum value of 4 squared and 16 SRAMs are configured.

As shown in FIG. 13B, for block A, eight thresholds A1 to A8 are read from eight SRAMs 0-7. Further, for block B, eight threshold values B1 to B8 are read from eight SRAMs 0 to 7. Also, for block C, eight thresholds C1 to C8 are read from eight SRAMs 8 to 15. Also, for block D, eight thresholds D1 to D8 are read from eight SRAMs 8 to 15.

For block E, eight thresholds E1 to E8 are read from eight SRAMs 0-7. Further, for the block F, eight threshold values F1 to F8 are read from eight SRAMs 0 to 7. Further, for the block G, eight threshold values G1 to G8 are read from eight SRAMs 8 to 15. Also, for block H, eight thresholds H1 to H8 are read from eight SRAMs 8 to 15.

In this way, the threshold value is read from different SRAMs for each block. That is, for any block, the threshold value of that block can be read in one clock cycle. Further, as shown in FIG. 13B, the storage capacity required for each SRAM may be 4 addresses of addresses 0 to 3, and it is not necessary to secure 8 × 8 = 64 addresses of the BN mask.

FIG. 14A is a diagram showing a case where the BN mask is tentatively 16 × 16. The block unit is 4 × 2 pixels as described above. Here, as shown in FIG. 16A, each block is designated as blocks A to Zf. Then, the positions in each block are defined as 1, 2, 3, 4 from the upper left to the upper right, and 5, 6, 7, 8 from the lower left to the lower right. That is, the block A has eight thresholds A1, A2, A3, A4, A5, A6, A7, and A8. The same applies to the other blocks B to Zf. FIG. 14B is a diagram showing how the equations (1) and (2) are stored in SRAMs 0 to 15 when the equations (1) and (2) are applied to FIG. 14 (a). The arrangement of SRAMs 0 to 15 in FIG. 14B is the same as the arrangement shown in FIGS. 3 and 6A. That is, since it is a block of 4 × 2 pixels, a maximum value of 4 squared and 16 SRAMs are configured.

For simplification of the figure, SRAM 0 in FIG. 14B is described as "A1 to D1, I1 to L1, Q1 to T1, Y1 to Zb1". This represents A1, B1, C1, D1, I1, J1, K1, L1, Q1, R1, S1, T1, Y1, Z1, Za1, Zb1. The same applies to the other SRAMs 1 to 15.

As shown in FIG. 14B, for example, for block A, eight thresholds A1 to A8 are read from eight SRAMs 0-7. Further, for block B, eight threshold values B1 to B8 are read from eight SRAMs 0 to 7. Also, for block C, eight thresholds C1 to C8 are read from eight SRAMs 8 to 15. Also, for block D, eight thresholds D1 to D8 are read from eight SRAMs 8 to 15.

The same applies to the other blocks, and the threshold value is read from different SRAMs for each block. That is, for any block, the threshold value of that block can be read in one clock cycle. Further, as shown in FIG. 14B, the storage capacity required for each SRAM may be 16 addresses of addresses 0 to 15, and 16 × 16 = 256 addresses of the BN mask need not be secured. The effects of FIGS. 13 and 14 are the same in the case of FIG. 7, and the storage capacity required for each SRAM may be 1024 addresses of addresses 0 to 1023, and 128 × 128 = 16384 addresses of the BN mask 701 are secured. You don't have to.

See FIG. 4 again. S406 to S413 indicate a process in which the dither processing module 163 receives the input data, sends a read request command to the SRAM array 162, compares the read threshold value with the pixel value of the input data, and outputs the result. ..

In S406, the image input unit 211 determines whether or not the input data has been received. When it is determined that the input data has been received, in S407, the image input unit 211 transmits the received 4 × 2 pixel block to the image processing unit 215 and also transmits an index acquisition command to the index acquisition unit 212.

In S408, when the index calculation unit 212 receives the index acquisition command, it acquires 4 × 2 indexes of the threshold value corresponding to the input block. The index acquisition unit 212 transmits the acquisition result to the threshold request transmission unit 213. When the threshold request transmission unit 213 receives the index value which is the index acquisition result, the threshold request transmission unit 213 issues a read request command for threshold data to the SRAM array 162 together with the index value. S414 performed in the SRAM array 162 will be described later.

In S409, the threshold data receiving unit 214 receives the threshold data corresponding to the issued read request command, that is, 4 × 2 thresholds. The threshold data receiving unit 214 transmits the received threshold data to the image processing unit 215. In S410, the image processing unit 215 compares the pixel value of the input data transmitted from the image input unit 211 with the threshold value of the threshold data transmitted from the threshold data receiving unit 214. When it is determined that the pixel value is larger than the threshold value, the image processing unit 215 substitutes "1" for the output result and transmits it to the data output unit 216. On the other hand, when it is determined that the pixel value is not larger than the threshold value, the image processing unit 215 substitutes "0" for the output result and transmits it to the data output unit 216.

In S413, the data output unit 216 outputs the comparison result transmitted from the image processing unit 215, that is, the binarized data of 4 × 2 pixels, to the outside of the dither processing module 163. In the present embodiment, the input data is converted into the binarized data as described above.

FIG. 8 is a diagram showing the acquisition result of the index value of S407. In the present embodiment, it is assumed that the image data has a size of 512 × 512. In the present embodiment, when performing screen processing, the image processing unit 118 applies a 128 × 128 BN mask 802 and a BN mask 802 to the right 90 with respect to the image data 801 as shown in FIG. It is mapped so as to be combined with the BN mask 803 rotated by the degree. By such mapping of the BN mask, the pattern peculiar to the matrix is made inconspicuous, and the capacity of the BN mask stored in the SRAM is 128 × 128 where a BN mask of 256 × 256 size or more is generally required. Can be suppressed to the size of.

The index acquired in S407 indicates the position of the pixel in the BN mask. In the present embodiment, as shown in FIG. 8, the position information indicating the position of each pixel is defined as the index value 0 to 16383 in the BN mask. In S407, eight index values corresponding to a block of 4 × 2 pixels are acquired. Further, the value in the BN mask 803 corresponding to the index value 0 of the block assigned in the BN mask 802 is the index value 16256.

See FIG. 4 again. S414 is a flowchart showing a process of reading a predetermined threshold value after the SRAM array 162 receives a read request command from the dither processing module 163. Further, FIG. 5 is a flowchart showing details of the process of S414.

In S501, the request receiving unit 301 determines whether or not a read request command has been received from the dither processing module 163. When it is determined that the read request command has been received from the dither processing module 163, the request receiving unit 301 transmits the read request command and the index acquisition result to the SRAM selection unit 302, the address generation unit 303, and the output control unit 305.

In S502, the SRAM selection unit 302 identifies the SRAM by the operation described with reference to FIG. 6A based on the received index acquisition result. In S503, the address generation unit 303 identifies the address by the operation described with reference to FIG. 6B based on the received index acquisition result.

In S504, the data storage unit 304 reads a threshold value from a predetermined SRAM and transmits it to the output control unit 305 based on the information for specifying the SRAM and the information for specifying the address. In S505, the output control unit 305 selects the necessary eight threshold values from the six threshold values and transmits them to the dither processing module 163 based on the index information transmitted to the request reception unit 301.

9 and 10 are diagrams for explaining the operation of reading the threshold data in S504 when different rotation patterns of the BN masks are used. The BN mask 901 of FIG. 9A is a non-rotating BN mask and corresponds to the BN mask 802 of FIG. In the BN mask 901, the threshold value corresponding to the 4 × 2 pixel block is read out in the blocks 902 and 903. As described with reference to FIGS. 13 and 14, the labels (A to P) displaying the SRAM do not overlap in the blocks 902 and 903, and the threshold value is read from different SRAMs. That is, 4 × 2 thresholds can be acquired in one clock cycle.

The BN mask 904 of FIG. 9B is a BN mask obtained by rotating the BN mask 901 to the right by 90 degrees, and corresponds to the BN mask 803 of FIG. The threshold value corresponding to the 4 × 2 pixel block is read out in blocks 905 and 906. As shown in FIG. 9B, the labels (A to P) displaying the SRAM do not overlap in the blocks 905 and 906, and the threshold value is read from different SRAMs. That is, 4 × 2 thresholds can be acquired in one clock cycle.

The BN mask 907 of FIG. 10A is a BN mask obtained by rotating the BN mask 901 by 180 degrees. The threshold value corresponding to the 4 × 2 pixel block is read out in blocks 908 and 909. As shown in FIG. 10, in the blocks 908 and 909, the labels (A to P) displaying the SRAM do not overlap, and the threshold value is read from different SRAMs. That is, 4 × 2 thresholds can be acquired in one clock cycle.

The BN mask 910 of FIG. 10B is a BN mask obtained by rotating the BN mask 901 to the right by 270 degrees. The threshold value corresponding to the 4 × 2 pixel block is read out in blocks 911 and 912. As shown in FIG. 10B, the labels (A to P) displaying the SRAM do not overlap in the blocks 911 and 912, and the threshold value is read from different SRAMs. That is, 4 × 2 thresholds can be acquired in one clock cycle.

Further, even when the mirror image of the BN mask 901 is used, the operation is the same as that of the BN mask 904, the BN mask 907, and the BN mask 910. That is, a plurality of threshold values are read from different SRAMs, and 4 × 2 threshold values can be acquired in one clock cycle.

As described above, according to the present embodiment, M × N threshold data can be read in one clock cycle regardless of the rotation pattern of the dither matrix. Further, since the storage area corresponding to the required size of the BN mask is realized by a plurality of SRAMs, the efficiency of using the storage area of the SRAM can be improved.

[Second Embodiment]
In the first embodiment, as shown in FIG. 8, a mode in which the rotated BN mask is bound has been described. In the present embodiment, a mode in which the BN mask is shifted by a predetermined pixel without rotating the BN mask will be described. Hereinafter, the points different from the first embodiment will be described with reference to FIGS. 4 and 5.

The process of the dither setting module 161 writing the threshold data to the SRAM array 162 is the same as the description of S401 to S405 in the first embodiment, and thus the description thereof will be omitted.

After the dither processing module 163 receives the input data, the threshold value is compared with the pixel value of the input data, and the result is output, except for S407, which is the same as the description of S406 to S413 in the first embodiment. Therefore, the description thereof will be omitted.

Hereinafter, the process of acquiring the index value in S407 in the present embodiment will be described. FIG. 11 is a diagram showing an index value of each pixel in the BN mask mapped to the image data 1101 in the present embodiment. In the present embodiment, as shown in FIG. 11, the 128 × 128 BN mask 1102 is mapped to the 512 × 512 image data 1101. Further, as shown in FIG. 11, the mapping in the main scanning direction (horizontal direction in the figure) is shifted by one pixel to the right every time the sub scanning direction (vertical direction in the figure) advances by 128 pixels. .. As shown in FIG. 11, the pixel of the index 127 is located below the pixel of the index 16256 between the BN masks in the sub-scanning direction.

In the present embodiment, as shown in FIG. 11, since the BN masks in the sub-scanning direction are shifted in the main scanning direction, the pattern peculiar to the matrix becomes inconspicuous. Further, as will be described later in FIG. 12, even if a block of 4 × 2 pixels straddles between BN masks, a plurality of threshold values will be read from different SRAMs, and 4 × 2 threshold values will be read in one clock cycle. Can be obtained.

The index acquisition unit 212 transmits the index information corresponding to the block of 4 × 2 pixels of interest to the threshold request transmission unit 213. Upon receiving the index information, the threshold request transmission unit 213 issues a read request command for threshold data to the SRAM array 162 together with the index information. After that, the corresponding threshold is read. The processing of S414 for reading a predetermined threshold value after the SRAM array 162 receives the read request command from the dither processing module 163 is the same as the description of S501 to S505 in the first embodiment, and thus the description thereof will be omitted. ..

FIG. 12 is a diagram for explaining the threshold reading operation in S504 in the present embodiment. The BN mask 1201 is a non-rotating BN mask. As described in the first embodiment, the threshold value corresponding to the block of 4 × 2 pixels is read from different SRAMs when it exists inside one BN mask.

FIG. 12 shows an example in which a block 1202 having 4 × 2 pixels straddles between BN masks. When the BN mask is mapped to the image data as shown in FIG. 12, even if the block 1202 of 4 × 2 pixels straddles between the BN masks, the labels (A to P) for displaying the SRAM are duplicated. Instead, the threshold will be read from different SRAMs. That is, 4 × 2 thresholds can be acquired in one clock cycle.

Although the non-rotating BN mask has been described with reference to FIGS. 11 and 12, threshold values are similarly read from different SRAMs at the same time even when the BN mask is a rotated pattern or a mirror image.

As described above, according to the present embodiment, even if a block of M × N pixels straddles between BN masks, a plurality of threshold values are read from different SRAMs, and M × N pieces are read in one clock cycle. Threshold can be obtained.

(Other Examples)
The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

100 Multifunction device: 112 CPU: 113 RAM: 116 ROM: 201 Control unit

Claims (10)

An image forming apparatus that executes halftone processing on image data.
A storage means for storing the threshold value set in the matrix used for the halftone processing in the storage unit, and
Pixel values are acquired from the image data in block units of M × N pixels smaller than the size of the matrix, and a threshold value corresponding to the block of M × N pixels is set from the matrix mapped to the image data in the storage unit. And the acquisition method to obtain from
An execution means for executing the halftone process based on the pixel value and the threshold value acquired by the acquisition means is provided.
The storage means distributes and stores a plurality of threshold values set in the matrix in a plurality of storage elements constituting the storage unit.
The plurality of threshold values are dispersed in the plurality of storage elements so that the M × N threshold values corresponding to the block of the M × N pixels are acquired from the M × N storage elements by the acquisition means. Stored,
The storage means stores, among the plurality of threshold values set in the matrix, a plurality of threshold values to be acquired by the acquisition means in one storage element for each position of the M × N pixel block.
An image forming apparatus characterized in that. The image forming apparatus according to claim 1, wherein the number of the plurality of storage elements is a squared value of the maximum value of M and N. A mapping means for mapping the matrix to the image data is further provided.
The acquisition means acquires a threshold value corresponding to the block of M × N pixels from the storage unit from the matrix mapped to the image data by the mapping means.
The image forming apparatus according to claim 1 or 2 . The image forming apparatus according to claim 3 , wherein the mapping means maps the matrix and a matrix obtained by rotating the matrix to the image data. The image forming apparatus according to claim 3 , wherein the mapping means maps the matrix to the image data while shifting the position where the matrix is mapped by a predetermined pixel. The image forming apparatus according to any one of claims 1 to 5 , wherein each of the plurality of storage elements is an SRAM. The image forming apparatus according to any one of claims 1 to 6 , wherein the matrix is a matrix used in the dither method. The image forming apparatus according to any one of claims 1 to 7 , wherein the matrix is a blue noise mask. A method executed in an image forming apparatus that performs halftone processing on image data.
A storage step of storing the threshold value set in the matrix used for the halftone processing in the storage unit, and
Pixel values are acquired from the image data in block units of M × N pixels smaller than the size of the matrix, and a threshold value corresponding to the block of M × N pixels is set from the matrix mapped to the image data in the storage unit. The acquisition process to be acquired from
It has an execution step of executing the halftone process based on the pixel value acquired in the acquisition step and the threshold value.
In the storage step, a plurality of threshold values set in the matrix are distributed and stored in a plurality of storage elements constituting the storage unit.
The plurality of threshold values are dispersed in the plurality of storage elements so that M × N threshold values corresponding to the block of M × N pixels are acquired from the M × N storage elements in the acquisition step. Stored,
In the storage step, among the plurality of threshold values set in the matrix, a plurality of threshold values to be acquired in the acquisition step are stored in one storage element for each position of the block of M × N pixels.
A method characterized by that. A program for operating a computer as each means according to the image forming apparatus according to any one of claims 1 to 8 .

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