JP6804414B2 - Evaluation device for semiconductor devices and evaluation method for semiconductor devices - Google Patents

Description

The present invention relates to an evaluation device for a semiconductor device for evaluating the electrical characteristics of a semiconductor element and an evaluation method for the semiconductor device.

Various inspections are performed on plate-shaped semiconductor devices such as wafers. In the inspection, for example, the electrical characteristics of a plurality of semiconductor elements formed in the semiconductor device are evaluated. In order to evaluate the electrical characteristics of each semiconductor element to be measured, first, one surface of the semiconductor device is fixed to the surface of the chuck stage by vacuum suction or the like. Then, the electrical characteristics of each semiconductor element are evaluated in a state where the probe is in contact with the other surface of the semiconductor device.

It should be noted that, for electric power semiconductor devices, a large number of probes have been used to supply a large current, apply a high voltage, and the like to one semiconductor element. Further, in addition to using many probes for one semiconductor element, a plurality of probes are provided on the probe card in order to evaluate a plurality of semiconductor elements at the same time.

The shape of the semiconductor device is generally disc-shaped (plate-shaped). Therefore, the shape of the peripheral edge of the semiconductor device is ring-shaped. Therefore, there are a plurality of imperfect semiconductor elements on the peripheral edge of the semiconductor device. Therefore, the probe cannot properly contact a plurality of imperfect semiconductor elements. In this case, the probe may come into contact with the periphery of the semiconductor device, that is, the surface of the chuck stage. When the probe comes into contact with the surface of the chuck stage, there is a problem that the chuck stage is damaged.

If the chuck stage is scratched, the adhesion between the semiconductor device and the chuck stage is reduced. Further, if the chuck stage is scratched, the semiconductor device may be damaged. Therefore, the situation where the chuck stage is scratched causes a decrease in the evaluation accuracy of the semiconductor device, a decrease in the yield, and the like.

Patent Document 1 discloses a configuration using a ring (hereinafter, also referred to as “related configuration A”) in order to solve the above problem. Specifically, in the related configuration A, a ring is arranged around the wafer in the fixed base. The ring is configured to surround the periphery of the wafer. Further, in the related configuration A, when measuring the electrical characteristics of the chip provided on the wafer, the contact pins located around the wafer among the plurality of contact pins are configured to come into contact with the upper surface of the ring. .. This suppresses the application of large pressure to the contact pins. The related configuration A is a configuration for evaluating the electrical characteristics of a chip that operates at a low voltage.

Japanese Unexamined Patent Publication No. 2010-287602

In the related configuration A, when the inner diameter of the ring is the same as the outer diameter of the semiconductor device (wafer), there is a high possibility that the ring comes into contact with the peripheral edge of the semiconductor device. Therefore, in the related configuration A, the inner diameter of the ring needs to be slightly larger than the outer diameter of the semiconductor device (wafer). Therefore, in the related configuration A, it is necessary to provide a gap at the boundary between the semiconductor device (wafer) and the ring. However, in the configuration in which the gap is provided, the tip of the probe may come into contact with the edge of the peripheral edge of the semiconductor device (wafer), and the peripheral edge may be damaged. Therefore, it is required that the upper surface of the peripheral edge of the semiconductor device is protected.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an evaluation device for a semiconductor device or the like capable of protecting the upper surface of a peripheral edge portion of the semiconductor device.

In order to achieve the above object, the evaluation device for a semiconductor device according to one aspect of the present invention has a function of evaluating the electrical characteristics of the semiconductor element. The evaluation device for a semiconductor device includes a stage for supporting a plate-shaped semiconductor device having a plurality of the semiconductor elements, a plurality of probes used for evaluating the electrical characteristics, and at least one cover. The plurality of probes are configured to move toward the upper surface of the semiconductor device, and the cover is configured so that the cover covers the side surfaces and the upper surface of the peripheral edge of the semiconductor device. A flexible insulating member is provided on a portion of the cover facing the side surface of the peripheral edge portion .

According to the present invention, the evaluation device for a semiconductor device includes a plurality of probes and a cover. The plurality of probes are configured to move toward the upper surface of the semiconductor device. The cover is configured so that the cover covers the side surfaces and the upper surface of the peripheral edge of the semiconductor device. Thereby, the upper surface of the peripheral edge portion of the semiconductor device can be protected.

It is a schematic diagram which shows the structure of the evaluation apparatus for semiconductor apparatus which concerns on Embodiment 1 of this invention. It is a top view which shows the semiconductor device. It is a figure for demonstrating a probe. It is a plan view of a stage. It is a cross-sectional view of a part of a stage along the line A1-A2 of FIG. It is a flowchart of the semiconductor device evaluation method which concerns on Embodiment 1 of this invention. It is a figure which shows the state which a probe is in contact with a cover. It is a figure for demonstrating the structure which concerns on the modification 1 of this invention. It is a flowchart of the semiconductor device evaluation method which concerns on modification 1 of this invention. It is sectional drawing of the cover which concerns on modification 1 of this invention, and the vicinity thereof. It is a figure for demonstrating the cover which concerns on modification 2 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings below, the same components are designated by the same reference numerals. The names and functions of the components with the same reference numerals are the same. Therefore, detailed description of a part of each component having the same reference numeral may be omitted.

The dimensions, materials, shapes, relative arrangements, and the like of each component exemplified in the embodiment may be appropriately changed depending on the configuration of the device to which the present invention is applied, various conditions, and the like. In addition, the dimensions of each component in each drawing may differ from the actual dimensions.

<Embodiment 1>
FIG. 1 is a schematic view showing the configuration of the evaluation device 100 for a semiconductor device according to the first embodiment of the present invention. In FIG. 1, the X direction, the Y direction, and the Z direction are orthogonal to each other.

The X, Y, and Z directions shown in the figure below are also orthogonal to each other. In the following, the direction including the X direction and the direction opposite to the X direction (−X direction) is also referred to as “X-axis direction”. Further, in the following, the direction including the Y direction and the direction opposite to the Y direction (−Y direction) is also referred to as “Y-axis direction”. Further, in the following, the direction including the Z direction and the direction opposite to the Z direction (−Z direction) is also referred to as “Z axis direction”.

Further, in the following, a plane including the X-axis direction and the Y-axis direction is also referred to as an “XY plane”. Further, in the following, a plane including the X-axis direction and the Z-axis direction is also referred to as an “XZ plane”. Further, in the following, a plane including the Y-axis direction and the Z-axis direction is also referred to as a “YZ plane”.

With reference to FIG. 1, the semiconductor device evaluation device 100 includes a stage St1, a probe base 20, an evaluation unit 4, a cover Cv1, and a moving mechanism 17.

The stage St1 is a chuck stage. The stage St1 has a main surface St1a. The main surface St1a is a surface on which the semiconductor device W1 is mounted. The semiconductor device W1 is a semiconductor wafer. In the following, the semiconductor wafer is also referred to as a “wafer” for simplification. The shape of the semiconductor device W1 is a plate shape (disk shape). The semiconductor device W1 includes a front surface W1a and a back surface W1b.

The semiconductor device W1 of the present embodiment has a vertical structure. The vertical structure is a structure in which a large current flows in the vertical direction (thickness direction) of the semiconductor device W1. A large current is a current of 1 ampere or more. The semiconductor device W1 may have a horizontal structure. The horizontal structure is a structure in which an electric current flows in a direction along the surface of a semiconductor device (wafer).

FIG. 2 is a plan view showing the semiconductor device W1. The semiconductor device W1 has a plurality of semiconductor elements Cp1 as chips. The plurality of semiconductor elements Cp1 are arranged in a plane in the semiconductor device W1. In order to make the configuration of the semiconductor element Cp1 easy to understand, the number of the semiconductor elements Cp1 shown in FIG. 2 is shown to be smaller than the actual number. Further, in FIG. 2, the pad Pd1 described later is not shown.

Again, with reference to FIG. 1, the base plate B1 described below, which is part of the probe substrate 20, is held by the moving arm 9. The moving arm 9 is configured to be movable in any direction. Therefore, the probe base 20 moves as the moving arm 9 moves. Note that FIG. 1 shows a state in which the probe base 20 (base plate B1) is held by one moving arm 9, but the present invention is not limited to this. The number of moving arms 9 holding the probe substrate 20 may be two or more. The semiconductor device W1 (stage St1) may be moved without moving the probe substrate 20.

The probe substrate 20 includes a base plate B1, a plurality of probes 10, and a connecting portion 8a. In FIG. 1, each probe 10 is shown in a simplified manner. Each probe 10 is used for evaluating the electrical characteristics of the semiconductor element Cp1, which will be described in detail later. In addition, each probe 10 has conductivity. Each probe 10 is made of, for example, a metal. The metal is, for example, copper, tungsten, rhenium tungsten or the like.

FIG. 3 is a diagram for explaining the probe 10. FIG. 3A is a diagram showing a detailed configuration of the probe 10. With reference to FIG. 3A, the probe 10 includes a plunger portion 12, a barrel portion 14, and a rod-shaped terminal 15.

The plunger portion 12 includes a contact portion Ct1 and a rod-shaped portion 13. The contact portion Ct1 is joined to the lower end of the rod-shaped portion 13. The surface of the contact portion Ct1 may be coated with gold, palladium, tantalum, platinum, etc. in order to improve conductivity, durability, and the like.

The shape of the barrel portion 14 is tubular. The barrel portion 14 is fixed to the base plate B1 of FIG. A spring member (not shown) such as a spring is provided inside the barrel portion 14. A plunger portion 12 (upper end of the rod-shaped portion 13) is joined to the spring member of the barrel portion 14. A rod-shaped terminal 15 is joined to the upper end of the barrel portion 14. The rod-shaped terminal 15 is electrically connected to the plunger portion 12 (contact portion Ct1) via the barrel portion 14. The rod-shaped terminal 15 functions as an output terminal to the outside.

Again, with reference to FIG. 1, a plurality of probes 10 are fixed to the base plate B1 at predetermined intervals. Further, the base plate B1 is provided with a connecting portion 8a. The connection portion 8a is electrically connected to the plurality of probes 10 via wiring (not shown). Further, the connection unit 8a is connected to the evaluation unit 4 via the signal line 6a. A connecting portion 8b is provided on the side surface of the stage St1. The connection unit 8b is connected to the evaluation unit 4 via the signal line 6b.

In the following, the state in which the semiconductor device W1 is mounted on the main surface St1a of the stage St1 is also referred to as “state St1”. Note that FIG. 1 shows the semiconductor device W1 in the state St1.

The cover Cv1 is a cover for protecting the stage St1 (chuck stage). The cover Cv1 is configured to cover at least a part of the semiconductor device W1 in the state St1, which will be described in detail later.

The moving mechanism 17 has a function of holding the cover Cv1 and a function of moving the cover Cv1 in an arbitrary direction. For example, the moving mechanism 17 has a function of moving the cover Cv1 in a direction (horizontal direction) along the upper surface (surface W1a) of the semiconductor device W1 and in a direction (Z-axis direction) orthogonal to the upper surface (surface W1a). Has. Since the moving mechanism 17 has a function of moving the cover Cv1 in the Z-axis direction (vertical direction), the cover Cv1 can be applied to, for example, a plurality of types of semiconductor devices W1 having different thicknesses.

In the following, the state in which the cover Cv1 covers at least a part of the semiconductor device W1 is also referred to as “state St2”. In addition, in FIG. 1, the cover Cv1 in the state St2 is shown.

FIG. 4 is a plan view of the stage St1 in the state St2. FIG. 5 is a cross-sectional view of a part of the stage St1 along the lines A1-A2 of FIG. In addition, in FIG. 5, in order to make it easy to understand the structure of the main part, a part of the structure is not shown. For example, in FIG. 5, the pad Pd1 described later is not shown.

With reference to FIGS. 4 and 5, the shape of the cover Cv1 in a plan view (XY plane) is a ring shape (closed loop shape). The cover Cv1 is configured so that the cover Cv1 can be put on the semiconductor device W1. Therefore, the inner diameter of the cover Cv1 is slightly larger than the outer diameter of the semiconductor device W1. In the state St2, there is a slight gap at the boundary between the cover Cv1 and the semiconductor device W1.

In the present embodiment, a state in which the size of the semiconductor device W1 in the plan view (XY plane) is smaller than the size of the stage St1 (main surface St1a) in the plan view (XY plane) will be described. Further, in the present embodiment, a state in which the cover Cv1 is arranged in the main surface St1a of the stage St1 will be described in a plan view (XY plane). For example, as shown in FIG. 5, the cover Cv1 is placed on the main surface St1a of the stage St1.

As shown in FIG. 3A, a pad Pd1 electrically connected to the semiconductor element Cp1 is provided on each semiconductor element Cp1. That is, a plurality of pads Pd1 are provided on the surface W1a of the semiconductor device W1. The pad Pd1 has conductivity. The pad Pd1 is a pad to be contacted with the contact portion Ct1 of the probe 10.

The stage St1 is a pedestal that supports the semiconductor device W1. The main surface St1a of the stage St1 contacts the back surface W1b of the semiconductor device W1. The stage St1 has, for example, a function of performing vacuum suction. The stage St1 fixes the back surface W1b of the semiconductor device W1 to the main surface St1a of the stage St1 by performing vacuum suction. The means for the stage St1 to fix the semiconductor device W1 is not limited to vacuum adsorption, and may be, for example, electrostatic adsorption.

The evaluation device 100 for a semiconductor device has a function of evaluating the electrical characteristics of the semiconductor element Cp1 of the semiconductor device W1. As described above, the semiconductor device W1 of the present embodiment has a vertical structure. When evaluating each semiconductor element Cp1 of the semiconductor device W1 having a vertical structure, two electrodes connected to the outside are used. One of the two electrodes is a probe 10 (contact portion Ct1) for contacting the pad Pd1 provided on the semiconductor element Cp1. The other of the two electrodes is the main surface St1a of the stage St1 in contact with the back surface W1b of the semiconductor device W1.

The main surface St1a of the stage St1 is electrically connected to the evaluation unit 4 via a connection portion 8b provided on the side surface of the stage St1 and a signal line 6b. In order to supply a large current to each semiconductor element Cp1, the probe substrate 20 is configured so that m probes 10 come into contact with each semiconductor element Cp1. "M" is an integer of 2 or more.

Further, it is preferable that the densities of the currents flowing through the probes 10 are substantially the same. For example, regardless of which of the plurality of probes 10 included in the probe substrate 20 is used, the current path from the connecting portion 8a provided on the base plate B1 to the connecting portion 8b via the used probe 10. It is preferable that the connecting portion 8a and the connecting portion 8b are provided so that the lengths of the two are substantially the same. Ideally, the connecting portion 8a and the connecting portion 8b are provided so that the connecting portion 8a faces the connecting portion 8b via the probe 10.

In the evaluation device 100 for semiconductor devices, the probe substrate 20 includes n sets of m probes 10 in order to collectively evaluate a plurality of semiconductor elements Cp1. "N" is an integer of 2 or more. That is, the probe substrate 20 includes k probes 10. “K” is an integer obtained by m × n.

Each probe 10 (rod-shaped terminal 15) is electrically connected to the connection portion 8a by a conductive wiring (not shown) provided on the base plate B1. The conductive wiring is made of, for example, metal or the like.

When the above-mentioned conductive wiring is provided on the base plate B1, it is desirable that the base plate B1 has an insulating property. When the conductive wiring is covered with an insulating member, the base plate B1 may be made of a metal or the like having no insulating property.

Next, the operation of the probe 10 will be described. In the process for evaluating the semiconductor element Cp1, the probe 10 in FIG. 3A moves downward (−Z direction) toward the pad Pd1. As a result, as shown in FIG. 3B, the contact portion Ct1 of the probe 10 comes into contact with the pad Pd1. When the probe 10 in the state of FIG. 3B is further moved downward (−Z direction), the rod-shaped portion 13 is pushed into the barrel portion 14 via a spring member (not shown). (See FIG. 3 (c)). That is, the rod-shaped portion 13 slides. As a result, the contact portion Ct1 surely contacts the pad Pd1. That is, the contact portion Ct1 physically and electrically contacts the pad Pd1.

The configuration of the probe 10 is not limited to the configuration in which the spring member is provided inside the barrel portion 14. For example, the configuration of the probe 10 may be such that a spring member is provided outside the barrel portion 14. Further, the configuration of the probe 10 is not limited to the spring type using a spring member. The configuration of the probe 10 may be, for example, a cantilever type. Further, the probe 10 may be a laminated probe, a wire probe, or the like.

Next, the detailed configuration of the cover Cv1 will be described. In the following, the peripheral edge portion of the semiconductor device W1 is also referred to as “peripheral portion W1e”. When the shape of the semiconductor device W1 in the plan view (XY plane) is a disk shape, the shape of the peripheral edge portion W1e in the plan view (XY plane) is a ring shape (closed loop) shape. In the following, the side surface of the peripheral edge portion W1e is also referred to as “side surface W1es”. Further, in the following, the upper surface of the peripheral edge portion W1e is also referred to as "upper surface W1eu". The upper surface W1eu is a part of the surface W1a. In the present embodiment, in the plan view (XY plane), the cover Cv1 surrounds the entire peripheral edge portion W1e of the semiconductor device W1.

As shown in FIG. 5, the cover Cv1 is configured so that the cover Cv1 covers the side surface W1es and the upper surface W1eu of the peripheral edge portion W1e of the semiconductor device W1. As described above, the shape of the cover Cv1 in the plan view (XY plane) is a ring shape (closed loop) shape. The cover Cv1 has a side surface Cv1s. In the above-mentioned state St2, the side surface Cv1s faces the side surface W1es of the peripheral edge portion W1e. That is, the side surface W1es corresponds to the portion of the cover Cv1 facing the side surface W1es of the peripheral edge portion W1e. The side surface W1es is provided with an insulating coating. Specifically, the side surface W1es is provided with a flexible insulating member 50. That is, the side surface W1es is covered with a flexible insulating member 50. The insulating member 50 provided on the side surface W1es is, for example, a fluororesin, PTFE, or the like. A flexible insulating member 50 may also be provided on the lower surface of the cover Cv1.

Further, the cover Cv1 has a base Cv1b and a protrusion Cv1x. The shape of the base Cv1b in a plan view (XY plane) is a ring shape (closed loop) shape. The protrusion Cv1x is a member that protrudes horizontally from the upper part of the base Cv1b. In a plan view (XY plane), the protrusion Cv1x overlaps with the peripheral edge W1e of the semiconductor device W1.

The base Cv1b is made of an insulating material. The insulating material is, for example, a resin material such as engineering plastic. Preferably, the insulating material constituting the base Cv1b is a high hardness PPS (polyphenylene sulfide) resin. Not only the base Cv1b but also the entire cover Cv1 may be made of the above-mentioned insulating material.

The protrusion Cv1x is configured so that no gap is formed between the cover Cv1 and the semiconductor device W1 in a plan view (XY plane). Specifically, in the state St2, as shown in FIG. 5, the protrusion Cv1x covers the upper surface W1eu of the peripheral edge W1e. The shape of the protrusion Cv1x in a plan view (XY plane) is a ring shape (closed loop) shape. The thickness of the protrusion Cv1x is smaller than the thickness of the semiconductor device W1.

Next, a method for evaluating the semiconductor device W1 (hereinafter, also referred to as “semiconductor device evaluation method Pr”) will be described. The semiconductor device evaluation method Pr is a process of evaluating the electrical characteristics of the semiconductor element Cp1 of the plate-shaped semiconductor device W1 by using the cover Cv1.

FIG. 6 is a flowchart of the semiconductor device evaluation method Pr according to the first embodiment of the present invention. Note that FIG. 6 shows only the main steps included in the semiconductor device evaluation method Pr. Before the semiconductor device evaluation method Pr is performed, a cover Cv1 having an appropriate size corresponding to the size of the semiconductor device W1 to be evaluated and the size of the main surface St1a of the stage St1 is selected. Further, the heights of the contact portions Ct1 of the plurality of probes 10 provided on the probe base 20 are aligned.

In the semiconductor device evaluation method Pr, first, a mounting step is performed (step S110). In the mounting step, a semiconductor device moving mechanism unit (not shown) having a function of moving the semiconductor device W1 in an arbitrary direction is used. In the mounting step, the semiconductor device moving mechanism unit mounts the semiconductor device W1 on the stage St1. As a result, the semiconductor device W1 is fixed to the stage St1.

Next, the placement step is performed (step S120). In the arranging step, a moving mechanism 17 having a function of moving the cover Cv1 in an arbitrary direction is used. In the arranging step, the moving mechanism 17 arranges the cover Cv1 on the stage St1. Specifically, the moving mechanism 17 arranges the cover Cv1 around the semiconductor device W1 so that the cover Cv1 covers the side surface W1es and the upper surface W1eu of the peripheral edge portion W1e of the semiconductor device W1.

Next, an evaluation step is performed (step S130). In the evaluation process, first, the probe movement process is performed. In the probe moving process, the moving arm 9 brings the plurality of probes 10 (probe base 20) to the upper surface of the semiconductor device W1 so that at least a part of the plurality of probes 10 comes into contact with the upper surface (surface W1a) of the semiconductor device W1. Move toward (surface W1a). That is, the plurality of probes 10 are configured to move toward the upper surface (surface W1a) of the semiconductor device W1 according to the operation of the moving arm 9.

In the following, among the plurality of probes 10 included in the probe substrate 20 in the probe movement process, the probe 10 facing the pad Pd1 is also referred to as a “pad-compatible probe”. Further, in the following, among the plurality of probes 10 included in the probe substrate 20 in the probe moving process, the probe 10 that does not face the semiconductor device W1 is also referred to as an “outside device probe” or a “probe 10a”. The external probe faces the peripheral region of the semiconductor device W1 in the probe movement process.

By the above-mentioned operation of the moving arm 9 in the probe moving process, the plurality of pad-compatible probes (contact portion Ct1) each come into contact with the plurality of pads Pd1 of the semiconductor device W1. The tip of the probe 10a (contact portion Ct1), which is an external probe, comes into contact with the upper surface of the cover Cv1 as shown in FIG. In FIG. 7, in order to make the configuration of the main part easy to understand, a part of the configuration is simplified and another part of the configuration is not shown. For example, probe 10 is shown in a simplified form. Further, the base plate B1 and the pad Pd1 are not shown.

In this way, the tip of the probe 10a (external probe) comes into contact with the upper surface of the cover Cv1. Therefore, the probe 10a does not damage the main surface St1a of the stage St1. That is, the cover Cv1 is a jig for bringing the probe 10a (external probe) into contact with the upper surface of the cover Cv1 in the evaluation step. Further, since the cover Cv1 can prevent the probe 10a from approaching the main surface St1a (surface) of the stage St1, it is possible to prevent the occurrence of the discharge phenomenon.

Further, in the evaluation step, a characteristic evaluation process is then performed. In the characteristic evaluation process, the evaluation unit 4 evaluates the electrical characteristics of the semiconductor element Cp1 of the semiconductor device W1. Since the process for evaluating the electrical characteristics of the semiconductor element Cp1 is a well-known process, it will be briefly described.

In the characteristic evaluation process, the electrical characteristics of each semiconductor element Cp1 are evaluated by passing a current through each semiconductor element Cp1 in a state where a plurality of pad-compatible probes are in contact with the pads Pd1 of the plurality of semiconductor elements Cp1. Will be done. The probe base 20 (pad-compatible probe) moves as needed. Based on the above, the electrical characteristics of the semiconductor element Cp1 are evaluated.

After completion of the evaluation process, the plurality of pad-compatible probes are separated from the plurality of pads Pd1. Next, the moving mechanism 17 separates the cover Cv1 from the stage St1. With the above, the semiconductor device evaluation method Pr is completed.

If necessary, the evaluated semiconductor device W1 is replaced with another semiconductor device W1 to be evaluated, and the process of evaluating the other semiconductor device W1 is continued. Further, depending on the size and thickness of another semiconductor device W1 to be evaluated, the cover Cv1 may be changed to another cover Cv1 corresponding to the size of the other semiconductor device W1.

As described above, according to the present embodiment, the semiconductor device evaluation device 100 includes a plurality of probes 10 and a cover Cv1. The plurality of probes 10 are configured to move toward the upper surface (surface W1a) of the semiconductor device W1. The cover Cv1 is configured so that the cover Cv1 covers the side surface W1es and the upper surface W1eu of the peripheral edge portion W1e of the semiconductor device W1. Thereby, the upper surface of the peripheral edge portion of the semiconductor device W1 can be protected. Further, even in a state where a gap exists at the boundary between the semiconductor device W1 and the cover Cv1, it is possible to prevent the probe 10 from entering the gap.

Further, in the present embodiment, the characteristic evaluation process is performed in the above-mentioned evaluation step. This makes it possible to collectively evaluate a plurality of semiconductor elements Cp1. Therefore, it is possible to shorten the time required for the evaluation process. Further, the number of semiconductor elements Cp1 to be evaluated can be maintained without considering the existence of the probe outside the device. Therefore, it is possible to prevent the time required for the evaluation process from becoming unnecessarily long.

Further, in the present embodiment, the tip end portion of the probe 10a (external probe) comes into contact with the upper surface of the cover Cv1. Therefore, it is possible to prevent damage to the peripheral edge of the semiconductor device W1 and scratches on the main surface St1a of the stage St1 (chuck stage) due to the movement of the probe 10a. Further, since the probe 10a can be prevented from approaching the main surface St1a (surface) of the stage St1, the occurrence of the discharge phenomenon can be prevented.

Further, in the present embodiment, the cover Cv1 (base Cv1b) is made of an insulating material. Therefore, even when the probe 10a (probe outside the device) comes into contact with the cover Cv1, it is possible to prevent the probe 10a from generating an unintended energization. The insulating material constituting the cover Cv1 (base Cv1b) is a high-hardness PPS resin. Therefore, it is possible to prevent the cover Cv1 from being scratched.

Further, in the present embodiment, a flexible insulating member 50 is provided on the side surface W1es of the cover Cv1. The presence of the insulating member 50 can prevent damage to the peripheral edge of the semiconductor device W1.

Further, in the present embodiment, the thickness of the protrusion Cv1x of the cover Cv1 is smaller than the thickness of the semiconductor device W1. Therefore, the steps in the cover Cv1 and the semiconductor device W1 are small. Therefore, as the probe 10, a probe having a small pushing amount can be applied. The probe having a small pushing amount is, for example, a cantilever probe card, a wire probe, or the like.

In the electrical characteristic evaluation process, in a semiconductor device for electric power to which a high voltage is applied, the tip of the probe touches the surface of the chuck stage when the probe is not in contact with the surface of the chuck stage. Proximity can cause discharge. When a discharge occurs, there is a problem that the semiconductor device in the vicinity of the location where the discharge occurs may be destroyed. Therefore, it is necessary to suppress the occurrence of electric discharge.

Further, in the related configuration A, as described above, it is necessary to provide a gap at the boundary between the semiconductor device (wafer) and the ring. However, in the configuration with a gap, there is a problem that the tip of the probe may come into contact with the edge of the peripheral edge of the semiconductor device (wafer) and the peripheral edge may be damaged.

Therefore, the evaluation device 100 for a semiconductor device of the present embodiment has the above-described configuration. Therefore, the semiconductor device evaluation device 100 of the present embodiment can solve each of the above problems. Further, according to the semiconductor device evaluation device 100 having the above configuration, as described above, in the manufacturing process of the semiconductor device (wafer), the probe contacts the parasitically formed unformed semiconductor element. Problems can also be solved.

When the probe 10a (probe outside the device) comes into contact with the cover Cv1, unintended energization can be stopped by the semiconductor device evaluation device 100. Therefore, in the present embodiment, the cover Cv1 (base Cv1b) is made of an insulating material, but the present invention is not limited to this. The base Cv1b of the cover Cv1 may be made of a metal that is easy to process (hereinafter, also referred to as "metal Mt1"). Further, the entire cover Cv1 may be made of metal Mt1. The metal Mt1 is, for example, iron, copper, aluminum, or the like.

Since the cover Cv1 is made of metal, it is possible to prevent the cover Cv1 from being damaged even when the probe 10a comes into contact with the cover Cv1. Therefore, it is possible to suppress the generation of debris (foreign matter) and the like due to the cover Cv1 being scratched.

When the cover Cv1 is made of the metal Mt1, the upper surface of the cover Cv1 may be covered with a high-hardness metal (hereinafter, also referred to as “metal Mt2”). The metal Mt2 is, for example, a metal having a hardness higher than the hardness of the metal Mt1. Further, when the cover Cv1 is composed of the metal Mt1, both the upper surface and the lower surface of the cover Cv1 may be covered with the metal Mt2. As a result, it is possible to further prevent the cover Cv1 from being scratched.

When the cover Cv1 is made of metal Mt1, the upper surface of the cover Cv1 may be covered with a ceramic material.

Further, in the present embodiment, the shape of the cover Cv1 in the plan view (XY plane) is not limited to the ring shape (closed loop shape). For example, if the protrusion Cv1x is configured to cover all the semiconductor elements Cp1 to be evaluated existing on the peripheral edge W1e of the semiconductor device W1, the shape of the cover Cv1 in the plan view (XY plane) will be. It may be a rectangle or the like.

Further, in order to facilitate the installation of the cover Cv1, the cover Cv1 may be provided with a handle.

<Modification example 1>
In the following, the configuration of the first embodiment is also referred to as “configuration Ct1”. Further, in the following, the configuration of this modification is also referred to as “configuration Ctm1”. The configuration Ctm1 is a configuration using a plurality of covers Cv1m. Configuration Ctm1 applies to Configuration Ct1 (Embodiment 1).

The evaluation device 100 for a semiconductor device to which the configuration Ctm1 is applied includes a plurality of covers Cv1m. Hereinafter, as an example, a configuration Ctm1 using four covers Cv1m will be described.

FIG. 8 is a diagram for explaining the configuration Ctm1 according to the first modification of the present invention. Note that FIG. 8 shows a state in which each cover Cv1m is held by the above-mentioned moving mechanism 17. Further, in FIG. 8, for simplification, only the portion of the moving mechanism 17 that holds the cover is shown.

Each cover Cv1m differs only in the shape in a plan view (XY plane) as compared with the cover Cv1. Since the other configurations of each cover Cv1m are the same as those of the cover Cv1, detailed description will not be repeated. Therefore, each cover Cv1m has a base Cv1b and a protrusion Cv1x, similarly to the cover Cv1. The cross-sectional shape of each cover Cv1m is the same as the shape of the cover Cv1 in FIG. Therefore, each cover Cv1m has a side surface W1es. Further, on the side surface W1es of each cover Cv1m, a flexible insulating member 50 is provided as in the case of the cover Cv1 of FIG.

The shapes of the four covers Cv1m in a plan view (XY plane) are, for example, the shapes shown in FIG. For example, as shown in FIG. 8, the four covers Cv1m are arranged at intervals so that the four covers Cv1m surround the semiconductor device W1. That is, the four covers Cv1m are arranged only at necessary locations. Further, the four covers Cv1m are arranged around the semiconductor device W1 so as to cover the side surface W1es and the upper surface W1eu of the peripheral edge portion W1e of the semiconductor device W1 as in the cover Cv1 of FIG.

In the configuration Ctm1, each moving mechanism 17 moves the cover Cv1m in the horizontal direction so that each cover Cv1m faces the side surface W1es of the semiconductor device W1. Each moving mechanism 17 moves the cover Cv1m in the horizontal direction so that the side surface W1es (insulating member 50) of the cover Cv1m comes into contact with the side surface W1es of the semiconductor device W1. Thereby, the position of the cover Cv1m can be easily performed.

Further, as described above, the moving mechanism 17 has a function of moving the cover Cv1m in the Z-axis direction (vertical direction). Therefore, for example, the cover Cv1m can be applied to a plurality of types of semiconductor devices W1 having different thicknesses.

In FIG. 8, all of the peripheral edges W1e of the semiconductor device W1 are not covered by the four covers Cv1m, but the present invention is not limited to this. For example, as shown in FIG. 4, the four covers Cv1m may be configured so that the four covers Cv1m cover all of the peripheral edges W1e of the semiconductor device W1. For example, the four covers Cv1m may be generated by dividing the ring-shaped cover Cv1 in FIG. 4 into four parts.

Further, the number of covers Cv1m in the configuration Ctm1 is not limited to 4, and may be 1, 2, or 5 or more.

Next, a method for evaluating the semiconductor device W1 in the configuration Ctm1 (hereinafter, also referred to as “semiconductor device evaluation method Pra”) will be described. FIG. 9 is a flowchart of the semiconductor device evaluation method Pra according to the first modification of the present invention. Note that FIG. 9 shows only the main steps included in the semiconductor device evaluation method Pra. In FIG. 9, the process of the same step number as the step number of FIG. 6 is the same as the process described in the first embodiment, so that the detailed description is not repeated. Hereinafter, the points different from those of the first embodiment will be mainly described.

In the semiconductor device evaluation method Pra, the mounting step is performed as in the first embodiment (step S110). Next, the placement step A is performed (step S120A). In the arrangement step A, the plurality of moving mechanisms 17 arrange the plurality of covers Cv1m around the semiconductor device W1 so that the plurality of covers Cv1m cover the side surface W1es and the upper surface W1eu of the peripheral edge portion W1e of the semiconductor device W1. To do. As a result, for example, as shown in FIG. 8, four covers Cv1m are arranged.

Next, the evaluation step is performed as in the first embodiment (step S130). As a result, the electrical characteristics of each semiconductor element Cp1 in the semiconductor device W1 are sequentially evaluated.

Next, a moving step is performed (step S140). The moving step is, in summary, a step of moving at least one of a plurality of covers Cv1m. In the moving step, for example, each moving mechanism 17 of FIG. 8 moves the cover Cv1m so that the cover Cv1m is separated from the semiconductor device W1. With the above, the semiconductor device evaluation method Pra is completed.

The semiconductor device evaluation method Pra is not limited to the above processing. For example, in the semiconductor device evaluation method Pra, u covers Cv1m may be moved according to the position of the semiconductor element Cp1 to be evaluated included in the semiconductor device W1 (hereinafter, also referred to as “configuration Ctm1a”). "U" is an integer of 1 or 2 or more.

In the following, a region in the vicinity of the semiconductor element Cp1 to be evaluated in the peripheral portion W1e of the semiconductor device W1 is also referred to as a “region near the evaluation target”. The configuration Ctm1a is also a configuration in which the cover Cv1m is arranged in the region near the evaluation target in the peripheral edge portion W1e of the semiconductor device W1.

In the semiconductor device evaluation method Pra in the configuration Ctm1, the mounting step (S110), the placement step A (S120A), the evaluation step (S130), the moving step (S140), and the evaluation step (S130) are sequentially performed. First, as in the first embodiment, the mounting step (S110) is performed. In the following, the four covers Cv1m in FIG. 8 are also referred to as covers Cv1ma, Cv1mb, Cv1mc, and Cv1md, respectively.

Here, it is assumed that the evaluation target neighborhood region corresponding to the first evaluation step in the configuration Ctm1a is a region of the peripheral portion W1e of the semiconductor device W1 covered by the covers Cv1ma and Cv1mb of FIG. ..

In this case, in the arrangement step A (S120A), the two moving mechanisms 17 move, for example, the two covers Cv1m and arrange them at the positions of the covers Cv1ma and Cv1mb in FIG. In other words, in the arrangement step A, the two moving mechanisms 17 cover the two covers Cv1m with the semiconductor device so that the two covers Cv1m cover the side surface W1es and the upper surface W1eu of the peripheral edge portion W1e of the semiconductor device W1. It is arranged around W1.

Next, in the first evaluation step (S130), the semiconductor element Cp1 to be evaluated is evaluated as in the first embodiment. Next, the moving step (S140) is performed. The moving step in the configuration Ctm1a is, in summary, a step of moving at least one of the plurality of covers Cv1m when the evaluation is performed in the evaluation step.

Here, it is assumed that the evaluation target neighborhood region corresponding to the second evaluation step in the configuration Ctm1a is a region of the peripheral edge portion W1e of the semiconductor device W1 covered by the covers Cv1mc and Cv1md of FIG. ..

In this case, in the moving step (S140) in the configuration Ctm1a, the two moving mechanisms 17 move the above-mentioned two covers Cv1m and arrange them at the positions of the covers Cv1mc and Cv1md in FIG. Then, the second evaluation step is performed. This completes the semiconductor device evaluation method Pra in the configuration Ctm1a.

Next, the size of the semiconductor device W1 in the plan view (XY plane) is the same as the size of the stage St1 (main surface St1a) in the plan view (XY plane) (hereinafter, also referred to as “same size state”). Will be described. In the same size state, the stage St1 exists below the semiconductor device W1 in FIG.

FIG. 10 is a cross-sectional view of the cover Cv1m of FIG. 8 and its vicinity in the same size state. Even in the same size state, the semiconductor device evaluation method Pra can be performed in the same manner as described above. The evaluation step of the semiconductor device evaluation method Pra in the same size state is performed in a state where the moving mechanism 17 holds the cover Cv1 m as shown in FIG.

As described above, according to the present modification, the same effect as that of the first embodiment can be obtained even in the configuration using a plurality of covers. Further, by moving the cover Cv1m in the horizontal direction, it is possible to arrange the cover Cv1m. Therefore, the cover Cv1m can be installed quickly, and the process of arranging the cover Cv1m can be shortened.

Further, in this modification, since a plurality of covers Cv1m are used, if a damaged cover Cv1m exists, only the damaged cover Cv1m can be easily replaced.

Further, in this modification, since a plurality of covers Cv1m are used, the size of each cover cover Cv1m is small, and each cover Cv1m is easy to handle. In addition, each cover Cv1m can be easily adapted to the existing equipment.

Further, according to the semiconductor device evaluation method Pra in the above-described configuration Ctm1a, the number of covers Cv1m required when the evaluation step is performed can be reduced.

<Modification 2>
In the following, the configuration of this modification will also be referred to as “configuration Ctm2”. The configuration Ctm2 is a configuration using a cover composed of a plurality of covers. Configuration Ctm2 applies to all or part of Configuration Ct1 (Embodiment 1) and Configuration Ctm1 (Modification 1).

As an example, the configuration Ctm1 (hereinafter, also referred to as “configuration Ctm12”) to which the configuration Ctm2 is applied is shown below. The configuration Ctm12 is a configuration in which the configuration Ctm2 is applied to the configuration of FIG.

The evaluation device 100 for a semiconductor device to which the configuration Ctm12 is applied includes a plurality of covers Cv2. FIG. 11 is a diagram for explaining the cover Cv2 according to the second modification of the present invention. As an example, FIG. 11 is a cross-sectional view of the cover Cv2 in the same size state as described above. Further, in FIG. 11, the size of the peripheral edge portion W1e in the X-axis direction is shown larger than that in FIG. 10 in order to make the configuration easy to understand.

With reference to FIG. 11, the cover Cv2 is composed of the covers Cv2a and Cv2b. Each of the covers Cv2a and Cv2b has a plate shape. The shapes of the covers Cv2a and Cv2b in a plan view (XY plane) are, for example, the same as the shape of the cover Cv1m in FIG.

The shape of the cover Cv2a is, for example, the same as the shape of the cover Cv2b. In the same size state described above, each of the covers Cv2a and Cv2b is held by the moving mechanism 17. The covers Cv2a and Cv2b can be moved independently by the two moving mechanisms 17. The cover Cv2 is configured by the two moving mechanisms 17 arranging the covers Cv2a and Cv2b as shown in FIG.

The cover Cv2a is a member that covers the side surface W1es of the peripheral edge portion W1e of the semiconductor device W1. The cover Cv2a has a side surface Cv2as facing the side surface W1es of the semiconductor device W1. Therefore, the side surface Cv2as of the cover Cv2a covers the side surface W1es of the peripheral edge portion W1e of the semiconductor device W1.

The cover Cv2b is a member mounted on the cover Cv2a. The cover Cv2b covers the upper surface W1eu of the peripheral edge portion W1e of the semiconductor device W1. That is, the cover Cv2b corresponds to the protrusion Cv1x of the cover Cv1.

The cover Cv2b is made of, for example, an insulating material. The insulating material is, for example, a material that does not break even if the probe 10 comes into contact with the insulating material at least once. The insulating material is, for example, a polyimide film. Further, the cover Cv2b may be made of the above-mentioned PPS resin.

The cover Cv2b may be made of the above-mentioned metal Mt1. When the cover Cv2b is made of the metal Mt1, the upper surface of the cover Cv2b may be covered with the above-mentioned high-hardness metal Mt2.

The cover Cv2a may be made of the same material as the material constituting the cover Cv2b. That is, the entire cover Cv2 may be made of the same material.

Further, of the cover Cv2a, the above-mentioned insulating member 50 having flexibility may be provided on the side surface Cv2as facing the side surface W1es of the semiconductor device W1.

As described above, according to the present modification, the same effect as that of the first embodiment and the first modification can be obtained. The cover Cv2b is prone to wear due to the above-mentioned evaluation step. Therefore, according to this modification, only the cover Cv2b can be replaced with another new cover Cv2b.

When the configuration Ctm2 is applied to the configuration Ct1 (Embodiment 1), the shapes of the covers Cv2a and Cv2b in a plan view (XY plane) are ring-shaped (closed loop-shaped). In the following, the cover Cv1m of FIG. 8 from which the protrusion Cv1x is removed is also referred to as “cover Cv1mn”. The cover Cv1mn is composed of only the base Cv1b of the cover Cv1m.

The shape of the cover Cv2a may be different from the shape of the cover Cv2b. Thereby, it is possible to realize a configuration in which the ring-shaped cover Cv2b is placed on the four covers Cv1mn arranged in the same manner as the four covers Cv1m in FIG. Further, the thickness of the cover Cv2b corresponding to the above-mentioned protrusion Cv1x may be smaller than the thickness of the semiconductor device W1.

It should be noted that, within the scope of the present invention, embodiments and modifications can be freely combined, and embodiments and modifications can be appropriately modified or omitted.

10, 10a probe, 17 moving mechanism, 100 evaluation device for semiconductor device, Cv1, Cv1m, Cv1mn, Cv2, Cv2a, Cv2b cover, Cv1x protrusion, St1 stage, W1 semiconductor device.

Claims (11)

An evaluation device for semiconductor devices that has the function of evaluating the electrical characteristics of semiconductor elements.
A stage that supports a plate-shaped semiconductor device having the plurality of the semiconductor elements, and
With a plurality of probes used to evaluate the electrical properties,
With at least one cover,
The plurality of probes are configured to move toward the upper surface of the semiconductor device.
The cover is configured so that the cover covers the side surfaces and the upper surface of the peripheral edge of the semiconductor device .
An evaluation device for a semiconductor device in which a flexible insulating member is provided on a portion of the cover facing the side surface of the peripheral edge portion . An evaluation device for semiconductor devices that has the function of evaluating the electrical characteristics of semiconductor elements.
A stage that supports a plate-shaped semiconductor device having the plurality of the semiconductor elements, and
With a plurality of probes used to evaluate the electrical properties,
With at least one cover,
The plurality of probes are configured to move toward the upper surface of the semiconductor device.
The cover is configured so that the cover covers the side surfaces and the upper surface of the peripheral edge of the semiconductor device.
The evaluation device for a semiconductor device includes a plurality of the covers.
For semi-conductor device evaluation apparatus. The cover has a protrusion that covers the upper surface of the peripheral edge portion.
The evaluation device for a semiconductor device according to claim 1 or 2 , wherein the thickness of the protrusion is smaller than the thickness of the semiconductor device. The evaluation device for semiconductor devices further includes
The evaluation device for a semiconductor device according to any one of claims 1 to 3, further comprising a moving mechanism having a function of moving the cover in a direction along the upper surface of the semiconductor device and in a direction orthogonal to the upper surface. .. The evaluation device for a semiconductor device according to any one of claims 2 to 4 , wherein a flexible insulating member is provided on a portion of the cover facing the side surface of the peripheral edge portion. The evaluation device for a semiconductor device according to any one of claims 1 to 5 , wherein the cover is made of an insulating material. The evaluation device for a semiconductor device according to any one of claims 1 to 5 , wherein the cover is made of a first metal. The evaluation device for a semiconductor device according to claim 7 , wherein the upper surface of the cover is covered with a second metal having a hardness higher than that of the first metal. The cover is
A first member that covers the side surface of the peripheral edge of the semiconductor device,
It is composed of a second member mounted on the first member.
The evaluation device for a semiconductor device according to any one of claims 1 to 8 , wherein the second member covers the upper surface of the peripheral edge portion. The evaluation device for a semiconductor device according to any one of claims 1 , 3, 4, 5, 6 , 7 , 8 and 9 , further comprising the plurality of covers. A method for evaluating a semiconductor device, which evaluates the electrical characteristics of a semiconductor element of a plate-shaped semiconductor device using at least one cover.
The cover is configured so that the cover covers the side surfaces and the upper surface of the peripheral edge of the semiconductor device.
The mounting process of mounting the semiconductor device on the stage and
An arrangement step of arranging the cover around the semiconductor device so that the cover covers the side surface and the upper surface of the peripheral edge of the semiconductor device.
A plurality of probes, the moving toward the upper surface of the semiconductor device, viewed including the an evaluation step of evaluating electrical characteristics of the semiconductor element of the semiconductor device,
In the method for evaluating a semiconductor device, a plurality of the covers are used.
In the arrangement step, the plurality of covers are arranged around the semiconductor device so that the plurality of covers cover the side surfaces and the upper surface of the peripheral edge portion of the semiconductor device.
The evaluation method of the semiconductor device further describes.
A method for evaluating a semiconductor device, which includes a moving step of moving at least one of the plurality of covers when the evaluation is performed in the evaluation step .

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