JP6809484B2 - Synchronous circuit and control method of synchronous circuit - Google Patents

Description

The present technology relates to a synchronous circuit and a control method of the synchronous circuit. More specifically, the present invention relates to a synchronization circuit that captures a data signal in synchronization with a periodic signal and a control method of the synchronization circuit.

Conventionally, a phase detector has been used in a phase-locked loop or the like to detect the phase difference between two signals. In an analog phase-locked loop that synchronizes a data signal and a clock signal, a hodge-type phase detector or the like is used (see, for example, Non-Patent Document 1). This hodge type phase detector is provided with a flip-flop and an XOR (exclusive OR) gate. The flip-flop holds the data signal in synchronization with the clock signal, and the XOR gate outputs a pulse signal according to the phase difference between the clock signal and the data signal.

Behzad Razavi, "Design of Integrated Circuits for Optical Communications," (USA), Wiley, pp294-303.

However, in the above-mentioned phase detector, if the control for matching the phases of the data signal and the clock signal is performed, the value of the data signal may change at the setup time or the hold time of the flip-flop. Here, the setup time is a period during which the change of the data signal is prohibited before the rise of the clock signal, and the hold time is the period during which the change of the data signal is prohibited after the rise of the clock signal. If the value of the data signal changes during the setup time or hold time, the flip-flop fails to capture the data signal and its output becomes a metastable. As a result, the phase detector malfunctions and the phase difference cannot be detected accurately. As described above, in a synchronization circuit (phase detector or the like) that captures a data signal in synchronization with a periodic signal such as a clock signal, there is a problem that a malfunction occurs due to a failure in capturing the data signal.

This technology was created in view of such a situation, and aims to suppress malfunction of a synchronization circuit that takes in a data signal in synchronization with a periodic signal.

The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a holding unit that holds an input signal in synchronization with a predetermined periodic signal, and the above-mentioned input signal and the above-mentioned predetermined. It is a synchronization circuit including a variable delay element which delays at least one of a periodic signal over a random delay time and supplies it to the holding part, and a control method thereof. This has the effect that the input signal delayed over a random delay time is held in synchronization with the periodic signal.

Further, in the first aspect, the phase of the input signal and the phase of the predetermined periodic signal may be matched by controlling the phase of at least one of the input signal and the predetermined periodic signal. This has the effect that the phase of the input signal and the phase of the periodic signal match.

Further, in the first aspect, a generator that generates a signal having a random value and supplies the signal to the variable delay element may be further provided. This has the effect of controlling the delay time of the variable delay element by the signal generated by the generator.

Further, in this first aspect, the generator may include a constant current source and a resistor connected to the constant current source. This has the effect of generating a thermal noise signal for the resistor.

Also, in this first aspect, the generator may further include an amplifier that amplifies the signal from the resistor. This has the effect of controlling the delay time of the variable delay element by the amplified signal.

Further, in the first aspect, the variable delay element may delay at least one of the input signal and the predetermined periodic signal by a variable capacitance that changes the capacitance according to a random voltage value. This has the effect that at least one of the input signal and the predetermined periodic signal is delayed by the variable capacitance over a random delay time.

Further, in the first aspect, the variable delay element has a variable current source that supplies a bias current of a random current value, and the input signal and the predetermined predetermined over a delay time corresponding to the supplied bias current. A transistor that delays at least one of the periodic signals of the above may be provided. As a result, at least one of the input signal and the predetermined periodic signal is delayed for a delay time corresponding to the bias current of the random current value.

Further, in the first aspect, the variable delay element includes a plurality of fixed capacitances having a constant electric capacity, a fixed delay element, each of the plurality of fixed capacitances according to a digital signal indicating a predetermined random number, and the fixed delay. A switch that opens and closes a path connecting the element may be provided. As a result, the path connecting each of the plurality of fixed capacitances and the fixed delay element is opened and closed according to a digital signal indicating a random number.

Further, in the first aspect, the variable delay element has a plurality of fixed current sources, each of which supplies a constant bias current, and the input signal and the predetermined value over a delay time corresponding to the sum of the bias currents. A transistor that delays at least one of the periodic signals of the above and a switch that opens and closes a path connecting each of the plurality of fixed current sources and the transistor according to a digital signal indicating a random number may be provided. This has the effect that the path connecting each of the plurality of fixed current sources and the transistor is opened and closed according to a digital signal indicating a random number.

Further, in the first aspect, the variable delay element may delay only the input signal over a random delay time. This has the effect that the input signal delayed over a random delay time is held in synchronization with the periodic signal.

Further, in the first aspect, the variable delay element may delay only the predetermined periodic signal over a random delay time. This has the effect that the input signal is held synchronously with the periodic signal delayed over a random delay time.

Further, in the first aspect, the variable delay element may delay both the input signal and the predetermined periodic signal over a random delay time. This has the effect that the input signal delayed over the random delay time is held synchronously with the periodic signal delayed over the random delay time.

Further, in the first aspect, a detection unit that detects a phase difference between the input signal and the predetermined periodic signal based on the held input signal, and an oscillation circuit that generates the predetermined periodic signal are provided. Further, the control unit may control the oscillation circuit based on the detected phase difference. This has the effect of controlling the oscillator circuit based on the detected phase difference.

Further, in the first aspect, the holding unit holds the input signal in synchronization with the rising edge of the predetermined periodic signal, and supplies the held signal as the first internal signal. The flip flop, the first post-stage flip flop that holds the first internal signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as the second internal signal, and the predetermined The second front flip flop that holds the input signal in synchronization with the falling edge of the periodic signal and supplies the held signal as a third internal signal, and the rising edge of the predetermined periodic signal in synchronization with the above. It includes a second rear-stage flipflop that holds a third internal signal and supplies the held signal as a fourth internal signal, and the detection unit uses the first internal signal and the fourth internal signal. A first exclusive logical sum gate that outputs the exclusive logical sum of the above, and a second exclusive logical sum gate that outputs the exclusive logical sum of the second internal signal and the fourth internal signal. The variable delay element may supply the delayed signal to the second pre-stage flip flop. As a result, the delayed signal is supplied to the second flip-flop that holds the signal in synchronization with the falling edge of the periodic signal.

Further, in the first aspect, edge data in which the input signal is delayed over the random input time and recovery data in which the input signal is delayed over a predetermined delay time are supplied to the holding unit. The variable delay circuit, the edge detection circuit for detecting the edge of the input signal, and the oscillation circuit for generating the predetermined periodic signal in synchronization with the timing at which the edge is detected are further provided. The variable delay circuit and the oscillation circuit may be controlled based on the retained edge data and recovery data. This has the effect of generating a periodic signal at the timing when the edge is detected.

Further, in the first aspect, the predetermined periodic signal includes the first and second periodic signals having different phases by π / 2, and the holding portion synchronizes with the rising edge of the first periodic signal. The recovery data is held and held in synchronization with the first flip flop that holds the edge data and supplies the held signal as the first edge data and the rising edge of the second periodic signal. The edge data is held in synchronization with the falling edge of the first periodic signal and the second flip flop that supplies the signal as the first recovery data, and the held signal is used as the second edge data. A third flip flop to be supplied and a fourth flip flop that holds the recovery data in synchronization with the falling edge of the second periodic signal and supplies the held signal as the second recovery data. The arithmetic circuit may control the variable delay circuit and the oscillation circuit based on the first and second edge data and the first and second recovery data. As a result, in the half-rate method, the recovery data and the edge data delayed over a random delay time are held in synchronization with the periodic signal.

Further, in the first aspect, the predetermined periodic signal includes the first, second, third and fourth periodic signals whose phases are different from each other by π / 4, and the holding unit has the first period. The first flip flop that retains the edge data in synchronization with the rising edge of the signal and supplies the held signal as the first edge data, and the recovery in synchronization with the rising edge of the second periodic signal. The second flip flop that retains the data and supplies the retained signal as the first recovery data, and the edge data that is retained and the retained signal synchronized with the rising edge of the third periodic signal. The third flip flop supplied as the second edge data and the recovery data are retained in synchronization with the rising edge of the fourth periodic signal, and the retained signal is supplied as the second recovery data. The flip flop, the fifth flip flop that holds the edge data in synchronization with the falling edge of the first periodic signal, and supplies the held signal as the third edge data, and the second flip flop. The sixth flip flop that holds the recovery data in synchronization with the falling edge of the periodic signal and supplies the held signal as the third recovery data, and synchronizes with the falling edge of the third periodic signal. The recovery data is held in synchronization with the seventh flip flop that holds the edge data and supplies the held signal as the fourth edge data, and the falling edge of the fourth periodic signal. It includes an eighth flip flop that supplies the held signal as fourth recovery data, and the arithmetic circuit includes the first, second, third, and fourth edge data and the first, second, and fourth edge data. The variable delay circuit and the oscillation circuit may be controlled based on the third and fourth recovery data. As a result, in the quarter rate method, the recovery data and the edge data delayed over a random delay time are held in synchronization with the periodic signal.

According to the present technology, it is possible to obtain an excellent effect that a malfunction of a synchronization circuit that captures a data signal in synchronization with a periodic signal can be suppressed. The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram which shows one configuration example of the communication system in 1st Embodiment of this technology. It is a block diagram which shows one configuration example of the clock data recovery circuit in the 1st Embodiment of this technique. It is a figure which shows the circuit which shows one configuration example of the random jitter generator and the noise characteristic in 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the phase detector in the 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the variable delay element in 1st Embodiment of this technique. It is a circuit diagram which shows one configuration example of the oscillation circuit in 1st Embodiment of this technique. It is a figure for demonstrating the setup time and hold time in the 1st Embodiment of this technique. It is a timing chart which shows an example of the signal before and after the phase shift in the 1st Embodiment of this technique. It is a figure which shows an example of the phase characteristic of the data signal and the clock signal in the 1st Embodiment of this technique. It is a figure which shows an example of the phase characteristic of a data signal and a clock signal in the comparative example of this technique. It is a timing chart which shows an example of the operation of the phase detector in the 1st Embodiment of this technique. It is a graph which shows an example of the relationship between the input phase difference and the output phase difference in the 1st Embodiment of this technique and a comparative example. It is a flowchart which shows an example of the operation of the clock data recovery circuit in 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the phase detector in the 1st modification of 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the phase detector in the 2nd modification of the 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the variable delay element in the 3rd modification of the 1st Embodiment of this technique. It is a block diagram which shows one configuration example of the clock data recovery circuit in the 4th modification of the 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the variable delay element in the 4th modification of the 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the variable delay element in the 5th modification of the 1st Embodiment of this technique. It is a block diagram which shows one configuration example of the clock data recovery circuit in the 2nd Embodiment of this technique. It is a circuit diagram which shows one structural example of the delay part and the holding part in the 2nd Embodiment of this technique. It is a circuit diagram which shows one configuration example of the oscillation circuit in the 2nd Embodiment of this technique. It is a block diagram which shows one structural example of the digital arithmetic circuit in 2nd Embodiment of this technique. It is a timing chart which shows an example of the operation of the delay part in the 2nd Embodiment of this technique. It is a circuit diagram which shows one configuration example of the random jitter generator in the 3rd Embodiment of this technique. It is a circuit diagram which shows one configuration example of the amplifier in the 3rd Embodiment of this technique. It is a circuit diagram which shows one structural example of a delay part and a holding part in 4th Embodiment of this technique. It is a timing chart which shows an example of the operation of the clock data recovery circuit in 4th Embodiment of this technique. It is a circuit diagram which shows one structural example of the delay part and the holding part in 5th Embodiment of this technique. It is a timing chart which shows an example of the operation of the clock data recovery circuit in 5th Embodiment of this technique.

Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example of holding a randomly delayed data signal in synchronization with a clock signal)
2. 2. Second embodiment (an example in which a randomly delayed data signal is held in synchronization with a clock signal and the phase and frequency of the clock signal are controlled).
3. 3. Third Embodiment (Example of holding a data signal randomly delayed by noise amplified by an amplifier in synchronization with a clock signal)
4. Fourth Embodiment (Example of holding a data signal randomly delayed in the half-rate method in synchronization with a clock signal)
5. Fifth Embodiment (Example of holding a data signal randomly delayed in the quarter rate method in synchronization with a clock signal)

<1. First Embodiment>
[Example of electronic device configuration]
FIG. 1 is a block diagram showing a configuration example of a communication system according to the first embodiment. This communication system includes a source device 100 and an electronic device 200. Further, the electronic device 200 includes a communication interface 210, a clock data recovery circuit 300, and a data processing unit 220.

The communication interface 210 transmits / receives a data signal to / from an external device such as the source device 100. The communication interface 210 receives the data signal DATA on which the clock signal is superimposed, and supplies the data signal DATA to the clock data recovery circuit 300 via the signal line 219. As the communication standard of this communication interface 210, for example, DisplayPort v1.3 and MIPI (Mobile Industry Processor Interface) M-PHY v4.0 standard are used.

The clock data recovery circuit 300 generates a clock signal CK substantially the same as the clock signal superimposed on the data signal DATA from the data signal DATA. The clock data recovery circuit 300 internally generates a clock signal CK by an oscillation circuit, and adjusts the phase of the clock signal CK according to the data signal. As a result, a signal that substantially matches the clock signal superimposed on the transmitting side is reproduced as the clock signal CK. The clock data recovery circuit 300 supplies the data signal DATA and the generated clock signal CK to the data processing unit 220 via the signal lines 308 and 309. The clock data recovery circuit 300 is an example of the synchronization circuit described in the claims.

The data processing unit 220 takes in and processes the data signal DATA in synchronization with the clock signal CK. The data processing unit 220 performs, for example, processing for converting serial data into parallel data, audio processing, image processing, and the like.

[Clock data recovery circuit configuration example]
FIG. 2 is a block diagram showing a configuration example of the clock data recovery circuit 300 according to the first embodiment. The clock data recovery circuit 300 includes a random jitter generator 310, a phase detector 320, a digital arithmetic circuit 330, and an oscillation circuit 340.

The random jitter generator 310 generates a voltage signal _VRJ having a random voltage value. The random jitter generator 310 supplies the voltage signal _VRJ to the phase detector 320.

The phase detector 320 detects the phase difference between the data signal DATA and the clock signal CK from the oscillation circuit 340. The phase detector 320 delays the data signal DATA for a delay time corresponding to the value of the voltage signal _VRJ (that is, at random), then captures and processes the data signal DATA, and detects the detection signals UP and DN indicating the phase difference. Generate. The detection signal UP indicates whether or not the phase of the clock signal CK is advanced with respect to the data signal DATA. For example, a high level is set for the detection signal UP when the clock signal CK is ahead, and a low level is set when the clock signal CK is behind.

On the other hand, the detection signal DN indicates whether or not the phase of the clock signal CK is delayed with respect to the data signal DATA. For example, when the clock signal CK is delayed, the detection signal DN is set to a high level, and when the clock signal CK is advanced, a low level is set.

Although the phase detector 320 detects the phase difference between the clock signal and the data signal, it may detect the phase difference between the data signal and a periodic signal other than the clock signal, such as a strobe signal.

The digital arithmetic circuit 330 matches the phases of the data signal DATA and the clock signal CK by controlling the phase of the clock signal CK with the control signal P _control based on the phase difference indicated by the detection signals UP and DN. .. The digital arithmetic circuit 330 counts the number of high levels for each of the detection count UP and DN. Then, the digital arithmetic circuit 330 delays the phase of the clock signal CK as the frequency at which the detection signal UP becomes high level is higher than the frequency at which the detection signal DN becomes high level. On the other hand, the higher the frequency at which the detection signal DN becomes high level than the frequency at which the detection signal UP becomes high level, the more the digital arithmetic circuit 330 advances the phase of the clock signal CK. The digital arithmetic circuit 330 is an example of the control unit described in the claims.

The oscillation circuit 340 generates a clock signal CK according to the control signal P _control and supplies it to the phase detector 320 and the data processing unit 220.

As described above, the clock data recovery circuit that controls the phase of the clock signal according to the phase difference is called a phase interpolation type clock data recovery circuit.

The random jitter generator 310, the phase detector 320, the digital arithmetic circuit 330, and the oscillation circuit 340 are provided in the clock data recovery circuit 300, but the configuration is not limited to this. These circuits may be provided in a phase-locked loop that synchronizes two clock signals. In this case, instead of the data signal DATA and the clock signal CK, two clock signals are input to the phase detector 320.

[Random jitter generator configuration example]
FIG. 3 is a diagram showing a circuit and noise characteristics showing a configuration example of the random jitter generator 310 according to the first embodiment. In the figure, a is a circuit diagram showing a configuration example of the random jitter generator 310. The random jitter generator 310 includes a constant current source 311 and a resistor 312. The constant current source 311 and the resistor 312 are connected in series between the power supply terminal and the ground terminal, and the voltage signal at these connection points is supplied to the phase detector 320 as _VRJ . The resistor 312 is used as a noise source, and the noise level of the thermal noise depends on the temperature T and the resistance value R. The random jitter generator 310 is an example of the generator described in the claims.

FIG. 3B is a diagram showing noise characteristics. In the figure, the vertical axis of b indicates the noise level of the noise source (resistor 312), and the horizontal axis indicates the noise frequency f. The voltage Vnoise of the resistor 312 is expressed by the following equation.
Vnoise = (2kRT · Δf) ^1/2
In the above equation, k is the Boltzmann constant. R is the resistance value of the resistor 312, and the unit is, for example, ohm (Ω). T is the temperature of the resistor 312 and the unit is, for example, Kelvin (K). Δf indicates the bandwidth of noise, and the unit is, for example, hertz (Hz).

The value of the voltage signal _VRJ is expressed by the following equation, where I ₀ is the current value supplied by the constant current source 311.
V _RJ = I ₀ · R ± V noise

In this way, a voltage signal of a random value is generated as _VRJ by using the thermal noise of the resistor 312. The random jitter generator 310 may use an element or circuit other than the resistor 312 as a noise source.

[Phase detector configuration example]
FIG. 4 is a circuit diagram showing a configuration example of the phase detector 320 according to the first embodiment. The phase detector 320 includes a fixed delay element 321, a variable delay element 400, front flip-flops 323 and 324, rear flip-flops 325 and 326, and XOR gates 327 and 328.

The fixed delay element 321 delays the data signal DATA over a fixed delay time. The delay time of the fixed delay element 321 is set to, for example, the average value of the delay times of the variable delay element 400. The fixed delay element 321 supplies the delayed data signal DATA to the front flip-flop 323.

The variable delay element 400 delays the data signal DATA over a delay time corresponding to the value of the voltage signal _VRJ (that is, at random). The variable delay element 400 supplies the delayed data signal DATA to the pre-stage flip-flop 324.

The variable delay element 400 is an element (that is, a buffer) that outputs the data signal DATA without being inverted, but may be an element (that is, an inverter) that outputs the data signal DATA in an inverted manner. In the case of an inverter, the pre-stage flip-flop 324 holds the data signal DATA in synchronization with the rising edge of the signal inverted by the inverter.

The pre-stage flip-flop 323 holds the data signal in synchronization with the rising edge of the clock signal CK. The front flip-flop 323 supplies the held signal as an internal signal Q1 to the XOR gate 327, the rear flip-flop 325, and the data processing unit 220. The front flip-flop 323 is an example of the first front flip-flop described in the claims.

The post-stage flip-flop 325 holds the internal signal Q1 in synchronization with the rising edge of the clock signal CK. The subsequent flip-flop 325 supplies the held signal as an internal signal Q2 to the XOR gate 328. The latter-stage flip-flop 325 is an example of the first rear-stage flip-flop described in the claims.

The pre-stage flip-flop 324 holds the data signal in synchronization with the falling edge of the clock signal CK. The front flip-flop 324 supplies the held signal as an internal signal Q3 to the rear flip-flop 326. The front flip-flop 324 is an example of the second front flip-flop described in the claims.

The post-stage flip-flop 326 holds the internal signal Q3 in synchronization with the rising edge of the clock signal CK. The subsequent flip-flop 326 supplies the held signal as an internal signal Q4 to the XOR gates 327 and 328. The latter-stage flip-flop 326 is an example of the second rear-stage flip-flop described in the claims.

The XOR gate 327 outputs the exclusive OR of the internal signals Q1 and Q4 as the detection signal DN. The XOR gate 328 outputs the exclusive OR of the internal signals Q2 and Q4 as a detection signal UP.

The circuit including the XOR gates 327 and 328 is an example of the detection unit described in the claims. Further, the XOR gate 327 is an example of the first exclusive OR gate described in the claims, and the XOR gate 328 is an example of the second exclusive OR gate described in the claims. is there.

Further, although the phase detector 320 is provided with a variable delay element 400 having a random delay time, if the synchronous circuit is provided with a holding unit such as a flip-flop or a latch circuit, the variable delay element 400 may be other than the phase detector. It can also be provided in the circuit. For example, the analog-digital converter may be provided with the variable delay element 400. In this case, the variable delay element 400 is inserted in the front stage of a flip-flop or the like that holds the signal in synchronization with the periodic signal.

[Configuration example of variable delay element]
FIG. 5 is a circuit diagram showing a configuration example of the variable delay element 400 according to the first embodiment. The variable delay element 400 includes P-type transistors 401 and 403, N-type transistors 402 and 404, and a variable capacitance 405. As the P-type transistor 401, P-type transistor 403, N-type transistor 402, and N-type transistor 404, for example, a MOS (Metal Oxide Semiconductor) transistor is used.

The P-type transistor 401 and the N-type transistor 402 are connected in series between the power supply terminal and the ground terminal. The P-type transistor 403 and the N-type transistor 404 are also connected in series between the power supply terminal and the ground terminal.

Further, a data signal DATA is input to the gates of the P-type transistor 401 and the N-type transistor 402. The drains of the P-type transistor 401 and the N-type transistor 402 are connected to the variable capacitance 405 and the gates of the P-type transistor 403 and the N-type transistor 404. The drains of the P-type transistor 403 and the N-type transistor 404 are connected to the pre-stage flip-flop 324.

The variable capacitance 405 is a capacitance whose electric capacity changes according to the value of the voltage signal _VRJ . As the variable capacitance 405, for example, a varicap diode is used. Due to this variable capacitance 405, the data signal is delayed and output over a random delay time.

When the variable delay element 400 is used as an inverter, the P-type transistor 403 and the N-type transistor 404 in the subsequent stage are unnecessary.

[Example of oscillator circuit configuration]
FIG. 6 is a circuit diagram showing a configuration example of the oscillation circuit 340 according to the first embodiment. The oscillation circuit 340 includes a selector 341 and an odd number (for example, 5) of inverters 342. The odd number of inverters 342 are connected in a ring shape. Further, each output terminal of the inverter 342 is commonly connected to the input terminal of the inverter 342 in the subsequent stage and the selector 341.

The selector 341 selects one of the output signals of the odd number of inverters 342 according to the control signal P _control . The selector 341 supplies the selected signal as a clock signal CK to the phase detector 320.

FIG. 7 is a diagram for explaining the setup time and the hold time in the first embodiment. In the figure, the period from the predetermined timing Ts before the rising edge of the clock signal CK to the rising timing Tr of the clock signal CK is a period during which the change of the data signal is prohibited. Further, the change of data is also prohibited during the period from the rising timing Tr to the subsequent predetermined timing Te. The period from Ts to Tr is called the setup time, and the period from Tr to Te is called the hold time.

If the value of the data signal changes during these setup times or hold times, the flip-flop fails to capture the data and its output becomes a metastable. At this time, the phase detector 320 malfunctions.

FIG. 8 is a timing chart showing an example of signals before and after the phase shift in the first embodiment. In the figure, a is a timing chart showing an example of fluctuations in the data signal DATA before the phase shift, the clock signal CK, and the voltage signal _VRJ . As illustrated in a in the figure, a data signal DATA such as "1010 ..." is input from the communication interface 210 in binary notation. Further, the voltage value of the voltage signal _VRJ fluctuates randomly.

Further, the phase of the clock signal CK is controlled based on the phase difference between the data signal DATA and the clock signal CK. For example, assuming that the duty ratio of the clock signal CK is halved, the phase of the rising edge of the clock signal CK is controlled (locked) at a position (T14, etc.) of 0.5 UI (Unit Interval) from the rising edge of the data signal DATA. Will be done. Here, the UI is the time for transferring 1 bit, and if the transfer speed of the data signal DATA is 10 Gbps (Giga Bit per second), it is 100 picoseconds (ps). By this control, the phase of the falling edge of the clock signal CK is controlled at a timing that substantially coincides with the rising edge of the data signal DATA.

FIG. 8B is a timing chart showing an example of fluctuations between the data signal DATA after the phase shift and the clock signal CK. The variable delay element 400, over a delay time corresponding to the voltage value of the voltage signal V _RJ, delaying the data signal DATA. As a result, the timings of the rising edge and the falling edge of the data signal DATA are randomly changed. In other words, jitter is superimposed on the data signal DATA.

FIG. 9 is a diagram showing an example of the phase characteristics of the data signal DATA and the clock signal CK according to the first embodiment. In the figure, a is a timing chart showing an example of fluctuations between the data signal DATA after the phase shift and the clock signal CK.

As described above, the falling edge of the clock signal CK is locked to the rising and falling edges of the data signal DATA. Therefore, in the pre-stage flip-flop 324 that holds the data signal DATA in synchronization with the falling edge of the clock signal, the value of the data signal DATA may change within the period of the hold time or the setup time. In this case, the pre-stage flip-flop 324 fails to capture the data signal DATA, resulting in an error. This error is called a setup time violation error or a hold time violation error.

In order to suppress the occurrence of such an error, in the present embodiment, the variable delay element 400 randomly changes each of the rising edge and the falling edge of the data signal DATA and supplies the data signal to the pre-stage flip-flop 324. This reduces the probability that the edge of the data signal DATA will fall within the setup time or holdup time period. As a result, the probability that the pre-stage flip-flop 324 fails to capture the data signal DATA is reduced.

The data signal DATA held in the first-stage flip-flop 324 is not supplied to the subsequent-stage data processing unit 220 as a recovered signal, so even if jitter is superimposed on the data signal DATA, it is processed in the subsequent-stage. No problem arises.

On the other hand, since jitter is not superimposed on the data signal held by the flip-flops other than the front-stage flip-flop 324 (such as the front-stage flip-flop 323), the recovered data signal is supplied to the rear-stage data processing unit 220.

The flip-flops other than the pre-stage flip-flop 324 hold the data signal DATA in synchronization with the rising edge of the clock signal CK. Here, as described above, since the phase of the rising edge of the clock signal CK is locked at the position of 0.5 UI from the rising edge of the data signal DATA, the data signal DATA does not fluctuate during setup or hold-up. Therefore, it is not necessary to randomly delay the signals to those flip-flops.

FIG. 9B is a graph showing an example of the phase characteristics of the data signal DATA and the clock signal CK. In the figure, the vertical axis of b indicates the phase of the rising edge and the falling edge of the signal, and the horizontal axis represents time. Further, the circle b in the figure indicates the phase of the data signal DATA, and the triangle mark indicates the phase of the clock signal CK. The line segments with arrows at both ends indicate the total period of the setup time and hold time of the pre-stage flip-flop 324 synchronized with the falling edge of the clock signal CK.

While the phase of the clock signal CK is constant, the phase of the data signal DATA fluctuates randomly. This makes it possible to reduce the probability that a setup time violation error or a hold time violation error will occur in the pre-stage flip-flop 324. For example, at the timing T21, the phase of the data signal DATA is within the setup time or hold time period, but at other timings T22 and the like, the phase is out of that period, and the occurrence of an error is suppressed.

FIG. 10 is a diagram showing an example of the phase characteristics of the data signal DATA and the clock signal CK in the comparative example. In the figure, a is a timing chart showing an example of fluctuations between the data signal DATA after the phase shift and the clock signal CK. In this comparative example, it is assumed that the phase of the data signal DATA does not fluctuate randomly.

FIG. 10B is a graph showing an example of the phase characteristics of the data signal DATA and the clock signal CK. In the figure, the vertical axis of b indicates the phase of the rising edge and the falling edge of the signal, and the horizontal axis represents time. Further, the circle b in the figure indicates the phase of the data signal DATA, and the triangle mark indicates the phase of the clock signal CK. The line segments with arrows at both ends indicate the total period of the flip-flop setup time and hold time synchronized with the falling edge of the clock signal CK.

In the comparative example, since the phase of the data signal DATA is constant, the data signal DATA changes within the setup time or the hold time, and the acquisition of the data signal DATA fails. As a result, the phase detector 320 malfunctions, making it impossible to detect an accurate phase difference. Therefore, in the comparative example, the phase of the clock signal is locked at a position slightly deviated from the ideal position so that the edge of the data signal does not enter within the setup time and the hold time.

As described above, in the comparative example in which the data signal DATA is not randomly delayed, the flip flop fails to capture the data signal, whereas the phase detector 320 in which the data signal DATA is randomly delayed fails to capture the data. The probability of doing is low.

FIG. 11 is a timing chart showing an example of the operation of the phase detector 320 according to the first embodiment. The pre-stage flip-flop 323 holds the data signal DATA in synchronization with the rising edge (timing T11 or the like) of the clock signal CK and outputs it as an internal signal Q1. Further, the subsequent flip-flop 325 holds the internal signal Q1 in synchronization with the rising edge (timing T13 or the like) of the clock signal CK and outputs it as the internal signal Q2.

Further, the front-stage flip-flop 324 holds the data signal DATA in synchronization with the falling edge (timing T12, T14, etc.) of the clock signal CK and outputs it as the internal signal Q3. Further, the subsequent flip-flop 326 holds the internal signal Q3 in synchronization with the rising edge (timing T13 or the like) of the clock signal CK and outputs it as the internal signal Q4.

Then, the XOR gate 327 outputs the exclusive OR of the internal signals Q1 and Q4 as the detection signal DN, and the XOR gate 328 outputs the exclusive OR of the internal signals Q2 and Q4 as the detection signal DN.

Based on these detection signals DN and UP, the digital arithmetic circuit 330 controls to match the phase of the falling edge of the clock signal CK with the rising edge of the data signal DATA. In this case, in the front-stage flip-flop 324 that operates in synchronization with the falling edge of the clock signal CK, a setup time violation error or a hold time violation error may occur. However, since the variable delay element 400 randomly delays the data signal DATA, the probability that a setup time violation error or a hold time violation error occurs can be reduced as compared with the case where the data signal DATA is not randomly delayed.

The clock data recovery circuit 300 described above uses a full-rate method for reproducing a clock signal CK having the same clock rate as the data rate of the data signal DATA. However, as will be described later, a half-rate method for reproducing a clock signal CK having a clock rate that is half the data rate may be used. Further, a quarter rate method for reproducing CK with a clock signal having a clock rate of 1/4 of the data rate may be used.

FIG. 12 is a graph showing an example of the relationship between the input phase difference and the output phase difference between the first embodiment and the comparative example. FIG. A in the figure is a graph showing an example of the relationship between the input phase difference and the output phase difference in the first embodiment. In the figure, the horizontal axis of a indicates the phase difference (input phase difference) of the data signal DATA and the clock signal CK, and the vertical axis indicates the phase difference (output phase difference) of the detection signals UP and DN. When the input phase difference is within a certain range near 0 degrees, an output phase difference proportional to the input phase difference can be obtained. Here, the output phase difference indicates an average value when detected over a certain number of times. On the other hand, outside the fixed range, the output phase difference is 180 degrees or −180 degrees.

FIG. B in the figure is a graph showing an example of the relationship between the input phase difference and the output phase difference in the comparative example in which the data signal DATA is not randomly delayed. The shaded portion of b in the figure indicates a region of the input phase difference in which the output phase difference becomes an indefinite value and an accurate phase difference cannot be detected. This area is called the dead zone. The output phase difference becomes an indefinite value in the dead zone because a setup time violation error or a hold time violation error occurs in this region and the output of the flip-flop becomes a metastable.

As described above, in the comparative example in which the data signal DATA is not randomly delayed, a dead zone is generated, whereas in the phase detector 320 in which the data signal DATA is randomly delayed, no dead thorn is generated and the phase difference is accurate. Can be detected.

FIG. 13 is a flowchart showing an example of the operation of the clock data recovery circuit 300 according to the first embodiment. This operation is started, for example, when the data signal DATA is input from the communication interface 210.

The random jitter generator 350 generates a voltage signal V _RJ of a random value (step S901), and the phase detector 320 shifts the phase of the data signal DATA according to the value of the voltage signal V _RJ (step S902). .. Then, the phase detector 320 detects the phase difference between the data signal DATA and the clock signal CK (step S903), and the digital arithmetic circuit 330 generates a control signal based on the phase difference (step S904). Then, the oscillation circuit 340 generates a clock signal CK according to the control signal (step S905). After step S905, the clock data recovery circuit 300 repeatedly executes step S901 and subsequent steps.

As described above, according to the first embodiment of the present technology, since the data signal delayed over a random delay time is held in synchronization with the clock signal, a setup time violation error or a hold time violation error occurs. Occurrence can be suppressed. By reducing the occurrence rate of these errors, it is possible to prevent the phase detector 320 from malfunctioning.

[First modification]
In the first embodiment described above, the data signal DATA is delayed by a random delay time (in other words, jitter is superimposed). A similar effect can be achieved by delaying the clock signal with a random delay time (in other words, superimposing jitter). The phase detector 320 in the first modification of the first embodiment is different from the first embodiment in that jitter is not superimposed on the data signal DATA.

FIG. 14 is a circuit diagram showing a configuration example of the phase detector 320 in the first modification of the first embodiment. The phase detector 320 in this first modification differs from the first embodiment in that it further includes fixed delay elements 322, 329, 411, and 412.

The fixed delay element 322 delays the data signal DATA over a fixed delay time. The fixed delay element 322 supplies the delayed data signal DATA to the pre-stage flip-flop 324.

The fixed delay element 329 delays the clock signal CK over a fixed delay time. The delay time of the fixed delay element 329 is set to, for example, the average value of the delay times of the variable delay element 400. The fixed delay element 329 supplies the delayed clock signal CK to the front flip-flop 323.

The fixed delay element 411 delays the clock signal CK over a fixed delay time. The fixed delay element 411 supplies the delayed clock signal CK to the subsequent flip-flop 325.

The fixed delay element 412 delays the clock signal CK over a fixed delay time. The fixed delay element 412 supplies the delayed clock signal CK to the subsequent flip-flop 326.

Further, the variable delay element 400 of the first modification of the first embodiment is different from the first embodiment in that the clock signal CK is delayed and supplied to the pre-stage flip-flop 324. By randomly delaying the clock signal CK, it is possible to reduce the probability that the edge of the data signal will be included in the setup time or the hold time in the pre-stage flip-flop 324 that operates in synchronization with the clock signal CK. As a result, the probability of a setup time violation error or a hold time violation error can be reduced.

As described above, according to the first modification of the first embodiment of the present technology, since the clock signal CK is delayed over a random delay time, the synchronization circuit is performed without superimposing jitter on the data signal. It is possible to prevent the malfunction of.

[Second variant]
In the first embodiment described above, only the data signal DATA is delayed with a random delay time, but delaying the clock signal with a random delay time is more effective in suppressing malfunction. The phase detector 320 in the second modification of this first embodiment differs from the first embodiment in that both the data signal DATA and the clock signal CK are delayed by a random delay time.

FIG. 15 is a circuit diagram showing a configuration example of the phase detector 320 in the second modification of the first embodiment. The phase detector 320 in this second modification is different from the first embodiment in that it further includes fixed delay elements 322, 329, 411 and 412, and variable delay elements 400 and 410. Further, the random jitter generator 310 of the second modification supplies voltage signals _VRJC and _VRJD of random values to the variable delay elements 400 and 410.

The fixed delay element 329 delays the clock signal CK over a fixed delay time. The fixed delay element 329 supplies the delayed clock signal CK to the front flip-flop 323.

Further, the delay time of the fixed delay element 321 is set to, for example, the average value of the delay times of the variable delay element 400. The delay time of the fixed delay element 329 is set to, for example, the average value of the delay times of the variable delay element 410.

The fixed delay element 411 delays the clock signal CK over a fixed delay time. The fixed delay element 411 supplies the delayed clock signal CK to the subsequent flip-flop 325.

The fixed delay element 412 delays the clock signal CK over a fixed delay time. The fixed delay element 412 supplies the delayed clock signal CK to the subsequent flip-flop 326.

The variable delay element 400 delays the data signal DATA over a random delay time and supplies it to the pre-stage flip-flop 324. The variable delay element 410 delays the clock signal CK over a random delay time and supplies it to the pre-stage flip-flop 324.

As described above, according to the second modification of the first embodiment of the present technology, both the data signal DATA and the clock signal CK are delayed over a random delay time, so that malfunction of the synchronization circuit is prevented. The effect of the clock can be increased.

[Third variant]
In the first embodiment described above, the digital arithmetic circuit 330 controls the delay time by adjusting the electric capacity of the variable capacitance 405 in the variable delay element 400. However, the parameter to be adjusted is not limited to the electric capacity as long as the delay time can be controlled. For example, the bias current supplied to the transistor may be adjusted. The phase detector 320 in the third modification of the first embodiment is different from the first embodiment in that the delay time is controlled by adjusting the bias current supplied to the transistor.

FIG. 16 is a circuit diagram showing a configuration example of the variable delay element 420 in the third modification of the first embodiment. The variable delay element 420 is arranged in place of the variable delay element 400 in the phase detector 320.

Further, the variable delay element 420 has the same configuration as the variable delay element 400 of the first embodiment except that the variable current sources 421 and 422 are provided instead of the variable capacitance 405. The variable current source 421 is inserted between the source of the P-type transistor 401 and the power supply terminal. Further, the variable current source 422 is inserted between the source of the N-type transistor 402 and the ground terminal. For example, MOS transistors are used as the variable current sources 421 and 422.

Further, the random jitter generator 310 of the third modification supplies voltage signals V _RJN and V _RJP of random values to the variable current sources 421 and 422.

Further, the variable current source 421 supplies a bias current having a current value corresponding to the voltage signal _VRJP (that is, at random). The variable current source 422 supplies a bias current having a current value corresponding to the voltage signal _VRJN .

The switching speeds of the P-type transistor 401 and the N-type transistor 402 change according to the bias currents from the variable current sources 421 and 422. Therefore, the random jitter generator 310 can control the delay time of the data signal DATA by adjusting its bias current.

As described above, according to the third modification of the first embodiment of the present technology, the variable capacitance 405 is used to control the delay time of the data signal DATA by adjusting the bias currents from the variable current sources 421 and 422. The delay time can be controlled without using it.

[Fourth variant]
In the first embodiment described above, the random jitter generator 310 controls the delay time of the data signal DATA by the analog voltage signal _VRJ , but it can also control the delay time of the data signal DATA by the digital signal. it can. The random jitter generator in this fourth modification differs from the first embodiment in that the delay time is controlled by a digital control signal.

FIG. 17 is a block diagram showing a configuration example of the clock data recovery circuit 300 in the fourth modification of the first embodiment. The clock data recovery circuit 300 of the fourth modification is different from the first embodiment in that the random jitter generator 350 is provided instead of the random jitter generator 310.

The random jitter generator 350 generates a digital control signal _DRJ indicating a random number instead of the analog voltage signal _VRJ . The random jitter generator 350 generates a control signal _DRJ by, for example, a linear feedback shift register. The random jitter generator 350 does not have a linear feedback register, and may generate a control signal _DRJ using an algorithm that generates pseudo-random numbers, such as a linear congruential method.

FIG. 18 is a circuit diagram showing a configuration example of the variable delay element 430 in the fourth modification of the first embodiment. The variable delay element 430 is arranged in place of the variable delay element 400 in the phase detector 320.

The variable delay element 430 is the same as the variable delay element 400 of the first embodiment, except that each includes a plurality of sets including a switch 431 and a fixed capacitance 432 instead of the variable capacitance 405.

One end of each of the plurality of switches 431 is commonly connected to the drain of the P-type transistor 401 and the N-type transistor 402, and the other end is connected to the corresponding fixed capacitance 432.

The fixed capacity 432 is a capacity having a constant electric capacity. The switch 431 opens and closes the path between the corresponding fixed capacitance 432 and the drains of the P-type transistor 401 and the N-type transistor 402 according to the control signal _DRJ . The number of bits of this control signal _DRJ is equal to or greater than the number of switches 431, and each of the bits is supplied to switches 431 that are different from each other.

The construction described above, the switch 431 is opened and closed the combined capacity of the plurality of fixed volume 432 changes randomly in accordance with the random value of the control signal D _RJ. Then, the data signal DATA is delayed and output for a delay time corresponding to the random combined capacitance.

As described above, according to the fourth modification of the first embodiment of the present technology, the random jitter generator 350 adjusts the combined capacitance of the fixed capacitance 432 by the digital control signal _DRJ, so that the analog voltage The delay time can be controlled without using the signal _VRJ .

[Fifth variant]
In the fourth modification of the first embodiment described above, the delay time is controlled by adjusting the combined capacitance of the fixed capacitance 432 in the variable delay element 430. However, the parameters to be adjusted are not limited to the combined capacitance as long as the delay time can be controlled. For example, the bias current supplied to the transistor may be adjusted. The phase detector 320 in the fifth modification of the first embodiment is different from the fourth modification in that the delay time is controlled by adjusting the bias current supplied to the transistor.

Also, random jitter generator 350 of the fifth modified example, provides a digital control signal _{D RJN} and _{D RJP} indicating a predetermined random number to the variable delay elements 400 and 410.

FIG. 19 is a circuit diagram showing a configuration example of the variable delay element 440 in the fifth modification of the first embodiment. The variable delay element 440 of the fifth modification of the first embodiment is the fourth except that the switches 441 and 443 and the fixed current sources 442 and 444 are provided instead of the switch 431 and the fixed capacitance 432. It is the same as the modification.

A plurality of sets, each consisting of a switch 441 and a fixed current source 442, are provided. Further, a plurality of sets each consisting of the switch 443 and the fixed current source 444 are also provided. One end of each of the plurality of switches 441 is commonly connected to the power supply terminal, and the other end is connected to the corresponding fixed current source 442. Further, one end of each of the plurality of switches 443 is commonly connected to the source of the N-type transistor 402, and the other end is connected to the corresponding fixed current source 444.

Each output terminal of the plurality of fixed current sources 442 is commonly connected to the source of the P-type transistor 401. Further, each output terminal of the plurality of fixed current sources 444 is connected to a ground terminal.

The fixed current sources 442 and 444 supply a constant bias current. The switch 441 opens and closes the path between the corresponding fixed current source 442 and the power supply terminal according to the control signal _DRJP . Further, the switch 443 opens and closes the path between the corresponding fixed current source 444 and the source of the N-type transistor 402 according to the control signal _DRJN .

The switching speeds of the P-type transistor 401 and the N-type transistor 402 change according to the sum of the bias currents from the fixed current sources 442 and 444. Therefore, the random jitter generator 350 can control the delay time of the data signal DATA by adjusting their bias currents.

As described above, according to the fifth modification of the first embodiment of the present technology, the combined capacitance is used to control the delay time of the data signal DATA by adjusting the bias currents from the fixed current sources 442 and 444. The delay time can be controlled without.

<2. Second Embodiment>
In the above-described first embodiment, the variable delay element 400 having a random delay time is provided in the phase interpolation type clock data recovery circuit 300, but the variable delay element 400 is provided in the clock data recovery circuit of a method other than the phase interpolation type. A delay element may be provided. For example, a variable delay element can be provided in an injection type clock data recovery circuit that detects an edge of a data signal. The clock data recovery circuit 300 of the second embodiment is different from the first embodiment in that it is an injection type.

FIG. 20 is a block diagram showing a configuration example of the clock data recovery circuit 300 according to the second embodiment. The clock data recovery circuit 300 of the second embodiment includes a delay unit 360, a holding unit 370, a digital arithmetic circuit 380, and an edge detection circuit 390 in place of the phase detector 320 and the digital arithmetic circuit 330. It is different from the embodiment of 1. Further, the clock data recovery circuit 300 of the second embodiment is different from the first embodiment in that the oscillation circuit 345 is provided instead of the oscillation circuit 340.

The delay unit 360 generates a data signal DATA delayed over a random delay time and a data signal DATA delayed over a fixed delay time. The delay unit 360 further delays those signals over the delay time indicated by the control signal P _control . Then, the delay unit 360 supplies the data signal on which the jitter is superimposed due to the random delay time as the edge data ED, and the data signal on the other side as the recovery data RD to the holding unit 370.

The holding unit 370 holds the edge data ED and the recovery data RD in synchronization with the clock signal CK, and outputs the held signals as the edge data E_DATA and the recovery data R_DATA. The edge data E_DATA is input to the digital arithmetic circuit 380, and the recovery data R_DATA is input to the digital arithmetic circuit 380 and the data processing unit 220.

The digital arithmetic circuit 380 generates a control signal P _control for controlling the phase of the data signal and a control signal F _control for controlling the frequency of the clock signal CK based on the edge data E_DATA and the recovery data R_DATA. Is. The digital arithmetic circuit 380 supplies the control signal P _control to the delay unit 360, and supplies the control signal F _control to the oscillation circuit 345.

The edge detection circuit 390 detects the edge of the data signal DATA. The edge detection circuit 390 detects both the rising edge and the falling edge of the data signal DATA, generates a pulse signal INJ, and supplies the pulse signal INJ to the oscillation circuit 345. For example, the edge detection circuit 390 sets the pulse signal INJ to a low level when the edge is not detected, and sets the pulse signal INJ to a high level for a certain period (for example, 0.5 UI) when the edge is detected. To do.

The oscillation circuit 345 generates a clock signal CK in synchronization with the pulse signal INJ. The oscillation circuit 345 controls the frequency of the clock signal CK according to the control signal F _control and supplies it to the holding unit 370, the digital arithmetic circuit 380, and the data processing unit 220.

FIG. 21 is a circuit diagram showing a configuration example of the delay unit 360 and the holding unit 370 according to the second embodiment. The delay unit 360 includes variable delay elements 361, 362 and 364 and a fixed delay element 363. In addition, the holding unit 370 includes flip-flops 371 and 372.

The variable delay element 361 delays the data signal DATA over a delay time corresponding to the value of the voltage signal _VRJ (that is, at random). The configuration of the variable delay element 361 is the same as that of the variable delay element 400 of the first embodiment. The variable delay element 361 supplies the delayed signal to the variable delay element 362.

The fixed delay element 363 delays the data signal DATA over a fixed delay time. The delay time of the fixed delay element 363 is set to, for example, the average value of the delay times of the variable delay element 361. The fixed delay element 363 supplies the delayed signal to the variable delay element 364.

The variable delay element 362 delays the signal from the variable delay element 361 for a delay time corresponding to the value of the control signal P _control . The variable delay element 362 supplies the delayed signal as a data signal ED to the flip-flop 371.

The variable delay element 364 delays the signal from the fixed delay element 363 for a delay time corresponding to the value of the control signal P _control . The variable delay element 364 supplies the delayed signal to the flip-flop 372 as a data signal RD.

The circuit including the variable delay elements 362 and 364 is an example of the variable delay circuit described in the claims.

The flip-flop 371 holds the edge data ED in synchronization with the falling edge of the clock signal CK. The flip-flop 371 supplies the held signal as edge data E_DATA to the digital arithmetic circuit 380.

The flip-flop 372 holds the recovery data RD in synchronization with the rising edge of the clock signal CK. The flip-flop 372 supplies the held signal as recovery data R_DATA to the digital arithmetic circuit 380.

FIG. 22 is a circuit diagram showing a configuration example of the oscillation circuit 345 according to the second embodiment. The oscillation circuit 345 includes an odd number (for example, 5) of inverters 346 and an AND (logical product) gate. These inverters 346 are connected in series between the input terminal and the output terminal of the AND gate.

The inverter 346 inverts the signal and delays it over a delay time according to the value of the control signal F _control .

The AND gate 347 outputs the logical product of the signal from the inverter 346 and the pulse signal INJ as a clock signal CK. The AND gate 347 supplies the clock signal CK to any input terminal of the inverter 346, the holding unit 370, the digital arithmetic circuit 380, and the data processing unit 220.

FIG. 23 is a block diagram showing a configuration example of the digital arithmetic circuit 380 according to the second embodiment. The digital arithmetic circuit 380 includes an edge detection circuit 381, a phase comparison circuit 382, a phase determination circuit 383, a frequency determination circuit 384, an integration circuit 385, and an integration circuit 386.

The edge detection circuit 381 detects the rising edge and the falling edge of the recovery data R_DATA based on the clock signal CK and the recovery data R_DATA. The edge detection circuit 381 generates a detection signal SE that becomes effective when those edges are detected and supplies the detection signal SE to the phase determination circuit 383 and the frequency determination circuit 384.

The phase comparison circuit 382 determines whether the phase of the clock signal CK is advanced or delayed based on the recovery data R_DATA and E_DATA and the clock signal CK, and generates the phase comparison signal SP. The phase comparison circuit 382 sets, for example, "1" in the phase comparison signal SP when the phase is advanced, and sets "0" when the phase is delayed. Then, the phase comparison circuit 382 supplies the phase comparison signal SP to the phase determination circuit 383 and the frequency determination circuit 384.

The phase determination circuit 383 determines whether to advance or delay the phase of the clock signal CK based on the detection signal SE, the phase comparison signal SP, and the clock signal CK, and generates a control signal SIGP for controlling the phase. Is. For example, the phase determination circuit 383 sets “+1” in the control signal SIGP when it determines that the phase of the clock signal CK should be advanced, and “-1” in the control signal SIGP when it determines that the phase should be delayed. To set. Further, the phase determination circuit 383 sets "0" in the control signal SIGP when it is determined that the phase of the clock signal CK should be maintained as it is. The phase determination circuit 383 supplies the control signal SIGP to the integration circuit 385.

The frequency determination circuit 384 determines whether to raise or lower the frequency of the clock signal CK based on the detection signal SE, the phase comparison signal SP, and the clock signal CK, and generates a control signal SIGF for controlling the frequency. Is what you do. For example, the frequency determination circuit 384 sets "+1" in the control signal SIGF when it determines that the frequency of the clock signal CK should be increased, and sets "-" in the control signal SIGF when it determines that the frequency should be decreased. 1 ”is set. Further, the frequency determination circuit 384 sets "0" in the control signal SIGF when it is determined that the frequency of the clock signal CK should be maintained as it is. The frequency determination circuit 384 supplies the control signal SIGF to the integration circuit 386.

The integrating circuit 385 integrates the value of the control signal SIGP. The integrating circuit 385 supplies a digital signal indicating the integrated value to the delay unit 360 as a control signal P _control . The integrating circuit 386 integrates the value of the control signal SIGF. The integrating circuit 386 supplies a digital signal indicating the integrated value to the oscillation circuit 345 as a control signal F _control .

FIG. 24 is a timing chart showing an example of the operation of the delay unit 360 according to the second embodiment. In the delay unit 360, the variable delay element 361 delays the data signal DATA over a random delay time and outputs it as edge data ED. Since the delay time is random, the rising edge and falling edge of the edge data ED fluctuate randomly, and jitter is superimposed on the data signal.

Further, the edge data ED is held in synchronization with the timings T21 and T23 of the falling edge of the clock signal. Since the edge data ED transitions randomly at those timings, the probability of a setup violation error or a hold time violation error can be reduced.

On the other hand, the fixed delay element 363 delays the data signal DATA over a certain delay time and outputs it as recovery data RD. Since the delay time is constant, the rising edge and falling edge of the recovery data RD do not fluctuate randomly.

Further, the recovery data RD is held in synchronization with the timings T22 and T24 of the rising edge of the clock signal. Since the recovery data RD does not transition at those timings, no setup violation error or hold time violation error occurs even if jitter is not superimposed on the data signal RD. Then, the recovery data RD on which the jitter is not superimposed is supplied to the data processing unit 220 as recovered data.

As described above, according to the second embodiment of the present technology, the data signal delayed over a random delay time is held in synchronization with the clock signal in the injection type clock data recovery circuit, so that an error occurs. The incidence can be reduced.

<3. Third Embodiment>
In the first embodiment described above, the random jitter generator 310 generated noise ( _VRJ ) solely from the constant current source 311 and the resistor 312, but in order to generate a large level of noise, a resistor It is necessary to increase the resistance value of 312. If the resistance value is large, the constant current source 311 needs to supply a small current, so that there is a problem that the specifications of the constant current source 311 are restricted. As a countermeasure against this problem, it is desirable to further amplify the signal generated by the constant current source 311 and the resistor 312 by an amplifier. The random jitter generator 310 of the third embodiment is different from the first embodiment in that an amplifier is further provided.

FIG. 25 is a circuit diagram showing a configuration example of the random jitter generator 310 according to the third embodiment. The random jitter generator 310 differs from the first embodiment in that it further includes m (m is an integer) of amplifiers 450. These amplifiers 450 are connected in series. The input terminal of the first stage amplifier 450 is connected to the connection point of the constant current source 311 and the resistor 312. Further, the output terminal of the amplifier 450 in the final stage is connected to the phase detector 320.

The amplifier 450 amplifies the input signal. Assuming that the gain of each amplifier 450 is Kv, the voltage Vnoise of the signal output from the final stage of m amplifiers 450 is expressed by the following equation.
Vnoise = Kv ^m・ (2kRT ・ Δf) ^1/2

Actually, the device noise in the amplifier 450 and the noise of the load resistance are added, but in the above equation, it is assumed that they can be ignored.

FIG. 26 is a circuit diagram showing a configuration example of the amplifier 450 according to the third embodiment. The amplifier 450 includes a constant current source 451, N-type transistors 451 and 456, a fixed capacitance 453, and resistors 454 and 455. As the N-type transistors 451 and 456, for example, MOS transistors are used.

The constant current source 451 and the N-type transistor 452 are connected in series between the power supply terminal and the ground terminal. The gate of the N-type transistor 452 is connected to the connection point of the constant current source 451 and the N-type transistor 452 and one end of the resistor 454. The other end of the resistor 454 is connected to one end of the fixed capacitance 453 and the gate of the N-type transistor 456. The other end of the fixed capacitance 453 is connected to the input terminal IN of the amplifier 450. Further, the resistor 455 and the N-type transistor 456 are connected in series between the power supply terminal and the ground terminal. The connection points of these resistors 455 and N-type transistors 456 are connected to the output terminal OUT of the amplifier 450.

As described above, according to the third embodiment of the present technology, since the random jitter generator 310 amplifies the signal by the amplifier 450, it is possible to generate sufficiently large noise by the resistance having a relatively small resistance value. ..

<4. Fourth Embodiment>
In the second embodiment described above, the clock data recovery circuit 300 uses a full-rate method for reproducing a clock signal CK having the same clock rate as the data rate of the data signal DATA. However, a half-rate method for reproducing a clock signal CK having a clock rate that is 1/2 of the data rate may be used. The clock data recovery circuit 300 of the fourth embodiment is different from the second embodiment in that the clock signal is recovered by the half rate method.

FIG. 27. It is a circuit diagram which shows one structural example of the delay part 360 and the holding part 370 in 4th Embodiment. The holding unit 370 of the fourth embodiment differs from the second embodiment in that it further includes flip-flops 373 and 374. Further, the oscillation circuit 345 of the fourth embodiment is different from the second embodiment in that the clock signals CKI and CKQ having different phases by π / 2 are supplied.

The flip-flop 371 holds the edge data ED in synchronization with the rising edge of the clock signal CKI, and supplies the held signal as edge data E_DATA1 to the digital arithmetic circuit 380. The flip-flop 372 holds the recovery data RD in synchronization with the rising edge of the clock signal CKQ, and supplies the held signal as the recovery data R_DATA1 to the digital arithmetic circuit 380.

Further, the flip-flop 373 holds the edge data ED in synchronization with the falling edge of the clock signal CKI, and supplies the held signal to the digital arithmetic circuit 380 as edge data E_DATA2. The flip-flop 374 holds the recovery data RD in synchronization with the falling edge of the clock signal CKQ, and supplies the held signal as the recovery data R_DATA2 to the digital arithmetic circuit 380.

The digital arithmetic circuit 380 of the fourth embodiment generates the control signal P _control and the control signal F _control based on E_DATA1, R_DATA1, E_DATA2 and R_DATA2. The arithmetic circuit 380 detects that the phase of the clock signal is delayed when there is a data transition and R_DATA1 = E_DATA1 or R_DATA2 = E_DATA2 is satisfied. On the other hand, when R_DATA1 ≠ E_DATA1 or R_DATA2 ≠ E_DATA2 is satisfied, the arithmetic circuit 380 detects that the phase of the clock signal is advanced. The digital arithmetic circuit 380 generates the control signal P _control and the control signal F _control based on the phase detection result.

In addition, the digital arithmetic circuit 380 determines whether or not the data signal has transitioned from two consecutive recovery data. For example, when R_DATA1 ≠ R_DATA2, it is determined that the data signal has transitioned.

FIG. 28 is a timing chart showing an example of the operation of the clock data recovery circuit 300 according to the fourth embodiment. The flip-flop 371 holds the edge data ED in synchronization with the rising edge (timing T31 or the like) of the clock signal CKI, and supplies the signal as the edge data E_DATA1. The flip-flop 372 holds the recovery data RD in synchronization with the rising edge (timing T32, etc.) of the clock signal CKQ, and supplies the signal as the recovery data R_DATA1.

Further, the flip-flop 373 holds the edge data ED in synchronization with the falling edge (timing T33 or the like) of the clock signal CKI, and supplies the signal as the edge data E_DATA2. The flip-flop 374 holds the recovery data RD in synchronization with the falling edge (timing T34 or the like) of the clock signal CKQ, and supplies the signal as the recovery data R_DATA2.

As described above, according to the fourth embodiment of the present technology, in order to retain the randomly delayed edge data ED and recovery data RD in synchronization with the clock signals CKI and CKQ, synchronization is performed in the half rate method. It is possible to prevent a malfunction of the circuit.

<5. Fifth Embodiment>
In the second embodiment described above, the clock data recovery circuit 300 uses a full-rate method for reproducing a clock signal CK having the same clock rate as the data rate of the data signal DATA. However, a quarter rate method for reproducing a clock signal CK having a clock rate of 1/4 of the data rate may be used. The clock data recovery circuit 300 of the fourth embodiment is different from the second embodiment in that the clock signal is recovered by the quarter rate method.

FIG. 29 is. It is a circuit diagram which shows one structural example of the delay part 360 and the holding part 370 in the 5th Embodiment. The holding unit 370 of the fifth embodiment differs from the second embodiment in that it further includes flip-flops 373, 374, 375 and 376. Further, the oscillation circuit 345 of the fourth embodiment is different from the second embodiment in that the clock signals CK1, CK2, CK3 and CK4 having phases different from each other by π / 4 are supplied.

The flip-flop 371 holds the edge data ED in synchronization with the rising edge of the clock signal CK1, and supplies the held signal as the edge data E_DATA1 to the digital arithmetic circuit 380. The flip-flop 372 holds the recovery data RD in synchronization with the rising edge of the clock signal CK2, and supplies the held signal as the recovery data R_DATA1 to the digital arithmetic circuit 380.

The flip-flop 373 holds the edge data ED in synchronization with the rising edge of the clock signal CK3, and supplies the held signal as edge data E_DATA2 to the digital arithmetic circuit 380. The flip-flop 374 holds the recovery data RD in synchronization with the rising edge of the clock signal CK4, and supplies the held signal as the recovery data R_DATA2 to the digital arithmetic circuit 380.

The flip-flop 375 holds the edge data ED in synchronization with the falling edge of the clock signal CK1, and supplies the held signal as edge data E_DATA3 to the digital arithmetic circuit 380. The flip-flop 376 holds the recovery data RD in synchronization with the falling edge of the clock signal CK2, and supplies the held signal as the recovery data R_DATA3 to the digital arithmetic circuit 380.

The flip-flop 377 holds the edge data ED in synchronization with the falling edge of the clock signal CK3, and supplies the held signal as edge data E_DATA4 to the digital arithmetic circuit 380. The flip-flop 378 holds the recovery data RD in synchronization with the falling edge of the clock signal CK4, and supplies the held signal as the recovery data R_DATA4 to the digital arithmetic circuit 380.

The digital arithmetic circuit 380 of the fifth embodiment generates the control signal P _control and the control signal F _control based on E_DATA1, R_DATA1, E_DATA2, R_DATA2, E_DATA3, R_DATA3, E_DATA4 and R_DATA4. The arithmetic circuit 380 detects that the phase of the clock signal is delayed when there is a data transition and R_DATAan = E_DATAan (n is an integer of 1 to 4). On the other hand, when R_DATAan ≠ E_DATAan, the arithmetic circuit 380 detects that the phase of the clock signal is advanced. The digital arithmetic circuit 380 generates the control signal P _control and the control signal F _control based on the phase detection result.

In addition, the digital arithmetic circuit 380 determines whether or not the data signal has transitioned from two consecutive recovery data. For example, when R_DATA2 ≠ R_DATA3, it is determined that the data signal has transitioned.

FIG. 30 is a timing chart showing an example of the operation of the clock data recovery circuit 300 according to the fifth embodiment. The flip-flop 371 holds the edge data ED in synchronization with the rising edge (timing T41 or the like) of the clock signal CK1, and supplies the signal as the edge data E_DATA1. The flip-flop 372 holds the recovery data RD in synchronization with the rising edge (timing T42, etc.) of the clock signal CK2, and supplies the signal as the recovery data R_DATA1.

Further, the flip-flop 373 holds the edge data ED in synchronization with the rising edge (timing T43 or the like) of the clock signal CK3, and supplies the signal as the edge data E_DATA2. The flip-flop 374 holds the recovery data RD in synchronization with the rising edge (timing T44 or the like) of the clock signal CK4, and supplies the signal as the recovery data R_DATA2.

The flip-flop 375 holds the edge data ED in synchronization with the falling edge (timing T45 or the like) of the clock signal CK1, and supplies the signal as the edge data E_DATA3. The flip-flop 376 holds the recovery data RD in synchronization with the falling edge (timing T46 or the like) of the clock signal CK2, and supplies the signal as the recovery data R_DATA3.

Further, the flip-flop 377 holds the edge data ED in synchronization with the falling edge (timing T47 or the like) of the clock signal CK3, and supplies the signal as the edge data E_DATA4. The flip-flop 378 holds the recovery data RD in synchronization with the falling edge (timing T48, etc.) of the clock signal CK4, and supplies the signal as the recovery data R_DATA4.

As described above, according to the fifth embodiment of the present technology, in order to retain the randomly delayed edge data ED and recovery data RD in synchronization with the clock signals CK1 to CK4, the quarter rate method is synchronized. It is possible to prevent a malfunction of the circuit.

The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.

Further, the processing procedure described in the above-described embodiment may be regarded as a method having these series of procedures, and as a program for causing a computer to execute these series of procedures or as a recording medium for storing the program. You may catch it. As this recording medium, for example, a CD (Compact Disc), MD (MiniDisc), DVD (Digital Versatile Disc), memory card, Blu-ray Disc (Blu-ray (registered trademark) Disc) and the like can be used.

The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

The present technology can have the following configurations.
(1) A holding unit that holds an input signal in synchronization with a predetermined periodic signal, and
A synchronization circuit including a variable delay element that delays at least one of the input signal and the predetermined periodic signal over a random delay time and supplies the input signal to the holding unit.
(2) The above-described (1), further comprising a control unit that matches the phase of the input signal with the phase of the predetermined periodic signal by controlling at least one phase of the input signal and the predetermined periodic signal. Synchronous circuit.
(3) The synchronization circuit according to claim 1, further comprising a generator that generates a signal having a random value and supplies the signal to the variable delay element.
(4) The generator is
The synchronous circuit according to (3) above, comprising a constant current source and a resistor connected to the constant current source.
(5) The synchronization circuit according to (4) above, wherein the generator further includes an amplifier that amplifies a signal from the resistor.
(6) The variable delay element is any one of (1) to (5) above, in which at least one of the input signal and the predetermined periodic signal is delayed by a variable capacitance that changes the capacitance according to a random voltage value. Synchronous circuit described in.
(7) The variable delay element is
A variable current source that supplies a bias current with a random current value,
The synchronization circuit according to any one of (1) to (5) above, comprising a transistor that delays at least one of the input signal and the predetermined periodic signal over a delay time corresponding to the supplied bias current. ..
(8) The variable delay element is
Multiple fixed capacities with constant electrical capacity and
Fixed delay element and
The synchronization circuit according to (1) or (2), further comprising a switch for opening and closing a path connecting each of the plurality of fixed capacitances and the fixed delay element according to a digital signal indicating a predetermined random number.
(9) The variable delay element is
With multiple fixed current sources, each supplying a constant bias current,
A transistor that delays at least one of the input signal and the predetermined periodic signal over a delay time corresponding to the sum of the bias currents.
The synchronization circuit according to (1) or (2), further comprising a switch that opens and closes a path connecting each of the plurality of fixed current sources and the transistor according to a digital signal indicating a random number.
(10) The synchronization circuit according to any one of (1) to (9), wherein the variable delay element delays only the input signal over a random delay time.
(11) The synchronization circuit according to any one of (1) to (9) above, wherein the variable delay element delays only the predetermined periodic signal over a random delay time.
(12) The synchronization circuit according to any one of (1) to (9) above, wherein the variable delay element delays both the input signal and the predetermined periodic signal over a random delay time.
(13) A detection unit that detects the phase difference between the input signal and the predetermined periodic signal based on the held input signal, and
It further includes an oscillation circuit that generates the predetermined periodic signal.
The synchronization circuit according to any one of (1) to (12), wherein the control unit controls the oscillation circuit based on the detected phase difference.
(14) The holding portion is
A first front flip-flop that holds the input signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as a first internal signal.
A first subsequent flip-flop that holds the first internal signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as a second internal signal.
A second pre-stage flip-flop that holds the input signal in synchronization with the falling edge of the predetermined periodic signal and supplies the held signal as a third internal signal.
A second rear-stage flip-flop that holds the third internal signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as a fourth internal signal is provided.
The detection unit
A first exclusive OR gate that outputs an exclusive OR of the first internal signal and the fourth internal signal, and
It includes a second exclusive OR gate that outputs an exclusive OR of the second internal signal and the fourth internal signal.
The synchronization circuit according to (13), wherein the variable delay element supplies the delayed signal to the second front flip-flop.
(15) A variable delay circuit for supplying edge data obtained by delaying the input signal over the random input time and recovery data obtained by delaying the input signal over a predetermined delay time and the above. An edge detection circuit that detects the edge of the input signal and
It further includes an oscillation circuit that generates the predetermined periodic signal in synchronization with the timing at which the edge is detected.
The synchronization circuit according to any one of (1) to (12), wherein the arithmetic circuit controls the variable delay circuit and the oscillation circuit based on the held edge data and recovery data.
(16) The predetermined periodic signal includes first and second periodic signals having different phases by π / 2.
The holding part is
A first flip-flop that holds the edge data in synchronization with the rising edge of the first periodic signal and supplies the held signal as the first edge data.
A second flip-flop that holds the recovery data in synchronization with the rising edge of the second periodic signal and supplies the held signal as the first recovery data.
A third flip-flop that holds the edge data in synchronization with the falling edge of the first periodic signal and supplies the held signal as the second edge data.
It includes a fourth flip-flop that holds the recovery data in synchronization with the falling edge of the second periodic signal and supplies the held signal as the second recovery data.
The synchronization circuit according to (15), wherein the arithmetic circuit controls the variable delay circuit and the oscillation circuit based on the first and second edge data and the first and second recovery data.
(17) The predetermined periodic signal includes first, second, third and fourth periodic signals having π / 4 phases different from each other.
The holding part is
A first flip-flop that holds the edge data in synchronization with the rising edge of the first periodic signal and supplies the held signal as the first edge data.
A second flip-flop that holds the recovery data in synchronization with the rising edge of the second periodic signal and supplies the held signal as the first recovery data.
A third flip-flop that holds the edge data in synchronization with the rising edge of the third periodic signal and supplies the held signal as the second edge data.
A fourth flip-flop that retains the recovery data in synchronization with the rising edge of the fourth periodic signal and supplies the retained signal as second recovery data.
A fifth flip-flop that retains the edge data in synchronization with the falling edge of the first periodic signal and supplies the retained signal as third edge data.
A sixth flip-flop that holds the recovery data in synchronization with the falling edge of the second periodic signal and supplies the held signal as the third recovery data.
A seventh flip-flop that holds the edge data in synchronization with the falling edge of the third periodic signal and supplies the held signal as the fourth edge data.
It includes an eighth flip-flop that holds the recovery data in synchronization with the falling edge of the fourth periodic signal and supplies the held signal as the fourth recovery data.
The arithmetic circuit controls the variable delay circuit and the oscillation circuit based on the first, second, third and fourth edge data and the first, second, third and fourth recovery data. The synchronization circuit according to (15) above.
(18) A holding procedure for holding an input signal in synchronization with a predetermined periodic signal, and
A method for controlling a synchronous circuit, comprising a delay procedure in which at least one of the input signal and the predetermined periodic signal is delayed over a random delay time and supplied to the holding unit.

100 Source equipment 200 Electronic equipment 210 Communication interface 220 Data processing unit 300 Clock data recovery circuit 310, 350 Random jitter generator 311, 451 Constant current source 312, 454, 455 Resistor 320 Phase detector 321, 322, 329, 363, 411 412 Fixed delay element 323, 324 Front flip-flop 325, 326 Rear flip-flop 327, 328 XOR (exclusive logical sum) Gate 330, 380 Digital arithmetic circuit 340, 345 Oscillation circuit 341 Selector 342, 346 Inverter 347 AND (logical product) ) Gate 360 Delay part 361, 362, 364, 400, 410, 420, 430, 440 Variable delay element 370 Holding part 371, 372, 373, 374, 375, 376, 377, 378 Flip-flop 381, 390 Edge detection circuit 382 Phase comparison circuit 383 Phase determination circuit 384 Frequency determination circuit 385, 386 Integrator circuit 401, 403 P-type transistor 402, 404, 452, 456 N-type transistor 405 Variable capacitance 421, 422 Variable current source 431, 441, 443 Switch 432, 453 Fixed capacity 442, 444 Fixed current source 450 amplifier

Claims (16)

A holding unit that holds the input signal in synchronization with a predetermined periodic signal,
A variable delay element that delays at least one of the input signal and the predetermined periodic signal over a random delay time and supplies the input signal to the holding unit.
A detection unit that detects the phase difference between the input signal and the predetermined periodic signal based on the held input signal, and
An oscillator circuit that generates the predetermined periodic signal and
A data processing unit that captures and processes a first internal signal in synchronization with the predetermined periodic signal.
A control unit that controls the oscillation circuit based on the detected phase difference is provided.
The holding part is
A first front flip-flop that holds the input signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as the first internal signal.
A first subsequent flip-flop that holds the first internal signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as a second internal signal.
A second front flip-flop that holds the input signal in synchronization with the falling edge of the predetermined periodic signal and supplies the held signal as a third internal signal.
A second rear-stage flip-flop that holds the third internal signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as a fourth internal signal is provided.
The detection unit
A first exclusive OR gate that outputs an exclusive OR of the first internal signal and the fourth internal signal, and
It includes a second exclusive OR gate that outputs an exclusive OR of the second internal signal and the fourth internal signal.
The variable delay element is a synchronization circuit that supplies the delayed signal to the second front flip-flop. The synchronization circuit according to claim 1, further comprising a control unit that matches the phase of the input signal with the phase of the predetermined periodic signal by controlling the phase of at least one of the input signal and the predetermined periodic signal. The synchronization circuit according to claim 1, further comprising a generator that generates a signal having a random value and supplies the signal to the variable delay element. The generator
The synchronization circuit according to claim 3, further comprising a constant current source and a resistor connected to the constant current source. The synchronization circuit according to claim 4, wherein the generator further includes an amplifier that amplifies a signal from the resistor. The synchronization circuit according to claim 1, wherein the variable delay element delays at least one of the input signal and the predetermined periodic signal by a variable capacitance that changes the capacitance according to a random voltage value. The variable delay element is
A variable current source that supplies a bias current with a random current value,
The synchronization circuit according to claim 1, further comprising a transistor that delays at least one of the input signal and the predetermined periodic signal over a delay time corresponding to the supplied bias current. The variable delay element is
Multiple fixed capacities with constant electrical capacity and
Fixed delay element and
The synchronization circuit according to claim 1, further comprising a switch that opens and closes a path connecting each of the plurality of fixed capacitances and the fixed delay element according to a digital signal indicating a predetermined random number. The variable delay element is
With multiple fixed current sources, each supplying a constant bias current,
A transistor that delays at least one of the input signal and the predetermined periodic signal over a delay time corresponding to the sum of the bias currents.
The synchronization circuit according to claim 1, further comprising a switch that opens and closes a path connecting each of the plurality of fixed current sources and the transistor according to a digital signal indicating a random number. The synchronization circuit according to claim 1, wherein the variable delay element delays only the input signal over a random delay time. The synchronization circuit according to claim 1, wherein the variable delay element delays only the predetermined periodic signal over a random delay time. The synchronization circuit according to claim 1, wherein the variable delay element delays both the input signal and the predetermined periodic signal over a random delay time. A holding unit that holds the input signal in synchronization with a predetermined periodic signal,
A variable delay element that delays at least one of the input signal and the predetermined periodic signal over a random delay time and supplies the input signal to the holding unit.
A variable delay circuit that supplies edge data obtained by delaying the input signal over the random input time and recovery data obtained by delaying the input signal over a predetermined delay time to the holding unit.
An edge detection circuit that detects the edge of the input signal and
An oscillator circuit that generates the predetermined periodic signal in synchronization with the timing at which the edge is detected, and
A synchronization circuit including the variable delay circuit and an arithmetic circuit that controls the oscillation circuit based on the held edge data and recovery data. The predetermined periodic signal includes first and second periodic signals having different phases by π / 2.
The holding part is
A first flip-flop that holds the edge data in synchronization with the rising edge of the first periodic signal and supplies the held signal as the first edge data.
A second flip-flop that holds the recovery data in synchronization with the rising edge of the second periodic signal and supplies the held signal as the first recovery data.
A third flip-flop that holds the edge data in synchronization with the falling edge of the first periodic signal and supplies the held signal as the second edge data.
It includes a fourth flip-flop that holds the recovery data in synchronization with the falling edge of the second periodic signal and supplies the held signal as the second recovery data.
The synchronization circuit according to claim 13, wherein the arithmetic circuit controls the variable delay circuit and the oscillation circuit based on the first and second edge data and the first and second recovery data. The predetermined periodic signal includes first, second, third and fourth periodic signals having π / 4 phases different from each other.
The holding part is
A first flip-flop that holds the edge data in synchronization with the rising edge of the first periodic signal and supplies the held signal as the first edge data.
A second flip-flop that holds the recovery data in synchronization with the rising edge of the second periodic signal and supplies the held signal as the first recovery data.
A third flip-flop that holds the edge data in synchronization with the rising edge of the third periodic signal and supplies the held signal as the second edge data.
A fourth flip-flop that retains the recovery data in synchronization with the rising edge of the fourth periodic signal and supplies the retained signal as second recovery data.
A fifth flip-flop that retains the edge data in synchronization with the falling edge of the first periodic signal and supplies the retained signal as third edge data.
A sixth flip-flop that holds the recovery data in synchronization with the falling edge of the second periodic signal and supplies the held signal as the third recovery data.
A seventh flip-flop that holds the edge data in synchronization with the falling edge of the third periodic signal and supplies the held signal as the fourth edge data.
It includes an eighth flip-flop that holds the recovery data in synchronization with the falling edge of the fourth periodic signal and supplies the held signal as the fourth recovery data.
The arithmetic circuit controls the variable delay circuit and the oscillation circuit based on the first, second, third and fourth edge data and the first, second, third and fourth recovery data. 13. The synchronization circuit according to claim 13. A holding procedure in which the holding unit holds the input signal in synchronization with a predetermined periodic signal,
A delay procedure in which the variable delay element delays at least one of the input signal and the predetermined periodic signal over a random delay time and supplies it to the holding unit.
A detection procedure in which the detection unit detects the phase difference between the input signal and the predetermined periodic signal based on the held input signal.
The procedure in which the oscillator circuit generates the predetermined periodic signal, and
A data processing unit that captures and processes a first internal signal in synchronization with the predetermined periodic signal.
It includes a control procedure for controlling the oscillation circuit based on the detected phase difference.
The holding part is
A first front flip-flop that holds the input signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as the first internal signal.
A first subsequent flip-flop that holds the first internal signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as a second internal signal.
A second front flip-flop that holds the input signal in synchronization with the falling edge of the predetermined periodic signal and supplies the held signal as a third internal signal.
A second rear-stage flip-flop that holds the third internal signal in synchronization with the rising edge of the predetermined periodic signal and supplies the held signal as a fourth internal signal is provided.
The detection unit
A first exclusive OR gate that outputs an exclusive OR of the first internal signal and the fourth internal signal, and
It includes a second exclusive OR gate that outputs an exclusive OR of the second internal signal and the fourth internal signal.
The variable delay element is a control method of a synchronization circuit that supplies the delayed signal to the second front flip-flop.

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