JP6818962B2 - Memory history management system - Google Patents

Description

The present invention relates to a system for reproducing the past state of the main memory.

There are various systems that reproduce the past state of main memory.
For example, Patent Document 1 discloses the following system.
Commands issued to the system bus are monitored. In addition, the cache memory has a bus snoop function. When the cache memory is updated, the data before the update is stored in the storage unit. Then, the data stored in the storage unit is written back to the main memory, so that the main memory is returned to the state at the time of checkpoint.

Japanese Unexamined Patent Publication No. 10-078918

In the system disclosed in Patent Document 1, when the bus command does not include the data before the update, it is necessary to read the data before the update from the main memory in order to store the data before the update in the storage unit. ..

An object of the present invention is to eliminate the need for a process of reading a data value from a main memory in order to record history information including the data value.

The memory history management system of the present invention uses the data value read from the main memory to the cache memory at the time of a cache miss in order to reproduce the state of the main memory before the occurrence of one or more access instructions. Manage one or more history information.
The cache memory has a plurality of entries corresponding to a plurality of storage areas in the main memory.
Each entry has a record flag.
The memory history management system
A history memory in which one or more of the history information is recorded, and
When a write instruction is generated, the record flag of the entry corresponding to the target area that is the target storage area of the generated write instruction is referred to, and the referenced record flag is unrecorded, which means that the history information has not been recorded. When indicating a state value, history information including a data value read from the target area to the cache memory is recorded in the history memory, and a record indicating that the history information has been recorded is recorded in the referenced recording flag. It is provided with a history recording circuit for setting a completed state value.

According to the present invention, the data value read from the main memory at the time of a cache miss is used. Therefore, it is possible to eliminate the process of reading the data value from the main memory in order to record the history information including the data value.

The block diagram of the memory history management system 100 in Embodiment 1. FIG. The block diagram of the main memory 202 in Embodiment 1. FIG. The block diagram of the cache memory 110 in Embodiment 1. FIG. FIG. 5 is a relationship diagram between the storage area of the main memory 202 and the entry of the cache memory 110 in the first embodiment. The block diagram of the history memory 120 in Embodiment 1. FIG. The flowchart of the history recording method in Embodiment 1. The figure which shows the access instruction list 211 in Embodiment 1. FIG. The figure which shows the access instruction list 212 in Embodiment 1. FIG. The figure which shows the specific example (the first access instruction of the 1st data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (the second access instruction of the 1st data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (third access instruction of the first data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (the 4th access instruction of the 1st data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (fifth access instruction of the 1st data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (sixth access instruction of the first data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (the seventh access instruction of the 1st data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (clearing of a recording flag) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (the first access instruction of the 2nd data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (the second access instruction of the 2nd data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (the second access instruction of the 2nd data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (third access instruction of the second data processing) of the history recording method in Embodiment 1. FIG. The figure which shows the specific example (third access instruction of the second data processing) of the history recording method in Embodiment 1. FIG. The flowchart of the memory reproduction method in Embodiment 1. The figure which shows the specific example (at the time of starting the 2nd data processing) of the memory reproduction method in Embodiment 1. FIG. The figure which shows the specific example (at the time of starting the 1st data processing) of the memory reproduction method in Embodiment 1. FIG. The flowchart of the history recording method in Embodiment 2. The figure which shows the specific example (the 4th access instruction of the 1st data processing) of the history recording method in Embodiment 2. FIG. The figure which shows the specific example (the second access instruction of the 2nd data processing) of the history recording method in Embodiment 2. FIG. The figure which shows the specific example (the second access instruction of the 2nd data processing) of the history recording method in Embodiment 2. FIG. The figure which shows the specific example of the history information 121 in Embodiment 2. FIG. The figure which shows the configuration example of the memory history management system 100 in embodiment.

In embodiments and drawings, the same or corresponding elements are designated by the same reference numerals. Descriptions of elements with the same reference numerals as the described elements will be omitted or simplified as appropriate. The arrows in the figure mainly indicate the flow of data or the flow of processing.

Embodiment 1.
The memory history management system 100 will be described with reference to FIGS. 1 to 24.

*** Explanation of configuration ***
The configuration of the memory history management system 100 will be described with reference to FIG.
The memory history management system 100 is provided in the computer 200.

The computer 200 includes a processor 201, a main memory 202, and a memory history management system 100.
A specific example of the processor 201 is a CPU (Central Processing Unit).
A specific example of the main memory 202 is a RAM (Random Access Memory).

The memory history management system 100 manages one or more history information in order to reproduce the state of the main memory 202 before the occurrence of one or more access instructions. The history information will be described later.

The memory history management system 100 includes a cache memory 110, a history memory 120, and a memory reproduction unit 130.

The cache memory 110 is a write-allocate type cache memory.
The write allocate method is a method in which a data value is read from the main memory to the cache memory when a write miss (a cache miss when a write instruction occurs) occurs. In the write allocate method, the data value is read from the main memory to the cache memory even when a read miss (a cache miss when a read instruction occurs) occurs. Data values are also simply called data.
In the memory history management system 100, the data value read from the main memory 202 to the cache memory 110 at the time of a cache miss is used. This eliminates the need for the operation of acquiring data values from the main memory 202 in order to record history information.

One or more history information is recorded in the history memory 120.
The history memory 120 may be a memory prepared separately from the main memory 202, or may be a part of the main memory 202.

The memory reproduction unit 130 is an element that reproduces the state of the main memory 202 before the occurrence of one or more write instructions, based on one or more history information recorded in the history memory 120.
The memory reproduction unit 130 may be realized by either software or hardware. Alternatively, the memory reproduction unit 130 may be realized by a combination of software and hardware.
When the memory reproduction unit 130 is realized by software, for example, a program for making the computer 200 function as the memory reproduction unit 130 is executed by the processor 201.
When the memory reproduction unit 130 is realized by hardware, for example, a dedicated circuit that functions as the memory reproduction unit 130 is mounted.

The configuration of the main memory 202 will be described with reference to FIG.
The main memory 202 has a plurality of storage areas.
Each storage area is identified by an address.

The configuration of the cache memory 110 will be described with reference to FIG.
The cache memory 110 has a plurality of entries 111. The plurality of entries 111 correspond to a plurality of storage areas in the main memory 202.
Each entry 111 is identified by an entry number.

Each entry 111 has a flag field, an address field, and a data value field.
The address of the storage area corresponding to the entry 111 is stored in the address field.
The data value of the storage area corresponding to the entry 111 is stored in the data value column.
The flag column has a valid flag (v), a dirty flag (d), and a recording flag (r).
The valid flag (v) indicates whether the address and the data value are valid or not. A flag value that means that an address and a data value are valid is referred to as a "valid value". A flag value that means that the address and data values are invalid is referred to as an "invalid value". That is, an invalid value (0) or a valid value (1) is set in the valid flag (v). The initial value of the valid flag (v) is the invalid value (0).
The dirty flag (d) indicates whether or not the data value has been written. Specifically, the dirty flag (d) indicates whether or not a write instruction for the storage area corresponding to entry 111 has occurred. The flag value that means that the data value has been written is referred to as a "write state value". A flag value that means that no data value has been written is referred to as an "immutable state value". That is, the invariant state value (0) or the write state value (1) is set in the dirty flag (d). When the dirty flag (d) indicates the write state value (1), the data value stored in the data value field of entry 111 may not match the data value stored in the storage area of the main memory 202. There is sex. When this entry 111 is invalidated, it is necessary to write the data value stored in the data value field to the storage area of the main memory 202. The initial value of the dirty flag (d) is the invariant state value (0).
The recording flag (r) indicates whether or not the history information has been recorded. The flag value that means that the history information has been recorded is referred to as a "recorded state value". A flag value that means unrecorded history information is referred to as an "unrecorded state value". That is, an unrecorded state value (0) or a recorded state value (1) is set in the recording flag (r). The initial value of the recording flag (r) is the unrecorded state value (0).

The cache memory 110 includes a cache control circuit 112 and a history recording circuit 113.
The cache control circuit 112 reads a data value from the storage area of the main memory 202 at the time of a cache miss, and stores the read data value in the entry 111 of the cache memory 110.
The history recording circuit 113 records one or more history information in the history memory 120.

The correspondence between the storage area of the main memory 202 and the entry 111 of the cache memory 110 will be described with reference to FIG.
The storage area and the entry 111 are associated with each other in a direct map manner. That is, the address of the storage area and the entry number of the entry 111 are associated with each other.
In the present embodiment, the storage area of the address "0xN ₁ N ₂ N ₃ " is associated with the entry 111 of the entry number "N ₂ ". “N ₁ ”, “N ₂ ” and “N ₃ ” represent single digit integers.
For example, the storage area at address “0x100” is associated with entry 111 at entry number “0”. Each of the storage area of the address "0x110" and the storage area of the address "0x110" is associated with the entry 111 of the entry number "1". The storage area of the address “0x120” is associated with the entry 111 of the entry number “2”. The storage area at address “0x130” is associated with entry 111 at entry number “3”.

The configuration of the history memory 120 will be described with reference to FIG.
One or more history information 121 is recorded in the history memory 120.
Each history information 121 includes a history number (#), a processing identifier, an address, and a data value.
The history number (#) identifies the history information 121.
The processing identifier identifies the data processing. A specific example of data processing is periodic processing. The periodic processing is periodically executed by the processor 201. A specific example of the processing identifier is the cycle number. The cycle number identifies the cycle process.

*** Explanation of operation ***
The operation of the memory history management system 100 corresponds to the memory history management method.
The memory history management method includes a history recording method and a memory reproduction method.
The history recording method corresponds to the operation of the history recording circuit 113.
The memory reproduction method corresponds to the operation of the memory reproduction unit 130.

Before explaining the history recording method and the memory reproduction method, the respective operations of the processor 201 and the cache control circuit 112 will be described.
Processor 201 executes a plurality of data processes in order.
Each data process includes one or more access instructions. The access instruction is a general term for a read instruction and a write instruction. The read instruction is an instruction to read a data value. The write instruction is an instruction to write a data value.
In the following description, the generation of the access instruction corresponds to the execution of the access instruction by the processor 201.

When an access instruction is generated, the information of the generated access instruction is input from the processor 201 to the cache control circuit 112. The information of the generated access instruction is the following information.
The information of the generated access instruction includes the processing identifier. This processing identifier identifies the data processing being performed. The data processing being executed is the data processing including the generated access instruction.
The information of the generated access instruction includes the address. This address identifies the storage area that is the target of the generated access instruction from the plurality of storage areas in the main memory 202.
The information of the generated access instruction includes the access type. This access type is the type of access instruction that has occurred.
When the generated access instruction is a write instruction, the information of the generated access instruction includes the write value. The write value is the data value specified by the write instruction, that is, the data value after writing.

Of the plurality of storage areas in the main memory 202, the storage area that is the target of the generated access instruction is referred to as a “target area”.
Of the plurality of entries 111 in the cache memory 110, the entry 111 corresponding to the target area is referred to as a “corresponding entry”.
Of a plurality of data processes, the data process including the generated access instruction is referred to as "target process". That is, the target process is the data process being executed.

The cache control circuit 112 reads a data value from the target area and stores the read data value in the data value column of the corresponding entry.
However, when the data value of the target area is stored in the corresponding entry, the cache control circuit 112 does not read the data value and store the data value.
Further, when the data value of the storage area different from the target area is stored in the data value column of the corresponding entry, the cache control circuit 112 writes back. That is, the cache control circuit 112 writes the data value stored in the data value column of the corresponding entry to the corresponding storage area, and then stores the read data value in the data value column of the corresponding entry.

Further, the cache control circuit 112 performs the following processing.
(1) When the generated access instruction is a write instruction, the cache control circuit 112 updates the data value (data value before writing) stored in the data value column of the corresponding entry to the data value after writing.
Further, the cache control circuit 112 sets a write state value in the dirty flag of the corresponding entry.
(2) The cache control circuit 112 sets the address of the target area in the address field of the corresponding entry.
(3) The cache control circuit 112 sets a valid value in the valid flag of the corresponding entry.

The information obtained by the cache control circuit 112 is input from the cache control circuit 112 to the history recording circuit 113.
Specifically, the information of the generated access instruction, the data value read from the target area, and the like are input to the history recording circuit 113.

The history recording method will be described with reference to FIG.
Steps S101 to S106 are executed each time an access instruction is issued.

In step S101, the history recording circuit 113 determines the type of the generated access instruction.
If the generated access instruction is a write instruction, the process proceeds to step S102.
If the generated access instruction is a read instruction, the process proceeds to step S105.

In step S102, the history recording circuit 113 refers to the recording flag of the corresponding entry.
If the recording flag of the corresponding entry indicates an unrecorded state value, the process proceeds to step S103.
If the record flag of the corresponding entry indicates a recorded state value, the process proceeds to step S105.

In step S103, the history recording circuit 113 generates history information, and records the generated history information in the history memory 120.
The recorded history information includes the processing number of the target processing, the address of the target area, and the data value before writing.
The data value before writing is the data value read from the target area into the cache memory 110 at the time of a cache miss.
However, if the data value of the target area is stored in the data value column of the corresponding entry at the start of the target processing, the data value before writing is before the data value after writing is written in the data value column of the corresponding entry. It is the data value stored in the data value column of the corresponding entry.

In step S104, the history recording circuit 113 sets the recorded state value in the recording flag of the corresponding entry.

In step S105, the history recording circuit 113 determines whether or not the target process has been completed.

For example, in the following cases, the history recording circuit 113 determines that the target process has been completed.
(1) When the r clear instruction is input from the processor 201, the history recording circuit 113 determines that the target process has been completed. The r-clear instruction is an instruction for clearing the recording flag of each entry 111.
(2) When the r clear signal is input from the outside, the history recording circuit 113 determines that the target process has been completed. The r-clear signal is an instruction for clearing the recording flag of each entry 111.
(3) When the generated access instruction is an access instruction targeting a specific area, the history recording circuit 113 determines that the target process has been completed. The specific area is a storage area that is accessed at the end of data processing.

When the target process is completed, the process proceeds to step S106.
If the target process is not completed, the process of the history recording method ends.

In step S106, the history recording circuit 113 sets an unrecorded state value in the recording flag of each entry 111.
After step S106, the process of the history recording method ends.

A specific example of the history recording method will be described below.
First, it is assumed that the first data processing is executed, and then the second data processing is executed.
The access instruction list 211 of FIG. 7 shows seven access instructions included in the first data processing.
The access instruction list 212 of FIG. 8 shows three access instructions included in the second data processing.

A history recording method when the first data processing is executed will be described with reference to FIGS. 9 to 16.
In FIG. 9, the first access instruction for the first data processing has occurred. The first access instruction of the first data processing is a read instruction targeting the storage area of the address "0x100".
The cache control circuit 112 reads the data value “0xaaaa” from the storage area of the address “0x100” and stores the read data value in the data value column of the 0th entry 111. Further, the cache control circuit 112 sets the address "0x100" in the address field of the 0th entry 111. Then, the cache control circuit 112 sets the valid value (1) in the valid flag (v).
Since the first access instruction is a read instruction, the history recording circuit 113 does not record the history information 121.

In FIG. 10, a second access instruction for the first data processing has occurred. The second access instruction of the first data processing is a write instruction targeting the storage area of the address "0x110". The light value is "0x1111".
The cache control circuit 112 reads the data value “0xbbbb” from the storage area of the address “0x110” and stores the read data value in the data value column of the first entry 111. Further, the cache control circuit 112 sets the address "0x110" in the address field of the first entry 111. Then, the cache control circuit 112 sets a valid value (1) in the valid flag (v) of the first entry 111.
Further, the cache control circuit 112 writes the write value “0x1111” in the data value column of the first entry 111. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the first entry 111.
The history recording circuit 113 generates history information 121 including the data value “0xbbbb” before writing read from the storage area of the address “0x110”, and records the generated history information 121 in the history memory 120. The history information 121 further includes a processing identifier "1" and an address "0x110". Then, the history recording circuit 113 sets the recorded state value (1) in the recording flag (r) of the first entry.

In FIG. 11, a third access instruction for the first data processing has occurred. The third access instruction of the first data processing is a read instruction targeting the storage area of the address "0x120".
The cache control circuit 112 reads the data value “0xcccc” from the storage area of the address “0x120” and stores the read data value in the data value column of the second entry 111. Further, the cache control circuit 112 sets the address "0x120" in the address field of the second entry 111. Then, the cache control circuit 112 sets the valid value (1) in the valid flag (v).
Since the second access instruction is a read instruction, the history recording circuit 113 does not record the history information 121.

In FIG. 12, a fourth access instruction for the first data processing has occurred. The fourth access instruction of the first data processing is a write instruction targeting the storage area of the address "0x120". The light value is "0xcccc".
The data value "0xcccc" read from the storage area of the address "0x120" is stored in the second entry 111.
The history recording circuit 113 acquires the data value “0xcccc” before writing from the second entry 111, generates the history information 121 including the acquired data value, and records the generated history information 121 in the history memory 120. The history information 121 further includes a processing identifier "1" and an address "0x120". Then, the history recording circuit 113 sets the recorded state value (1) in the recording flag (r) of the second entry 111.
The cache control circuit 112 writes the write value “0xcccc” in the data value column of the second entry. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the second entry.

In FIG. 13, the fifth access instruction for the first data processing has occurred. The fifth access instruction of the first data processing is a write instruction targeting the storage area of the address "0x130". The light value is "0xdddd".
The cache control circuit 112 reads the data value “0xdddd” from the storage area of the address “0x130” and stores the read data value in the data value column of the third entry 111. Further, the cache control circuit 112 sets the address "0x130" in the address field of the third entry 111. Then, the cache control circuit 112 sets a valid value (1) in the valid flag (v) of the third entry 111.
Further, the cache control circuit 112 writes the write value “0xdddd” in the data value column of the third entry 111. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the third entry 111.
The history recording circuit 113 generates history information 121 including the data value “0xdddd” before writing read from the storage area of the address “0x130”, and records the generated history information 121 in the history memory 120. The history information 121 further includes a processing identifier "1" and an address "0x130". Then, the history recording circuit 113 sets the recorded state value (1) in the recording flag (r) of the third entry.

In FIG. 14, a sixth access instruction for the first data processing has occurred. The sixth access instruction of the first data processing is a write instruction targeting the storage area of the address "0x130". The light value is "0x2222".
The data value "0xdddd" read from the storage area of the address "0x130" is stored in the third entry 111.
Since the recording flag (r) of the third entry 111 indicates the recorded value (1), the history recording circuit 113 does not record the history information 121.
The cache control circuit 112 writes the write value “0x2222” in the data value column of the third entry 111. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the third entry 111.

In FIG. 15, a seventh access instruction for the first data processing has occurred. The seventh access instruction of the first data processing is a read instruction targeting the storage area of the address "0x130".
The data value "0x2222" for the storage area of the address "0x130" is stored in the third entry 111.
Since the recording flag (r) of the third entry 111 indicates the recorded value (1), the history recording circuit 113 does not record the history information 121.

In FIG. 16, since the first data processing is completed, the history recording circuit 113 sets the recording flag (r) of each entry 111 to the unrecorded state value (0).

A history recording method when the second data processing is executed will be described with reference to FIGS. 17 to 20.
In FIG. 17, the first access instruction for the second data processing has occurred. The first access instruction of the second data processing is a write instruction targeting the storage area of the address "0x110". The light value is "0x3333".
The data value "0x1111" for the storage area of the address "0x110" is stored in the data value column of the first entry 111.
Since the recording flag (r) of the first entry 111 indicates the unrecorded state value (0), the history recording circuit 113 records the history information 121. Specifically, the history recording circuit 113 acquires the data value "0x1111" from the data value column of the first entry 111, generates the history information 121 including the acquired data value, and generates the generated history information 121. Record in the history memory 120. The history information 121 further includes a processing identifier "2" and an address "0x110". Then, the history recording circuit 113 sets the recorded state value (1) in the recording flag (r) of the first entry 111.
The cache control circuit 112 writes the write value “0x3333” in the data value column of the first entry 111. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the first entry 111.

In FIG. 18, the second access instruction for the second data processing has occurred. The second access instruction of the second data processing is a write instruction targeting the storage area of the address "0x210". The light value is "0xeeee".
The data value "0x3333" for the storage area of the address "0x110" is stored in the first entry 111 corresponding to the storage area of the address "0x210".
Therefore, the cache control circuit 112 writes back. That is, the cache control circuit 112 writes the data value “0x3333” stored in the data value column of the first entry 111 to the storage area of the address “0x110”.
After the writeback, the cache control circuit 112 (or the history recording circuit 113) sets the recording flag (r) of the first entry 111 to the unrecorded state value (0).

In FIG. 19, after the write-back, the cache control circuit 112 reads the data value “0xeeee” from the storage area of the address “0x210” and stores the read data value in the data value column of the first entry 111. Further, the cache control circuit 112 sets the address "0x210" in the address field of the first entry 111. Then, the cache control circuit 112 sets a valid value (1) in the valid flag (v) of the first entry 111.
Further, the cache control circuit 112 writes the write value “0xeeee” in the data value column of the first entry 111. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the first entry 111.
The history recording circuit 113 generates history information 121 including the data value “0xeeee” before writing read from the storage area of the address “0x210”, and records the generated history information 121 in the history memory 120. The history information 121 further includes a processing identifier "2" and an address "0x210". Then, the history recording circuit 113 sets the recorded state value (1) in the recording flag (r) of the first entry.

In FIG. 20, a third access instruction for the second data processing has occurred. The third access instruction of the second data processing is a write instruction targeting the storage area of the address "0x110". The light value is "0x4444".
The first entry 111 corresponding to the storage area of the address "0x110" stores the data value "0xeeee" for the storage area of the address "0x210".
Therefore, the cache control circuit 112 writes back. That is, the cache control circuit 112 writes the data value “0xeeee” stored in the data value column of the first entry 111 to the storage area of the address “0x210”.
After the writeback, the cache control circuit 112 (or the history recording circuit 113) sets the recording flag (r) of the first entry 111 to the unrecorded state value (0).

In FIG. 21, after writing back, the cache control circuit 112 reads the data value “0x3333” from the storage area of the address “0x110” and stores the read data value in the data value column of the first entry 111. Further, the cache control circuit 112 sets the address "0x110" in the address field of the first entry 111. Then, the cache control circuit 112 sets a valid value (1) in the valid flag (v) of the first entry 111.
Further, the cache control circuit 112 writes the write value “0x3333” in the data value column of the first entry 111. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the first entry 111.
The history recording circuit 113 generates history information 121 including the data value “0x3333” before writing read from the storage area of the address “0x110”, and records the generated history information 121 in the history memory 120. The history information 121 further includes a processing identifier "2" and an address "0x110". Then, the history recording circuit 113 sets the recorded state value (1) in the recording flag (r) of the first entry.

A memory reproduction method will be described with reference to FIG.
In step S111, the memory reproduction unit 130 determines whether or not one or more history information is recorded in the history memory 120.

However, when reproducing the state of the main memory 202 when the target data processing is started, the memory reproduction unit 130 has one or more histories including the processing identifiers of the data processing executed after the target data processing. It is determined whether the information is recorded in the history memory 120.
In this case, one or more historical information including the processing identifier of the data processing executed after the target data processing is simply referred to as one or more historical information.

If one or more history information is recorded in the history memory 120, the process proceeds to step S112.
If one or more history information is not recorded in the history memory 120, the process of the memory reproduction method ends.

In step S112, the memory reproduction unit 130 selects one unselected history information from one or more history information in the reverse order of the recording order.
This reverse order corresponds to the newest order of one or more historical information.

In step S113, the memory reproduction unit 130 writes the data value included in the selected history information in the storage area (corresponding area) corresponding to the selected history information.
Specifically, the corresponding area is a storage area identified by an address included in the selected history information among a plurality of storage areas in the main memory 202.

In step S114, the memory reproduction unit 130 determines whether or not there is history information (unselected history information) that has not been selected in step S112.
If there is unselected history information, the process proceeds to step S112.
If there is no unselected history information, the processing of the memory reproduction method ends.

From step S112 to step S114, the state of the main memory 202 before one or more access instructions are generated is reproduced.
For example, the state of the main memory 202 when the target data processing is started is reproduced.

A specific example of the memory reproduction method will be described below.
It is assumed that the six history information 121 shown in FIG. 21 is recorded in the history memory 120.

A memory reproduction method for reproducing the state of the main memory 202 when the second data processing is started will be described with reference to FIG. 23.
The memory reproduction unit 130 selects each history information 121 from the three history information 121 including the processing identifier “2” in the reverse order of the recording order, and is selected as the storage area corresponding to the selected history information 121. Write the data value included in the history information 121.

Specifically, the memory reproduction unit 130 operates as follows.
First, the memory reproduction unit 130 selects the history information 121 having the history number “6”. The storage area corresponding to the history information 121 of the history number “6” is the storage area of the address “0x110”. The data value included in the history information 121 of the history number "6" is "0x3333". Therefore, the memory reproduction unit 130 writes the data value “0x3333” in the storage area of the address “0x110”.
Next, the memory reproduction unit 130 selects the history information 121 having the history number “5”. The storage area corresponding to the history information 121 of the history number “5” is the storage area of the address “0x210”. Further, the data value included in the history information 121 of the history number "5" is "0xeeee". Therefore, the memory reproduction unit 130 writes the data value “0xeeee” in the storage area of the address “0x210”.
Then, the memory reproduction unit 130 selects the history information 121 of the history number “4”. The storage area corresponding to the history information 121 of the history number “5” is the storage area of the address “0x210”. Further, the data value included in the history information 121 of the history number "5" is "0xeeee". Therefore, the memory reproduction unit 130 writes the data value “0xeeee” in the storage area of the address “0x210”.

As a result, the state of the main memory 202 when the second data processing is started is reproduced.

A memory reproduction method for reproducing the state of the main memory 202 when the first data processing is started will be described with reference to FIG. 24.
The memory reproduction unit 130 executes the following processing after the processing described with reference to FIG. 23.
The memory reproduction unit 130 selects each history information 121 from the three history information 121 including the processing identifier "1" in the reverse order of the recording order, and is selected as the storage area corresponding to the selected history information 121. Write the data value included in the history information 121.

Specifically, the memory reproduction unit 130 operates as follows.
First, the memory reproduction unit 130 selects the history information 121 having the history number “3”. The storage area corresponding to the history information 121 of the history number “3” is the storage area of the address “0x130”. Further, the data value included in the history information 121 of the history number "3" is "0xdddd". Therefore, the memory reproduction unit 130 writes the data value “0xdddd” in the storage area of the address “0x130”.
Next, the memory reproduction unit 130 selects the history information 121 having the history number “2”. The storage area corresponding to the history information 121 of the history number “2” is the storage area of the address “0x120”. The data value included in the history information 121 of the history number "2" is "0xcccc". Therefore, the memory reproduction unit 130 writes the data value “0xcccc” in the storage area of the address “0x120”.
Then, the memory reproduction unit 130 selects the history information 121 having the history number “1”. The storage area corresponding to the history information 121 of the history number “1” is the storage area of the address “0x110”. Further, the data value included in the history information 121 of the history number "1" is "0xbbbb". Therefore, the memory reproduction unit 130 writes the data value “0xbbbb” in the storage area of the address “0x110”.

As a result, the state of the main memory 202 when the first data processing is started is reproduced.

*** Effect of Embodiment 1 ***
The memory history management system 100 has a recording flag in each entry of the cache memory 110. The history flag indicates whether or not the history memory 120 has been written. Further, the memory history management system 100 reproduces the past data values in the main memory 202 based on the latest data values in the main memory 202 and the history information in the history memory 120. To be equipped.
As a result, the memory history management system 100 can reproduce the state of the main memory 202 with a small memory capacity. For example, in a computer system that performs periodic processing, the memory history management system 100 can reproduce a memory value of a past cycle with a small memory capacity. The memory value is a data value in the main memory 202.
Since the past data value is reproduced based on the history information indicating the difference from the latest memory value, the amount of data required for reproduction is small. When the history memory 120 becomes full, the memory history management system 100 can continue recording new history information by overwriting the history information in chronological order. On the other hand, in the method of recording the initial value and the difference data at the time of writing, if the old history information is overwritten because the history memory is full, the past data value cannot be reproduced.
Since each entry in the cache memory 110 has a record flag, it is possible to suppress the recording of history information for a plurality of write instructions for the same entry. Specifically, even if a plurality of write instructions for the same entry occur, the history information can be recorded once. Therefore, the amount of historical information recorded is reduced.
In the memory history management system 100, the write-allocate type cache memory 110 is used. Then, the data value read from the main memory 202 at the time of a cache miss is used as the data value before writing. This eliminates the need to acquire the data value before writing from the main memory 202 for recording the history information.
In the memory history management system 100, the recording of history information is performed by hardware (history recording circuit 113). Therefore, the history information can be recorded without affecting the processing time of the software (data processing).

*** Other configurations ***
When it is not necessary to reproduce the main memory 202 for each data processing, it is not necessary to manage the history information for each data processing. That is, it is not necessary to include the processing identifier in the history information.

The history recording circuit 113 does not have to clear the recording flag (set the unrecorded state value) for each data process. That is, the history recording circuit 113 may clear the recording flag of each entry each time two or more data processes are completed. For example, the history recording circuit 113 may clear the recording flag of each entry every two cycles or every four cycles. In this case, the state of the main memory 202 can be reproduced only every two cycles or every four cycles. However, since the number of recorded history information is reduced, the capacity of the history memory 120 can be reduced.

Embodiment 2.
A mode in which history information is not recorded when the memory value after writing is the same as the memory value before writing will be described mainly different from the first embodiment with reference to FIGS. 25 to 29.

*** Explanation of configuration ***
The configuration of the memory history management system 100 is the same as the configuration in the first embodiment (see FIGS. 1 to 5).

*** Explanation of operation ***
The history recording method will be described with reference to FIG. 25.
In step S201, the history recording circuit 113 determines the type of the generated access instruction.
Step S201 is the same as step S101 in the first embodiment (see FIG. 6).
If the generated access instruction is a write instruction, the process proceeds to step S202.
If the generated access instruction is a read instruction, the process proceeds to step S206.

In step S202, the history recording circuit 113 refers to the recording flag of the corresponding entry.
Step S202 is the same as step S102 in the first embodiment (see FIG. 6).
If the recording flag of the corresponding entry indicates an unrecorded state value, the process proceeds to step S203.
If the recording flag of the corresponding entry indicates a recorded state value, the process proceeds to step S206.

In step S203, the history recording circuit 113 compares the data value after writing of the generated write instruction with the data value before writing read from the target area of the generated write instruction into the cache memory 110.
If the data value after writing is different from the data value before writing, the process proceeds to step S204.
If the data value after writing is the same as the data value before writing, the process proceeds to step S206.

In step S204, the history recording circuit 113 records the history information including the data value before writing in the history memory 120.
Step S204 is the same as step S103 in the first embodiment (see FIG. 6).

In step S205, the history recording circuit 113 sets the recorded state value in the recording flag of the corresponding entry.
Step S205 is the same as step S104 in the first embodiment (see FIG. 6).

In step S206, the history recording circuit 113 determines whether or not the target process has been completed.
When the target processing is completed, the history recording circuit 113 sets an unrecorded state value in the recording flag of each entry 111.
Step S206 is the same as step S105 and step S106 in the first embodiment (see FIG. 6).

A specific example of the history recording method will be described below.
First, it is assumed that the first data processing is executed, and then the second data processing is executed.
In the first data processing, as in the first embodiment, seven access instructions are generated (see FIG. 7).
In the second data processing, as in the first embodiment, three access instructions are generated (see FIG. 8).

The processing when three access instructions from the first access instruction of the first data processing to the third access instruction of the first data processing are generated is as described in the first embodiment (FIGS. 9 to 11). reference).

In FIG. 26, a fourth access instruction for the first data processing has occurred. The fourth access instruction of the first data processing is a write instruction targeting the storage area of the address "0x120". The data value after writing is "0xcccc".
The data value “0xcccc” before writing read from the storage area of the address “0x120” is stored in the second entry 111.
The data value "0xcccc" after writing is the same as the data value "0xcccc" before writing.
Therefore, the history recording circuit 113 does not record the history information 121. Further, the history recording circuit 113 does not set the recorded state value (1) in the recording flag (r) of the second entry 111.

The processing when three access instructions from the fifth access instruction of the first data processing to the seventh access instruction of the first data processing are generated is as described in the first embodiment (FIGS. 13 to 15). reference).

The processing when the first access instruction of the second data processing is generated is as described in the first embodiment (see FIG. 17).

In FIG. 27, the second access instruction for the second data processing has occurred. The second access instruction of the second data processing is a write instruction targeting the storage area of the address "0x210". The data value after writing is "0xeeee".
The data value "0x3333" for the storage area of the address "0x110" is stored in the first entry 111 corresponding to the storage area of the address "0x210".
Therefore, the cache control circuit 112 writes back. That is, the cache control circuit 112 writes the data value “0x3333” stored in the data value column of the first entry 111 to the storage area of the address “0x110”.
After the writeback, the cache control circuit 112 (or the history recording circuit 113) sets the recording flag (r) of the first entry 111 to the unrecorded state value (0).
The process in FIG. 27 is the same as the process in FIG. 18 of the first embodiment.

In FIG. 28, after writing back, the cache control circuit 112 reads the data value “0xeeee” from the storage area of the address “0x210” and stores the read data value in the data value column of the first entry 111. Further, the cache control circuit 112 sets the address "0x210" in the address field of the first entry 111. Then, the cache control circuit 112 sets a valid value (1) in the valid flag (v) of the first entry 111.
Further, the cache control circuit 112 writes the write value “0xeeee” in the data value column of the first entry 111. Then, the cache control circuit 112 sets the write state value (1) in the dirty flag (d) of the first entry 111.
The data value "0xeeee" after writing is the same as the data value "0xeeee" before writing.
Therefore, the history recording circuit 113 does not record the history information 121. Further, the history recording circuit 113 does not set the recorded state value (1) in the recording flag (r) of the first entry 111.

The processing when the third access instruction of the second data processing is generated is as described in the first embodiment (see FIGS. 20 and 21).

The history memory 120 when the first data processing and the second data processing are completed will be described with reference to FIG. 29.
Four history information 121 are recorded in the history memory 120. On the other hand, in the first embodiment, six history information 121s were recorded (see FIG. 21).
The first history information 121 corresponds to the first history information 121 in the first embodiment.
The second history information 121 corresponds to the third history information 121 in the first embodiment.
The third history information 121 corresponds to the fourth history information 121 in the first embodiment.
The fourth history information 121 corresponds to the sixth history information 121 in the first embodiment.
The history information 121 corresponding to each of the second history information 121 in the first embodiment and the fifth history information 121 in the first embodiment is not recorded in the history memory 120 of FIG. 29.

*** Effect of Embodiment 2 ***
Since the history information is not recorded when the data value does not change, the capacity of the history memory 120 can be reduced. When a part of the main memory 202 is used as the history memory 120, the number of writes to the history memory 120 is reduced, so that the bandwidth of the main memory 202 can be reduced.

*** Other configurations ***
Instead of the history recording circuit 113, the cache control circuit 112 may compare the data value after writing with the data value before writing.
When the data value after writing is the same as the data value before writing, the cache control circuit 112 does not set the write state value in the dirty flag of the corresponding entry. That is, the dirty flag of the corresponding entry indicates an immutable state value. The history recording circuit 113 refers to the dirty flag of the corresponding entry. If the dirty flag of the corresponding entry does not indicate a write state value, that is, if the dirty flag of the corresponding entry indicates an immutable state value, the history recording circuit 113 does not record history information.

*** Supplement to the embodiment ***
The configuration of the memory history management system 100 is not limited to the configurations described with reference to FIGS. 1 to 5.
For example, each of the cache control circuit 112 and the history recording circuit 113 may be provided outside the cache memory 110.
For example, the memory reproduction unit 130 may be provided in a computer other than the computer 200.

An example in which the memory reproduction unit 130 is provided in the memory reproduction device 220 will be described with reference to FIG.
The memory reproduction device 220 is a computer provided separately from the computer 200, and includes hardware such as a processor 221 and a main memory 222. Further, the memory reproduction device 220 includes a software element called a memory reproduction unit 223.
A memory reproduction program is stored in the main memory 222, and the processor 221 executes the memory reproduction program.
The memory reproduction program is a program for operating a computer as a memory reproduction unit 223.
However, the memory reproduction unit 223 may be realized by hardware such as a dedicated circuit.

The embodiments are examples of preferred embodiments and are not intended to limit the technical scope of the invention. The embodiment may be partially implemented or may be implemented in combination with other embodiments. The procedure described using the flowchart or the like may be appropriately changed.

100 memory history management system, 110 cache memory, 111 entries, 112 cache control circuit, 113 history recording circuit, 120 history memory, 121 history information, 130 memory reproduction unit, 200 computers, 201 processor, 202 main memory, 211 access instruction list , 212 access instruction list, 220 memory reproduction device, 221 processor, 222 main memory, 223 memory reproduction unit.

Claims (7)

One or more history information is managed by using the data value read from the main memory to the cache memory at the time of a cache miss in order to reproduce the state of the main memory before the occurrence of one or more access instructions. It is a memory history management system
The cache memory has a plurality of entries corresponding to a plurality of storage areas in the main memory.
Each entry has a record flag
The memory history management system
A history memory in which one or more of the history information is recorded, and
When a write instruction is generated, the record flag of the entry corresponding to the target area that is the target storage area of the generated write instruction is referred to, and the referenced record flag is unrecorded, which means that the history information has not been recorded. When indicating a state value, history information including a data value read from the target area to the cache memory is recorded in the history memory, and a record indicating that the history information has been recorded is recorded in the referenced recording flag. A memory history management system equipped with a history recording circuit for setting completed state values. Each history information is selected from one or more history information recorded in the history memory in the reverse order of the recording order, and the data value included in the history information selected in the storage area corresponding to the selected history information is selected. The memory history management system according to claim 1, further comprising a memory reproduction unit that reproduces the state of the main memory before the one or more access instructions are generated by writing. The history recording circuit
When a write instruction is generated during each execution of a plurality of data processes to be executed in order, history information including a process identifier that further identifies the data process being executed is recorded in the history memory.
The memory history management system according to claim 1, wherein the recording flag of each entry is updated to the unrecorded state value at the end of each of the plurality of data processes. Select each history information from one or more history information including the processing identifier of the data processing executed after the target data processing in the reverse order of the recording order, and select it as the storage area corresponding to the selected history information. The memory history management system according to claim 3, further comprising a memory reproduction unit that reproduces the state of the main memory when the target data processing is started by writing a data value included in the history information. The history recording circuit refers to the recording flag of the corresponding entry corresponding to the target area when the write instruction is generated, and when the referenced recording flag indicates the unrecorded state value, the write of the generated write instruction is written. The later data value is compared with the data value before writing read from the target area into the cache memory, and when the data value after writing is different from the data value before writing, the data value before writing is described. The memory history management system according to any one of claims 1 to 4, wherein history information including the above is recorded in the history memory, and the recorded state value is set in the referenced recording flag. The cache memory is a write-allocate type cache memory.
The memory history according to any one of claims 1 to 5, wherein the history recording circuit records history information including data values read from the target area into the cache memory at the time of a write error in the history memory. Management system. The memory history management system includes the cache memory.
The memory history management system according to any one of claims 1 to 6, wherein the cache memory includes the history recording circuit.

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