JP6832672B2 - System stabilization system - Google Patents

Description

The present disclosure relates to a grid stabilization system for a power system having a transmission line for connecting a generator to another power system.

Conventionally, the excitation control device of a generator connected to the power system includes an automatic voltage regulator (AVR) for keeping the terminal voltage of the generator constant at the target voltage, and the target voltage is adjusted. A system stabilizer (PSS) is provided to stabilize the operation of the generator.

The PSS generates a stabilization signal for suppressing system sway based on input signals such as generator active power and shaft rotation speed. The stabilization signal is added to the terminal voltage set value of the excitation control device, and the electric output of the generator changes due to the change in the field voltage to suppress the shaking. Here, the PSS operates effectively when the generator is connected to the power system, but when the generator is disconnected from the power system, the stabilization signal output by the PSS continues the operation of the generator. May have an adverse effect on.

Therefore, Patent Document 1 (Japanese Patent Laid-Open No. 56-15194) discloses a power system stabilizer that detects a frequency change of a generator, performs phase compensation, and gives a stabilization signal to an automatic voltage regulator. There is. This power system stabilizer includes a circuit that detects at least one of the current and the electric power of the generator and opens the output of the stabilizer when the detected value is equal to or less than a specified value.

Further, Patent Document 2 (Japanese Unexamined Patent Publication No. 64-81699) discloses a control device for a synchronous generator including a stabilizer and an automatic voltage regulator. This control device includes a single system discriminator that outputs an output stop signal that stops the output of the output stabilization signal when the interconnection between the synchronous generator and the power system is interrupted.

Japanese Unexamined Patent Publication No. 56-15194 Japanese Unexamined Patent Publication No. 64-81699

In the technique according to Patent Document 1, the output of the stabilizer is locked when the output value of the generator becomes equal to or less than the specified value. Here, even when the generator is cut off from another power system and the power generation side becomes a single system, the generator output does not decrease if the load is larger than the total output of the generator in the single system. Therefore, in such a case, the technique according to Patent Document 1 cannot quickly lock the PSS.

Further, in the technique according to Patent Document 2, the open / closed state of each circuit breaker is monitored, and an output stop signal is output by a certain logic. Here, each circuit breaker is connected to a bus at the end of the generator. Therefore, the open / closed state of the circuit breaker provided at another distant point (for example, an electric station or the like) connected from the bus via the transmission line is not considered.

The present disclosure has been made in view of the above problems, and the purpose in a certain aspect is to be quicker and more accurate even when the interconnection between the generator and another power system is interrupted. It is to provide a system stabilization system that can often suppress the fluctuation of the power system.

According to one embodiment, a grid stabilization system for a power system is provided that includes a generator provided at a power plant and a transmission line for connecting the generator to another power system. The generator has one or more first circuit breakers that open and close between each of the bus lines of one or more electric stations and the transmission line, and a second circuit breaker that opens and closes between the bus bus and the transmission line of the power plant. It is connected to another power system via. The system stabilization system has a detection means for detecting the open / closed state of each of one or more first circuit breakers and a second circuit breaker, and one or more first circuit breakers and second circuit breakers detected by the detection means, respectively. A state determining means for determining whether or not one or more of the first circuit breakers and the second circuit breakers are in the open state based on the open / closed state of the above, and one or more first circuit breakers. Based on the judgment result of the state determination means that one of the circuit breakers and the second circuit breaker is in the open state, the PSS (power system) provided in the power plant for suppressing the fluctuation of the power system. It is provided with an output control means for locking the system stabilization signal output by the circuit breaker).

According to the present disclosure, even when the interconnection between the generator and another power system is interrupted, it is possible to suppress the fluctuation of the power system more quickly and accurately.

It is a figure which shows an example of the whole structure of the system stabilization system according to this embodiment. It is a figure which shows an example of the hardware composition of the output control device which follows this embodiment. It is a figure for demonstrating the PSS lock determination method according to this embodiment. It is a figure for demonstrating the PSS lock output system according to this embodiment. It is a figure for demonstrating the PSS validity determination method according to this embodiment. It is a figure for demonstrating the PSS effective output system according to this embodiment. It is a schematic diagram which shows the functional structure of the system stabilization system according to this embodiment. It is a flowchart which shows an example of the processing procedure of the system stabilization system according to this embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same reference code may be attached to the same or corresponding part, and the explanation may not be repeated. Further, in the embodiments described below, when the number, quantity, etc. are referred to, the scope of the present invention is not necessarily limited to the number, quantity, etc., unless otherwise specified. Further, in the following embodiments, each component is not necessarily essential for the present invention unless otherwise specified.

<System configuration>
FIG. 1 is a diagram showing an example of the overall configuration of the system stabilization system 1000 according to the present embodiment. With reference to FIG. 1, the system stabilization system 1000 functions as a system for stabilizing the power system 4 connected to the backbone system 6, which is an example of another power system. The electric power system 4 is provided with a plurality of electric stations 100A to 100C and a power plant 102, and these are connected to each other via a transmission line L.

The electric stations 100A to 100C are provided with bus lines 2A to 2C, transformers TRa to TRc, and terminal devices 10A to 10C, respectively. Further, the electric station 100A is provided with circuit breakers CBa1 and CBa2, the electric station 100B is provided with circuit breakers CBb1 and CBb2, and the electric station 100C is provided with circuit breakers CBc1 and CBc2. In the present embodiment, the configuration in which the electric stations 100A to 100C are substations will be described, but the present invention is not limited to the configuration, and may be a switchyard for opening and closing the electric circuit.

The power plant 102 is provided with a generator G, a bus 2D, a main transformer TRm, a circuit breaker CBd1, a circuit breaker 8, a terminal device 10D, an output control device 20, and an excitation control device 30. .. Hereinafter, when the configurations and functions common to each of the terminal devices 10A to 10D are described, they are collectively referred to as "terminal device 10".

The transmission line L is, for example, a three-phase, two-line long-distance transmission line, and is divided by four bus lines 2A to 2D. In the present specification, the transmission line corresponding to the section from the backbone system 6 to the bus 2A is referred to as L1, the transmission line corresponding to the section from the bus 2A to the bus 2B is referred to as L2, and the section from the bus 2B to the bus 2C. The transmission line corresponding to is referred to as L3, and the transmission line corresponding to the section from the bus 2C to the bus 2D is referred to as L4. The line corresponding to the section from the bus 2D to the generator G provided in the power plant 102 is referred to as Lg.

Transformers TRa to TRc are connected to the bus lines 2A to 2C, respectively. Each transformer TRa to TRc is a step-down transformer for stepping down the transmission voltage. A secondary bus (not shown) is provided on the secondary side, and a load (factory, general household, etc.) is provided on the secondary bus. Consumers) are connected.

Further, a circuit breaker for opening and closing between the bus and the transmission line L is connected to each of the bus 2A to 2D. Specifically, the circuit breaker CBa1 opens and closes between the bus 2A and the transmission line L1, and the circuit breaker CBa2 opens and closes between the bus 2A and the transmission line L2. The circuit breaker CBb1 opens and closes between the bus 2B and the transmission line L2, and the circuit breaker CBb2 opens and closes between the bus 2B and the transmission line L3. The circuit breaker CBc1 opens and closes between the bus 2C and the transmission line L3, and the circuit breaker CBc2 opens and closes between the bus 2C and the transmission line L4. The circuit breaker CBd1 opens and closes between the bus 2D and the transmission line L4.

Further, a generator G composed of a synchronous generator is connected to the bus 2D via a line Lg. Specifically, a main transformer TRm for boosting and a circuit breaker 8 are connected between the bus 2D and the generator G.

As described above, in the electric power system 4 according to the present embodiment, the generator G is connected to the transmission line L extending from the main system 6. Specifically, the generator G has a plurality of circuit breakers CBa1, CBa2, CBb1, CBb2, CBc1, CBc2, which open and close between each of the bus bars 2A to 2C of the plurality of electric stations 100A to 100C and the transmission line L. It is connected to the backbone system 6 via a circuit breaker CBd1 that opens and closes between the bus 2D of the power plant 102 and the transmission line L. Then, the main system 6 and the generator G are configured to maintain the voltage of the transmission line L.

Each terminal device 10 receives an input of the open / closed state of the corresponding circuit breaker. Specifically, the terminal device 10A accepts the input of the open / closed state of the circuit breakers CBa1 and CBa2, the terminal device 10B receives the input of the open / closed state of the circuit breakers CBb1 and CBb2, and the terminal device 10C receives the input of the open / closed state of the circuit breakers CBc1 and CBc2. The terminal device 10D accepts the input of the state, and receives the input of the open / closed state of the circuit breaker CBd1 and the circuit breaker 8. Each terminal device 10 transmits information indicating an open / closed state of each corresponding circuit breaker to the central control device 80.

The central control device 80 executes a predetermined process based on the open / closed state of each circuit breaker CBa1, CBa2, CBb1, CBb2, CBc1, CBc2, CBd1 (hereinafter, also simply referred to as "each circuit breaker CB"). , It is determined whether or not to lock the system stabilization function of the excitation control device 30. The central control device 80 transmits information indicating the determination result to the output control device 20. The details of the operation of the central control device 80 will be described later.

The output control device 20 takes in the current of the line Lg via the instrument transformer CT and the bus voltage of the bus 2D via the voltage transformer VT, and is predetermined based on these amounts of electricity. Perform a relay operation. The output control device 20 is a lock signal for locking (disabled) the system stabilization function of the excitation control device 30 based on the relay calculation result and the determination result received from the central control device 80, or the function. Is output to the excitation control device 30 as an effective signal for making the effective state. The details of the operation of the output control device 20 will be described later.

The excitation control device 30 includes a system stabilizer (PSS) 32 that has a system stabilization function and an automatic voltage regulator (AVR) 34 that has a constant terminal voltage control function. Hereinafter, an example of the operation of the excitation control device 30 will be described.

The PSS 32 detects the output power of the generator G based on the current and voltage measured through an instrument transformer (not shown) and a voltage transformer (not shown). The PSS 32 outputs a system stabilization signal to the AVR 34 for suppressing the fluctuation of the power system by stabilizing the output power of the generator G so as not to fluctuate significantly.

The AVR34 uses a deviation signal that compares the terminal voltage of the generator G and the terminal voltage set value measured via a voltage transformer (not shown) as a deviation signal, and the deviation signal and system stabilization input from the PSS 32. An excitation control signal superimposed on the signal is output to an exciter (not shown). The exciter controls the exciting current of the field winding 40 of the generator G according to the excitation control signal.

Typically, the PSS 32 outputs a system stabilization signal so as to sharply decrease the exciting current when the output power suddenly increases, and a system stabilization signal so as to sharply increase the exciting current when the output power suddenly decreases. Is output.

When the excitation control device 30 receives the input of the lock signal from the output control device 20, the system stabilization function is locked. That is, the PSS 32 is in a locked state in which the system stabilization signal is not output to the AVR 34. On the other hand, when the excitation control device 30 receives the input of the valid signal from the output control device 20 while the PSS 32 is in the locked state, the locked state of the PSS 32 is released and the PSS 32 becomes the valid state. That is, the PSS 32 is in a state of outputting a system stabilization signal to the AVR 34.

<Hardware configuration>
FIG. 2 is a diagram showing an example of the hardware configuration of the output control device 20 according to the present embodiment. With reference to FIG. 3, the output control device 20 includes an auxiliary transformer 50, an AD (Analog to Digital) conversion unit 60, and an arithmetic processing unit 70.

The auxiliary transformer 50 takes in the system electricity amount from the instrument transformer CT and the instrument transformer VT, converts it into a smaller amount of electricity, and outputs it.

The AD conversion unit 60 takes in the system electric quantity (analog quantity) output from the auxiliary transformer 50 and converts it into digital data. Specifically, the AD conversion unit 60 includes an analog filter, a sample hold circuit, a multiplexer, and an AD converter.

The analog filter removes high frequency noise components from the current and voltage waveform signals output from the auxiliary transformer 50. The sample hold circuit samples the current and voltage waveform signals output from the analog filter at a predetermined sampling cycle. Based on the timing signal input from the arithmetic processing unit 70, the multiplexer sequentially switches the waveform signal input from the sample hold circuit in chronological order and inputs it to the AD converter. The AD converter converts the waveform signal input from the multiplexer from analog data to digital data. The AD converter outputs the digitally converted waveform signal (digital data) to the arithmetic processing unit 70.

The arithmetic processing unit 70 communicates with a CPU (Central Processing Unit) 72, a ROM 73, a RAM 74, a DI (digital input) circuit 75, a DO (digital output) circuit 76, and an input interface (I / F) 77. Includes interface (I / F) 78. These are connected by a bus 71.

The CPU 72 controls the operation of the output control device 20 by reading and executing a program stored in the ROM 73 in advance. The ROM 73 stores various information used by the CPU 72. The CPU 72 is, for example, a microprocessor. The hardware may be an FPGA (Field Programmable Gate Array) other than the CPU, an ASIC (Application Specific Integrated Circuit), or a circuit having other arithmetic functions.

The CPU 72 takes in digital data from the AD conversion unit 60 via the bus 71. The CPU 72 executes a control operation using the captured digital data according to the program stored in the ROM 73.

The CPU 72 outputs a control command to an external device via the DO circuit 76 based on the control calculation result. Further, the CPU 72 receives a response to the control command via the DI circuit 75. The input interface 77 is typically various buttons and the like, and receives various setting operations from the system operator. Further, the CPU 72 transmits and receives various information to and from other devices (terminal device 10, central control device 80, etc.) via the communication interface 78.

The hardware configuration of the terminal device 10 and the central control device 80 is the same as the hardware configuration of the output control device 20. Typically, the terminal device 10, the output control device 20, and the central control device 80 are configured as digital protection relay devices.

<Lock PSS function>
The locking method of the PSS function according to the present embodiment will be described. Specifically, the PSS lock determination method by the central control device 80 and the PSS lock output method by the output control device 20 will be described.

FIG. 3 is a diagram for explaining a PSS lock determination method according to the present embodiment. FIG. 4 is a diagram for explaining a PSS lock output method according to the present embodiment.

With reference to FIG. 3, the terminal device 10A includes an open state detection element 500A for detecting an open state of the circuit breaker CBa1 (hereinafter, also referred to as an “open state”) and an open state detection of the circuit breaker CBa2. Includes element 502A. The terminal device 10B includes an open state detection element 500B of the circuit breaker CBb1 and an open state detection element 502B of the circuit breaker CBb2. The terminal device 10C includes an open state detection element 500C of the circuit breaker CBc1 and an open state detection element 502C of the circuit breaker CBc2. The terminal device 10D includes an open state detection element 500D of the circuit breaker CBd1.

When the circuit breaker CBa1 detects the open state (that is, the interconnection between the generator G and the backbone system 6 is interrupted by the circuit breaker CBa1), the open state detection element 500A logically outputs the output value “1”. Output to gate 510. Similarly, when the open state detection element 500B, the open state detection element 500C, and the open state detection element 500D detect the open state of the circuit breakers CBb1, CBc1, and CBd1, the output value "1" is set to the central control device 80. Output to the logic gate 510. The open state detection element 502A, the open state detection element 502B, and the open state detection element 502C output an output value "1" to the logic gate 510 when the open state of the circuit breakers CBa2, CBb2, and CBc2 is detected, respectively.

The central controller 80 includes a logic gate 510 and a lock determination output element 512. The logic gate 510 performs an OR operation on each output value of the open state detection elements 500A to 500D and 502A to 502C, and outputs the operation result to the lock determination output element 512. When the lock determination output element 512 receives the input of "1" from the logic gate 510, the lock determination output element 512 outputs the output value "1" to the output control device 20 (the logic gate 530 of FIG. 4), and the logic gate 510 to "0". When the input of "" is received, the value "0" is output to the output control device 20.

With reference to FIG. 4, the output control device 20 includes an active power change rate relay element 514, an off-delay timer 516, an underfrequency relay element 518, an overfrequency relay element 520, a frequency change rate relay element 522, and the like. It includes an off-relay timer 524, a logic gate 526, an off-relay timer 528, a logic gate 530, and an output circuit 532. It should be noted that each of the above relay elements shall output "1" at the time of operation (at the time of abnormality detection) and "0" at the time of non-operation (at the time of steady operation).

The active power change rate relay element 514 operates when the change rate of the active power (passing active power of the bus 2D) output from the generator G to the transmission line L is equal to or higher than the reference change rate, and operates as an output value. “1” is output to the off delay timer 516. The active power is calculated based on the current of the line Lg measured by the current transformer CT for the instrument and the voltage of the bus 2D measured by the transformer VT for the instrument.

When the active power change rate relay element 514 outputs an output value “1”, the off-delay timer 516 maintains the output value “1” for the time T1 and outputs the output value to the logic gate 526. The time T1 is, for example, 3 seconds.

The insufficient frequency relay element 518 operates when the frequency of the voltage of the bus 2D is insufficient (that is, when the frequency becomes less than the set frequency F1), and outputs the output value “1” to the logic gate 526.

The overfrequency relay element 520 operates when the frequency of the voltage of the bus 2D becomes excessive (that is, when the set frequency F2 or more is larger than the set frequency F1), and the output value “1” is logically gated. Output to 526.

The frequency change rate relay element 522 operates when the frequency change rate of the voltage of the bus 2D becomes excessive (when it becomes equal to or higher than the set change rate), and outputs an output value "1" to the off delay timer 524. ..

When the frequency change rate relay element 522 outputs an output value “1”, the off-delay timer 524 maintains the output value “1” for the time T2 and outputs the value to the logic gate 526. The time T2 is, for example, 30 seconds.

The logic gate 526 performs OR calculation of each output value of the off-delay timer 516, the shortage frequency relay element 518, the over-frequency relay element 520, and the off-delay timer 524, and outputs the calculation result to the off-delay timer 528.

When the logic gate 526 outputs an output value "1", the off delay timer 528 maintains the value for the time T3 and outputs the output value to the logic gate 530. The time T3 is, for example, 1 second.

The logic gate 530 performs an AND operation on each output value of the lock determination output element 512 and the off delay timer 528, and outputs the operation result to the output circuit 532. When the output circuit 532 receives the input of the output value “1” from the logic gate 530, the output circuit 532 outputs “1” for a certain period of time.

According to the above-mentioned logic, when the interconnection between the generator G and the backbone system 6 is interrupted by any of the circuit breakers CB, and an abnormality is detected by each relay element (a failure has occurred in the power system 4). ), A lock signal is output (that is, "1" is output from the output circuit 532).

<Enable PSS function>
Next, a method for enabling the PSS function according to the present embodiment will be described. Specifically, the PSS valid determination method by the central control device 80 and the PSS valid output method by the output control device 20 will be described.

FIG. 5 is a diagram for explaining a PSS validity determination method according to the present embodiment. FIG. 6 is a diagram for explaining a PSS effective output method according to the present embodiment.

With reference to FIG. 5, the operations of the open state detection elements 500A to 500D and 502A to 502C are the same as the operations described with reference to FIG. 3, and therefore the detailed description thereof will not be repeated.

The central controller 80 includes a logic gate 610 and a valid determination output element 612. The logic gate 610 performs an AND operation of each value in which the logic levels of the outputs of the open state detection elements 500A to 500D and 502A to 502C are inverted. The logic gate 610 outputs the calculation result to the valid determination output element 612.

When the valid determination output element 612 receives the input of "1" from the logic gate 610, the output value "1" is output to the output control device 20 (the logic gate 624 of FIG. 6), and the logic gate 610 to "0". When the input of "" is received, the output value "0" is output to the output control device 20.

With reference to FIG. 6, the output control device 20 outputs the underfrequency relay element 518, the overfrequency relay element 520, the logic gate 620, the on-delay timer 622, the logic gate 624, the on-delay timer 626, and the output. Includes circuit 628. Since the operation of the under-frequency relay element 518 and the over-frequency relay element 520 is the same as the operation described with reference to FIG. 4, the detailed description thereof will not be repeated.

The logic gate 620 performs an AND operation of each value obtained by inverting the logic level of each output of the underfrequency relay element 518 and the overfrequency relay element 520, and outputs the operation result to the on-delay timer 622.

The on-delay timer 622 outputs an output value “1” to the logic gate 624 when the output value “1” from the logic gate 620 is maintained for the time T4. The time T4 is set to a time during which the frequency of the bus 2D can be considered to be stable.

The logic gate 624 performs an AND operation on each output value of the valid determination output element 612 and the on-delay timer 622, and outputs the calculation result to the on-delay timer 626. The on-delay timer 626 outputs an output value “1” to the logic gate 628 to the output circuit 628 when the output value “1” from the logic gate 624 is maintained for the time T5. The logic gate 628 outputs "1" for a certain period of time when the output circuit 628 receives an input of an output value "1" from the on-delay timer 626.

According to the above-mentioned logic, when the interconnection between the generator G and the backbone system 6 is not interrupted by each circuit breaker CB, and no abnormality is detected by each relay element (a failure has occurred in the power system 4). If not), a valid signal for enabling the PSS function is output (that is, "1" is output from the output circuit 628).

<Functional configuration>
FIG. 7 is a schematic diagram showing a functional configuration of the system stabilization system 1000 according to the present embodiment. With reference to FIG. 7, the terminal device 10 includes an open / close state detection unit 110 and an open / close information transmission unit 120. The central control device 80 includes an open / close information receiving unit 810, a state determination unit 820, and a determination result transmission unit 830. The output control device 20 includes a determination result receiving unit 210, an electric energy acquisition unit 220, a failure determination unit 230, and an output control unit 240. Each of these functions is realized, for example, by the CPU of the arithmetic processing unit of each device executing a program stored in the ROM. Note that some or all of these functions may be configured to be realized by hardware.

The open / closed state detection unit 110 of the terminal device 10 detects the open / closed state of each circuit breaker CB via the DI circuit. The open / close state detection unit 110 detects whether each circuit breaker CB is in the open state or the closed state (that is, the closed state). The open / close information transmission unit 120 transmits information (open / close information) indicating an open / closed state, which is a detection result, to the central control device 80 via the communication interface. The open / close state detection unit 110 and the open / close information transmission unit 120 of the terminal device 10A correspond to, for example, the open state detection element 500A and the open state detection element 502A in FIG.

The opening / closing information receiving unit 810 of the central control device 80 receives the opening / closing information transmitted from each terminal device 10 via the communication interface. The state determination unit 820 determines whether or not any of the circuit breakers CB is in the open state based on the open / closed state of each circuit breaker CB. The determination result transmission unit 830 uses the communication interface to determine the determination result of the state determination unit 820 (the determination result that any of the circuit breakers CB is in the open state, or all of the circuit breakers CB. (Result of determination that is in the closed state) is transmitted to the output control device 20.

The open / close information receiving unit 810 and the state determination unit 820 correspond to, for example, the logic gate 510 in FIG. 3 and the logic gate 610 in FIG. The determination result transmission unit 830 corresponds to, for example, the lock determination output element 512 in FIG. 3 and the valid determination output element 612 in FIG.

The determination result receiving unit 210 of the output control device 20 receives the determination result transmitted from the central control device 80 via the communication interface. The electric energy acquisition unit 220 acquires the electric energy via the current transformer CT for the instrument and the transformer VT for the instrument. Specifically, the electric energy acquisition unit 220 acquires the current of the line Lg between the bus 2D and the generator G via the current transformer CT for the instrument, and obtains the voltage of the bus 2D for the voltage transformer VT. Get through.

The failure determination unit 230 determines whether or not a failure has occurred in the power system 4 by executing a relay calculation based on the acquired electric energy. Specifically, the failure determination unit 230 has an active power change rate relay that operates when the change rate of the passing active power of the bus 2D of the power plant 102 is abnormal, and the magnitude of the frequency F of the voltage of the bus 2D. It includes a frequency relay that operates when it is abnormal and a frequency change rate relay that operates when the rate of change of frequency F is abnormal. The frequency relay includes a shortage frequency relay that operates when the frequency F becomes less than the set frequency F1 and an overfrequency relay that operates when the frequency F becomes the set frequency F2 or more. That is, the frequency relay operates when the frequency F deviates from the settling range (F1 ≦ F <F2).

The failure determination unit 230 determines that a failure has occurred in the power system 4 when at least one of the active power change rate relay, the frequency relay, and the frequency change rate relay operates. Further, the failure determination unit 230 causes a failure in the power system 4 when the time during which the frequency relay does not operate (the time during which no frequency abnormality has occurred) exceeds a predetermined time (for example, time T4). Judge that it is not done.

The output control unit 240 locks or enables the system stabilization signal output by the PSS 32 based on the determination result of the open / closed state of each circuit breaker. Specifically, in a certain aspect, the output control unit 240 locks the system stabilization signal output by the PSS 32 at least based on the determination result that one of the circuit breakers CB is in the open state. To do. In this case, the output control unit 240 outputs the lock signal to the excitation control device 30. In another aspect, the output control unit 240 enables the system stabilization signal output based on the determination result that each circuit breaker CB is in the closed state (that is, the system stabilization signal is locked). If so, unlock the lock). In this case, the output control unit 240 outputs an effective signal to the excitation control device 30.

The output control unit 240 is configured to lock or enable the system stabilization signal output by the PSS 32 in consideration of the determination result by the failure determination unit 230 in addition to the determination result of the open / closed state of each circuit breaker CB. There may be. Specifically, in a certain situation, the output control unit 240 determines that one of the circuit breakers CB is in the open state, and that the power system 4 has a failure. If so, lock the grid stabilization signal output. In this case, the output control unit 240 outputs the lock signal to the excitation control device 30. In another aspect, when the system stabilization signal output of the PSS 32 is locked, the output control unit 240 determines that all the circuit breakers CB are in the closed state, and no failure has occurred in the power system 4. When it is determined that, the system stabilization signal output is enabled.

Further, referring to FIGS. 4, 6 and 7, the determination result receiving unit 210 corresponds to, for example, the logic gates 530 and 624. The failure determination unit 230 includes, for example, an active power change rate relay element 514, an underfrequency relay element 518, an overfrequency relay element 520, a frequency change rate relay element 522, an off-delay timer 516,524,528, an on-delay timer 622, and Corresponds to logic gates 526,620. The output control unit 240 corresponds to, for example, the logic gates 530 and 624, the on-delay timer 626, and the output circuits 532 and 628.

<Processing procedure>
FIG. 8 is a flowchart showing an example of a processing procedure of the system stabilization system 1000 according to the present embodiment. Typically, each step shown in FIG. 8 is performed by the CPU of each device.

With reference to FIG. 8, the terminal device 10 detects the open / closed state of each circuit breaker CB (step S10), and transmits the open / close information indicating the open / closed state to the central control device 80 (step S12).

The central control device 80 receives information indicating the open / closed state of each circuit breaker CB from each terminal device 10 (step S14), and determines whether or not all the circuit breaker CBs are in the closed state based on the information. (Step S16).

When all the circuit breakers CB are in the closed state (YES in step S16), the central controller 80 determines that all the circuit breakers are in the closed state (the generator G and the backbone system 6 are connected). The determination result that the system is connected) is transmitted to the output control device 20 (step S18). If this is not the case (NO in step S16), the central controller 80 determines that one of the circuit breakers is in the open state (the connection between the generator G and the backbone system 6 is cut off). The determination result) is transmitted to the output control device 20 (step S20).

The output control device 20 acquires the amount of electricity via the current transformer CT for the instrument and the transformer VT for the instrument (step S22), and receives the determination result transmitted from the central control device 80 (step S24).

The output control device 20 determines whether or not it has received the determination result that the interconnection between the generator G and the backbone system 6 is cut off (step S26). When the determination result is received (YES in step S26), the output control device 20 determines whether or not a failure has occurred in the power system 4 based on the amount of electricity (step S28). When a failure has occurred (that is, when the interconnection between the generator G and the backbone system 6 has been interrupted and a failure has occurred) (YES in step S28), the output control device 20 has , The lock signal for locking the system stabilization signal is output to the excitation control device 30 (step S30). On the other hand, if no failure has occurred (NO in step S28), the output control device 20 ends the process. In this case, the output control device 20 does not output the lock signal.

On the other hand, when the determination result that the generator G and the backbone system 6 are connected is received (NO in step S26), the output control device 20 uses the electric power system based on the amount of electricity. In step 4, it is determined whether or not a failure has occurred (step S32). When no failure has occurred (that is, when the generator G and the backbone system 6 are connected and no failure has occurred) (NO in step S32), the output control device 20 is connected to the system. An effective signal for validating the stabilization signal is output to the excitation control device 30 (step S34). On the other hand, if a failure has occurred (YES in step S32), the output control device 20 ends the process. In this case, the output control device 20 does not output an effective signal.

<Advantage>
According to this embodiment, not only the opening / closing information of the circuit breaker CBd1 connected to the bus 2D in the power plant 102 but also the bus 2A to 2C in each electric station 100A to 100C away from the power plant 102. It is determined whether or not the interconnection between the generator G and the backbone system 6 is interrupted in consideration of the opening / closing information of each circuit breaker CBa1 to CBc2. Therefore, since the disconnection of the interconnection between the generator G and the main system 6 can be accurately grasped at each point of the transmission line L, the PSS can be quickly locked when the power generation side becomes a single system. As a result, it is possible to prevent a voltage rise due to PSS-free operation when a single system is generated. Further, when the generator G is connected to the main system, the stability of the power system can be maintained by promptly enabling the PSS.

Further, according to the present embodiment, the PSS can be locked and enabled regardless of the output of the generator G.

Further, according to the present embodiment, the PSS can be locked and enabled in consideration of the presence or absence of a failure in the power system 4. According to this, it is possible to prevent unnecessary PSS from being locked when the power system 4 has not failed, and to prevent unnecessary PSS from being activated when the power system 4 has a failure. it can.

[Other embodiments]
In the above-described embodiment, the output control device 20 describes a configuration in which the active power change rate relay, the frequency relay, and the frequency change rate relay are used when determining the presence or absence of a failure in the power system 4. However, the configuration is not limited to this. For example, the output control device 20 may use at least one of the three relays to perform a determination of the presence or absence of a failure. Further, the type of relay is not limited to the above, and the output control device 20 includes an overvoltage relay that operates when the bus 2D exceeds the set voltage, and an undervoltage relay that operates when the bus 2D falls below the set voltage. It may be used to execute a failure determination.

In the above-described embodiment, the central control device 80 and the output control device 20 have been described as separate devices, but they may be configured as an integrated device. In this case, the control device in which the central control device 80 and the output control device 20 are integrated has each of these functions. Typically, the control device includes an open / close information receiving unit 810, a state determination unit 820, an electric energy acquisition unit 220, a failure determination unit 230, and an output control unit 240 in FIG. 7. In this case, the control device is provided in the power plant 102.

Further, the terminal device 10D and the output control device 20 may be configured as an integrated device. In this case, the device typically includes an open / closed state detection unit 110, a state determination unit 820, and a determination result transmission unit 830 in FIG. 7.

Further, in the above-described embodiment, the terminal device 10D, the central control device 80, and the output control device 20 may be configured as an integrated control device. In this case, the control device includes an open / closed state detection unit 110, a state determination unit 820, an electric energy acquisition unit 220, a failure determination unit 230, and an output control unit 240 in FIG. 7.

The configuration exemplified as the above-described embodiment is an example of the configuration of the present invention, and can be combined with another known technique, and a part thereof may be omitted without departing from the gist of the present invention. , Can be modified and configured.

Further, in the above-described embodiment, the process or configuration described in the other embodiments may be appropriately adopted and implemented.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims, not the above description, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

2A, 2B, 2C, 2D bus, 4 power system, 6 backbone system, 10 terminal device, 20 output control device, 30 excitation control device, 40 field winding, 50 auxiliary transformer, 60 AD converter, 70 arithmetic processing Unit, 71 bus, 72 CPU, 73 ROM, 74 RAM, 75 DI circuit, 76 DO circuit, 77 input interface, 80 central controller, 100A-100C electric station, 102 power plant, 110 open / close state detector, 120 open / close information Transmitter, 210 Judgment result receiver, 220 Electricity acquisition unit, 230 Failure judgment unit, 240 Output control unit, 512 Lock judgment output element, 514 Active power change rate relay element, 516,524,528 Off delay timer, 518 Insufficient Frequency relay element, 520 over-frequency relay element, 522 frequency change rate relay element, 532,628 output circuit, 612 valid judgment output element, 622,626 on-delay timer, 810 open / close information receiver, 820 status judgment part, 830 judgment result Transmitter, 1000 system stabilization system, transformer for CT instrument, G generator, L transmission line, Lg line, TRa, TRb, TRc transformer, TRm main transformer, transformer for VT instrument.

Claims (3)

A system stabilization system for a power system having a generator provided in a power plant and a transmission line for connecting the generator to another power system.
The generator has one or more first circuit breakers that open and close between each of the bus bars of one or more electric stations and the transmission line, and a second circuit breaker that opens and closes between the bus bar of the power plant and the transmission line. It is connected to the other power system via a circuit breaker.
A detection means for detecting the open / closed state of each of the one or more first circuit breakers and the second circuit breaker.
Any one of the one or more first circuit breakers and the second circuit breaker based on the open / closed state of each of the one or more first circuit breakers and the second circuit breakers detected by the detection means. A state judgment means for determining whether or not the circuit breaker has been opened, and
The electric power provided in the power plant based on the determination result of the state determining means that any one of the one or more first circuit breakers and the second circuit breaker is in the open state. e Bei and an output control means for locking the system stabilizing the signal output by the PSS (power system stabilizer) for suppressing agitation of the system,
In the output control means, one or more of the first circuit breakers and the second circuit breaker are in an open state, and the rate of change of the active power passing through the bus of the power plant is changed. The first relay that operates when there is an abnormality, the second relay that operates when the magnitude of the frequency of the bus voltage of the power plant is abnormal, and the rate of change in the frequency of the bus voltage of the power plant are abnormal. A system stabilization system that locks the system stabilization signal output when at least one of the third relays that operates in the above case operates. The output control means, before Symbol 1 or more first circuit breaker and said second breaker it closed der, and reaches or exceeds the time period for the second relay does not operate the predetermined If, to enable the system stabilizing the signal output, the system stabilizing system according to claim 1. A system stabilization system for a power system having a generator provided in a power plant and a transmission line for connecting the generator to another power system.
The generator has one or more first circuit breakers that open and close between each of the bus bars of one or more electric stations and the transmission line, and a second circuit breaker that opens and closes between the bus bar of the power plant and the transmission line. It is connected to the other power system via a circuit breaker.
A detection means for detecting the open / closed state of each of the one or more first circuit breakers and the second circuit breaker.
Any one of the one or more first circuit breakers and the second circuit breaker based on the open / closed state of each of the one or more first circuit breakers and the second circuit breakers detected by the detection means. A state judgment means for determining whether or not the circuit breaker has been opened, and
The electric power provided in the power plant based on the determination result of the state determining means that any one of the one or more first circuit breakers and the second circuit breaker is in the open state. It is equipped with an output control means that locks the system stabilization signal output by a PSS (power system stabilizer) to suppress system sway.
The output control means is a relay that operates when the one or more first circuit breakers and the second circuit breaker are in a closed state and the frequency magnitude of the bus voltage of the power plant is abnormal. A system stabilization system that enables the system stabilization signal output when the non-operation time exceeds a predetermined time.