JP6836065B2 - Information processing device, PLD management program and PLD management method - Google Patents

Description

The present invention relates to an information processing device, a PLD management program, and a PLD management method.

A programmable logic device (hereinafter referred to as PLD) is an integrated circuit in which a plurality of logic circuit elements, memory circuit elements, wirings, switches, etc. are formed in advance, and a circuit capable of executing a predetermined process is configured. When the configuration data is set or written, the circuit that can execute the predetermined process is reconfigured. Such a PLD is, for example, an FPGA (Field Programmable Gate Array), and is an LSI capable of reconfiguring an internal circuit into various logic circuits by rewriting the configuration data. Hereinafter, FPAG, which is one of the PLDs, will be described as an example.

When a processor executes a predetermined process of software (for example, a job) in a dedicated circuit of hardware, the processor sets or writes configuration data for configuring the dedicated circuit in the FPGA and sets the dedicated circuit in the FPGA. Configure and let the dedicated circuit perform a given process. In addition, when the dedicated circuit finishes the predetermined processing, the configuration data of another dedicated circuit that executes different processing is set or written to the FPGA to configure another dedicated circuit in the FPGA, and the configuration data is changed to another dedicated circuit. Let the process be executed. The FPGA is used as the accelerator of the processor by causing the processor to execute the predetermined processing of the software in the dedicated circuit of the FPGA. As a result, the information processing device (computer) having a processor can be made power-saving and highly functional.

With the increase in the scale of FPGA, it is possible to configure multiple logic circuits in the FPGA and operate multiple logic circuits in parallel. In addition, while operating multiple logic circuits configured in the FPGA, some logic circuits are reconfigured to start the operation of new logic circuits, and multiple logic circuits are dynamically reconfigured asynchronously. It can be configured and operated asynchronously and in parallel.

The configuration of a plurality of circuits in an FPGA is disclosed in the following patent documents. Patent Document 5 is a prior application, but is not a known example.

Japanese Unexamined Patent Publication No. 2015-154417 Japanese Unexamined Patent Publication No. 2004-32043 Japanese Unexamined Patent Publication No. 2016-76867 JP-A-2015-231205 Japanese Patent Application No. 2016-248297

On the other hand, when a plurality of users use an information processing device equipped with a processor and an FPGA, a plurality of logic circuits configured in the FPGA may process specific processes of the programs of the plurality of users. In that case, the programs of multiple users configure each logic circuit in the FPGA without being aware of each other's logic circuits, and the configured logic circuits partially and dynamically share the FPGA. To do. As a result, the used bandwidth of the bus between the FPGA and the memory may reach the upper limit of the bus bandwidth, causing a bottleneck in the bus bandwidth.

When a bottleneck occurs in the bus band, it is conceivable to reduce the degree of parallelism of a predetermined logic circuit and instead increase the degree of parallelism of another logic circuit to suppress deterioration of the overall execution time. The reduction in execution time when the degree of parallelism is increased differs depending on the type of logic circuit.

Therefore, an object of the present invention is to provide an information processing device, a PLD management program, and a PLD management method for improving the efficiency of using PLD circuit resources.

The first aspect of the embodiment is a processor that executes the program and
A programmable logic circuit device (hereinafter referred to as PLD) having a reconfiguration area for configuring a logic circuit required by the configuration request in response to a configuration request from the processor.
The processor
Of the plurality of logic circuits configured and operating in the reconfiguration area, the parallel degree adjustment for lowering the parallelism of the first logic circuit and increasing the parallelism of the second logic circuit is performed. The first execution time of the plurality of logic circuits is compared with the second execution time of the plurality of logic circuits when the degree of parallelism adjustment is not performed.
If the first execution time is shorter than the second execution time, the PLD is requested to adjust the degree of parallelism, and if it is not short, the PLD is not requested to adjust the degree of parallelism. is there.

According to the first aspect, the efficiency of using the circuit resources of the PLD can be improved.

It is a figure which shows the configuration example of the information processing apparatus in this embodiment. It is a figure which shows the configuration example of FPGA. It is a figure which shows an example of the reconfiguration area of FPGA. It is a figure explaining an example that the logic circuit of a plurality of users is dynamically configured and deleted. It is a figure which shows the control example of the degree of parallelism of the logic circuit configured in FPGA. It is a figure explaining the bottleneck of the bus bandwidth in FPGA. It is a figure which shows the control example of the degree of parallelism by the FPGA management method in 1st Embodiment. It is a figure explaining the execution time in the case of a CI processing circuit. It is a figure which shows the difference of the execution time of a CI processing circuit when the degree of parallelism Pi is changed. It is a flowchart of the FPGA management program in 1st Embodiment. It is a figure which shows the parameter of the user circuit managed by a processor. It is a flowchart of the parallel degree adjustment process S8 of a user circuit. It is a flowchart which shows the process which increases the degree of parallelism of process S13A. It is a figure which shows the detailed flowchart of the process S15, S15B, S15C, S15D of FIG. It is a flowchart which shows the process of process S17. It is a figure which shows the 1st concrete example. It is a figure which shows the 2nd specific example.

FIG. 1 is a diagram showing a configuration example of an information processing device according to the present embodiment. The server 10 which is an information processing device connects a processor or CPU (Central Processing Unit) 11 that executes an OS, an application program, or a middleware program, and a first bus BUS_1 such as a CPU bus that connects a main memory 12 such as a DRAM. Have. Further, the server 10 stores an I / O device (13) such as a mouse, a keyboard, and a display panel, a NIC (Network Interface Card) 14 connected to the network NET, an OS, an application program APL, and data DATA. It has an auxiliary storage device 17 such as an HDD (Hard Disk Drive) and an SSD (Solid State Drive). Then, they are connected to the first bus BUS_1 via a second bus BUS_2 such as a PCI bus.

Further, the server 10 has a PLD (Programmable Logic Drive) 15 capable of reconfiguring an arbitrary logic circuit, a memory 16 for storing PLD configuration data and the like, and a third bus BUS_3 which is a bus connecting them. Has. The PLD is, for example, an FPGA, the memory 16 is a memory for FPGA, and the third bus is an FPGA bus.

For example, when the job management program of the OS executed by the CPU 11 detects a job that can be processed by the logic circuit in the FPGA in the running application program, the CPU outputs the configuration data for configuring the logic circuit. Write (or configure) the logic in the FPGA to configure the logic and execute the logic.

The auxiliary storage device 17 stores the FPGA management program that manages the FPGA and the configuration data C_DATA that configures the logic circuit. When the server 10 starts up, the OS, application APL, and FPGA management program in the auxiliary storage device are expanded in the main memory 12 and executed by the processor 11. In addition, the configuration data C_DATA in the auxiliary storage device is expanded in the FPGA memory.

Since the FPGA 15 can configure various logic circuits by changing the configuration data, even after the server 10 is manufactured, the processing of various jobs can be performed in the FPGA by changing the configuration data. It can be processed at high speed with the logic circuit configured in.

In a cloud service or the like, a plurality of users execute their respective application programs on the server 10. As a result, the processor 11 of the server 10 executes the application programs of a plurality of users in parallel. Then, a logic circuit that executes a predetermined process (job) of each application program is asynchronously constructed in the FPGA 15, and a plurality of constructed logic circuits (user circuits) operate in parallel to perform each predetermined process. Execute (job).

FIG. 2 is a diagram showing an example of FPGA configuration. The FPGA 15 in FIG. 2 includes a bus interface circuit BUS_IF with the third bus BUS_3 of the FPGA, a control circuit 151 that controls writing of configuration data and other controls, and a configuration data memory C_RAM to which configuration data is written. , It has a reconfiguration area RC_REG in which various logic circuits are reconfigured by the written configuration data, and an internal bus I_BUS.

Although not shown, a plurality of logic circuit elements, memory circuit elements, wirings, switches, etc. are formed in advance in the reconfiguration area RC_REG. In addition, the reconfiguration area RC_REG is divided into a plurality of logically or physically divided partial reconfiguration blocks PB. Then, the logic circuit to be reconfigured is configured in each one or a plurality of partial reconfiguration blocks with the circuit block accommodated in each partial reconfiguration block PB as a configuration unit. Therefore, for example, the configuration data memory C_RAM is divided into a plurality of storage areas corresponding to a plurality of partial reconfiguration blocks PB, and when the configuration data C_DATA is written to each storage area, the portion corresponding to the storage area. Each logic circuit is configured in the reconfiguration block PB.

Further, a logic circuit (user circuit) that executes a certain job may be configured in a plurality of partial reconfiguration blocks PB. In that case, the configuration data for configuring the logic circuit is written in the storage area corresponding to the multiple functional block areas, and the multiple circuits configured in each partial reconfiguration block of the above-mentioned job. A logic circuit (user circuit) that executes processing is configured.

As described above, the reconfiguration area RC_REG in the FPGA is configured with multiple partial reconfiguration blocks PB. Then, the logic circuit that executes a predetermined process (job) in each user's application program is configured in a single partial reconfiguration block PB or in a plurality of partial reconfiguration block PBs. It may be done.

Input data is input from the CPU to the logic circuit configured in the reconfiguration area RC_REG via the bus interface BUS_IF, and the processing result of the input data is output to the CPU. Further, the plurality of logic circuits configured in the reconfiguration area RC_REG transmit and receive operating data to and from the FPGA memory 16 via the internal bus I_BUS, the bus interface BUS_IF, and the FPGA bus BUS_3.

FIG. 3 is a diagram showing an example of the reconfiguration area of the FPGA. As shown in FIG. 2, the reconfiguration area RC_REG is divided into a plurality of partial reconfiguration blocks PB arranged in a matrix. Further, the reconfiguration area RC_REG is configured for data transfer between a plurality of logic circuits configured in a plurality of partial reconfiguration block PBs, and in the bus interface BUS_IF and the partial reconfiguration block PB in FIG. It has an operation circuit OC for data transfer to and from a logic circuit. The operation circuit OC includes network wiring, a network switch, a routing circuit, and the like.

In the example of FIG. 3, the logic circuit UC_A of user A is configured by the circuit configured in the 3 × 3 partial reconfiguration block PB on the left side of the plurality of partial reconfiguration block PBs, and the logic circuit UC_A on the right side is 2 The logic circuit UC_B of user B is configured by the circuit configured in the partial reconfiguration block PB of × 4. Also, eight partially reconfigured blocks PB with no circuit configured are shown colorless.

FIG. 4 is a diagram illustrating an example in which logic circuits of a plurality of users are dynamically configured and deleted. At time T1, no logic circuit is configured in the reconfiguration area RC_REG in the FPGA. Next, at time T2, the logic circuit of user A is configured in the two partial reconfiguration blocks and starts executing the job. After that, at time T3, the logic circuit of user B is configured in six partial reconfiguration blocks and starts execution. After time T3, the logic circuit of user A completes the process, and at time T4, the logic circuit of user C is configured in four partial reconfiguration blocks and starts execution. After that, at time T5, the logic circuit of user B finishes processing, and at time T6, the logic circuit of user D is configured in four partial reconfiguration blocks and starts execution. When the processing of each configured logic circuit is completed, for example, the partial reconfiguration block in which the logic circuit was configured is released, and the other logic circuits are released in a configurable state. In that case, for example, the configuration data in the configuration data memory C_RAM is not deleted until another logic circuit is configured in the released partial reconfiguration block, and the same logic circuit configuration request is made again. When it occurs, the configured logic circuit is activated.

As shown in FIG. 4, different logic circuits of the same user or different users are asynchronously configured in the reconfiguration area of the FPGA, and the configured logic circuits execute the job. Then, the FPGA management program in the server 10 described above controls to reconfigure the logic circuit in the FPGA.

FIG. 5 is a diagram showing a control example of the degree of parallelism of the logic circuit configured in the FPGA. A logic circuit is configured in the FPGA, which is one of the PLDs, by setting the configuration data, and the logic circuit executes the job and has the function of the accelerator of the CPU. However, since the logic circuit in the FPGA is configured by the lookup table or switching circuit reconfigured with the configuration data, the operating speed is lower than that of a normal custom integrated circuit. Therefore, as one method for using the logic circuit in the FPGA as an accelerator of the CPU, it is conceivable to configure a plurality of the same logic circuits in the FPGA and operate them in parallel with the plurality of logic circuits.

For example, when a processor that executes an FPGA management program configures a logic circuit that executes processing of a certain job in the FPGA, if there is space in the reconfiguration area RC_REG, the same logic circuit should be configured multiple times. Controls the FPGA and causes multiple same logic circuits to execute jobs in parallel.

In the example of FIG. 5, at time T11, the processor executing the FPGA management program configures user A's logic circuit UC_A into six partial reconfiguration blocks and user B's logic circuit UC_B into two parts. Configure in the reconfiguration block. Then, at the subsequent time T12, the processor configures the logic circuit UC_B2 of the second user B into two partial reconfiguration blocks, and causes the two logic circuits UC_B and UC_B2 to perform parallel operations. Similarly, at time T13, the processor configures the second user A's logic circuit UC_A2 into six partial reconfiguration blocks, causing the two logic circuits UC_A and UC_A2 to operate in parallel. As a result, the operating speed of the logic circuit in the FPGA can be increased.

For example, if the user's logic circuit is an adder and one adder completes the operation in N cycles, if two adders are configured and the addition operation is performed in parallel, the operation is performed in N / 2 cycles. To complete. This is an example of increasing the degree of parallelism of logic circuits and shortening the job execution time.

[Bus band bottleneck]
FIG. 6 is a diagram illustrating a bus bandwidth bottleneck in FPGA. The logic circuit configured in the FPGA accesses the FPGA memory 16 shown in FIGS. 1 and 2 via the FPGA bus BUS_3. The FPGA memory 16 stores the configuration data of the reconfigured logic circuit and the data accessed by the configured logic circuit. Therefore, when the processor that executes the FPGA management program requests the configuration of the logic circuit in the FPGA, the control circuit in the FPGA accesses the memory for FPGA and downloads the configuration data of the logic circuit. Furthermore, when the logic circuits configured in the FPGA execute each job, each logic circuit accesses the data stored in the memory for FPGA. Therefore, the logic circuit configured in the PFGA uses the band corresponding to each data transfer amount among the bands that can be provided by the FPGA bus BUS_3.

In the example of FIG. 6, at time T21, the user circuits UC_1, UC_3, and UC_4 of the users 1, 3 and 4 are configured with the degree of parallelism 1 in the reconfiguration area RC_REG of the FPGA, and the user circuit UC2 of the user 2 is set. It is configured with a degree of parallelism of 2. The bandwidth that can be provided by the FPGA bus BUS_3 (upper limit of the data transfer amount) is, for example, 1350MB / S, and the average data transfer amount of the user circuits UC_1, UC_2, UC_3, and UC_4 of users 1, 2, 3, and 4 is 100MB, respectively. / S, 200MB / S, 200MB / S, 300MB / S. In the state of FIG. 6, the total value of the average data transfer amount of the configured user circuits UC_1 to UC_4 is 100 + 200 * 2 + 200 + 300 = 1000MB / S. Therefore, the total value of 1000MB / S has not reached the upper limit of 1350MB / S. In this state, there is no bottleneck in FPGA bus BUS_3, each user circuit operates with the predicted data transfer amount, and the job execution time is also the predicted execution time.

On the other hand, at time T22, the processor executing the FPGA management program requests the control circuit of the FPGA to increase the parallelism of the logic circuit UC_2 of the user 2 to 4, and the parallelism of the logic circuit UC_2 is increased to 4. There is. In this case, the processor has a space in the partial reconfiguration block required to increase the degree of parallelism of the logic circuit UC_2 to 4 in the reconfiguration area, and the prediction of the data transfer amount of the logic circuit UC_2 is low. Therefore, it is considered that it was predicted that the upper limit of the bus bandwidth would not be exceeded even if the degree of parallelism was increased to 4.

However, in reality, the total amount of data transferred in the operating logic circuit is 100 + 200 * 4 + 200 + 300 = 1400MB / S, which exceeds the upper limit of 1350MB / S on the FPGA bus, and the PFGA bus A bottleneck may occur in the band. As a result, the logic circuit UC_2 of user 2 whose degree of parallelism has been increased to 4 cannot use the band required for job execution, and the execution time of one job by the logic circuit UC_2 of user 2 is predicted. It will be longer than the execution time.

As mentioned above, if there is space in the partial reconfiguration block in the reconfiguration area RC_REG in the FPGA, even if the degree of parallelism of the logic circuit is increased, the bandwidth of the FPGA bus is insufficient and the data transfer amount of the logic circuit The total value of may reach the upper limit of the bus bandwidth, causing a bottleneck in the bus bandwidth. As a result, the performance of the logic circuit with the increased degree of parallelism does not improve, and the partial reconfiguration block in the reconfiguration area is wasted.

[First Embodiment]
FIG. 7 is a diagram showing an example of controlling the degree of parallelism by the FPGA management method in the first embodiment. In this FPGA management method, the user's logic circuit has an execution time measurement circuit that measures the execution time required to execute one job, and the data transfer amount per unit time of bus access by monitoring access to the FPGA bus. A data transfer amount measuring circuit for measuring the average value of is included. These measurement circuits can be configured by the FPGA configuration data. Then, in the FPGA control circuit, when the user's logic circuit is configured with the configuration data, the measurement circuit is also configured with the configuration data at the same time. Alternatively, the measurement circuit may be formed in the partial reconfiguration block in advance and used as the measurement circuit of the logic circuit configured in the partial reconfiguration block.

Then, the processor that executes the FPGA management program acquires the measured value of the data transfer amount of the plurality of logic circuits that are configured and operating in the reconfiguration area in the FPGA, and obtains the measured value of the acquired data transfer amount. Increase the number of parallels of each of the multiple logic circuits configured in the reconfiguration area within the range where the total does not exceed the upper limit of the data transfer amount of the FPGA bus.

Further, in the first embodiment, the processor satisfies a predetermined condition among the plurality of logic circuits when the total of the measured values of the acquired data transfer amount reaches the upper limit value of the data transfer amount of the FPGA bus. Reduce the degree of parallelism of logic circuits. Then, the processor increases the degree of parallelism of any of the logic circuits other than the logic circuit in which the degree of parallelism is reduced within a range not exceeding the upper limit of the data transfer amount of the FPGA bus. As a result, it can be expected that the operation of the logic circuit with the increased degree of parallelism will be completed in a shorter time than expected. After the operation of another logic circuit having an increased degree of parallelism is completed, the processor increases the degree of parallelism of the logic circuit having a decreased degree of parallelism within a range not exceeding the upper limit value. As a result, it can be expected that the operation of the logic circuit will be completed in a shorter time than expected.

Explaining with the example of FIG. 7, the processor acquires the measured value of the data transfer amount of the logic circuit operating in the state of time T22 of FIG. 6, and the total value reaches the limit value of the FPGA bus. To detect. As a result, as shown at time T23 in FIG. 7, the processor reduces the degree of parallelism of the user 2 logic circuit UC_2, which is considered to be the cause of the bus bottleneck, from 4 to 2. After that, the degree of parallelism of the logic circuit UC_1 of the user 1 whose data transfer amount of the logic circuit is low is increased from 1 to 4. As a result, the total measured value of the data transfer amount of the operating logic circuit becomes 100 * 4 + 200 * 2 + 200 + 300 = 1300MB / S, which is less than the upper limit of FPGA bus 1350MB / S, and the bus band. The bottleneck is eliminated.

As a result, it is predicted that the operation time of the logic circuit UC_1 of the user 1 will be shortened and the operation will be completed in a short time. Then, as shown in time T24, when the operation of the logic circuit UC_1 of the user 1 is completed, the processor preferentially increases the logic circuit UC_2 of the user 2 whose degree of parallelism is reduced from the degree of parallelism 2 to 4. Then, the processor acquires the measured value of the data transfer amount of the operating logic circuit, and the total of the measured values 200 * 4 + 200 + 300 = 1300MB / S is less than the upper limit value 1350MB / S of the FPGA bus. To detect. Even in this state, the bottleneck of the bus band is eliminated, and the logic circuit can operate sufficiently.

[Data processing types CI and DI]
When the degree of parallelism of the user circuit UC_1 is increased at the time T23 in FIG. 7, the degree of shortening of the execution time differs depending on the data processing pattern of the user circuit UC_1. For example, there are two types of data processing patterns: Data Intensive (DI) and Computation Intensive (CI). Generally, in the case of a DI processing circuit, increasing the degree of parallelism shortens the execution time proportionally, but in the case of a CI processing circuit, even if the degree of parallelism is increased, the reduction in execution time may be small.

In the case of a DI processing circuit, while the circuit is operating, data read (load) and data write (store) always occur, and the operation rate of the load store unit (LSU) that accesses the memory in the user circuit is high, and the bus The bandwidth used for is also high. Therefore, it causes a bus bottleneck. When a bus bottleneck occurs, the performance of the DI processing circuit deteriorates and the job execution time tends to be long. Further, in the DI processing circuit, the execution time is generally shortened to 1 / N times when the degree of parallelism is increased by N times.

On the other hand, in the case of a CI processing circuit, memory access occurs at the beginning and end of the circuit operation. That is, the input data required for data processing is read from the memory at the beginning of the circuit operation, and the output data after the data processing is written to the memory at the end of the circuit operation. Memory access rarely occurs during data processing. Therefore, the CI processing circuit does not use the bus bandwidth for a relatively long time, the bus bandwidth is small, the performance of the CI processing circuit does not deteriorate even if a bus bottleneck occurs, and the job execution time does not change much. Absent. In addition, the CI processing circuit generally does not reduce the execution time even if the degree of parallelism is increased.

In the case of FIG. 7, when the logic circuit UC_1 of user 1 is a DI processing circuit at time T23, if the degree of parallelism is increased, the job execution time becomes shorter according to the rate of increase, while the logic circuit UC_1 performs CI processing. In the case of a circuit, increasing the degree of parallelism does not significantly reduce the job execution time. The reason for this is that the user circuit usually has a pipeline structure, and data processing is already parallelized in the pipeline structure. Therefore, in the case of a CI processing circuit, even if the degree of parallelism of the circuit is increased, the execution time is shortened only by the initiation interval of the pipeline. On the other hand, in the case of a DI processing circuit, if the degree of parallelism of the circuit is increased, the memory access during data processing is also parallelized. Normally, if the degree of parallelism is multiplied by N, the execution time is shortened to 1 / N.

FIG. 8 is a diagram illustrating an execution time in the case of a CI processing circuit. The execution time of the CI processing circuit is the above-mentioned number of executions N, the data set S processed by one execution, the input data load (read) time T _LD, and the output data store (write) time T _ST. It can be predicted by the processing time T _{COMP_SINGLE of one data set and the initiation interval T II} , which is the processing start interval of multiple data.

As shown in FIG. 8, the CI processing circuit performs the processing LD of loading the input data from the memory at the start of execution, pipelines the input data calculation processing COMP S times, and finally stores the output data in the memory. Execute process ST. Then, the pipeline processing of S times is started at the interval of the _{initiation interval T II.} The execution time of the calculation processing COMP of one data set is T _{COMP_SINGLE} , and the initiation interval T _II of the data set S times is Δi. As described above, in the CI processing circuit, the data load LD and the data store ST occur at the beginning and the end of the data processing, and the COMP hardly generates the memory access during the data processing.

Therefore, the i-th execution time Ti of the N execution times included in one job is as follows.
Ti ＝ T _LD ＋ Δi ＋ T _{COMP_SINGLE} ＋ T _ST formula 1
Here, Δi is _{(S-1) times T II} , so it is as follows.
Δi ＝ T _II * (S-1)

Further, assuming that the degree of parallelism of the CI processing circuit is Pi, Δi is shortened according to the degree of parallelism Pi as follows.
Δi ＝ T _II * {(S / Pi) -1}

FIG. 9 is a diagram showing a difference in execution time of the CI processing circuit when the degree of parallelism Pi is changed. In the example of FIG. 9, the data set S is S = 4. Then, Δ is shown when the degree of parallelism Pi is Pi = 1, Pi = 2, and Pi = S = 4. When Pi = 1, Δi = 3 * T _II , when Pi = 2, Δi = T _II , and when Pi = S = 4, Δi = 0.

As described above, the i-th execution time Ti in the case of the CI processing circuit is as follows according to the above equation 1 assuming the degree of parallelism Pi.

Since the memory access times T _LD and T _ST are sufficiently smaller than _{the data processing time, if the T LD} and T _ST are omitted from Equation 1, the execution time Ti is as follows.

Therefore, the difference in execution time (shortening time in the case of Pi <Pj) when the degree of parallelism Pi of the circuit is changed to Pj is as follows.

Further, in Equation 2, when the degree of parallelism of the CI processing circuit is set to the maximum Pi = S, the execution time Ti becomes the _{shortest execution time T min as follows.}

_{The total execution time T CI_total} of the number of executions N of the CI processing circuit is as follows, where the degree of parallelism at the time of the i-th execution is Pi.

In Formula 5 above, the total execution time and T _{CI_total_before} before the change when changing from the parallel score Pi to Pj, respectively total running time T _{CI_total_after} the changed parallelism of Formula 5 to Formula you Pi and Pj Become.

Furthermore, when the degree of parallelism Pi becomes the maximum value S (Pi = S) in all N executions (Pi = S in all the elements i of [1: N]), the total execution time is the following minimum value T. It becomes _{CI_total_min.}

Next, the degree of parallelism and the execution time of the DI processing circuit will be described. In the DI processing circuit, the data load LD and the data store ST also occur during the data processing COMP of each data set. Therefore, unlike the CI processing circuit, most of the execution time Ti of the DI processing circuit does not _{have the arithmetic processing time T COMP_SINGL.} Therefore, in the present embodiment, the DI processing circuit calculates the execution time on the assumption that the execution time is shortened to 1 / N times if the degree of parallelism is multiplied by N.

In the present embodiment, a bus bottleneck occurs, the degree of parallelism of a predetermined user circuit is reduced to eliminate the bus bottleneck, and instead, the degree of parallelism of a user circuit different from the predetermined user circuit is increased. However, the total execution time of all user circuits before _{parallel adjustment T total_before} and the total execution time of all user circuits after parallel adjustment T _{total_after} are compared to determine whether to perform parallel degree adjustment. To do. That is, if the adjusted T _{total_after} is shorter than the T _{total_before} before the adjustment, the parallel degree adjustment for eliminating the bottleneck is executed, and if it is not shortened, the parallel degree adjustment is not executed.

The above T _{total_before} and T _{total_after} are both the total execution times of the CI processing circuit and the DI processing circuit as follows.
T _{total_before} ＝ T _DI _ _{total_before} ＋ T _CI _ _{total_before}
T _{total_after} ＝ T _{DI_total_after} ＋ T _{CI_total_after}

The execution time after adjusting the degree of parallelism of the CI processing circuit is predicted by the above equations 5 and 6. On the other hand, the execution time after adjusting the degree of parallelism of the DI processing circuit is predicted by multiplying the measured value of the execution time before adjustment by the reciprocal 1 / N of the degree of parallelism N times. Further, the distinction between the CI processing circuit and the DI processing circuit can be determined, for example, at the time of compiling the processing program. Alternatively, from the measured value of the band used, it can be determined that the circuit in which the band is used only at the beginning and the end of the data processing is a CI processing circuit, and the other circuits are DI processing circuits.

[Outline processing of FPGA management program]
FIG. 10 is a flowchart of the FPGA management program according to the first embodiment. For example, the OS (Operating System) job management program monitors the jobs of the user's application program executed by the processor, and if the job processing can be executed by the logic circuit in the FPGA, the processor configures a new user circuit. Generates a request interrupt.

When the processor that executes the FPGA management program receives a request to configure a new user circuit from the OS (Operating System) (YES in S1), it processes the request as follows. First, the processor determines whether or not the value obtained by subtracting the total area of the operating user circuit from the total area of the reconfiguration area of the FPGA is larger than the area of the new user circuit (S2). The total area of the FPGA reconfiguration area is, for example, the number of partial reconfiguration blocks PB, and the total area of the operating user circuit is, for example, the partial reconfiguration block in which the operating user circuit is configured. Is the number of.

If the determination in step S2 is YES, the processor requests the FPGA to configure a new user circuit (S3). Then, when the FPGA notifies the completion of the configuration of the new user circuit (YES in S4), the processor notifies the FPGA of the start of the job by the user circuit (S5). On the other hand, if the determination in step S2 is NO, the processor does not request the FPGA to configure the new user circuit, but stores a new circuit configuration request in the request queue (request queue) (S9). The request in the request queue is checked as a new user circuit construction request in step S1 described above in the next cycle.

Further, when the processor receives the job execution completion notification of the user circuit from the FPGA (S6), the processor notifies the FPGA of the release of the user circuit whose job execution is completed (S7). As a result, the control circuit in the FPGA releases the user circuit configured in the reconfiguration area.

Further, the processor executes the parallel degree adjustment process S8 of the user circuit. The parallel degree adjustment process of the user circuit will be described later. Then, the processor repeatedly executes the above steps S1 to S8.

[User circuit parameters]
Before explaining the parallel degree adjustment process S8, first, examples of various parameters of the user circuit managed by the processor will be described.

FIG. 11 is a diagram showing parameters of a user circuit managed by the processor. In the chart of FIG. 11, for each of the user circuits UC_1, UC_2, UC_3, and UC_4 configured in the FPGA reconfiguration area, the degree of parallelism of the logic circuit P, the predicted configuration time CT_E, the predicted execution time ET_E, and the predicted The values of the used band BD_E, the measurement execution time ET_M, and the measurement used band BD_M are shown.

Predicted configuration time CT_E is a predicted value of the time required to download the configuration data of the logic circuit from the FPGA memory and set it in the configuration data memory C_RAM in the FPGA. The predicted execution time ET_E is a predicted value of the time until the execution of one job is completed by the logic circuit. The predicted bandwidth BD_E is a predicted value of the bus bandwidth (data transfer amount) per unit time used by the logic circuit during job execution, and the unit is MB / S.

On the other hand, the measurement execution time ET_M and the measurement use band BD_M are the measured values of the execution time measurement circuit and the data transfer amount measurement circuit provided in the logic circuit.

In addition, the upper limit of the FPGA bus bandwidth is BD_L. This bandwidth upper limit value BD_L is the bandwidth of the FPGA bus, and the total amount of data transferred to the FPGA bus of the logic circuit configured in the reconfiguration area cannot exceed this bandwidth upper limit value BD_L. Therefore, when the total amount of data transferred by the logic circuits configured in the reconfiguration area reaches the bandwidth upper limit value BD_L, it can be considered that a bottleneck has occurred in the bus band.

Further, the parameters of FIG. 11 include circuit types CI (Computation Intensive) and DI (Data Intensive) indicating circuit processing patterns for each of the user circuits UC_1, UC_2, UC_3, and UC_4. The number of times the user circuit is executed for the job N, the number of data sets processed in one execution S, the input data read time T _LD , the output data write time T _ST, and the processing time of one data set. It has T _{COMP_SINGLE} and the initiation interval time T _II of the pipeline circuit.

In the parallel degree adjustment process S8 of the user's logic circuit, the processor controls the parallelism of the user's logic circuit in the reconfiguration area of the FPGA based on the value shown in FIG.

FIG. 12 is a flowchart of the parallel degree adjustment process S8 of the user circuit. Every time the processor that executes the FPGA management program waits for a certain period of time (YES in S10), the execution time measurement circuit of the user circuit configured in the FPGA and the measurement execution time ET_M that the band used measurement circuit is measuring The measurement use band BD_M is read from both circuits or received from the control circuit 151 in the FPGA (S11).

[Control of increase in parallelism (1)]
Then, the processor is the minimum required to increase the degree of parallelism of any of the user circuits being configured in the FPGA by subtracting the total measured bandwidth of the user circuit from the bandwidth upper limit BD_L of the FPGA bus. Determine if it is larger than the band (S12). If the determination in step S12 is YES, the processor increases the degree of parallelism of the user circuit within the range satisfying Equations 1 and 2 shown below (S13A).

FIG. 13 is a flowchart showing a process of increasing the degree of parallelism in step S13A. First, the processor sorts a plurality of (n) user circuits in a predetermined order (for example, in ascending order of measurement use band BD_M) (S131). Let the coefficients i = 1 to n be the order of the sorted user circuits. Then, the processor increases the degree of parallelism Pi of the i-th user circuit to be processed by one for each i of the coefficients i = 1 to n (S132-S135) in the sorted order, that is, in the coefficient order. It is determined whether or not the following equations 1 and 2 are satisfied by the degree of parallelism PXi (= Pi + 1) (S133).

Equations 1 and 2 are shown in FIG. 11 and are as follows.
Σ (BD_Mj / Pj) * PXj <BD_L Equation 1
Σ (Aj * PXj) ≤ A_L Equation 2
Here, Σ is the sum of all user circuits j = 1 to n. The PXj in Equations 1 and 2 is PXj = Pj + 1 if j = i and PXj = Pj if j ≠ i, increasing the degree of parallelism Pj by +1 only for the i-th user circuit to be processed, and at the i-th. No other user circuits remain parallel degree Pj which does not increase.

That is, Equation 1 in the case of n = 4 and i = 2 is as follows.
(BD_M1 / P1) * P1 + (BD_M2 / P2) * PX2 + (BD_M3 / P3) * P3 + (BD_M4 / P4) * P4 <BD_L
The first term on the left side of the above is (BD_M1 / P1) * P1 = BD_M1, and the same applies to the third and fourth terms.
BD_M1 + (BD_M2 / P2) * PX2 + BD_M3 + BD_M4 <BD_L

Further, Aj in Equation 2 is the circuit area of the user circuit having a degree of parallelism 1 (for example, the number of partial reconfiguration blocks), and A_L is the total circuit area of the reconfiguration area (for example, the total number of partial reconfiguration blocks). is there. Equation 2 for n = 4 and i = 2 is as follows.
A1 * P1 + A2 * PX2 + A3 * P3 + A4 * P4 ≤ A_L

When Equation 1 is satisfied, it means that the total bandwidth used by all the user circuits after increasing the degree of parallelism Pi by one only for the i-th user circuit to be processed is smaller than the bandwidth upper limit value BD_L of the FPGA bus. In Equation 1, (BD_M2 / P2) * PX2 means that the measurement bandwidth is proportional to the degree of parallelism. On the other hand, when Equation 2 is satisfied, it means that the total used area of all user circuits after increasing the degree of parallelism Pi by one only for the i-th user circuit to be processed is equal to or less than the total circuit area A_L of the FPGA. To do.

If the determination in step S133 is YES (YES in S133), the processor sets the increased degree of parallelism PXi to the degree of parallelism Pi in its user circuit UC_i (S134). If step S133 is YES in all of the coefficients i = 1 to n, it means that the degree of parallelism Pi of all user circuits has been increased by +1.

On the other hand, if the coefficient i is any of 1 to n and the determination in step S133 is NO (NO in S133), the loop of S132 to S135 is exited. That is, the degree of parallelism is increased by +1 in the order of the user circuits, and when the determination in step S133 becomes NO in a certain user circuit, the processing of loops S132 to S135 ends.

Then, the CPU makes a request to the FPGA to reconfigure the user circuit UC_i with the newly set parallel degree Pi, and after receiving the reconfiguration completion notification of the user circuit, notifies the resumption of job execution of the user circuit ( S137).

In FIG. 13, the user circuits having the smaller measurement bandwidths are sorted in ascending order, and the degree of parallelism is increased preferentially for the user circuits with the smaller measurement bandwidths. It may be determined whether or not the degree of parallelism can be increased. In that case, in general, the smaller the measurement bandwidth, the smaller the increase in the bandwidth used when the degree of parallelism is increased by +1. Therefore, the bandwidth can be suppressed to less than the upper limit of the bus bandwidth. Therefore, this is to increase the degree of parallelism of the user circuit, shorten the job execution time, and complete the job execution faster. After the job execution of the user circuit is completed, the degree of parallelism of other user circuits may be increased to shorten the execution time of those jobs.

[Decrease in parallelism of user circuits, which is presumed to be the cause of bus bandwidth bottlenecks, and increase in parallelism of other user circuits]
Returning to FIG. 12, if the determination in step S12 is NO, the processor determines whether or not the total measurement bandwidth has reached the upper limit of the FPGA bus bandwidth (S14). If the determination in this step S14 is YES, it means that a bottleneck has occurred in the band of the FPGA bus.

Therefore, the processor reduces the degree of parallelism of the predetermined user circuit UC_MAX so that the band used is less than the upper limit of the band (S15). As the predetermined user circuit UC_MAX, as the first example, the user circuit having the largest measurement bandwidth is selected. The processor calculates the predicted bandwidth used by the predetermined user circuit UC_MAX as the amount of decrease in the degree of parallelism, and selects a value such that the sum with the measured bandwidth of other user circuits is less than the bandwidth upper limit. In general, a DI processing circuit is often selected as a user circuit having a large measurement bandwidth.

As a second example, as the predetermined user circuit UC_MAX, the user circuit having the largest difference between the execution time ET_E and the measurement execution time ET_M is selected. It is highly probable that such a user circuit cannot use the FPGA bus band as much as the predicted usage band BD_E due to the bus bottleneck. Therefore, by reducing the degree of parallelism of the user circuit, it is possible to improve the situation where a part of the user circuit does not operate sufficiently due to the bus bottleneck and is unnecessarily configured in the FPGA.

As a third example, the user circuit of the target that reduces the degree of parallelism may be selected with the maximum difference between the predicted used band BD_E and the measured used band BD_M. In this case, the user circuit with the largest difference is the user circuit that cannot use the FPGA bus band as much as the predicted use band BD_E due to the bus bottleneck, so such a user circuit is used as a target to reduce the degree of parallelism. select.

Further, as a fourth example, the user circuit having the maximum degree of parallelism may be selected to reduce the degree of parallelism. In this case, the user circuit whose degree of parallelism is controlled to the maximum can be said to be a user circuit which is more favored than other user circuits, and therefore such a user circuit is selected as a target for reducing the degree of parallelism.

The processor reduces the degree of parallelism of the predetermined user circuit UC_MAX and increases the degree of parallelism of the user circuits other than the predetermined user circuit UC_MAX (S15). Various examples can be considered for selecting a user circuit that increases the degree of parallelism. In the first example, as in FIG. 13, other user circuits are sorted in an arbitrary order, and the degree of parallelism is increased in order within a range satisfying Equations 1 and 2. That is, among the user circuits other than the predetermined user circuit UC_MAX in the FPGA, the DI processing circuit and the CI processing circuit are not distinguished, and the degree of parallelism of any user circuit is increased.

In the second example, the CI processing circuit is preferentially selected to increase the degree of parallelism. Since the CI processing circuit uses a small bandwidth, there is a possibility that the execution time can be shortened while satisfying the bandwidth upper limit or less. However, the reduction in the execution time of the CI processing circuit may not be so large as described above.

In the third example, among the CI processing circuits, a circuit having a large degree of reduction in execution time due to an increase in the degree of parallelism is selected, and a part of the DI processing circuits is selected, and both selected CI processing circuits and DI processing are selected. Increase the degree of parallelism of the circuit. In this case, if the execution time of the circuit with the increased degree of parallelism can be shortened, and the degree of parallelism of a predetermined user circuit whose degree of parallelism has been reduced to eliminate the bus bottleneck after the execution is completed can be increased to shorten the total execution time. desirable.

Next, when the processor does not adjust the increase and decrease of the degree of parallelism in step S15, the total execution time until the job is completed in all the user circuits, the total execution time before adjustment (unadjusted) _{, T total_before,} and so on. The total of the same execution time when the above adjustment is made and the adjusted (adjusted) total execution time T _{total_after} are calculated, and it is determined whether or not _{T total_after} <T _{total_before (S15B).}

If the determination result is YES, the processor executes the adjustment of the degree of parallelism (S15C). If the test result is NO, the processor does not perform parallelism adjustment (S15D). That is, while allowing the bus bottleneck state, the degree of parallelism of the user circuit is not adjusted and is left unadjusted. The user circuit in the FPGA is configured in the FPGA during processing. Therefore, if the total execution time until the job is completed in all the user circuits is shortened, it means that the utilization efficiency of the circuit resources of the FPGA becomes high. By determining the process S15B by the processor, it is possible to determine whether or not to eliminate the bus bottleneck state from the viewpoint of whether or not the utilization efficiency of the FPGA circuit resources is high.

FIG. 14 is a diagram showing a detailed flowchart of steps S15, S15B, S15C, and S15D of FIG. The processor extracts the user circuit UC_MAX having the maximum measurement bandwidth as a process of lowering the parallelism of the predetermined user circuit UC_MAX (S151), lowers the parallelism of the user circuit UC_MAX, and calculates a new bandwidth to be used. Predict. Forecasting the new bandwidth used, for example, estimates that if the degree of parallelism is reduced to 1 / N, the bandwidth used will also be reduced 1 / N times.

Then, the processor determines whether or not the predicted used bandwidth is less than the upper limit (S153), and if it is not less than the upper limit, the process S152 is executed again to further reduce the degree of parallelism. If it is less than, the processor determines whether the difference between the upper bandwidth limit and the sum of the estimated bandwidths of all user circuits exceeds a predetermined reference value Vth (S154). When this predetermined reference value Vth is exceeded, the degree of parallelism of the user circuit other than the user circuit UC_MAX is increased, and a new bandwidth used by the user circuit is predicted (S155).

_{Then, the processor predicts the total value T total_before} of the execution times of all user circuits at the parallel degree before adjustment (former parallel degree) that decreases and increases the parallel degree, and at the same time, after the adjustment that decreases and increases the parallel degree. _Predict the total value T total_after of the execution time of all user circuits at the degree of parallelism (new degree of parallelism) (S156). Further, the processor compares the predicted values _{to determine whether T total_after} <T _{total_before} (S157).

If this determination result is YES (YES in S157), the processor requests the FPGA for a new degree of parallelism of the user circuit, and after receiving the circuit reconfiguration completion notification, restarts the job of the user circuit whose degree of parallelism has been updated. Is notified (S161). The processor executes step S161 even when the determination result of step S154 described above is NO. Then, the processor stores the user circuit UC_MAX in the parallelism reduction list (S162).

On the other hand, _{if the judgment result of T total_after} <T _{total_before} is NO (NO in S157), does the processor include a DI processing circuit with unadjusted parallelism in the user circuit other than the user circuit UC_MAX with reduced parallelism? Judge whether or not (S158). If it is included (YES in S158), the determination result in step S157 may be YES by increasing the degree of parallelism of the DI processing circuit instead of the CI processing circuit. Therefore, the processor changes the combination of the DI processing circuit and the CI processing circuit of the first user circuit that increases the degree of parallelism (S160), and executes steps S155, S156, and S157 again.

For example, for the first user circuit, if the degree of parallelism of a certain DI processing circuit is increased instead of increasing the degree of parallelism of a certain CI processing circuit, the adjusted execution time T _{total_after} is compared with the adjusted execution time T _{total_before} . It may be possible to shorten it. For example, among the first user circuits with increased parallelism, CI processing circuits with a large circuit scale and less reduction in execution time due to increased parallelism are used after stopping the increase in parallelism. It is desirable to secure possible circuit resources and select a DI processing circuit instead of the CI processing circuit to increase the degree of parallelism.

Then, if the determination in step S157 becomes YES, the processor executes steps S161 and S162, and executes the parallel degree adjustment process.

On the other hand, if the determination in step S157 is NO even after changing the combination of the DI processing circuit and CI processing circuit of the first user circuit K times (NO in S159), the degree of parallelism of the predetermined user circuit UC_MAX No adjustment is made for the decrease and the increase in the degree of parallelism of the first user circuit (S15D). Even when the determination in step S158 is NO, the possibility that the determination result in step S157 is reversed is small, so that the processor does not adjust the degree of parallelism of the user circuit (S15D).

According to the flowchart of FIG. 14, the processor adjusts the decrease in the degree of parallelism of the predetermined user circuit UC_MAX for eliminating the bus bottleneck and the increase in the degree of parallelism of the other user circuits (first user circuit). Search for a first user circuit combination in which the total execution time in the state of is shorter than the total execution time in the state before adjustment. As a result, both the elimination of bus bottlenecks and the effective use of FPAG circuit resources can be achieved.

[Control to increase the degree of parallelism of the user circuit UC_MAX]
Returning to FIG. 12, when the processor waits for a certain period of time (NO in S10) and receives the job execution completion notification of the user circuit (YES in S16), the degree of parallelism of the user circuit UC_MAX within the range satisfying Equations 1 and 2. Is controlled to increase (S17). If the job execution completion notification is not received while waiting for a certain period of time, the processor terminates the parallel degree adjustment process S8 of the user circuit.

FIG. 15 is a flowchart showing the process of step S17. Upon receiving the job execution completion notification of the user circuit (YES in S16 of FIG. 12), the processor determines whether the user circuit UC_MAX exists in the parallelism reduction list (S171). If present (YES in S171), the processor calculates the maximum new parallelism PX of the user circuit UC_MAX within the range satisfying Equations 1 and 2 (S172). Equations 1 and 2 are the same as Equations 1 and 2 in FIG. However, here, since the immediately preceding user circuit is released after completing the job execution, the released user circuit is excluded from Equations 1 and 2. The target for increasing the degree of parallelism is the predetermined user circuit UC_MAX.

For example, assuming that the circuit UC_2 of the user 2 is stored in the parallelism reduction list and the job execution of the circuits UC_1 and UC_3 of the user 1 and the user 3 is completed, the equations 1 and 2 are as follows.
(BD_M2 / P2) * PX2 + BD_M4 <BD_L Equation 1
A2 * PX2 + A4 * P4 ≤ A_L Equation 2

The processor calculates the maximum new degree of parallelism PX2 within the range that satisfies the above equation. As a result, the user circuit UC_MAX (UC_2) can be controlled to preferentially increase the degree of parallelism when the execution of another user circuit is completed.

Then, the processor requests the FPGA to configure the logic circuit at the new parallel degree PX of the user circuit UC_MAX, and when it receives the circuit reconfiguration completion notification, it notifies the job execution to be restarted (S173). The processor also removes the increased parallelism user circuit UC_MAX from the reduced parallelism list (S173).

Returning to FIG. 12, the parallel degree adjustment control of the user circuit by the processor is summarized as follows. The processor normally acquires the measurement execution time ET_M and the measurement bandwidth BD_M from the measurement circuit of the user circuit in the FPGA at regular intervals (S11). Then, when the difference between the total measured bandwidth of all user circuits and the upper limit of the bandwidth of the FPGA bus is larger than the bandwidth required to increase the degree of parallelism (YES in S12), the processor uses Equation 1, Equation 1. The degree of parallelism of a certain user circuit is increased within the range satisfying 2 (S13A). Also, if a user circuit completes job execution (YES in S16) and there is no user circuit UC_MAX with reduced parallelism (NO in S171), it is based on the measurement bandwidth BD_M acquired in the next measurement cycle. The determination in step S12 becomes YES, and the processor again gives priority to a predetermined user circuit within the range satisfying Equations 1 and 2 and increases the degree of parallelism (S13A).

On the other hand, if the total bandwidth used for measurement has reached the upper limit of the FPGA bus bandwidth (YES in S14), the processor selects a predetermined user circuit UC_MAX that is suspected to be the cause of the FPGA bus bandwidth bottleneck. The degree of parallelism is reduced so that the bus bottleneck disappears (S15). For the user circuit UC_MAX that lowers the degree of parallelism, for example, a DI processing circuit having a large bandwidth used is selected. Further, the processor increases the degree of parallelism of the remaining user circuits in the range where the user circuits other than the user circuit UC_MAX satisfy Equations 1 and 2 (S15). For the user circuit that increases the degree of parallelism, for example, a CI processing circuit having a small bandwidth used is selected.

Then, when the total predicted execution time of all user circuits in the state after the parallel degree adjustment is shorter than the total predicted execution time of all user circuits in the state before the parallel degree adjustment, the processor executes the change of the parallel degree. However (S15C), if not short, the processor does not perform a degree of parallelism change (S15D).

Furthermore, when the job execution of a certain user circuit is completed (YES in S16), the processor increases the degree of parallelism of the user circuit UC_MAX with the reduced degree of parallelism to the maximum degree of parallelism within the range satisfying equations 1 and 2. (S17). This causes the processor to temporarily reduce the parallelism of the user circuit UC_MAX, which is considered to be the cause of the bus bandwidth bottleneck, but increases the parallelism of other user circuits, resulting in a shorter total execution time of them. .. Then, when the execution of the job of another user circuit is completed, the parallel degree of the user circuit UC_MAX whose parallel degree is temporarily lowered is increased again. As a result, by adjusting the degree of parallelism when a bus bottleneck occurs, the bus bottleneck may be eliminated and the total execution time of all user circuits may be shortened.

[Specific example of parallelism adjustment]
FIG. 16 is a diagram showing a first specific example. The horizontal axis is time TIME, and in the vertical direction (1) predicted execution time when a bus bottleneck does not occur, (2) predicted execution time when a bus bottleneck occurs and the degree of parallelism is not adjusted, (3) bus bottle The estimated execution time when a bottleneck occurs and the degree of parallelism is adjusted is shown. The first specific example is the simplest example in which the user circuits UC-A and UC-B are configured in the FPAG, the user circuit UC-A is the DI processing circuit, and the user circuit UC-B is the CI processing circuit. Is.

In (1) of FIG. 16, the user circuit UC-A is a DI processing circuit, the degree of parallelism P = 4, one execution time is 8, and the job is completed when the number of executions is 5. On the other hand, the user circuit UC-B is a CI processing circuit, and the degree of parallelism P = 2, one execution time is 25 (T _LD = 1, initiation interval Δ = 2, T _COMP = 21, T _ST = 1). ), The job is completed with 2 executions.

(2) When a bus bottleneck occurs and the degree of parallelism is not adjusted, a bus bottleneck occurs at time t1 and it takes time to access the memory in the user circuits UC-A and UC-B. And even if a bus bottleneck occurs, the degree of parallelism of both user circuits is not changed. As a result, the execution time of the user circuit UC-A is 6 longer, and that of the user circuit UC-B is 3 longer.

(3) When a bus bottleneck occurs and the degree of parallelism is adjusted, as a result of reducing the degree of parallelism P of the user circuit UC-A from 4 to 2, the execution time at one time is doubled from 8 to 16. Then, the degree of parallelism P of the user circuit UC-B was doubled from 2 to 4, but because of the CI processing circuit, the initiation interval Δ was only reduced from 2 to 1, and the execution time was one time. It's only slightly shortened from 25 to 24. Then, after the execution of the user circuit UC-B was completed, the degree of parallelism P of the user circuit UC-A was changed from 2 to 8, and the final execution time was shortened to 4.

Therefore, when comparing the total execution time of the two user circuits in the cases of (2) and (3), the user circuit UC-A is 22 longer and the user circuit UC-B is 1 shorter, so (2). The total execution time after adjustment of (3) T _{total_after} is longer than the total execution time T _{total_before before adjustment of).} Therefore, when a bus bottleneck occurs, the processor determines that the degree of parallelism of the user circuit is not adjusted.

FIG. 17 is a diagram showing a second specific example. The horizontal axis and (1), (2), and (3) are the same as those in FIG. In the second specific example, in addition to the user circuits UC-A and UC-B, UC-C is further configured in the FPAG, and the user circuits UC-A and UC-C are DI processing circuits and the user circuit UC-B. Is the CI processing circuit.

In (1) of FIG. 17, the user circuits UC-A and UC-B are the same as those of FIG. The user circuit UC-C is a DI processing circuit, and the job is completed when the degree of parallelism P = 3, the execution time of one time is 12, and the number of executions is 4.

(2) When a bus bottleneck occurs and the degree of parallelism is not adjusted, a bus bottleneck occurs at time t1, and it takes time to access the memory in the user circuits UC-A, UC-B, and UC-C. And even if a bus bottleneck occurs, the degree of parallelism of both user circuits is not changed. As a result, the execution time of the user circuit UC-A is 6 longer, that of the user circuit UC-B is 3 longer, and that of the user circuit UC-C is 6 longer.

(3) When a bus bottleneck occurs and the degree of parallelism is adjusted, the degree of parallelism P of the user circuit UC-A is reduced from 4 to 2, and as a result, one execution time is doubled from 8 to 16. As described in Specific Example 1, even if the degree of parallelism of the user circuit UC-B is increased, the reduction in the execution time is small, so that the degree of parallelism P of the user circuit UC-B does not increase from 2. Instead, the degree of parallelism P of the user circuit UC-C is changed from 3 to 4. As a result, the reconfiguration time of the user circuit UC-B is eliminated and the execution time of one time is 25, which is the same as (1), while the execution time of the user circuit UC-C is shortened from 12 to 9. .. In this example, since the bandwidth used by the user circuit UC-C was small, the degree of parallelism could be increased below the upper bandwidth limit.

Then, after the execution of the user circuit UC-C was completed, the degree of parallelism P of the user circuit UC-A was changed from 2 to 8, and the execution time of the last three times was shortened to 4 respectively.

Therefore, when comparing the total execution time of the two user circuits in the cases of (2) and (3), the user circuit UC-A is 14 longer, while the user circuit UC-B is 3 shorter, and the user circuit UC. -C is 12 shorter. As a result, more of the total execution time T _{Total_after} after adjustment becomes shorter than the total running time T _{Total_before} before adjustment (2) (3). Therefore, when a bus bottleneck occurs, it is determined that the degree of parallelism of the user circuit is adjusted.

In the second specific example, when a bus bottleneck occurs, the degree of parallelism of the user circuit UC-A of the DI processing circuit is lowered to eliminate the bus bottleneck, and the surplus bus band and circuit resources in the FPAG are used. This is an example of increasing the degree of parallelism of the user circuit UC-C of the DI processing circuit instead of the CI processing circuit. In this case, since the total execution time after adjustment is shorter, it is determined that the degree of parallelism is adjusted.

As described above, in the present embodiment, when a bus bottleneck occurs, the processor temporarily lowers the degree of parallelism of a predetermined user circuit in order to eliminate the bus bottleneck, and uses the circuit resources that have a margin. Then, the degree of parallelism of another user circuit is increased, and the degree of parallelism of a predetermined user circuit is increased after the execution of another user circuit is completed. However, whether or not to adjust the degree of parallelism as described above is determined by comparing the total predicted execution time in the state before the adjustment with the total predicted execution time in the adjusted state.

Normally, when a bus bottleneck occurs, the parallelism of DI processing circuits with a large bandwidth is lowered and the parallelism of CI processing circuits with a small bandwidth is increased to eliminate the bus bottleneck and worsen the execution time. Suppress.

However, in the CI processing circuit, the degree of reduction of the execution time is small even if the degree of parallelism is lowered, and the total execution time may not be shortened even if the degree of parallelism is adjusted. In that case, it is determined that the degree of parallelism is not adjusted.

However, even in CI processing circuits, there is a range in the degree of reduction in execution time due to the increase in parallelism, and a CI processing circuit with a long reduction time is selected to increase parallelism, and another DI processing that does not become a bus bottleneck. By selecting a circuit and increasing the degree of parallelism to shorten the execution time, it may be possible to eliminate the bus bottleneck and suppress the deterioration of the execution time.

In the above embodiment, when a bus bottleneck occurs, it is adjusted whether or not to adjust the degree of parallelism that lowers the degree of parallelism of some user circuits and increases the degree of parallelism of other user circuits. Judgment was made by comparing the total execution time of each of the previous state and the adjusted state. However, not only when a bus bottleneck occurs, but also when, for example, the upper limit of FPGA power consumption is reached (power consumption bottleneck occurs), the degree of parallelism of a user circuit with large power consumption is reduced, and power consumption is reduced. Whether or not to adjust the degree of parallelism that increases the degree of parallelism of other user circuits having a small value may be determined by comparing the total execution time before and after the adjustment.

The above embodiments can be summarized as follows.

(Appendix 1)
The processor that executes the program and
A programmable logic circuit device (hereinafter referred to as PLD) having a reconfiguration area for configuring a logic circuit required by the configuration request in response to a configuration request from the processor.
The processor
Of the plurality of logic circuits configured and operating in the reconfiguration area, the parallel degree adjustment for lowering the parallelism of the first logic circuit and increasing the parallelism of the second logic circuit is performed. The first execution time of the plurality of logic circuits is compared with the second execution time of the plurality of logic circuits when the degree of parallelism adjustment is not performed.
An information processing device that requests the PLD to adjust the degree of parallelism when the first execution time is shorter than the second execution time, and does not request the PLD to adjust the degree of parallelism when the first execution time is not short.

(Appendix 2)
The processor
Obtain the measured values of the data transfer amount of a plurality of logic circuits that are configured and operating in the reconfiguration area.
The information processing apparatus according to Appendix 1, wherein when the total amount of data transferred reaches the upper limit of the amount of data transferred on the PLD bus, the comparison is executed.

(Appendix 3)
In the comparison, the total of the first execution times of the plurality of logic circuits and the total of the second execution times are compared.
If the total value of the first execution time is shorter than the total value of the second execution time, the PLD is requested to adjust the degree of parallelism, and if it is not short, the PLD is requested to adjust the degree of parallelism. No, the information processing device according to Appendix 1.

(Appendix 4)
The processor further
The information processing apparatus according to Appendix 1, which calculates the first execution time and the second execution time of the plurality of logic circuits.

(Appendix 5)
The processor
As the first execution time of the plurality of logic circuits, after adjusting the degree of parallelism by lowering the degree of parallelism of the first logic circuit and increasing the degree of parallelism of the second logic circuit, the second logic circuit The information processing apparatus according to Appendix 4, which calculates the execution time of the plurality of logic circuits predicted when the degree of parallelism of the first logic circuit is increased after the execution is completed.

(Appendix 6)
The plurality of logic circuits include one or both of a data-intensive processing circuit in which memory access occurs during data processing and a computation-intensive processing circuit in which memory access occurs at the beginning and end of data processing.
The processor
When the degree of parallelism of the data-intensive processing circuit is multiplied by N, the first execution time is calculated so that the execution time is multiplied by 1 / N.
When the degree of parallelism of the Computation Intention processing circuit is multiplied by N, the execution time is increased by 1 / N times so that the initiation interval time in the pipeline processing of the Computation Intention processing circuit is multiplied by N. The information processing apparatus according to Appendix 4, which calculates the execution time of 1.

(Appendix 7)
The plurality of logic circuits include both a data-intensive processing circuit in which memory access occurs during data processing and a computation-intensive processing circuit in which memory access occurs at the beginning and end of data processing.
The processor
The information processing apparatus according to Appendix 1, wherein the first logic circuit is selected from the data-intensive processing circuit, and the second logic circuit is selected from the computation-intensive processing circuit.

(Appendix 8)
The processor
The information processing apparatus according to Appendix 7, wherein when the first execution time is not shorter than the second execution time, the second logic circuit is changed and the comparison is performed again.

(Appendix 9)
The processor
The data-intensive processing circuit is replaced with the computation-intensive processing circuit in which the execution time is less shortened when the degree of parallelism is increased in the second logic circuit. The information processing apparatus according to Appendix 8, wherein the information processing apparatus is selected.

(Appendix 10)
A PLD management program that causes a processor to execute a programmable logic circuit device (hereinafter referred to as PLD) management process having a reconfiguration area for configuring a logic circuit required by the configuration request in response to a configuration request from the processor. ,
The management process is
Of the plurality of logic circuits configured and operating in the reconfiguration area, the parallel degree adjustment for lowering the parallelism of the first logic circuit and increasing the parallelism of the second logic circuit is performed. The first execution time of the plurality of logic circuits is compared with the second execution time of the plurality of logic circuits when the degree of parallelism adjustment is not performed.
If the first execution time is shorter than the second execution time, the PLD is requested to adjust the degree of parallelism, and if it is not short, the PLD is not requested to adjust the degree of parallelism. Management program.

(Appendix 11)
The processor that executes the program and
The PLD management method for an information processing device having a programmable logic circuit device (hereinafter referred to as PLD) having a reconfiguration area for configuring a logic circuit required by the configuration request in response to a configuration request from the processor. hand,
Of the plurality of logic circuits configured and operating in the reconfiguration area, the parallel degree adjustment for lowering the parallelism of the first logic circuit and increasing the parallelism of the second logic circuit is performed. The first execution time of the plurality of logic circuits is compared with the second execution time of the plurality of logic circuits when the degree of parallelism adjustment is not performed.
A PLD management method in which if the first execution time is shorter than the second execution time, the PLD is requested to adjust the degree of parallelism, and if it is not short, the PLD is not requested to adjust the degree of parallelism.

10: Information processing device 11: CPU, processor 12: Main memory 15: FPGA, PLD
16: Auxiliary storage device 17: Data memory for FPGA
BUS_1: CPU bus
BUS_2: PCI bus
BUS_3: FPGA bus
I_BUS: FPGA internal bus
RC_REG: Reconfiguration area
OC: FPGA operation circuit
PB: Partial reconfiguration block
UC_A, UC_B: User circuit 151: C_DATA write control circuit
C_RAM: Configuration data memory
P: degree of parallelism
ET_E: Predicted execution time
BD_E: Predicted bandwidth
ET_M: Measurement execution time
BD_M: Measurement band, used band
A1, A2: User circuit area
BD_L: Upper limit band
A_L: Total circuit area
T _{total_after} : 1st execution time, 1st total execution time, total execution time after adjusting the degree of parallelism
T _{total_before} : 2nd execution time, 2nd total execution time, total execution time before parallelism adjustment
CI: Computation Intensive Processing Circuit
DI: Data intensive processing circuit

Claims (10)

The processor that executes the program and
A programmable logic circuit device (hereinafter referred to as PLD) having a reconfiguration area for configuring a logic circuit required by the configuration request in response to a configuration request from the processor.
The processor
Of the plurality of logic circuits configured and operating in the reconfiguration area, the parallel degree adjustment for lowering the parallelism of the first logic circuit and increasing the parallelism of the second logic circuit is performed. The first execution time of the plurality of logic circuits is compared with the second execution time of the plurality of logic circuits when the degree of parallelism adjustment is not performed.
An information processing device that requests the PLD to adjust the degree of parallelism when the first execution time is shorter than the second execution time, and does not request the PLD to adjust the degree of parallelism when the first execution time is not short. The processor
Obtain the measured values of the data transfer amount of a plurality of logic circuits that are configured and operating in the reconfiguration area.
The information processing apparatus according to claim 1, wherein when the total of the data transfer amounts reaches the upper limit value of the data transfer amount of the PLD bus, the comparison is executed. In the comparison, the total of the first execution times of the plurality of logic circuits and the total of the second execution times are compared.
If the total value of the first execution time is shorter than the total value of the second execution time, the PLD is requested to adjust the degree of parallelism, and if it is not short, the PLD is requested to adjust the degree of parallelism. The information processing device according to claim 1. The processor further
The information processing apparatus according to claim 1, wherein the first execution time of the plurality of logic circuits and the second execution time are calculated. The processor
As the first execution time of the plurality of logic circuits, after adjusting the degree of parallelism by lowering the degree of parallelism of the first logic circuit and increasing the degree of parallelism of the second logic circuit, the second logic circuit The information processing apparatus according to claim 4, wherein the execution time of the plurality of logic circuits predicted when the degree of parallelism of the first logic circuit is increased after the execution is completed is calculated. The plurality of logic circuits include one or both of a data-intensive processing circuit in which memory access occurs during data processing and a computation-intensive processing circuit in which memory access occurs at the beginning and end of data processing.
The processor
When the degree of parallelism of the data-intensive processing circuit is multiplied by N, the first execution time is calculated so that the execution time is multiplied by 1 / N.
When the degree of parallelism of the Computation Intensive Processing Circuit is multiplied by N, the execution time is multiplied by 1 / N so that the initiation interval time in the pipeline processing of the Computation Intensive Processing Circuit is multiplied by N. The information processing apparatus according to claim 4, wherein the execution time is calculated. The plurality of logic circuits include both a data-intensive processing circuit in which memory access occurs during data processing and a computation-intensive processing circuit in which memory access occurs at the beginning and end of data processing.
The processor
The information processing apparatus according to claim 1, wherein the first logic circuit is selected from the data intensive processing circuit, and the second logic circuit is selected from the computational intensive processing circuit. The processor
The information processing apparatus according to claim 7, wherein when the first execution time is not shorter than the second execution time, the second logic circuit is changed and the comparison is performed again. A PLD management program that causes a processor to execute a programmable logic circuit device (hereinafter referred to as PLD) management process having a reconfiguration area for configuring a logic circuit required by the configuration request in response to a configuration request from the processor. ,
The management process is
Of the plurality of logic circuits configured and operating in the reconfiguration area, the parallel degree adjustment for lowering the parallelism of the first logic circuit and increasing the parallelism of the second logic circuit is performed. The first execution time of the plurality of logic circuits is compared with the second execution time of the plurality of logic circuits when the degree of parallelism adjustment is not performed.
If the first execution time is shorter than the second execution time, the PLD is requested to adjust the degree of parallelism, and if it is not short, the PLD is not requested to adjust the degree of parallelism. Management program. The processor that executes the program and
The PLD management method for an information processing device having a programmable logic circuit device (hereinafter referred to as PLD) having a reconfiguration area for configuring a logic circuit required by the configuration request in response to a configuration request from the processor. hand,
Of the plurality of logic circuits configured and operating in the reconfiguration area, the parallel degree adjustment for lowering the parallelism of the first logic circuit and increasing the parallelism of the second logic circuit is performed. The first execution time of the plurality of logic circuits is compared with the second execution time of the plurality of logic circuits when the degree of parallelism adjustment is not performed.
A PLD management method in which if the first execution time is shorter than the second execution time, the PLD is requested to adjust the degree of parallelism, and if it is not short, the PLD is not requested to adjust the degree of parallelism.

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